High uis reliability planar gate silicon carbide vdmos

Abstract

This invention provides a high UIS reliability planar gate silicon carbide VDMOS, comprising: a drift layer connected to a silicon carbide substrate; a gate protection zone and a shunt region within the drift layer, the gate protection zone being connected to the shunt region; a protrusion on the drift layer; a source protection zone connected to the drift layer and the protrusion; a grounded source protection zone; a P-type well region connected to the source protection zone and the protrusion; an N-type source region and a P-type source region on the P-type well region, the N-type source region being connected to the P-type source region and the P-type well region; a lower side of an insulating dielectric layer connected to the P-type well region and the protrusion; a lower side of a gate metal layer connected to the upper side of the insulating dielectric layer; source metal layers connected to the P-type source region and the N-type source region respectively; and a drain metal layer connected to the lower side of the silicon carbide substrate. The UIS resistance and reliability of the device are improved through the gate protection zone and the grounded source protection zone.

Description

Technical Field

[0001] This utility model relates to a planar gate silicon carbide VDMOS with high UIS reliability. Background Technology

[0002] Due to their wide bandgap characteristics, silicon carbide VDMOS devices naturally possess lower gate charge and higher switching speeds compared to SiVDMOS devices. However, under high-voltage (above 1000V) and high-current (above 100A) application conditions, a single silicon carbide VDMOS device cannot meet the application requirements, necessitating the parallel connection of multiple devices. During the turn-off process of parallel devices, since the device distribution cannot be completely stacked, current may surge towards a single silicon carbide VDMOS device, causing it to burn out. Therefore, existing technologies place higher demands on the UIS characteristics of VDMOS devices. Utility Model Content

[0003] The technical problem to be solved by this utility model is to provide a planar gate silicon carbide VDMOS with high UIS reliability. Through the gate protection zone and the source protection zone connected to ground, the parasitic NPN transistor inside the device is guaranteed to be turned off when the drain voltage is impacted, thereby improving the UIS resistance of the device and improving the reliability of the device.

[0004] This invention provides a high UIS reliability planar gate silicon carbide VDMOS, comprising:

[0005] silicon carbide substrate,

[0006] A drift layer is provided, the lower side of which is connected to the silicon carbide substrate. A gate protection zone and a shunt zone are provided in the drift layer. The outer side of the gate protection zone is connected to the inner side of the shunt zone. A protrusion is provided on the drift layer.

[0007] A source polar protection zone is provided, wherein the lower side of the source polar protection zone is connected to the upper side of the drift layer, and the inner side of the source polar protection zone is connected to the outer side of the protrusion; the source polar protection zone is grounded.

[0008] A P-type well region is provided, wherein the lower side of the P-type well region is connected to the upper side of the source protection zone, the inner side of the P-type well region is connected to the outer side of the protrusion, and an N-type source region and a P-type source region are provided on the P-type well region, wherein the outer side of the N-type source region is connected to the inner side of the P-type source region, and the inner side of the N-type source region is connected to the P-type well region.

[0009] An insulating dielectric layer, the lower side of which is connected to the P-type well region and the protrusion;

[0010] A gate metal layer, wherein the lower side of the gate metal layer is connected to the upper side of the insulating dielectric layer;

[0011] A source metal layer, wherein the source metal layer is connected to the P-type source region and the N-type source region respectively;

[0012] And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.

[0013] The advantages of this utility model are:

[0014] I. This utility model constructs a source protection zone, which is grounded. The P-type region in the middle of the NPN transistor in the N-type source region-P-type well region-source protection zone-drift layer inside the device is always at a low potential, and the NPN transistor cannot be turned on, thereby improving the source UIS characteristics of the device.

[0015] II. This utility model constructs a gate protection zone and a shunt zone structure. When the drain is subjected to high voltage, the gate protection zone protects the gate structure. The shunt zone enables potential transfer from the drift layer near the drain to the drift layer near the gate, thereby ensuring that the NPN structure in both the lateral and vertical directions of the device will not be conductive. In addition to the potential transfer function, the shunt zone can also reduce the device's bulk resistance, which can effectively reduce the device's on-resistance and conduction loss. Attached Figure Description

[0016] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0017] Figure 1 This is a schematic diagram of a high UIS reliability planar gate silicon carbide VDMOS according to this utility model.

[0018] Figure 2 This is a cross-sectional view of the process of a high UIS reliability planar gate silicon carbide VDMOS according to this utility model. Figure 1 .

[0019] Figure 3 This is a cross-sectional view of the process of a high UIS reliability planar gate silicon carbide VDMOS according to this utility model. Figure 2 .

[0020] Figure 4 This is a cross-sectional view of the process of a high UIS reliability planar gate silicon carbide VDMOS according to this utility model. Figure 3 .

[0021] Figure 5 This is a cross-sectional view of the process of a high UIS reliability planar gate silicon carbide VDMOS according to this utility model. Figure 4 .

[0022] Figure 6 This is a cross-sectional view of the process of a high UIS reliability planar gate silicon carbide VDMOS according to this utility model. Figure 5 .

[0023] Figure 7 This is a cross-sectional view of the process of a high UIS reliability planar gate silicon carbide VDMOS according to this utility model. Figure 6 .

[0024] Figure 8 This is a cross-sectional view of the process of a high UIS reliability planar gate silicon carbide VDMOS according to this utility model. Figure 7 .

[0025] Figure 9 This is a cross-sectional view of the process of a high UIS reliability planar gate silicon carbide VDMOS according to this utility model. Figure 8 .

[0026] Figure 10 This is a cross-sectional view of the process of a high UIS reliability planar gate silicon carbide VDMOS according to this utility model. Figure 9 .

[0027] Figure 11 This is a cross-sectional view of the process of a high UIS reliability planar gate silicon carbide VDMOS according to this utility model. Figure 10 . Detailed Implementation

[0028] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0030] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "in contact with," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this utility model, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.

[0031] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.

[0032] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0033] like Figure 1 As shown, this application embodiment provides a high UIS reliability planar gate silicon carbide VDMOS, comprising:

[0034] Silicon carbide substrate 1,

[0035] A drift layer 2 is provided, the lower side of which is connected to the silicon carbide substrate 1. A gate protection zone 21 and a shunt zone 22 are provided in the drift layer 2. The outer side of the gate protection zone 21 is connected to the inner side of the shunt zone 22. A protrusion 23 is provided on the drift layer 2.

[0036] Source protection zone 3, the lower side of source protection zone 3 is connected to the upper side of drift layer 2, and the inner side of source protection zone 3 is connected to the outer side of protrusion 23; source protection zone 3 is grounded;

[0037] P-type well region 4, the lower side of the P-type well region 4 is connected to the upper side of the source protection zone 3, the inner side of the P-type well region 4 is connected to the outer side of the protrusion 23, the P-type well region 4 is provided with an N-type source region 41 and a P-type source region 42, the outer side of the N-type source region 41 is connected to the inner side of the P-type source region 42, and the inner side of the N-type source region 41 is connected to the P-type well region 4;

[0038] An insulating dielectric layer 5, the lower side of which is connected to the P-type well region 4 and the protrusion 23;

[0039] A gate metal layer 6, the lower side of which is connected to the upper side of the insulating dielectric layer 5;

[0040] Source metal layer 7, which is connected to the P-type source region 42 and the N-type source region 41 respectively;

[0041] And a drain metal layer 8, which is connected to the lower side of the silicon carbide substrate 1.

[0042] In this embodiment, preferably, the width of the gate protection zone 21 is equal to the width of the protrusion 23, and the gate protection zone 21 is located directly below the protrusion 23.

[0043] In this embodiment, preferably, the thickness of the gate protection zone 21 is less than the thickness of the shunt zone 22, and the lower side of the gate protection zone 21 and the lower side of the shunt zone 22 are located on the same plane.

[0044] In this embodiment, preferably, the doping concentration of the gate protection zone 21 is less than the doping concentration of the shunt region 22.

[0045] In this embodiment, preferably, the width of the diversion zone 22 is equal to the width of the source protection zone 3, and the diversion zone 22 is located directly below the source protection zone 3.

[0046] In this embodiment, preferably, the doping concentration of the source protection zone 3 is greater than the doping concentration of the drift layer 2, and the doping concentration of the source protection zone 3 is greater than the doping concentration of the P-type well region 4.

[0047] In this embodiment, preferably, the doping concentration of the P-type well region 4 is less than the doping concentration of the drift layer 2.

[0048] In this embodiment, preferably, the silicon carbide substrate 1, the drift layer 2, and the shunt region 22 are N-type; the gate protection zone 21 and the source protection zone 3 are P-type.

[0049] like Figures 1 to 11 As shown, the method for preparing silicon carbide VDMOS obtained by the above manufacturing method includes the following steps:

[0050] Step 1: Deposit metal on the lower side of silicon carbide substrate 1 to form drain metal layer 8; grow epitaxially on the upper side of silicon carbide substrate 1 to form drift layer 2;

[0051] Step 2: Form a barrier layer 100 above the drift layer 2, etch the barrier layer 100 to form a via, and implant ions to form a gate protection zone 21;

[0052] Step 3: Remove the barrier layer 100 from Step 2, reform the barrier layer 100, etch the barrier layer 100 to form a via, and implant ions to form a shunt region 22.

[0053] Step 4: Remove the barrier layer 100 from Step 3, reform the barrier layer 100, etch the barrier layer 100 to form a via, perform ion implantation to form the source protection zone 3; and ground the source protection zone 3.

[0054] Step 5: Perform ion implantation again to form a P-type trap region 4, and form a protrusion 23 on the drift layer 2;

[0055] Step 6: Remove the barrier layer 100 from step 4, reform the barrier layer 100, etch the barrier layer 100 to form a via, and implant ions to form a P-type source region 42.

[0056] Step 7: Remove the barrier layer 100 from step 6, reform the barrier layer 100, etch the barrier layer 100 to form a via, and implant ions to form an N-type source region 41.

[0057] Step 8: Remove the barrier layer 100 from step 7, reform the barrier layer 100, etch the barrier layer 100 to form a via, and deposit to form an insulating dielectric layer 5;

[0058] Step 9: Remove the barrier layer 100 from step 8, reform the barrier layer 100, etch the barrier layer 100 to form a via, and deposit to form the gate metal layer 6.

[0059] Step 10: Remove the barrier layer 100 from step 9, reform the barrier layer 100, etch the barrier layer 100 to form a via, deposit and form the source metal layer 7, remove the barrier layer 100, and complete the fabrication.

[0060] In another embodiment of this invention, the doping concentration of the silicon carbide substrate 1 is 2-8e18cm. -3 The doping concentration of drift layer 2 is 6-10e16cm. -3 The doping concentration of the gate protection zone 21 is 5-8e16cm. -3 The doping concentration of the shunt region 22 is 1-5e18cm. -3 The doping concentration of source protection zone 3 is 5-8e18cm. -3 The doping concentration of P-type well region 4 is 1-5e15cm. -3 The doping concentration of the P-type source region 42 is 1-5e19cm. -3 The insulating dielectric layer 5 can be made of silicon dioxide, and the doping concentration of the N-type source region 41 is 2-8e18cm. -3 ;

[0061] The doping concentration of the silicon carbide substrate 1 is to ensure a low-resistance ohmic contact with the drain metal layer 8, reducing the overall on-resistance of the device. The doping concentration of the drift layer 2 is a trade-off between the reverse breakdown voltage and on-resistance of the device. The doping concentration of the gate protection zone 21 is designed to reduce the impact on the device's conduction characteristics while ensuring device protection. The doping concentration of the shunt region 22 is not only to reduce the device's bulk resistance and conduction loss, but also to transfer the potential from below the gate protection zone 21 to above it, preventing the NPN transistor inside the device from conducting and affecting device reliability. The doping concentration of the source protection zone 3 is designed to transfer a low potential to the P-type well region inside the device, thereby preventing the structure of N-type source region 41-P-type well region 4-source protection zone 3-drift layer 2 from conducting, improving the device's UIS resistance.

[0062] The doping concentration of the P-type source region 42 is not only to reduce the contact resistance between the P-type source region 42 and the source metal layer 7, thereby reducing the conduction loss of the parasitic PN junction body diode of the device, but also to ensure that the diffusion rate of the space charge region to the device gate and source is reduced when the drain voltage is high within the P-type source region 42.

[0063] The doping concentration of the P-type well region 4 is to reduce the gate charge of the device gate, improve the switching speed of the device, and also to form a buffer between the P-type source region 42 and the N-type source region 41, thereby reducing the electric field strength near the N-type source region 41 and improving the reliability of the device near the N-type source region 41.

[0064] The silicon carbide substrate 1 of the device has a thickness of 1 μm, the drift layer 2 has a thickness of 50-100 μm, which is adjusted within the above range according to different requirements for the device's withstand voltage characteristics. The gate protection zone 21 has a thickness of 1 μm, and its top is 10 μm away from the bottom of the source protection zone 3. The thickness of the gate protection zone 21 is designed to ensure the structure's ability to protect the device's gate. The distance between the gate protection zone 21 and the source protection zone 3 is designed to avoid affecting the device's conductive channel while keeping the ion implantation depth as shallow as possible to reduce the fabrication difficulty. The thickness of the shunt region 22 is 1.5 times the thickness of the gate protection zone 21. The lower side of the shunt region 22 is flush with the lower side of the gate protection zone 21. This structure can transfer the potential from the lower side of the gate protection zone 21 to the upper side of the gate protection zone 21, thereby ensuring that the parasitic diode does not conduct. The thickness relationship between the shunt region 22 and the gate protection zone 21 can reduce the bulk resistance of the device and reduce the conduction loss. The thickness of the source protection zone 3 is 500nm, which is to ensure the protection performance of the device source. The thickness of the P-type well region 4 is 600nm, the thickness of the N-type source region 41 and the P-type source region 42 is 300nm, and the thickness of the device insulating dielectric layer 5 is 50nm.

[0065] The width of the P-type source region 42 is 1 μm, the width of the N-type source region 41 is 500 nm, and the width of the P-type well region 4 is 1.8 μm. The width of the P-type source region 42 is designed to ensure the freewheeling capability of the device's body diode. The width of the N-type source region 41 only needs to ensure a low-resistance ohmic contact with the source metal layer 7, and its width has little impact on the device's characteristics. The width of the P-type well region 4 is formed by creating a gate control structure based on the P-type source region 42 and the N-type source region 41. The width of the source protection zone 3 is 1.8 μm to ensure the complete potential flow to the P-type well region 4. For transmission, the width of the insulating dielectric layer 5 is 2.7 μm, distributed in the center of the device, and the width of the gate metal layer 6 is 2.6 μm. This is to ensure the gate control capability and gate structure fabrication margin of the device. The thickness of the gate metal layer 6 is 250 nm, the thickness of the source metal layer 7 is 300 nm, the width of the shunt region 22 is 1.8 μm, and the width of the gate protection zone 21 is 2 μm. This is to reduce the process cost by using the same photomask as the source protection zone 3 for the fabrication of the shunt region 22 without affecting the device characteristics.

[0066] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A high UIS reliability planar gate silicon carbide VDMOS, characterized in that: include: silicon carbide substrate, A drift layer is provided, the lower side of which is connected to the silicon carbide substrate. A gate protection zone and a shunt zone are provided in the drift layer. The outer side of the gate protection zone is connected to the inner side of the shunt zone. A protrusion is provided on the drift layer. A source polar protection zone is provided, wherein the lower side of the source polar protection zone is connected to the upper side of the drift layer, and the inner side of the source polar protection zone is connected to the outer side of the protrusion; the source polar protection zone is grounded. A P-type well region is provided, wherein the lower side of the P-type well region is connected to the upper side of the source protection zone, the inner side of the P-type well region is connected to the outer side of the protrusion, and an N-type source region and a P-type source region are provided on the P-type well region, wherein the outer side of the N-type source region is connected to the inner side of the P-type source region, and the inner side of the N-type source region is connected to the P-type well region. An insulating dielectric layer, the lower side of which is connected to the P-type well region and the protrusion; A gate metal layer, wherein the lower side of the gate metal layer is connected to the upper side of the insulating dielectric layer; A source metal layer, wherein the source metal layer is connected to the P-type source region and the N-type source region respectively; And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.

2. The high UIS reliability planar gate silicon carbide VDMOS as described in claim 1, characterized in that: The width of the gate protection zone is equal to the width of the protrusion, and the gate protection zone is located directly below the protrusion.

3. The high UIS reliability planar gate silicon carbide VDMOS as described in claim 1, characterized in that: The thickness of the gate protection zone is less than the thickness of the shunt zone, and the lower side of the gate protection zone and the lower side of the shunt zone are located on the same plane.

4. The high UIS reliability planar gate silicon carbide VDMOS as described in claim 1, characterized in that: The doping concentration of the gate protection zone is less than that of the shunt zone.

5. A high UIS reliability planar gate silicon carbide VDMOS as described in claim 1, characterized in that: The width of the diversion zone is equal to the width of the source protection zone, and the diversion zone is located directly below the source protection zone.

6. The high UIS reliability planar gate silicon carbide VDMOS as described in claim 1, characterized in that: The doping concentration of the source protection zone is greater than the doping concentration of the drift layer, and the doping concentration of the source protection zone is greater than the doping concentration of the P-type well region.

7. A high UIS reliability planar gate silicon carbide VDMOS as described in claim 1, characterized in that: The doping concentration of the P-type well region is less than the doping concentration of the drift layer.

8. A high UIS reliability planar gate silicon carbide VDMOS as described in claim 1, characterized in that: The silicon carbide substrate, drift layer, and shunt region are N-type; the gate protection zone and source protection zone are P-type.

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