Serial port switching system of computer equipment

Abstract

The utility model provides a kind of serial ports switching system of computer equipment, it is related to computer equipment technical field, the serial ports switching system includes: processor, contains debugging serial port, eSPI interface and GPIO control unit;Baseboard management controller, contains first UART interface, eSPI interface is used to establish communication connection between processor and baseboard management controller;Logic control module, its signal input end is connected to the signal line of processor debugging serial port and the signal line of baseboard management controller's first UART interface respectively, and the control end of logic control module is connected GPIO control unit;Level conversion module, the signal output end of logic control module is connected to the signal input end of level conversion module, and the signal output end of level conversion module is used to connect external serial communication interface;Wherein, logic control module responds to the control signal of GPIO control unit, selectively debugging serial port or first UART interface is connected to level conversion module.

Description

Technical Field

[0001] This utility model relates to the field of computer equipment technology, and specifically to a serial port switching system for computer equipment. Background Technology

[0002] With the rapid development of server technology, the serial port, as a crucial interface for server debugging and interaction with external devices, is vital for server operation and management due to its diverse functionality and stability. Currently, serial port implementation in the server field mainly relies on the collaborative design of the motherboard integrated controller (such as the BMC, baseboard management controller) and the CPU's own interface. However, there are significant differences in serial port solutions for different server architectures, especially in AMD CPU servers, where existing implementations are gradually showing functional limitations.

[0003] In existing servers, mainstream solutions often use a BMC (Browser Controller Module) integrated with a Super IO controller. The BMC integrates multiple full-featured UART (Universal Asynchronous Receiver / Transmitter) interfaces, and the BIOS can configure one of these UARTs as the host serial port for connecting traditional serial devices such as mice and modems, or as a regular communication interface during system operation. Because the Super IO controller supports a full-featured UART design, this approach is compatible with the communication protocols of various traditional serial devices, ensuring stable operation when external devices are connected. However, the serial port design of AMD CPU servers differs significantly. Since the UART interfaces integrated into AMD CPUs are mostly non-full-featured, only supporting basic debug log output (such as information printing during BIOS startup), they cannot fully implement standard serial protocols such as RS232. This often leads to communication anomalies, device recognition failures, or data transmission errors when traditional devices such as serial mice or hard drives are connected externally, severely impacting the server's external device expansion capabilities. Utility Model Content

[0004] In view of the above problems, this utility model provides a serial port switching system for a computer device, the serial port switching system for the computer device includes: a processor, the processor including a debug serial port, an eSPI interface and a GPIO control unit;

[0005] A baseboard management controller, the baseboard management controller including a first UART interface, the eSPI interface being used to establish a communication connection between the processor and the baseboard management controller;

[0006] The logic control module has its signal input terminals connected to the signal lines of the processor's debug serial port and the signal lines of the first UART interface of the baseboard management controller, respectively, and its control terminal is connected to the GPIO control unit.

[0007] A level conversion module is provided, wherein the signal output terminal of the logic control module is connected to the signal input terminal of the level conversion module, and the signal output terminal of the level conversion module is used to connect to an external serial communication interface.

[0008] The logic control module responds to the control signals of the GPIO control unit and selectively connects the debug serial port or the first UART interface to the level conversion module.

[0009] In one possible implementation, the baseboard management controller further includes a second UART interface connected to the logic control module, which is used to receive debug serial port data transmitted by the logic control module.

[0010] In one possible implementation, the logic control module is a CPLD or an FPGA.

[0011] In one possible implementation, the level conversion module is an RS232 level conversion circuit, which is used to convert between UART level and RS232 level.

[0012] In one possible implementation, the RS232 level conversion circuit includes a level conversion chip of model MAX3243.

[0013] In one possible implementation, the substrate management controller includes a BMC chip of model AST2600.

[0014] In one possible implementation, the external serial communication interface is a DB9 interface.

[0015] The above-described one or more technical solutions in the embodiments of this application have at least one or more of the following technical effects:

[0016] This utility model provides a serial port switching system for a computer device. Through the collaborative work of a logic control module and the processor's GPIO control unit, during the power-on debugging phase, the GPIO control unit can drive the logic control module to connect the processor's debugging serial port with the level conversion module. At this time, information such as the BIOS self-test log output from the debugging serial port is output through an external serial interface after level conversion, meeting the information interaction requirements of the debugging phase. After the BIOS completes its self-test, the GPIO control unit switches the state of the logic control module, connecting the full-function first UART interface of the baseboard management controller with the level conversion module. Utilizing the BMC UART's full support for standard serial port protocols such as RS232, traditional devices such as external serial mice and hard drives can be stably connected and data can be transmitted transparently. This completely solves the problems of communication anomalies and device identification failures caused by the lack of protocols in the AMD CPU's own non-full-function UART. This solution retains the information output function during the debugging phase and overcomes hardware limitations by relying on the first UART interface of the baseboard management controller, effectively improving the server's adaptability to external serial devices and operational reliability.

[0017] The above description is merely an overview of the technical solution of this utility model. In order to better understand the technical means of this utility model and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this utility model more obvious and understandable, specific embodiments of this utility model are given below. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the module structure of the serial port switching system of the computer device in this embodiment of the utility model.

[0020] Figure 2 This is a schematic diagram of the logic control module of the serial port switching system of the computer device in this embodiment of the present utility model.

[0021] Figure 3 This is a hardware block diagram of the serial port switching system of the computer device in this embodiment of the present utility model.

[0022] Explanation of reference numerals in the attached diagram: 100, processor; 110, debug serial port; 120, eSPI interface; 130, GPIO control unit; 200, baseboard management controller; 210, first UART interface; 220, second UART interface; 300, logic control module; 400, level conversion module; 500, external serial communication interface. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this utility model clearer, the embodiments of this utility model will be described in further detail below with reference to the accompanying drawings.

[0024] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. In the following description, when referring to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this invention as detailed in the appended claims.

[0025] The overall concept of the technical solution provided by this utility model is as follows:

[0026] Please see Figures 1 to 3 The serial port switching system of computer equipment includes:

[0027] Processor 100 includes a debug serial port 110, an eSPI interface 120, and a GPIO control unit 130. The debug serial port 110 is primarily used to output debug information during system startup or operation, such as BIOS self-test logs, error codes, and system status. It provides a low-level communication interface, allowing developers and engineers to monitor and diagnose system problems. During the power-on debugging phase, the debug serial port 110 is the main output interface for transmitting BIOS self-test logs and other debug information. eSPI is an interface standard for communication between processor 100 and the board management controller 200, replacing the traditional LPC (Low Pin) interface. The eSPI interface 120 provides higher bandwidth and more flexible configuration. It supports multiple communication protocols and functions, including power management, firmware updates, and sensor data reading. The eSPI interface 120 establishes a communication connection between the processor 100 and the board management controller 200, enabling the board management controller 200 to receive commands from the processor 100 and return status information. The GPIO control unit 130 allows the processor 100 to control the state (high or low level) of general-purpose input / output pins through software. The GPIO control unit 130 acts as a control signal source in the serial port switching system. According to the instructions of the processor 100, it sends control signals to the logic control module 300 to switch the serial port connection. For example, during the power-on debugging phase, the GPIO control unit 130 sends a signal to connect the debugging serial port 110 to the level conversion module 400. After the BIOS completes the self-test, the GPIO module outputs high or low level signals according to the instructions of the BIOS. These signals are used to control the state switching of the logic control module 300.

[0028] The baseboard management controller 200 includes a first UART interface 210 and an eSPI interface 120 for establishing a communication connection between the processor 100 and the baseboard management controller 200. As can be understood, the UART (Universal Asynchronous Receiver / Transmitter) interface is a standard interface for serial communication. The first UART interface 210 in the baseboard management controller 200 is a full-featured serial port supporting multiple serial communication protocols, such as RS232. This interface can handle high-speed data transmission, support complex communication protocols, and provide a stable communication link. After the BIOS self-test is completed, the first UART interface 210 becomes the main external serial communication interface 500, responsible for data communication with external serial devices (such as serial mice, serial hard drives, etc.), ensuring stable access and data pass-through for these devices. Because the first UART interface 210 is a full-featured design, it fully supports standard serial protocols such as RS232, solving the AMD... The CPU itself has a non-full-function UART interface protocol missing problem; the eSPI interface 120 is used to use the first UART interface 210 inside the baseboard management controller 200 as the serial port of the host system. Through the eSPI interface 120, the baseboard management controller 200 can extend the function of its first UART interface 210 to the processor 100, so that it can work like the serial port of the processor 100 itself.

[0029] The logic control module 300 has its signal input terminals connected to the signal lines of the debug serial port 110 of the processor 100 and the signal lines of the first UART interface 210 of the baseboard management controller 200, respectively. The control terminal of the logic control module 300 is connected to the GPIO control unit 130. The logic control module 300 is an electronic circuit module used to switch or route different signal paths based on the input control signals. The logic control module 300 receives control signals from the GPIO control unit 130 through its control terminal and then switches the signal path according to the control signals from the GPIO control unit 130. For example, when the GPIO control unit 130 outputs a high level, the logic control module 300 connects the first UART interface 210 of the baseboard management controller 200 to the level conversion module 400; when it outputs a low level, the debug serial port 110 is connected to the level conversion module 400.

[0030] The signal output terminal of the logic control module 300 is connected to the signal input terminal of the level conversion module 400. The signal output terminal of the level conversion module 400 is used to connect to the external serial communication interface 500. The level conversion module 400 is a circuit module used to convert signals between different voltage levels. It can convert a signal of one level to another to meet the communication needs between different devices. For example, it can convert the TTL / CMOS level signal of the processor 100 or the board management controller 200 into an RS232 standard level signal to meet the communication needs of external serial devices. The converted signal is connected to the external serial communication interface 500 through the output terminal of the level conversion module 400 to realize communication with external devices.

[0031] The logic control module 300 responds to the control signals of the GPIO control unit 130 and selectively connects the debug serial port 110 or the first UART interface 210 to the level conversion module 400.

[0032] For example, during power-up, the debug serial port 110 of the processor 100 begins to output BIOS self-test logs, error codes and other debugging information. At the same time, the debug serial port 110 of the processor 100 can also receive input information from the outside for interactive debugging.

[0033] During the power-on startup phase, the logic control module 300 connects the debug serial port 110 of the processor 100 to the level conversion module 400. The logic control module 300 receives the output information from the debug serial port 110 of the processor 100. The logic control module 300 outputs the received debug information to the receiving terminal (such as a serial console, debugging device, etc.) through the external serial communication interface 500. System debugging personnel can view and process this debug information through the receiving terminal to evaluate the problems in the self-test process of the processor 100.

[0034] After the BIOS of processor 100 completes the self-test configuration, the BIOS will control the GPIO control unit 130 in processor 100 to send a GPIO signal to inform the logic control module 300 that the power-on self-test has been completed, indicating that the BIOS firmware has completed its work. When the logic control module 300 receives the GPIO signal, it will switch from the debug serial port 110 of processor 100 to the first UART interface 210 of the baseboard management controller 200.

[0035] Since the first UART interface 210 of the baseboard management controller 200 is a full-function serial port, it can support standard serial port protocols such as RS232 and realize stable communication with external serial devices. The serial port information of the host system is transmitted to the external serial communication interface 500 through the logic control module 300. Therefore, the aforementioned external serial communication interface 500 is a full-function serial port under the host system and can normally realize communication with serial devices, such as serial mice, serial printers, and serial hard drives.

[0036] Through the coordinated operation of the logic control module 300 and the GPIO control unit 130 of the processor 100, during the power-on debugging phase, the GPIO control unit 130 can drive the logic control module 300 to connect the processor 100 debugging serial port 110 with the level conversion module 400. At this time, the BIOS self-test log and other information output by the debugging serial port 110 are output through the external serial interface after level conversion, meeting the information interaction requirements of the debugging phase. After the BIOS completes the self-test, the GPIO control unit 130 switches the state of the logic control module 300 and connects the full-function first UART interface 210 of the baseboard management controller 200 with the level conversion module 400. By utilizing the full support capability of the baseboard management controller 200's UART for standard serial port protocols such as RS232, traditional devices such as external serial mice and hard drives can be stably connected and data can be transmitted transparently, completely solving the problems of communication abnormalities and device identification failures caused by the lack of protocols in the AMD CPU's own non-full-function UART. This solution retains the information output function during the debugging phase, and overcomes hardware limitations by relying on the first UART interface 210 of the baseboard management controller 200, effectively improving the server's adaptability to external serial devices and operational reliability.

[0037] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0038] For further details, please refer to Figure 1The baseboard management controller 200 also includes a second UART interface 220, which is connected to the logic control module 300. The second UART interface 220 is used to receive debug serial port 110 data transparently transmitted by the logic control module 300. The second UART interface 220 is an asynchronous serial input / output controller specifically designed to receive debug serial port 110 information from the processor 100 transparently transmitted by the logic control module 300. This data typically includes BIOS self-test logs, error codes, system status, and other information. Through the second UART interface 220, the data from the debug serial port 110 is transparently transmitted through the logic control module 300 to the second UART interface 220 of the baseboard management controller 200 as SOL (System Logical Received) information. Through the SOL function, debug information can be transmitted to a remote management system via a network to achieve remote debugging and monitoring. The second UART interface 220 differs from the first UART interface 210 of the baseboard management controller 200. The first UART interface 210 is mainly used for communication with external serial devices, while the second UART interface 220 focuses on internal data transmission and debugging.

[0039] Furthermore, the logic control module 300 can be either a CPLD or an FPGA. A CPLD (Complex Programmable Logic Device) is a programmable logic device with high integration and flexibility. It is typically used to implement small- to medium-scale logic functions, offering fast startup time and low cost. An FPGA (Field-Programmable Gate Array) is a highly programmable logic device capable of implementing complex logic functions. It offers higher logic capacity and flexibility, making it suitable for applications requiring large amounts of logic resources and complex designs. Users can choose between a CPLD or an FPGA as the logic control module 300 based on their actual needs, with a CPLD being preferred.

[0040] More specifically, the level conversion module 400 is an RS232 level conversion circuit, which is used to convert UART levels to RS232 levels. UART typically uses TTL (transistor-to-transistor logic) or CMOS levels, with a voltage range of 0V to 3.3V or 5V. RS232 uses negative logic, with logic "1" typically ranging from -3V to -15V and logic "0" typically ranging from +3V to +15V. The RS232 level conversion circuit is a circuit module used to convert UART (typically TTL or CMOS level) signals to RS232 standard level signals.

[0041] For example, an RS232 level conversion circuit includes the MAX3243 level conversion chip. The MAX3243 is an RS232 level conversion chip from Maxim Integrated, designed specifically for multi-channel RS232 communication. It can convert TTL / CMOS level signals to RS232 level signals and vice versa. Its built-in charge pump and multiple protection functions make it an ideal choice for RS232 level conversion, suitable for various applications.

[0042] Furthermore, the Baseboard Management Controller 200 includes an AST2600 BMC chip. The Baseboard Management Controller 200 (BMC) is responsible for managing and monitoring various hardware functions of the server, including power management, temperature monitoring, remote management, and serial communication. The AST2600 is a high-performance BMC chip launched by ASPEED Technology, designed specifically for server and data center applications. It integrates multiple functional modules to achieve comprehensive server management and monitoring.

[0043] Furthermore, the external serial communication interface 500 is a DB9 interface. The external serial communication interface 500 is responsible for connecting the server with external serial devices, enabling data communication and control signal transmission. The DB9 interface (D-subminiature 9-pin) is a common serial communication interface standard with 9 pins used for serial data transmission between devices. The DB9 interface is widely used in computers, industrial control equipment, network equipment, and other fields, and is one of the commonly used physical interfaces of the RS232 standard.

[0044] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the present invention.

[0045] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this utility model without departing from the spirit and scope of the embodiments of this utility model. Therefore, if these modifications and variations to the embodiments of this utility model fall within the scope of the claims of this utility model and their equivalents, then this utility model also intends to include these modifications and variations.

Claims

1. A serial port switching system for a computer device, characterized in that, include: The processor includes a debug serial port, an eSPI interface, and a GPIO control unit; A baseboard management controller, the baseboard management controller including a first UART interface, the eSPI interface being used to establish a communication connection between the processor and the baseboard management controller; The logic control module has its signal input terminals connected to the signal lines of the processor's debug serial port and the signal lines of the first UART interface of the baseboard management controller, respectively, and its control terminal is connected to the GPIO control unit. A level conversion module is provided, wherein the signal output terminal of the logic control module is connected to the signal input terminal of the level conversion module, and the signal output terminal of the level conversion module is used to connect to an external serial communication interface. The logic control module responds to the control signals of the GPIO control unit and selectively connects the debug serial port or the first UART interface to the level conversion module.

2. The serial port switching system for a computer device according to claim 1, characterized in that, The baseboard management controller also includes a second UART interface, which is connected to the logic control module and is used to receive debug serial port data transmitted by the logic control module.

3. The serial port switching system for a computer device according to claim 1, characterized in that, The logic control module is a CPLD or FPGA.

4. The serial port switching system for a computer device according to claim 1, characterized in that, The level conversion module is an RS232 level conversion circuit, which is used to convert between UART level and RS232 level.

5. A serial port switching system for a computer device according to claim 4, characterized in that, The RS232 level conversion circuit includes a level conversion chip of model MAX3243.

6. A serial port switching system for a computer device according to claim 1, characterized in that, The substrate management controller includes a BMC chip of model AST2600.

7. A serial port switching system for a computer device according to any one of claims 1-6, characterized in that, The external serial communication interface is a DB9 interface.

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