Test circuit for internal bias current of chip and chip

Abstract

The application provides a chip internal bias current test circuit and a chip, and belongs to the field of semiconductor integrated circuit chips. A measured current mirror module, a test mirror module and a path control module are arranged in the chip. The measured current mirror module generates a bias current in the chip. The test mirror module is connected with the measured current mirror module, and mirrors the bias current when the test mirror module is turned on, so as to adjust the total current of the chip. When the control signal is a first level, the path control module controls the test mirror module to be disconnected. When the control signal is a second level, the path control module controls the test mirror module to be turned on. The detection processing module is connected with the power supply of the chip, and detects the first total current of the chip when the circuit is disconnected and the second total current of the chip when the circuit is turned on, so as to determine the bias current. No additional special test chip peripheral pin is needed, the layout area is reduced, and the problems in the prior art are solved.

Description

Technical Field

[0001] This application belongs to the field of semiconductor integrated circuit chip technology, and particularly relates to a test circuit for the internal bias current of a chip and the chip itself. Background Technology

[0002] The internal bias current of a chip serves as a reference current to provide a stable operating point for the active components (such as transistors and operational amplifiers) within the chip. Its core function is to ensure that these components operate in a preset state, thereby guaranteeing the normal function and stable performance of the chip. Testing the internal bias current of a chip is a crucial step in chip functional verification, performance assurance, and quality screening, directly impacting the final usability of the chip.

[0003] However, traditional techniques require pins to be brought out for testing, limiting the method of testing the current of a specific branch within the chip to adding more chip ports for dedicated testing. Therefore, testing the bias current inside the chip using traditional techniques not only increases the number of external pins but also increases the layout area. Utility Model Content

[0004] The purpose of this application is to provide a test circuit and chip for the internal bias current of a chip, which aims to solve the above-mentioned problems existing in the conventional technology.

[0005] This application provides a test circuit for the internal bias current of a chip, the chip including a current-under-test mirror module for generating bias current, and the test circuit including:

[0006] A test mirror module is located inside the chip and is connected to the current under test mirror module. It is used to mirror the bias current when the test mirror module is turned on, so as to adjust the total current of the chip.

[0007] A path control module, located inside the chip, is connected to the test mirror module. The path control module is used to control the test mirror module to disconnect when the control signal is at a first level, and the path control module is also used to control the test mirror module to turn on when the control signal is at a second level.

[0008] The detection and processing module is connected to the chip power supply and is used to detect the total current of the first chip when the test mirror module is disconnected and the total current of the second chip when it is connected, and to determine the bias current based on the total current of the second chip and the total current of the first chip.

[0009] In some embodiments, the current-under-test mirror module includes:

[0010] The main bias transistor has its gate terminal connected to its drain terminal, its source terminal grounded, and its drain terminal connected to the chip power supply to generate the bias current.

[0011] The image transistor under test (IPT) has its gate terminal connected to the gate terminal of the main bias transistor, its source terminal grounded, and its drain terminal used to obtain the transistor bias voltage.

[0012] In some embodiments, the test circuit for the internal bias current of the chip further includes:

[0013] A current source is located inside the chip. The input terminal of the current source is connected to the chip's power supply, and the output terminal of the current source is connected to the drain terminal of the main bias transistor. The current source is used to provide a reference current to the main bias transistor so that the main bias transistor generates the bias current.

[0014] In some embodiments, the test image module includes:

[0015] At least one test mirror transistor, the gate terminal of which is connected to the gate terminal of the main bias transistor and the gate terminal of the test mirror transistor, the source terminal of which is grounded, and the drain terminal of which is connected to the path control module.

[0016] In some embodiments, the access control module includes:

[0017] An inverter, wherein the input terminal of the inverter is used to acquire the control signal and invert the control signal to obtain an inverted control signal;

[0018] The first switching transistor has its gate connected to the input of the inverter to acquire the control signal, and its drain is used to acquire the transistor bias voltage.

[0019] The second switching transistor has its gate connected to the output of the inverter to obtain the inverting control signal, and its drain is used to obtain the transistor bias voltage.

[0020] A path bias transistor is provided, wherein the gate terminal of the path bias transistor is connected to the source terminals of the first switching transistor and the second switching transistor, the drain terminal of the path bias transistor is connected to the chip power supply, and the source terminal of the path bias transistor is connected to the drain terminal of the test mirror transistor.

[0021] In some embodiments, the access control module further includes:

[0022] The third switch has its gate connected to the output of the inverter to acquire the inverting control signal. The drain of the third switch is connected to the gate of the bias transistor, and the source of the third switch is grounded.

[0023] In some embodiments, the access control module further includes:

[0024] A non-volatile memory is connected to the input terminal of the inverter and is used to output the control signal to the input terminal of the inverter.

[0025] In some embodiments, the main bias transistor, the under-test mirror transistor, the test mirror transistor, the first switch transistor, the path bias transistor, and the third switch transistor are N-type field-effect transistors.

[0026] In some embodiments, the second switching transistor is a P-type field-effect transistor.

[0027] This application provides a chip, including a test current mirror module, a test mirror module, a path control module, and a current source of the test circuit for the internal bias current of the chip as described in any of the above embodiments.

[0028] The beneficial effects of this utility model embodiment compared with the prior art are:

[0029] The current under test (DUT) mirror module can be understood as a specific current mirror module within the chip that generates the chip's internal bias current. The test mirror module can be understood as a mirror module within the chip that tests the DUT mirror module. When it is conducting, it mirrors the bias current, or replicates it. Furthermore, the test mirror module ensures that the mirrored current is proportional to the bias current. Therefore, when the test mirror module is conducting, mirroring the bias current will cause a change in the chip's total current.

[0030] The path control module is connected to the test mirror module. When the control signal is at the first level, the test mirror module is disconnected, preventing it from mirroring the bias current. No current flows through the test mirror module, meaning there is no mirrored current, thus preventing the chip from generating a first total chip current. When the control signal is at the second level, the path control module turns the test mirror module on, allowing it to mirror the bias current and generate a mirrored current, changing the chip's total current and generating a second total chip current.

[0031] The detection and processing module can obtain the chip's total current by connecting to the chip's power supply pins. Therefore, by detecting the total current of the first and second chips, the module can determine the changes in the total chip current when the test mirror module is switched on and off. The difference between the total current of the second and first chips allows us to determine the current after the test mirror module mirrors the bias current. Furthermore, since the current mirrored by the test mirror module has a mirror-ratio relationship with the bias current, the bias current can be determined.

[0032] Therefore, this application provides a test circuit for the internal bias current of a chip. By detecting the total current of the first chip and the total current of the second chip when the chip power supply is turned off and on respectively using a detection processing module, the bias current can be obtained, thus realizing the test of the internal bias current of the chip. Therefore, this application provides a test circuit for the internal bias current of a chip. By detecting the total current of the chip at the chip power supply pin using a detection processing module, the internal bias current of the chip can be tested without adding additional dedicated external pins for testing, reducing the layout area and solving the problem of increasing the chip's external pins and layout area required in traditional technologies for testing the internal bias current of a chip. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or exemplary technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This application provides a schematic diagram of the connection structure of the test current mirror module, test mirror module, path control module, and detection processing module for the test circuit of the chip internal bias current in some embodiments.

[0035] Figure 2 The diagram shows the connection structure of the current mirror module, test mirror module, path control module, detection and processing module, and current source of the test circuit for the internal bias current of the chip in some embodiments provided in this application.

[0036] Figure 3 The diagram shows the specific circuit connection structure of the test circuit for the internal bias current of the chip in some embodiments provided in this application. Detailed Implementation

[0037] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0038] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0039] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0040] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0041] Please see Figure 1 This application provides a test circuit for the internal bias current of a chip. The chip includes a current-under-test (UUT) mirror module 10 for generating a bias current. The test circuit for the internal bias current of the chip includes the UUT mirror module 10, a test mirror module 20, a path control module 30, and a detection and processing module 40. The UUT mirror module 10, the test mirror module 20, and the path control module 30 are all disposed inside the chip. The UUT mirror module 10 is used to generate the internal bias current I1 of the chip. The test mirror module 20 is connected to the UUT mirror module 10 and is used to mirror the bias current I1 when the test mirror module 20 is turned on, so as to adjust the total current of the chip.

[0042] The path control module 30 is connected to the test mirror module 20 and is used to control the test mirror module 20 to disconnect when the control signal is at the first level. The path control module 30 is also used to control the test mirror module 20 to conduct when the control signal is at the second level. The detection processing module 40 is connected to the chip power supply VDD and is used to detect the total current of the first chip when the test mirror module 20 is disconnected and the total current of the second chip when it is conducted, and to determine the bias current I1 based on the total current of the second chip and the total current of the first chip.

[0043] In this embodiment, the current under test mirror module 10 can be understood as a current mirror module within the chip that generates a bias current I1 within the chip. The test mirror module 20 can be understood as a mirror module within the chip that tests the current under test mirror module 10. When it is conducting, it mirrors the bias current I1, or it can be understood as replicating the bias current I1. Furthermore, the test mirror module 20 can make the mirrored current, such as... Figure 1 The current I3 can be proportional to the bias current I1. Therefore, when the test mirror module 20 is turned on, the bias current I1 is mirrored by the test mirror module 20, which will cause the total current of the chip to change.

[0044] The path control module 30 is connected to the test mirror module 20. When the control signal is at the first level, the test mirror module 20 is disconnected, preventing it from mirroring the bias current I1. No current flows through the test mirror module 20, meaning there is no current I3 mirrored from the bias current I1, resulting in a first total chip current. When the control signal is at the second level, the path control module 30 turns the test mirror module 20 on, allowing it to mirror the bias current I1, creating a current I3 mirrored from I1. This changes the total chip current, resulting in a second total chip current.

[0045] The detection and processing module 40 can obtain the total current of the chip by connecting to the chip's power supply VDD pin. Therefore, by detecting the total current of the first chip and the total current of the second chip, the detection and processing module 40 can determine the change in the total current of the chip when the test mirror module 20 is turned off and on. The difference between the total current of the second chip and the total current of the first chip can be used to determine the current I3 after the test mirror module 20 mirrors the bias current I1. Furthermore, since the current I3 after the test mirror module 20 mirrors the bias current I1 has a mirror ratio relationship with the bias current I1, the bias current I1 can be determined.

[0046] Therefore, the chip internal bias current test circuit provided in this application obtains the bias current I1 by detecting the total current of the first chip and the total current of the second chip when the chip power supply VDD is turned off and on, respectively, through the detection and processing module 40. This enables the testing of the chip's internal bias current I1. Thus, the chip internal bias current test circuit provided in this application can test the chip's internal bias current simply by detecting the total current at the chip power supply VDD pin through the detection and processing module 40, without requiring additional dedicated external pins for testing. This reduces the layout area and solves the problem of increasing the chip's external pins and layout area required for testing the chip's internal bias current in traditional technologies.

[0047] In some embodiments, the detection processing module 40 is located externally to the chip and connected to the chip power supply VDD. The detection processing module 40 can be an external testing instrument, such as a multimeter or power analyzer. The total chip current of the chip power supply can be detected through the detection processing module 40.

[0048] In some embodiments, the detection processing module 40 can also detect chip power consumption, where chip power consumption PDD = VDD * IDD. When the test mirror module 20 is off and on, the total current of the first chip and the total current of the second chip are different, and thus the corresponding chip power consumption will also be different. Therefore, the chip internal bias current test circuit provided in this application can also detect the chip power consumption through the detection processing module 40 to test the chip internal bias current.

[0049] Please see Figure 2 In some embodiments, the test circuit for the internal bias current of the chip further includes a current source 50, which is disposed inside the chip. The input terminal of the current source 50 is connected to the chip power supply VDD, and the output terminal of the current source 50 is connected to the current-under-test mirror module 10.

[0050] In this embodiment, the current source 50 is connected between the chip power supply VDD and the current mirror module 10 under test, which can provide the current mirror module 10 under test with a precise and stable reference current, ensuring the stable operation of the current mirror module 10 under test, and causing the current mirror module 10 under test to generate a bias current I1.

[0051] Please see Figure 3In some embodiments, the current under test (DUT) mirror module 10 includes a main bias transistor 110 and a current under test (DUT) mirror transistor 120. The gate terminal of the main bias transistor 110 is connected to its drain terminal. The drain terminal of the main bias transistor 110 is connected to the chip power supply to generate a bias current I1. The source terminal of the main bias transistor 110 is grounded. The gate terminal of the DUT mirror transistor 120 is connected to the gate terminal of the main bias transistor 110, the source terminal of the DUT mirror transistor 120 is grounded, and the drain terminal of the DUT mirror transistor 120 is used to acquire the transistor bias voltage VBIAS.

[0052] In this embodiment, the source terminal of the main bias transistor 110 is grounded. The gate and drain terminals of the main bias transistor 110 are connected, and then connected to the gate terminal of the image transistor 120 under test. The source terminal of the image transistor 120 under test is grounded, forming a current mirror circuit structure. The bias current I1 under test flows through the drain terminal of the main bias transistor 110. The drain terminal of the image transistor 120 under test obtains the transistor bias voltage VBIAS. The transistor bias voltage VBIAS allows the image transistor 120 under test to enter the saturation region, mirroring the bias current I1 and correspondingly forming a second mirror current I2.

[0053] In one embodiment, the number of main bias transistors 110 is equal to the number of transistors in the image transistor under test 120, i.e. Figure 3 The M=1 of the main bias transistor 110 and the M=1 of the image transistor 120 under test. Therefore, the second image current I2 flowing from the drain terminal of the image transistor 120 under test is equal to the bias current I1.

[0054] In some embodiments, the test circuit for the internal bias current of the chip further includes a current source 50, which is disposed inside the chip. The input terminal of the current source 50 is connected to the chip power supply VDD, and the output terminal of the current source 50 is connected to the drain terminal of the main bias transistor 110.

[0055] In this embodiment, the current source 50 is connected between the chip power supply VDD and the drain terminal of the main bias transistor 110, which can provide a precise and stable reference current to the main bias transistor 110 so that the main bias transistor 110 generates a bias current I1.

[0056] In some embodiments, the test mirror module 20 includes at least one test mirror transistor 210. The gate terminal of the test mirror transistor 210 is connected to the gate terminal of the main bias transistor 110 and the gate terminal of the test mirror transistor 120. The source terminal of the test mirror transistor 210 is grounded. The drain terminal of the test mirror transistor 210 is connected to the path control module 30.

[0057] In this embodiment, the gate terminal of the test mirror transistor 210 is connected to the gate terminal of the main bias transistor 110 and the gate terminal of the test mirror transistor 120. The source terminal of the test mirror transistor 210 is grounded. The drain terminal of the test mirror transistor 210 is connected to the path control module 30. When the path control module 30 controls the circuit to be off, no current flows, and the current I3 after the test mirror module 20 mirrors the bias current I1, i.e., the third mirror current I3, will not be formed, which corresponds to the total current of the first chip, or the power consumption of the first chip. When the path control module 30 controls the circuit to be on, current flows, forming the third mirror current I3, which corresponds to the total current of the second chip, or the power consumption of the second chip. The third mirror current I3 flowing through the test mirror transistor 210 is N*I1. Therefore, the total current of the second chip when the path control module 30 controls the circuit to be on will be more than the total current of the first chip when the path control module 30 controls the circuit to be off by the third mirror current I3. This can also be understood as the power consumption of the second chip when the path control module 30 controls it to be on being I3*VDD more than the power consumption of the second chip when the path control module 30 controls it to be off. By the difference between the total current of the second chip and the total current of the first chip, the third mirror current I3 can be obtained, and thus the bias current I1 to be measured can be obtained.

[0058] In some embodiments, such as Figure 3 As shown, the M=N of the test mirror transistor 210, where N can be a positive integer such as 1, 2, 3, 4, etc. N can also be understood as the mirror ratio between the test mirror transistor 210 and the main bias transistor 110. The third mirror current I3=N*I1. The N test mirror transistors 210 are connected in parallel, and the circuit structure is the same.

[0059] In some embodiments, the path control module 30 includes an inverter 310, a first switch 320, a second switch 330, and a path biasing transistor 340. The input terminal of the inverter 310 is used to acquire the control signal OE and invert the control signal OE to obtain the inverted control signal OEN. The gate terminal of the first switch 320 is connected to the input terminal of the inverter 310 and is used to acquire the control signal OE. The drain terminal of the first switch 320 is used to acquire the transistor bias voltage VBIAS.

[0060] The gate of the second switch 330 is connected to the output of the inverter 310 to obtain the inversion control signal OEN. The drain of the second switch 330 is used to obtain the transistor bias voltage VBIAS. The gate of the path bias transistor 340 is connected to the source of the first switch 320 and the source of the second switch 330. The drain of the path bias transistor 340 is connected to the chip power supply VDD. The source of the path bias transistor 340 is connected to the drain of the test mirror transistor 210.

[0061] In this embodiment, the control signal OE at the input terminal of inverter 310 is connected to the gate terminal of the first switching transistor 320. The inverting control signal OEN at the output terminal of inverter 310 is connected to the gate terminal of the second switching transistor 330. The source terminal of the first switching transistor 320 is connected to the gate terminal of the path bias transistor 340, and the drain terminal of the first switching transistor 320 is connected to the transistor bias voltage VBIAS. The source terminal of the second switching transistor 330 is connected to the gate terminal of the path bias transistor 340, and the drain terminal of the second switching transistor 330 is connected to the transistor bias voltage VBIAS. The control signal OE and the inverting control signal OEN can control the switching on and off of the transmission circuit composed of the first switching transistor 320, the second switching transistor 330, and the third switching transistor 350.

[0062] In some embodiments, the path control module 30 further includes a third switch 350. The gate terminal of the third switch 350 is connected to the output terminal of the inverter 310 to obtain the inversion control signal OEN. The drain terminal of the third switch 350 is connected to the gate terminal of the path bias transistor 340, and the source terminal of the third switch 350 is grounded.

[0063] In this embodiment, the inverting control signal OEN at the output of inverter 310 is connected to the gate of the third switch 350. The control signal OE and the inverting control signal OEN can control the on / off state of the transmission circuit composed of the first switch 320, the second switch 330, and the third switch 350. When the control signal OE is high and the inverting control signal OEN is low, the transmission transistor bias voltage VBIAS is applied to the gate of the path bias transistor 340, causing the path bias transistor 340 to conduct. Subsequently, the drain of the path bias transistor 340 is connected to the chip power supply VDD, and the connection circuit between the path bias transistor 340 and the test mirror transistor 210 is activated, generating a third mirror current I3.

[0064] When the control signal OE is low and the inverting control signal OEN is high, the gate of the path bias transistor 340 is pulled down to ground, causing the path bias transistor 340 to disconnect. Consequently, the connection circuit between the path bias transistor 340 and the test mirror transistor 210 is disconnected, and it does not conduct, thus preventing the generation of the third mirror current I3.

[0065] The path control module 30 differs from traditional transmission gates. When the path control module 30 is turned on, it transmits the bias voltage VBIAS to the gate terminal of the path bias transistor 340, thus turning the path bias transistor 340 on. When the path control module 30 is not turned on, it does not leave the gate terminal of the path bias transistor 340 floating in an indeterminate state, but instead pulls the gate terminal of the path bias transistor 340 down to ground, thus turning it off.

[0066] In some embodiments, the path control module 30 further includes a non-volatile memory 360. The non-volatile memory 360 is connected to the input of the inverter 310 and is used to output a control signal OE to the input of the inverter 310.

[0067] In this embodiment, the non-volatile memory 360 can also be represented as an EEPROM. The EEPROM outputs a control signal OE. After passing through the inverter 310, the control signal OE forms an inverted control signal OEN. The path control module 30 consists of a transmission circuit composed of the non-volatile memory 360, the inverter 310, the first switch 320, the second switch 330, and the third switch 350, as well as a path bias transistor 340. The path control module 30 can control the current flow of the test mirror transistor 210. When the transmission circuit is on, the third mirror current I3 flows through the test mirror transistor 210. When the transmission circuit is off, no current flows through the test mirror transistor 210.

[0068] In some embodiments, when the internal bias current I1 of the chip is tested by the chip internal bias current test circuit provided in this application, the current characteristics are replicated by the current mirror (which can also be understood as the mirror current characteristics). When the number of the main bias transistor 110 is equal to the number of the test mirror transistor 120 (i.e., M=1) and the number of the test mirror transistor 210 is M=N, the second mirror current I2 is equal to the bias current I1, and the third mirror current I3 = N*I1.

[0069] Furthermore, utilizing the EEPROM programming function, when the chip is programmed and configured with the control signal OE low and the inverting control signal OEN high, the measured total current of the first chip is IDD1 = IDD. When the chip is programmed and configured with the control signal OE high and the inverting control signal OEN low, the measured total current of the second chip is IDD2 = IDD + I3.

[0070] By subtracting the total current of the second chip from the total current of the first chip under two different programming biases, the measured bias current I1 can be obtained.

[0071] I1=(IDD2-IDD1) / N=[(IDD+I3)-IDD] / N=[(IDD+N*I1)-IDD] / N.

[0072] Wherein, IDD1 is the measured total current of the first chip when the chip programming configuration control signal OE is low, and IDD2 is the measured total current of the second chip when the chip programming configuration control signal OE is high. Therefore, IDD1 and IDD2 are known quantities, I1 is the bias current of the main bias transistor 110 under test, I2 is the mirror current of the image transistor 120 under test, I3 is the mirror current of the test image transistor 210, and N is the number of test image transistors 210.

[0073] Therefore, by utilizing the chip internal bias current test circuit provided in this application, which combines EEPROM programming functionality and current mirror replication features, it is not necessary to bring out an additional port specifically for testing the chip's internal bias current. Instead, the magnitude of the bias current I1 of the main bias transistor 110 under test is indirectly measured through the total current difference of the chip. Thus, the chip internal bias current test circuit provided in this application eliminates the need for additional chip test pins, saving layout area and reducing chip package pins.

[0074] In some embodiments, the main bias transistor 110, the under-test mirror transistor 120, the test mirror transistor 210, the first switch transistor 320, the path bias transistor 340, and the third switch transistor 350 are N-type field-effect transistors.

[0075] In some embodiments, the second switch 330 is a P-type field-effect transistor.

[0076] The types of the main bias transistor 110, the under test mirror transistor 120, the test mirror transistor 210, the first switch transistor 320, the second switch transistor 330, the path bias transistor 340, and the third switch transistor 350 can also be adjusted according to the actual application scenario.

[0077] This application provides a chip, including a test current mirror module 10, a test mirror module 20, a path control module 30, and a current source 50 of the chip internal bias current test circuit of any of the above embodiments.

[0078] In this embodiment, the chip internal bias current test circuit can be applied to semiconductor integrated circuit chips to test the chip internal bias current, thereby understanding the chip's internal workings and helping to troubleshoot chip malfunctions.

[0079] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application.

[0080] In the above embodiments, the descriptions of each embodiment have their own emphasis. Parts not described in detail or in a particular embodiment can be referred to in the relevant descriptions of other embodiments. Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0081] The division into modules or units is merely a logical functional division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0082] The units described as separate components may or may not be physically separate. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs. Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated units described above can be implemented in hardware or as software functional units.

[0083] The embodiments described above are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A test circuit for the internal bias current of a chip, characterized in that, The chip includes a current-under-test mirror module (10) for generating a bias current, and the test circuit includes: The test mirror module (20) is located inside the chip. The test mirror module (20) is connected to the current under test mirror module (10) and is used to mirror the bias current when the test mirror module (20) is turned on, so as to adjust the total current of the chip. The path control module (30) is located inside the chip. The path control module (30) is connected to the test mirror module (20) and is used to control the test mirror module (20) to disconnect when the control signal is at the first level. The path control module (30) is also used to control the test mirror module (20) to turn on when the control signal is at the second level. The detection processing module (40) is connected to the chip power supply and is used to detect the total current of the first chip when the test mirror module (20) is disconnected and the total current of the second chip when it is turned on, and to determine the bias current based on the total current of the second chip and the total current of the first chip.

2. The test circuit for the internal bias current of the chip as described in claim 1, characterized in that, The measured current mirror module (10) includes: A main bias transistor (110) is provided, wherein the gate terminal of the main bias transistor (110) is connected to the drain terminal of the main bias transistor (110), the source terminal of the main bias transistor (110) is grounded, and the drain terminal of the main bias transistor (110) is connected to the chip power supply to generate the bias current. The image transistor under test (120) has its gate terminal connected to the gate terminal of the main bias transistor (110), its source terminal grounded, and its drain terminal used to obtain the transistor bias voltage.

3. The test circuit for the internal bias current of the chip as described in claim 2, characterized in that, The test circuit for the internal bias current of the chip also includes: A current source (50) is located inside the chip. The input terminal of the current source (50) is connected to the power supply of the chip, and the output terminal of the current source (50) is connected to the drain terminal of the main bias transistor (110). The current source (50) is used to provide a reference current to the main bias transistor (110) so that the main bias transistor (110) generates the bias current.

4. The test circuit for the internal bias current of the chip as described in claim 2, characterized in that, The test image module (20) includes: At least one test mirror transistor (210) is provided, the gate terminal of which is connected to the gate terminal of the main bias transistor (110) and the gate terminal of the test mirror transistor (120), the source terminal of which is grounded, and the drain terminal of which is connected to the path control module (30).

5. The test circuit for the internal bias current of the chip as described in claim 4, characterized in that, The pathway control module (30) includes: An inverter (310) is used to acquire the control signal and invert the control signal to obtain an inverted control signal. The first switching transistor (320) has its gate terminal connected to the input terminal of the inverter (310) to obtain the control signal, and its drain terminal is used to obtain the transistor bias voltage. The second switch (330) has its gate connected to the output of the inverter (310) to obtain the inverting control signal, and its drain is used to obtain the bias voltage of the switch. A path bias transistor (340) is provided, the gate of which is connected to the source of the first switch transistor (320) and the source of the second switch transistor (330), the drain of which is connected to the chip power supply, and the source of which is connected to the drain of the test mirror transistor (210).

6. The test circuit for the internal bias current of the chip as described in claim 5, characterized in that, The pathway control module (30) also includes: The third switch (350) has its gate connected to the output of the inverter (310) to obtain the inverting control signal. The drain of the third switch (350) is connected to the gate of the path bias transistor (340), and the source of the third switch (350) is grounded.

7. The test circuit for the internal bias current of the chip as described in claim 5, characterized in that, The pathway control module (30) also includes: A non-volatile memory (360) is connected to the input terminal of the inverter (310) and is used to output the control signal to the input terminal of the inverter (310).

8. The test circuit for the internal bias current of the chip as described in claim 6, characterized in that, The main bias transistor (110), the under-test mirror transistor (120), the test mirror transistor (210), the first switch transistor (320), the path bias transistor (340), and the third switch transistor (350) are N-type field-effect transistors.

9. The test circuit for the internal bias current of the chip as described in claim 6, characterized in that, The second switch (330) is a P-type field-effect transistor.

10. A chip, characterized in that, The test circuit includes a test current mirror module (10), a test mirror module (20), a path control module (30), and a current source (50) for the test circuit of the internal bias current of the chip as described in any one of claims 1 to 9.

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