Edge computing device control circuit and edge computing device

Abstract

The application relates to the field of communication and discloses an edge computing device control circuit and an edge computing device. The edge computing device control circuit comprises a first processor and a second processor, a micro control unit connected with the first processor and the second processor, and a switching device connected with the micro control unit. The switching device is connected with a timing pin of the micro control unit, the first processor is connected with a first control pin of the micro control unit, and the second processor is connected with a second control pin of the micro control unit. The timing pin is used for recording the closing duration of the switching device, the micro control unit is used for controlling the first processor through the first control pin when the closing duration is less than a set duration and controlling the second processor through the second control pin when the closing duration is greater than or equal to the set duration. The application solves the technical problems of increased difficulty in design and maintenance and high cost of the edge computing device in the prior art.

Description

Technical Field

[0001] This application relates to the field of communications, specifically to an edge computing device control circuit and an edge computing device. Background Technology

[0002] In today's rapidly evolving digital age, edge computing, with its unique advantages such as low latency, high bandwidth utilization, and data privacy protection, has been widely adopted across various fields, including industrial manufacturing, intelligent transportation, smart homes, and healthcare. As a crucial component of the edge computing architecture, edge computing devices are responsible for collecting, processing, and analyzing data close to the data source, significantly reducing the computing burden on the cloud and substantially improving system response speed and overall performance.

[0003] Currently, edge computing devices on the market typically use a method where each CPU (Central Processing Unit) is individually controlled by a button, as the CPU is the core component of a computer or other electronic device responsible for executing instructions and processing data. In the early stages of edge computing development, this control method offered a degree of intuitiveness and operability. Operators could perform basic operations such as starting, stopping, and restarting specific CPUs by simply pressing the corresponding button. In some small-scale and relatively simple edge computing scenarios, such as simple environmental monitoring nodes where only occasional maintenance operations on the CPU are required, this button control method was sufficient.

[0004] However, from a system scalability perspective, when edge computing devices need to be upgraded by adding new CPUs to improve computing power, the individual button control for each CPU makes wiring and control logic extremely complex, increasing the difficulty of system design and maintenance. Furthermore, the additional buttons also increase the production cost of edge computing devices. Utility Model Content

[0005] In view of this, it is necessary to provide an edge computing device control circuit and an edge computing device to solve the technical problems of increased design and maintenance difficulty and high cost of existing edge computing devices.

[0006] To address the aforementioned technical problems, in a first aspect, this application provides an edge computing device control circuit, comprising: a first processor and a second processor, a microcontroller unit respectively connected to the first processor and the second processor, and a switching device connected to the microcontroller unit;

[0007] The switching device is connected to the timing pin of the microcontroller unit, the first processor is connected to the first control pin of the microcontroller unit, and the second processor is connected to the second control pin of the microcontroller unit.

[0008] The timing pin is used to record the closing duration of the switching device. The microcontroller is used to control the first processor via the first control pin when the closing duration is less than the set duration, and to control the second processor via the second control pin when the closing duration is greater than or equal to the set duration.

[0009] In one possible embodiment, one end of the switching device is connected to the timing pin and the other end is grounded, and the timing pin is grounded when the switching device is closed.

[0010] When the timing pin is grounded, it is in a low-level state. The first control pin is in a low-level state when the timing pin is in a low-level state for less than the set duration, and in a high-level state when the timing pin is in a low-level state for more than or equal to the set duration. The second control pin is in a high-level state when the timing pin is in a low-level state for less than the set duration, and in a low-level state when the timing pin is in a low-level state for more than or equal to the set duration.

[0011] In one possible embodiment, the microcontroller further includes a status pin for receiving a status signal from the edge computing device. The status pin is in a high-level state when the status signal is received and in a low-level state when the status signal is not received.

[0012] The first control pin includes a first type of first control pin and a second type of first control pin, and the second control pin includes a second type of second control pin and a second type of second control pin;

[0013] The first type of control pin is in a low-level state when the timing pin is kept in a low-level state for less than the set duration and the status pin is in a high-level state, and in a high-level state when the timing pin is kept in a low-level state for more than or equal to the set duration and the status pin is in a high-level state.

[0014] The second type of first control pin is in a low-level state when the timing pin is kept in a low-level state for less than the set duration and the status pin is in a low-level state, and in a high-level state when the timing pin is kept in a low-level state for more than or equal to the set duration and the status pin is in a low-level state.

[0015] The first type of second control pin is in a high-level state when the timing pin is kept in a low-level state for less than the set duration and the status pin is in a high-level state, and in a low-level state when the timing pin is kept in a low-level state for more than or equal to the set duration and the status pin is in a high-level state;

[0016] The second type of control pin is in a high-level state when the timing pin is kept at a low level for less than the set duration and the status pin is in a low-level state, and in a low-level state when the timing pin is kept at a low level for more than or equal to the set duration and the status pin is in a low-level state.

[0017] In one possible embodiment, the first processor includes a first I / O pin, the second processor includes a second I / O pin, the first I / O pin is connected to the first type of first control pin, and the second I / O pin is connected to the second type of second control pin;

[0018] When the first control pin is in a low voltage state, the first I / O pin is in a low voltage state, and the first processor is restored to factory settings.

[0019] When the second control pin is in a low voltage state, the second IO pin is also in a low voltage state, and the second processor is restored to factory settings.

[0020] In one possible embodiment, a programming control chip is also included. The programming control chip includes a first programming control pin, a second programming control pin, a first selection pin, and a second selection pin. The first processor includes a first programming switch pin, and the second processor includes a second programming switch pin. The first programming control pin is connected to the first programming switch pin, and the second programming control pin is connected to the second programming switch pin. The first selection pin and the second selection pin are connected to the two types of first control pins.

[0021] When the first control pin of the second type is in a high-level state, the second selection pin is in a high-level state, the second programming control pin is in a high-level state, and the second programming switch pin is in a high-level state.

[0022] When the first control pin of the second type is in a low-level state, the first selection pin is in a high-level state, the first programming control pin is in a high-level state, and the first programming switch pin is in a high-level state.

[0023] In one possible embodiment, a programming data download chip is also included. The programming data download chip includes a first programming pin, a second programming pin, and a programming selection pin. The first processor includes a first download pin, and the second processor includes a second download pin. The first programming pin is connected to the first download pin, the second programming pin is connected to the second download pin, and the programming selection pin is connected to the second type of second control pin.

[0024] When the second type of control pin is in a high-level state, the programming selection pin is in a low-level state, the first programming pin is in a high-level state, the first download pin is in a high-level state, and the first processor performs programming.

[0025] When the second control pin is in a low-level state, the programming selection pin is in a high-level state, the second programming pin is in a high-level state, the second download pin is in a high-level state, and the second processor performs programming.

[0026] In one possible embodiment, a transistor is also included, wherein the programming select pin is connected to the collector of the transistor, the second control pin is connected to the base of the transistor, the emitter of the transistor is grounded, and the programming select pin is grounded.

[0027] In one possible embodiment, a programming interface circuit is also included, wherein the programming data download chip includes programming interface pins, and the programming interface pins are connected to the programming interface circuit.

[0028] Secondly, this application provides an edge computing device, comprising:

[0029] As described above, the edge computing device control circuit and control buttons are connected to the switching device.

[0030] In one possible embodiment, the edge computing device control circuit is the aforementioned edge computing device control circuit, and the edge computing device further includes a programming interface, which is connected to the programming interface circuit.

[0031] The beneficial effects of this application are:

[0032] Compared with related technologies, the edge computing device control circuit provided in this application connects the timing pin of the microcontroller unit to the switching device, and simultaneously connects the first control pin of the microcontroller unit to the first processor and the second control pin of the microcontroller unit to the second processor. The timing pin can record the closing duration of the switching device, and based on the relationship between the closing duration and the set duration, the first processor and the second processor are controlled respectively through the first and second control pins, thereby achieving the purpose of controlling multiple processors simultaneously with a single switching device. If more processors are subsequently added, it is only necessary to connect the added processors to the microcontroller unit, without the need for additional switching devices, thus solving the technical problem of increased system design and maintenance difficulty in the prior art. In addition, controlling multiple processors simultaneously with a single switching device only requires setting a corresponding physical button for a single switching device, eliminating the need for multiple buttons and reducing the production cost of the edge computing device. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a circuit structure diagram of an edge computing device control circuit provided in one embodiment of this application;

[0035] Figure 2 A circuit structure diagram of an edge computing device control circuit provided in another embodiment of this application;

[0036] Figure 3 This is a schematic diagram of the structure of an edge computing device provided in one embodiment of this application;

[0037] Figure 4 This is a schematic diagram of the structure of an edge computing device provided in another embodiment of this application. Detailed Implementation

[0038] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0039] In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more. "And / or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0040] The terms "first," "second," etc., used in the embodiments of this application are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a technical feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature.

[0041] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0042] This application provides an edge computing device control circuit and an edge computing device, which will be described below.

[0043] Please refer to Figure 1 One embodiment of this application provides a control circuit for an edge computing device, including: a first processor 100, a second processor 200, a microcontroller unit 300, and a switching device 400. The microcontroller unit 300 includes a first control pin PA1, a second control pin PA2, and a timing pin PA3. The timing pin PA3 is connected to the switching device 400, the first control pin PA1 is connected to the first I / O pin IO1 of the first processor 100, and the second control pin PA2 is connected to the second I / O pin IO2 of the second processor 200.

[0044] The timing pin PA3 is used to record the closing duration of the switching device 400. The microcontroller unit 300 is used to control the first processor 100 via the first control pin PA1 when the closing duration is less than the set duration, and to control the second processor 200 via the second control pin PA2 when the closing duration is greater than or equal to the set duration.

[0045] For details, please continue to refer to... Figure 1One end of the switching device 400 is connected to the timing pin PA3, and the other end is grounded. When the switching device 400 is closed, the timing pin PA3 is grounded through the switching device 400, and is in a low-level state. The microcontroller unit 300 can time the duration for which the timing pin PA3 remains in a low-level state. The first control pin PA1 is in a low-level state when the timing pin PA3 remains in a low-level state for less than a set duration, and in a high-level state when the timing pin PA3 remains in a low-level state for more than or equal to the set duration. The second control pin PA2 is in a high-level state when the timing pin PA3 remains in a low-level state for less than a set duration, and in a low-level state when the timing pin PA3 remains in a low-level state for more than or equal to the set duration. By switching the first control pin PA1 and the second control pin PA2 between high-level and low-level states, the control process of the first processor 100 and the second processor 200 is realized.

[0046] The set duration can be a pre-set fixed duration, which can be set according to different factors such as the model of the microcontroller 300 and the actual control requirements of the first processor 100 and the second processor 200. As a preferred embodiment, the set duration can be 10 seconds, 8 seconds, 5 seconds, 4 seconds, etc.

[0047] Compared with related technologies, the edge computing device control circuit provided in this embodiment connects the timing pin PA3 of the microcontroller 300 to the switching device 400, the first control pin PA1 of the microcontroller 300 to the first processor 100, and the second control pin PA2 of the microcontroller 300 to the second processor 200. The timing pin PA3 can record the closing duration of the switching device 400, and according to the relationship between the closing duration and the set duration, the first processor 100 and the second processor 200 are controlled by the first control pin PA1 and the second control pin PA2 respectively, thereby achieving the purpose of controlling multiple processors simultaneously by a single switching device 400. If more processors are added in the future, it is only necessary to connect the added processors to the microcontroller 300, without the need to set up additional switching devices 400, thus solving the technical problem of increased system design and maintenance difficulty in the prior art. In addition, by controlling multiple processors simultaneously by a single switching device 400, only a corresponding physical button needs to be set for the single switching device 400, without the need to set up multiple buttons, which can also reduce the production cost of the edge computing device.

[0048] Please refer to Figure 2Another embodiment of this application provides an edge computing device control circuit, which includes the first processor 100, second processor 200, microcontroller unit 300, and switching device 400 provided in the foregoing embodiments. The difference is that in this embodiment, the microcontroller unit 300 further includes a status pin VBAT, and the first control pin PA1 includes a first control pin PA4 and a second control pin PA5, and the second control pin PA2 includes a second control pin PA6 and a second control pin PA7. The status pin VBAT is used to access the status signal of the edge computing device; the status pin VBAT is high when a status signal is accessed and low when no status signal is accessed.

[0049] In a specific embodiment, a first control pin PA4 is in a low-level state when the timing pin PA3 remains low for less than a set duration and the status pin VBAT is high, and in a high-level state when the timing pin PA3 remains low for more than or equal to the set duration and the status pin VBAT is high; a second control pin PA6 is in a high-level state when the timing pin PA3 remains low for less than the set duration and the status pin VBAT is high, and in a low-level state when the timing pin PA3 remains low for more than or equal to the set duration and the status pin VBAT is high. By switching between high and low levels using the first control pin PA4 and the second control pin PA6, the first processor 100 and / or the second processor 200 can perform a certain function.

[0050] In a specific embodiment, the second type of first control pin PA5 is in a low-level state when the timing pin PA3 remains low for less than a set duration and the status pin VBAT is low, and in a high-level state when the timing pin PA3 remains low for more than or equal to the set duration and the status pin VBAT is low; the second type of second control pin PA7 is in a high-level state when the timing pin PA3 remains low for less than a set duration and the status pin VBAT is low, and in a low-level state when the timing pin PA3 remains low for more than or equal to the set duration and the status pin VBAT is low. By switching between high and low levels on the first type of first control pin PA5 and the second type of second control pin PA7, the first processor 100 and / or the second processor 200 can implement two types of functions.

[0051] It should be noted that by accessing the status signal of the edge computing device through the status pin VBAT, the first processor 100 and the second processor 200 can perform at least two different functions based on two control conditions: whether the status signal is received and the closing duration of the switch device 400. That is, only a single switch device 400 needs to be set to enable the first processor 100 and the second processor 200 to perform at least two different functions.

[0052] Please continue to refer to Figure 2 In the embodiments of this application, the first processor 100 includes a first IO pin IO1, and the second processor 200 includes a second IO pin IO2. The first IO pin IO1 is connected to a first control pin PA4, and the second IO pin IO2 is connected to a second control pin PA6. When the first control pin PA4 is in a low voltage state, the first IO pin IO1 is in a low voltage state, and the first processor 100 is restored to factory settings. When the second control pin PA6 is in a low voltage state, the second IO pin IO2 is in a low voltage state, and the second processor 200 is restored to factory settings.

[0053] Please continue to refer to Figure 2 In embodiments of this application, the edge computing device control circuit may further include: a programming control chip 500, a programming data download chip 600, and a programming interface circuit 700. The first processor 100 may further include a first programming switch pin DOWNLOAD1, and the second processor 200 may further include a second programming switch pin DOWNLOAD2.

[0054] In a specific embodiment, the programming control chip 500 includes a first programming control pin COM1, a second programming control pin COM2, a first selection pin IN1, and a second selection pin IN2. The first programming control pin COM1 is connected to the first programming switch pin DOWNLOAD1, the second programming control pin COM2 is connected to the second programming switch pin DOWNLOAD2, the first selection pin IN1 and the second selection pin IN2 are connected to the second type of first control pin PA5, and the first selection pin IN1 and the second selection pin IN2 are respectively connected to the timing pin PA3 and simultaneously connected to the switching device 400.

[0055] In a specific embodiment, the programming data download chip includes a first programming pin HSD1, a second programming pin HSD2, and a programming selection pin S. The first processor 100 includes a first download pin USB1, and the second processor 200 includes a second download pin USB2. The first programming pin is connected to the first download pin USB1, the second programming pin HSD2 is connected to the second download pin USB2, and the programming selection pin S is connected to the second type of second control pin PA7.

[0056] When the first control pin PA5 is at a high level, the second selection pin, the second programming control pin, and the second programming switch pin DOWNLOAD2 are all at a high level, and the second processor 200 starts the programming function. At the same time, when the second control pin PA7 is at a low level, the programming selection pin S is at a high level, the second programming pin HSD2 is at a high level, the second download pin USB2 is at a high level, and the second processor 200 performs programming.

[0057] When the first control pin PA5 is low, the first selection pin, the first programming control pin, and the first programming switch pin DOWNLOAD1 are all high, and the first processor 100 starts the programming function. Simultaneously, when the second control pin PA7 is high, the programming selection pin S is low, the first programming pin HSD1 is high, the first download pin USB1 is high, and the first processor 100 performs programming.

[0058] Please continue to refer to Figure 2 In this embodiment, the edge computing device control circuit may further include a transistor Q. The programming selection pin S is connected to the collector of the transistor, the second control pin PA7 is connected to the base of the transistor, the emitter of the transistor is grounded, and the programming selection pin S is grounded. When the second control pin PA7 is at a low level, the collector and emitter of the transistor are conducting, causing the programming selection pin S to be at a high level, the second programming pin HSD2 to be at a high level, the second download pin USB2 to be at a high level, and the second processor 200 to perform programming. Conversely, when the second control pin PA7 is at a high level, the collector and emitter of the transistor are not conducting, causing the programming selection pin S to be at a low level, the first programming pin HSD1 to be at a high level, the first download pin USB1 to be at a high level, and the first processor 100 to perform programming.

[0059] Please continue to refer to Figure 2 The data download chip also includes a programming interface pin D, which is connected to the programming interface circuit to receive programming data and transmit the programming data to the first processor 100 and the second processor 200 for programming.

[0060] On the other hand, please refer to Figure 3This application also provides an edge computing device, including an edge computing device control circuit and a control button 10 as provided in the previous embodiment. The control button 10 is connected to the switching device 400 in the previous embodiment. When the control button 10 is pressed, the switching device 400 is turned off, and when the control button 10 is not pressed, the switching device 400 is turned off.

[0061] For further details, please refer to Figure 4 The edge computing device may also include a programming interface 20, which is connected to the programming interface circuit 700 in the aforementioned embodiment. Specifically, the programming interface 20 may be a TYPE-C interface, used to connect to a programming data source, obtain programming data from the programming data source, and program the first processor 100 and the second processor 200.

[0062] The control circuit and edge computing device of the edge computing device provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A control circuit for an edge computing device, characterized in that, include: A first processor and a second processor, a microcontroller unit connected to the first processor and the second processor respectively, and a switching device connected to the microcontroller unit; The switching device is connected to the timing pin of the microcontroller unit, the first processor is connected to the first control pin of the microcontroller unit, and the second processor is connected to the second control pin of the microcontroller unit. The timing pin is used to record the closing duration of the switching device. The microcontroller is used to control the first processor via the first control pin when the closing duration is less than the set duration, and to control the second processor via the second control pin when the closing duration is greater than or equal to the set duration.

2. The edge computing device control circuit according to claim 1, characterized in that, One end of the switching device is connected to the timing pin and the other end is grounded. When the switching device is closed, the timing pin is grounded. When the timing pin is grounded, it is in a low-level state. The first control pin is in a low-level state when the timing pin is in a low-level state for less than the set duration, and in a high-level state when the timing pin is in a low-level state for more than or equal to the set duration. The second control pin is in a high-level state when the timing pin is in a low-level state for less than the set duration, and in a low-level state when the timing pin is in a low-level state for more than or equal to the set duration.

3. The edge computing device control circuit according to claim 2, characterized in that, The microcontroller unit further includes a status pin, which is used to receive the status signal of the edge computing device. The status pin is in a high-level state when the status signal is received and in a low-level state when the status signal is not received. The first control pin includes a first type of first control pin and a second type of first control pin, and the second control pin includes a second type of second control pin and a second type of second control pin; The first type of control pin is in a low-level state when the timing pin is kept in a low-level state for less than the set duration and the status pin is in a high-level state, and in a high-level state when the timing pin is kept in a low-level state for more than or equal to the set duration and the status pin is in a high-level state. The second type of first control pin is in a low-level state when the timing pin is kept in a low-level state for less than the set duration and the status pin is in a low-level state, and in a high-level state when the timing pin is kept in a low-level state for more than or equal to the set duration and the status pin is in a low-level state. The first type of second control pin is in a high-level state when the timing pin is kept in a low-level state for less than the set duration and the status pin is in a high-level state, and in a low-level state when the timing pin is kept in a low-level state for more than or equal to the set duration and the status pin is in a high-level state; The second type of control pin is in a high-level state when the timing pin is kept at a low level for less than the set duration and the status pin is in a low-level state, and in a low-level state when the timing pin is kept at a low level for more than or equal to the set duration and the status pin is in a low-level state.

4. The edge computing device control circuit according to claim 3, characterized in that, The first processor includes a first I / O pin, and the second processor includes a second I / O pin. The first I / O pin is connected to the first type of control pin, and the second I / O pin is connected to the second type of control pin. When the first control pin is in a low voltage state, the first I / O pin is in a low voltage state, and the first processor is restored to factory settings. When the second control pin is in a low voltage state, the second IO pin is also in a low voltage state, and the second processor is restored to factory settings.

5. The edge computing device control circuit according to claim 3, characterized in that, It also includes a programming control chip, which includes a first programming control pin, a second programming control pin, a first selection pin, and a second selection pin. The first processor includes a first programming switch pin, and the second processor includes a second programming switch pin. The first programming control pin is connected to the first programming switch pin, and the second programming control pin is connected to the second programming switch pin. The first selection pin and the second selection pin are connected to the two types of first control pins. When the first control pin of the second type is in a low level state, the second selection pin is in a high level state, the second programming control pin is in a high level state, and the second programming switch pin is in a high level state; When the first control pin of the second type is in a high-level state, the first selection pin is in a high-level state, the first programming control pin is in a high-level state, and the first programming switch pin is in a high-level state.

6. The edge computing device control circuit according to claim 5, characterized in that, It also includes a data download chip, which includes a first programming pin, a second programming pin, and a programming selection pin. The first processor includes a first download pin, and the second processor includes a second download pin. The first programming pin is connected to the first download pin, and the second programming pin is connected to the second download pin. The programming selection pin is connected to the second type of second control pin. When the second type of control pin is in a high-level state, the programming selection pin is in a low-level state, the first programming pin is in a high-level state, the first download pin is in a high-level state, and the first processor performs programming. When the second control pin is in a low-level state, the programming selection pin is in a high-level state, the second programming pin is in a high-level state, the second download pin is in a high-level state, and the second processor performs programming.

7. The edge computing device control circuit according to claim 6, characterized in that, It also includes a transistor, wherein the programming selection pin is connected to the collector of the transistor, the second type control pin is connected to the base of the transistor, the emitter of the transistor is grounded, and the programming selection pin is grounded.

8. The edge computing device control circuit according to claim 6, characterized in that, It also includes a programming interface circuit, wherein the programming data download chip includes programming interface pins, and the programming interface pins are connected to the programming interface circuit.

9. An edge computing device, characterized in that, include: The edge computing device control circuit and control button as described in any one of claims 1 to 8, wherein the control button is connected to the switching device.

10. The edge computing device according to claim 9, characterized in that, The edge computing device control circuit is the edge computing device control circuit of claim 8, and the edge computing device further includes a programming interface, which is connected to the programming interface circuit.

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