Method for manufacturing an optoelectronic semiconductor chip

Abstract

Method for manufacturing an optoelectronic semiconductor chip (10) comprising the steps: - Providing a silicon growth substrate (1), - Generating a III nitride buffer layer (3) on the growth substrate (1) by sputtering, and - Growth of a III nitride semiconductor layer sequence (2) with an active layer (2a) above the buffer layer (3), wherein - the buffer layer (3) is based on AlN and is applied directly to the growth substrate (1), - oxygen is added to the buffer layer (3), wherein a weight fraction of the oxygen is between 0.1% and 10% inclusive, and - wherein the oxygen content in the buffer layer (3) decreases strictly monotonically in a direction away from the growth substrate (1).

Description

[0001] A method for manufacturing an optoelectronic semiconductor chip is described.

[0002] In the publication Dadgar, A. [et al.]: Thick, crack-free blue light-emitting diodes on Si (111) using low-temperature AlN interlayers and in situ SixNy masking. In: Applied physics letters, Vol. 80, 2002, No. 20, pp. 3670-3672, a method for producing blue light-emitting diodes on silicon is described.

[0003] The publication DE 100 34 263 B4 describes a method for producing a quasisubstrate.

[0004] The publication DE 10 2006 008 929 A1 describes a nitride semiconductor device and a method for its manufacture.

[0005] The publication DE 601 21 768 T2 relates to a process for manufacturing a semiconductor device with a nitride composition of group III.

[0006] Nitride semiconductor structures are described in the publication US 2008 / 0 220 555 A1.

[0007] Publication US 2009 / 0 142 870 A1 describes a manufacturing process for group III nitride light-emitting semiconductor devices.

[0008] Publication WO 2011 / 108422A1 describes a manufacturing process for a nitride semiconductor device.

[0009] Document US 5,741,724 A describes a method for growing gallium nitride on a spinel substrate.

[0010] One task to be solved is to specify a method for the efficient production of an optoelectronic semiconductor chip.

[0011] This problem is solved by a method according to claim 1.

[0012] According to at least one embodiment of the method, this includes the step of providing a growth substrate. The growth substrate is preferably a silicon substrate. A surface prepared for growth is preferably a Si-111 surface. The surface provided for growth can be particularly smooth and have a roughness of at most 10 nm. The thickness of the growth substrate is preferably at least 50 µm or at least 200 µm.

[0013] According to at least one embodiment of the method, this includes the step of generating a III nitride buffer layer on the growth substrate. The buffer layer is generated by sputtering. Thus, the buffer layer is not generated via a gas-phase epitaxy such as metal-organic vapor-phase epitaxy (MOVPE).

[0014] According to at least one embodiment of the method, a III nitride semiconductor layer sequence with an active layer is grown above the buffer layer. During operation of the semiconductor chip, the active layer of the semiconductor layer sequence is configured to generate electromagnetic radiation, particularly in the ultraviolet or visible spectral range. Specifically, the wavelength of the generated radiation is between 430 nm and 680 nm, inclusive. The active layer preferably comprises one or more pn junctions or one or more quantum well structures.

[0015] The semiconductor material is preferably a nitride compound semiconductor material such as Al n In 1-n-m Ga mN with 0 ≤ n ≤ 1, 0 ≤ m ≤ 1 and n + m ≤ 1. The semiconductor layer sequence may contain dopants and additional components. For the sake of simplicity, however, only the essential components of the crystal lattice of the semiconductor layer sequence, namely Al, Ga, In and N, are specified, even though these may be partially replaced and / or supplemented by small amounts of other substances.

[0016] According to at least one embodiment of the method, the following applies: 0 ≤ n ≤ 0.2 and / or 0.35 ≤ m ≤ 0.95 and / or 0 < 1 nm ≤ 0.5. The specified value ranges for n and m preferably apply to all sublayers of the semiconductor layer sequence, excluding dopants. However, it is possible that the semiconductor layer sequence has one or more intermediate layers for which the specified values ​​for n and m deviate, and instead, 0.75 ≤ n ≤ 1 or 0.80 ≤ n ≤ 1 applies.

[0017] In at least one embodiment of the method, it is configured for the production of an optoelectronic semiconductor chip, in particular a light-emitting diode. The method comprises at least the following steps, preferably in the order shown: - Providing a silicon growth substrate, - Creating a III nitride buffer layer on the growth substrate by sputtering, and - Growth of a III nitride semiconductor layer sequence with an active layer on or above the buffer layer.

[0018] In contrast to MOVPE, sputtering allows for the relatively cost-effective production of thick films at relatively high growth rates. For example, films up to 1 µm thick, such as those made of AlN, can be deposited within a few minutes.

[0019] Furthermore, the sputtering system can be gallium-free. Gallium is typically present as an impurity in MOVPE epitaxial systems because gallium-containing layers are required, especially for LEDs emitting in the blue spectral range. However, gallium impurities can cause meltback in combination with silicon substrates. Meltback refers to a brownish, relatively soft compound of gallium and silicon. The gallium dissolves silicon from the growth substrate, resulting in blooms and holes on the surface of the silicon substrate intended for growth. This can lead to poorer growth results.

[0020] Furthermore, generating the buffer layer by sputtering can shorten and / or simplify the subsequent MOVPE process. In particular, it is possible to dispense with a nucleation layer directly on the substrate and to apply the buffer layer directly to the growth substrate.

[0021] Furthermore, sputtering the buffer layer allows for a reduction in the use of aluminum in the MOVPE process for generating the semiconductor layer sequence. Due to the high temperatures in the MOVPE process, graphite holders are typically used as substrate supports. In MOVPE, the graphite holder can be coated with a thin, whitish layer of aluminum and / or gallium, which alters the thermal radiation and heating behavior of the graphite holder. By generating the buffer layer via sputtering outside of a gas-phase epitaxy reactor, the aluminum coating on the graphite holder is significantly reduced, and parameters for the MOVPE process are easier to adjust.

[0022] According to at least one embodiment of the method, the buffer layer is deposited in multiple layers. For example, a first sublayer of the buffer layer, closest to the growth substrate, is formed by a thin aluminum layer. The thickness of this aluminum layer is, for example, one, two, or three atomic monolayers. Preferably, this aluminum layer is free or substantially free of nitrogen, so that the growth substrate does not come into direct contact with nitrogen at the growth surface.

[0023] According to at least one embodiment of the method, the buffer layer comprises a second sublayer of AlN, which is deposited more slowly than a subsequent third sublayer of AlN. The second and third sublayers preferably follow directly one another and, furthermore, preferably follow directly after the first sublayer. In particular, the buffer layer consists of three such sublayers.

[0024] According to at least one embodiment of the method, oxygen is added to the buffer layer during sputtering. The weight fraction of oxygen in the buffer layer, which is particularly based on aluminum nitride, is preferably at least 0.1%, at least 0.2%, or at least 0.5%. Furthermore, the weight fraction of oxygen in the buffer layer is preferably at most 10%, at most 5%, or at most 1.5%. The introduction of oxygen into buffer layers is also described in German patent application DE 100 34 263 B4, the disclosure of which is incorporated herein by reference.

[0025] According to at least one embodiment of the method, the oxygen content in the buffer layer decreases strictly monotonically in a direction away from the growth substrate. In particular, the highest oxygen concentration is found in a thin layer with a thickness between 10 nm and 30 nm (inclusive) directly adjacent to the silicon growth substrate. The oxygen content can decrease linearly in the direction away from the growth substrate.

[0026] According to at least one embodiment of the method, the buffer layer is grown with a thickness of at least 10 nm, or at least 30 nm, or at least 50 nm. Alternatively or additionally, the thickness of the buffer layer is at most 1000 nm, or at most 200 nm, or at most 150 nm. In particular, the thickness of the buffer layer is approximately 100 nm.

[0027] According to at least one embodiment of the method, an intermediate layer is applied directly to the buffer layer. The intermediate layer is applied by sputtering or by a gas-phase epitaxy such as MOVPE. The intermediate layer is preferably based on AlGaN.

[0028] According to at least one embodiment of the method, the intermediate layer is grown in such a way that the aluminium content decreases monotonically or strictly monotonically in a direction away from the growth substrate, i.e., for example, in a stepwise or linear fashion.

[0029] According to at least one embodiment of the process, the intermediate layer is grown in multiple layers. In individual layers of the intermediate layer, the aluminum content is preferably constant or approximately constant. The individual layers preferably have thicknesses between 20 nm and 100 nm, particularly approximately 50 nm. The intermediate layer comprises, in particular, between two and six layers, preferably four layers. The total thickness of the intermediate layer is, for example, between 50 nm and 500 nm, or between 100 nm and 300 nm, preferably approximately 200 nm.

[0030] According to at least one embodiment of the method, a growth layer is grown directly onto the intermediate layer. The growth layer is preferably a doped or undoped GaN layer. The thickness of the growth layer is preferably between 50 nm and 300 nm. The growth layer is preferably produced by sputtering or by MOVPE.

[0031] According to at least one embodiment of the method, a masking layer is applied directly to the growth layer. The masking layer is formed, for example, from silicon nitride, silicon oxide, silicon oxynitride, boron nitride, or magnesium oxide. The thickness of the masking layer is preferably at most 2 nm, 1 nm, or 0.5 nm. In particular, the masking layer is produced with a thickness that averages one or two monolayers. The masking layer can be produced by sputtering or by MOVPE.

[0032] According to at least one embodiment of the method, the masking layer is applied to the underlying layer with a coverage of at least 20%, 50%, or 55%. Preferably, the coverage is at most 90%, 80%, or 70%. In other words, the growth substrate and / or the growth layer, viewed from above, is then covered by the aforementioned proportions of the masking layer material. Thus, the growth layer is partially exposed.

[0033] According to at least one embodiment of the method, a coalescing layer is grown directly onto the masking layer and onto the growth layer, which is partially exposed. The coalescing layer is preferably based on undoped or substantially undoped GaN. The coalescing layer grows onto the partially exposed growth layer and thus into openings in the masking layer. Starting from these openings in the masking layer, the coalescing layer grows into a closed layer with comparatively few defects.

[0034] According to at least one embodiment of the method, the coalescing layer is grown with a thickness of at least 300 nm or at least 400 nm. Alternatively or additionally, the thickness is at most 3 µm or at most 1.2 µm.

[0035] According to at least one embodiment of the method, a middle layer is grown onto the coalescing layer, particularly in direct physical contact. The middle layer is preferably an AlGaN layer with an aluminum content between 75% and 100% inclusive. The thickness of the middle layer is preferably between 5 nm and 50 nm inclusive, and particularly between 10 nm and 20 nm inclusive. The middle layer may be doped.

[0036] According to at least one embodiment of the method, several intermediate layers are grown, each of which can be identical within the manufacturing tolerances. Preferably, a GaN layer, which can be doped or undoped, is located between each pair of adjacent intermediate layers. The GaN layer is also preferably in direct contact with the two adjacent intermediate layers. The thickness of the GaN layer is then preferably at least 20 nm, at least 50 nm, or at least 500 nm, and can alternatively or additionally be at most 1000 nm, at most 2000 nm, or at most 3000 nm.

[0037] According to at least one embodiment of the method, the semiconductor layer sequence with the active layer is grown on the middle layer or one of the middle layers that is furthest from the growth substrate. The semiconductor layer sequence is preferably in direct contact with the middle layer and is based on AlInGaN or InGaN. A layer of the semiconductor layer sequence adjacent to the middle layer is preferably n-doped. n-Doping is achieved, for example, with silicon and / or germanium.

[0038] According to at least one embodiment of the method, the sputtering of the buffer layer and / or the growth layer and / or the masking layer takes place at a temperature between 550 °C and 900 °C, inclusive. Furthermore, the pressure during sputtering is particularly between 10 °C and inclusive. -3 mbar and once 10 -2 mbar.

[0039] According to at least one embodiment of the method, the growth rate during sputtering of the buffer layer or other layers produced by sputtering is at least 0.03 nm / s and / or at most 0.5 nm / s. Sputtering is preferably carried out under an atmosphere of argon and nitrogen. The argon-to-nitrogen ratio is preferably 1:2, with a tolerance of at most 15% or at most 10%.

[0040] According to at least one embodiment of the method, a support substrate is applied to a side of the semiconductor layer sequence opposite the growth substrate. Subsequently, the growth substrate is removed, for example, by laser removal or etching. Further layers, in particular mirror layers, electrical contact layers, and / or bonding agent layers such as solders, may be located between the semiconductor layer sequence and the support substrate.

[0041] According to at least one embodiment of the method, the buffer layer is produced in a sputtering deposition system, and the semiconductor layer sequence is grown in a separate gas-phase epitaxial reactor. The sputtering deposition system is particularly preferably free of gallium and / or graphite.

[0042] Furthermore, an optoelectronic semiconductor chip is specified. The optoelectronic semiconductor chip can be manufactured using a method as described in one or more of the embodiments described above. Features of the method are therefore also disclosed for the optoelectronic semiconductor chip and vice versa.

[0043] In at least one embodiment of the optoelectronic semiconductor chip, it comprises a semiconductor layer sequence with an active layer designed for radiation generation. The semiconductor layer sequence further includes at least one n-doped layer and at least one p-doped layer, these doped layers preferably being directly adjacent to the active layer. The semiconductor layer sequence is based on AlInGaN or InGaN.

[0044] The semiconductor chip comprises a substrate on one p-side of the semiconductor layer sequence. On the side of the n-doped layer of the semiconductor layer sequence facing away from the substrate, there is a middle layer based on AlGaN, which has a high aluminum content and is grown with a thickness between 5 nm and 50 nm. Multiple middle layers can be formed, with gallium nitride layers between them.

[0045] On a side of the middle layer or layers facing away from the substrate, there is a coalescing layer of doped or undoped GaN with a thickness between 300 nm and 1.5 µm. Furthermore, the semiconductor chip is provided with a roughening that extends from the coalescing layer to or into the n-doped layer of the semiconductor layer sequence. A radiation emission surface of the semiconductor layer sequence is partially formed by the coalescing layer. The roughening exposes at least one of the middle layers in certain areas.

[0046] The following section provides a more detailed explanation of a method and a semiconductor chip described herein, with reference to the drawing and illustrated by exemplary embodiments. Identical reference numerals indicate identical elements in the individual figures. However, the figures are not to scale; rather, individual elements may be exaggerated for clarity.

[0047] They show: Fig. 1 a schematic representation of an embodiment of a method described herein for the production of an optoelectronic semiconductor chip described herein, and Fig. 2 to 5 schematic sectional views of exemplary embodiments of the optoelectronic semiconductor chips described herein.

[0048] In Fig. Figure 1 schematically illustrates a method for manufacturing an optoelectronic semiconductor chip 10. According to Fig. In step 1A, a silicon growth substrate 1 is provided in a sputter deposition system A. In the process step according to Fig. In the sputter deposition system A, a buffer layer 3 is sputtered onto the growth substrate 1. The buffer layer 3 is an AlN layer, preferably oxygenated.

[0049] The temperature during sputtering of the buffer layer 3 is preferably around 760 °C. The pressure in the sputtering deposition system A is preferably around 5 × 10 -2 mbar, with an argon-nitrogen atmosphere. The deposition rate during sputtering of the buffer layer 3 is approximately 0.15 nm / s. A sputtering power is preferably between 0.5 kW and 1.5 kW, particularly around 0.5 kW. The buffer layer 3 is produced with a thickness of approximately 100 nm. The sputtering deposition system A is gallium-free.

[0050] In the procedural step according to Fig. In step 1C, the growth substrate 1 with the buffer layer 3 is transferred from the sputtering deposition unit A to a MOVPE reactor B. The growth substrate 1 is located on a substrate holder b, which is preferably made of graphite. Because the AlN buffer layer 3 is produced in the sputtering deposition unit A and not in the MOVPE reactor B, the formation of a reflective layer of aluminum and / or gallium on the substrate holder b can be prevented or significantly reduced.

[0051] To grow a semiconductor layer sequence 2 with an active layer intended for radiation generation, the growth substrate 1 with the buffer layer 3 remains in the MOVPE reactor B. The semiconductor layer sequence 2 is thus epitaxially deposited onto the sputtered buffer layer 3.

[0052] Since the growth of the gallium-containing semiconductor layer sequence 2 is spatially separated from the formation of the buffer layer 3, it is possible to prevent gallium contamination in the sputtering deposition unit A. This ensures that no gallium comes into direct contact with the silicon growth substrate 1 or with any of its growth surfaces. This prevents meltback.

[0053] The process preferably takes place in a wafer stack. Further process steps, such as separating into individual semiconductor chips or creating additional functional layers, are omitted for the sake of simplicity. Fig. 1 not shown.

[0054] In Fig. Figure 2 schematically illustrates an embodiment of the optoelectronic semiconductor chip 10. The sputtered buffer layer 3 is located on the silicon growth substrate 1. In addition to oxygen, or alternatively, the buffer layer 3 can also contain indium and / or silicon.

[0055] The buffer layer 3 is immediately followed by an intermediate layer 4. The intermediate layer 4 preferably has several layers, in Fig. 2 not shown. The layers, for example, each have a thickness of approximately 50 nm and exhibit an aluminum content decreasing in the direction away from the growth substrate 1, whereby the aluminum content of the individual layers can be approximately 95%, 60%, 30% and 15%, in particular with a tolerance of at most ten percentage points or at most five percentage points.

[0056] The intermediate layer 4 is directly followed by a growth layer 8 of doped or undoped GaN. The thickness of the growth layer 8 is preferably approximately 200 nm. If the growth layer 8 is doped, the dopant concentration is preferably at least a factor of 2 lower than the dopant concentration of an n-doped layer 2b of the semiconductor layer sequence 2.

[0057] In a direction away from the growth substrate 1, the growth layer 8 is directly followed by a masking layer 6. The masking layer 6 preferably covers approximately 60% or approximately 70% of the growth layer 8. The growth layer 8 is formed from a few monolayers of silicon nitride.

[0058] In openings of the masking layer 6, a coalescing layer 7 of doped or undoped GaN grows onto the growth layer 8. In the direction away from the growth substrate 1, the coalescing layer 7 grows together to form a continuous layer. The coalescing layer 7 is preferably thinner than 2 µm or 1.5 µm. The thickness of the coalescing layer 7 is preferably between 0.5 µm and 1.0 µm inclusive.

[0059] A middle layer 9 directly follows the coalescing layer 7. Preferably, the middle layer 9 is an AlGaN layer with a high aluminum content and a thickness of approximately 15 nm or approximately 20 nm.

[0060] The middle layer 9 is followed by the n-doped layer 2b of the semiconductor layer sequence 2, which borders an active layer 2a. At least one p-doped layer 2c is located on a side of the active layer 2a facing away from the growth substrate 1. The layers 2a, 2b, 2c of the semiconductor layer sequence 2 are preferably based on InGaN. The dopant concentration of the n-doped layer 2b is preferably between 5 × 10⁻⁶ and including 5 × 10⁻⁶. 18 / ccm and 1 × 10 20 / ccm or between and including 1 × 10 19 / ccm or 6 × 10 19 / ccm. The n-doped layer 2b is preferably doped with germanium and / or silicon. The p-doped layer 2c is preferably doped with magnesium.

[0061] The thickness D of the n-doped layer 2b is, for example, between 1.0 µm and 4 µm inclusive, and in particular between 1.5 µm and 2.5 µm inclusive. In a region of the n-doped layer 2b closest to the middle layer 9, wherein this region preferably has a thickness between 100 nm and 500 nm inclusive, the dopant concentration is optionally reduced and is, for example, between 5 × 10⁻⁶ inclusive in this region. 17 / ccm and 1 × 10 19 / ccm, especially approximately 1 × 10 18 / ccm. This area is not shown in the figures.

[0062] In the embodiment of the semiconductor chip 10 according to Fig. 3. The growth substrate 1, the buffer layer 3, and the intermediate layer 4 have been removed, as is also the case in connection with Fig. 2. A first contact layer 12a is attached to a p-side of the semiconductor layer sequence 2. The semiconductor layer sequence 2 is connected to a support substrate 11 via the first contact layer 12a. The thickness of the support substrate 11 is preferably between 50 µm and 1 mm inclusive.

[0063] A roughening 13 is produced on a side of the semiconductor layer sequence 2 facing away from the support substrate 11. The roughening 13 extends to or into the n-doped layer 2b of the semiconductor layer sequence 2. Thus, the roughening exposes the n-doped layer 2b and the middle layer 9 in certain areas. Preferably, the masking layer 6 is completely removed by the roughening 13.

[0064] Optionally, a further contact layer 12b is attached to the side facing away from the substrate, via which the semiconductor chip 10 can be electrically contacted and energized, for example by means of a bond wire. Further optional layers such as mirror layers or bonding agent layers are shown in Fig. 3 not drawn.

[0065] Another embodiment of the semiconductor chip 10 is shown in Fig. 4 can be seen. Layers such as contact layers or mirror layers are omitted for simplification of the representation in Fig. 4 not illustrated. The semiconductor chip 10 according to Fig. 4 has two middle layers 9, between which there is a GaN layer 5.

[0066] The roughening 13 extends through both middle layers 5 into the n-doped layer 2b. Contrary to the drawing, it is possible that one of the middle layers 9 is not affected by the roughening. Furthermore, it is possible that the middle layer 9 closest to the active layer 2a is configured as an etch stop layer for generating the roughening 13. Unlike in Fig. As shown in Figure 4, there can also be more than two middle layers 9, which are either structured the same or differently from each other.

[0067] In Fig. Figure 5 shows a further embodiment of the semiconductor chip 10. The semiconductor layer sequence 2 is attached to the substrate 11 via a bonding agent 18, which is, for example, a solder. The side of the semiconductor layer sequence 2 facing the substrate 11 is electrically contacted via a first electrical connection layer 14 and via the substrate 11.

[0068] One side of the semiconductor layer sequence 2 facing away from the support substrate 11 is further contacted via a second electrical connection layer 16. The second connection layer 16 penetrates the active layer 2a, viewed from the support substrate 11, and is located laterally next to the semiconductor layer sequence 2. For example, the second connection layer 16 can be connected laterally next to the semiconductor layer sequence 2 by a bond wire (not shown).

[0069] The roughening 13 does not extend to the second connection layer 16. Furthermore, the connection layers 16 and 14 are electrically insulated from each other by a separating layer 15, for example made of silicon oxide or silicon nitride. Fig. Figure 5 does not show the middle layer or the coalescing layer. The semiconductor chip 10 can therefore be designed similarly to that described in US 2010 / 0171135 A1, the disclosure of which is incorporated by cross-reference.

Claims

[1] Method for manufacturing an optoelectronic semiconductor chip (10) comprising the steps: - Providing a silicon growth substrate (1), - Generating a III nitride buffer layer (3) on the growth substrate (1) by sputtering, and - Growth of a III nitride semiconductor layer sequence (2) with an active layer (2a) above the buffer layer (3), wherein - the buffer layer (3) is based on AlN and is applied directly to the growth substrate (1), - oxygen is added to the buffer layer (3), wherein a weight fraction of the oxygen is between 0.1% and 10% inclusive, and - wherein the oxygen content in the buffer layer (3) decreases strictly monotonically in a direction away from the growth substrate (1). [2] Method according to the preceding claim, wherein the buffer layer (3) has a thickness between 10 nm and 1000 nm inclusive. [3] Method according to any of the preceding claims, wherein the buffer layer (3) has a thickness between 50 nm and 200 nm inclusive. [4] Method according to one of the preceding claims, wherein an intermediate layer (4) is applied directly onto the buffer layer (3) by means of sputtering or by means of gas phase epitaxy, wherein the intermediate layer (4) is based on AlGaN and the Al content in the intermediate layer (4) decreases monotonically in the direction away from the growth substrate (1). [5] Method according to the preceding claim, wherein the following layers are produced directly on top of each other and in the specified sequence on the intermediate layer (4): - a growth layer (8) based on GaN, produced by sputtering or gas-phase epitaxy, - a masking layer (6) based on SiN, wherein the masking layer (6) covers the growth layer (8) with a coverage between 50% and 90% inclusive, and the masking layer (6) is produced by sputtering or gas-phase epitaxy, - a coalescence layer (7) based on GaN and grown with gas-phase epitaxy, - one or more intermediate layers (9) of AlGaN, wherein in the case of several intermediate layers (9) a GaN layer (5) with gas phase epitaxy is grown between each of two adjacent intermediate layers (9), and - the semiconductor layer sequence (2a, 2b, 2c) is based on AlInGaN and is grown using gas phase epitaxy. [6] A method according to any of the preceding claims, wherein the sputtering is carried out at a temperature between 550 °C and 900 °C inclusive and at a pressure between 1 × 10 -3 mbar and 1 × 10 -2 mbar is used. [7] Method according to any of the preceding claims, wherein a growth rate during sputtering is set between inclusive 0.03 nm / s and 0.5 nm / s, wherein the sputtering is carried out under an atmosphere containing Ar and N2 and the ratio of Ar to N2 is 1 to 2, with a tolerance of at most 15%. [8] Method according to one of the preceding claims, wherein a support substrate (11) is attached to a side of the semiconductor layer sequence (2) facing away from the growth substrate (1) and the growth substrate (1) is subsequently removed. [9] Method according to any of the preceding claims, wherein the buffer layer (3) is produced in a sputtering deposition system (A) and the semiconductor layer sequence (2) is grown in a gas phase epitaxy reactor (B) different therefrom, wherein the sputtering deposition system (A) is free of gallium.

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