METHOD FOR STRUCTURING INTEGRATED CIRCUITS

Abstract

Method for structuring a support layer (202), the method comprising: forming a hard mask layer (204) over the support layer (202), wherein the hard mask layer (204) comprises amorphous silicon; forming a first material layer (206) over the hard mask layer (204), wherein the material of the first material layer (206) is different from the material of the hard mask layer (204) and the first material layer (206) comprises silicon, hydrogen, oxygen and / or carbon; forming a trench (214) in the first material layer (206), wherein forming the trench (214) in the first material layer (206) comprises: forming a lacquer layer (210) over the first material layer (206); structuring the lacquer layer (210) to form a trench (212) in the lacquer layer (210);and transferring the trench (212) in the lacquer layer (210) to the first material layer (206) by etching the first material layer (206) through the trench (212) in the lacquer layer (210), and removing the lacquer layer (210); treating the hard mask layer (204) with an ion beam (216) through the trench (214) in the first material layer (206), wherein the ion beam (216) is a BF2 ion beam, and the etch rate of a treated section (204A) of the hard mask layer (204) with respect to an etching process is reduced, while the etch rate of untreated sections (204B) of the hard mask layer (204) remains unchanged with respect to the etching process, and the etching process uses tetramethylammonium hydroxide; after treating the hard mask layer (204) with the ion beam (216), tempering the hard mask layer (204); after tempering the hard mask layer (204), removal of the first material layer (206);Removing the untreated sections (204B) of the hard mask layer (204) by the etching process, thereby forming an island-shaped hard mask over the substrate layer (202); and etching the substrate layer (202) with the island-shaped hard mask as the etch mask.

Description

BACKGROUNDThe semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each generation having smaller and more complex circuits than the previous generation. In the course of IC development, the functional density (i.e., the number of interconnected devices per chip area) has generally increased, while the geometric size (i.e., the smallest component (or line) that can be created with a fabrication process) has decreased. This downscaling process generally offers advantages by increasing production efficiency and decreasing associated costs. However, this scaling down has also increased the complexity of processing and manufacturing ICs, and similar developments in IC processing and manufacturing are required to implement these advantages.For example, lithography is a technique regularly used in IC fabrication to transfer an IC design to a semiconductor carrier layer. A common lithography process includes forming a hard mask layer over a support layer (substrate), patterning the hard mask layer to form a hard mask, and etching the hard mask using the hard mask as an etch mask. Patterning the hard mask layer typically includes coating the hard mask layer with a resist (or photoresist), exposing the resist to radiation such as deep ultraviolet (DUV) radiation or extreme ultraviolet (EUV) radiation, and developing and partially removing the resist to leave a patterned resist over the hard mask layer. The patterned resist is then used in subsequent etching of the hard mask layer to form the hard mask. As device shrinkage progresses, there is often a need to produce small island-shaped hard masks. With regard to the prior art, reference is made to U.S. Pat. Nos. 5,300,445 A, 4,438,556 A, DE 103 41 321 A1, DE 101 63 346 A1, U.S. Pat. No. 2011 / 0 300 711 A1, DE 103 02 544 A1, U.S. Pat. No. 2011 / 0 020 753 A1, U.S. Pat. No. 2014 / 0 024 215 A1 and U.S. Pat. No. 2015 / 0 194 317 A1.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure will be best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with standard practice in the industry, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 is a flow diagram of a method of forming a target structure or device on a substrate for carrying out one or more embodiments of the present disclosure. FIGS. 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2I, and 2J are cross-sectional views of formation of a target device according to the method of FIG. 1, according to an embodiment.DETAILED DESCRIPTIONThe spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented differently (90 degrees or rotated in other orientations) and the spatially relative descriptors used herein may also be interpreted accordingly.The present disclosure generally relates to forming an integrated circuit (IC) structure or device using a lithography process. More particularly, the present disclosure relates to forming small island-shaped hard masks for sophisticated IC fabrication processes.FIG. 1 shows a flow diagram of a method 100 for forming a target structure or device according to various aspects of the present disclosure. Additional operations may be provided before, during, and after the method 100, and some described operations may be replaced, suspended, or moved for additional embodiments of the method. The method 100 is only an example and is not intended to limit the present disclosure beyond what is expressly recited in the claims. The method 100 is described below in connection with FIGS. 2A-2J, which show schematic cross-sectional views of an apparatus 200 at various stages of a manufacturing process. The device 200 may be an IC, or a portion thereof, which may include static random access memory (SRAM) and / or other logic circuits, passive components such as resistors, capacitors, and inductors, and active components such as p-type field effect transistors (PFET), n-type FET (NFET), metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor field effect transistors (CMOS), bipolar transistors, high voltage transistors, high frequency transistors, other memory cells, and combinations thereof. The device 200 may include three-dimensional devices and multi-gate devices, such as dual-gate FETs, FinFETs, three-gate FETs, omega FETs, and gate-all-around (GAA) devices including vertical GAA devices and horizontal GAA devices.At operation 102, the method 100 (FIG. 1 ) provides a carrier layer 202 as shown in FIG. 2A. Referring to FIG. 2A, in various embodiments, the carrier layer 202 includes one or more material layer(s). In an embodiment, the carrier layer 202 is a semiconductor carrier layer (e.g., a wafer). In an embodiment, the carrier layer 202 comprises silicon in a crystalline structure. In alternative embodiments, the carrier layer 202 comprises other elementary semiconductors such as germanium; a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide; or an alloy semiconductor such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. The support layer 202 may include a silicon-on-insulator (SOI) support layer, be strained / strained for performance enhancement, include epitaxial regions, include isolation regions, include doped regions, include one or more semiconductor device(s) or portions thereof, include conductive and / or non-conductive layers, and / or include other suitable properties and layers. For example, the substrate 202 may include silicon fin field effect transistors (FinFETs).At operation 104, the method 100 (FIG. 1 ) forms a hard mask layer 204 over the carrier layer 202. Referring to FIG. 2B, in the present embodiment, the hard mask layer 204 uses amorphous silicon (a-Si). In alternative embodiments, the hard mask layer 204 may use silicon oxide (SiO 2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon carbide (SiC), other suitable materials, or a combination thereof. Further, in the present embodiment, the hard mask layer 204 uses an amorphous silicon layer having a thickness in the range of about 1 nm to about 200 nm. The hard mask layer 204 may be formed by chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable deposition methods. For example, the hard mask layer 204 may be formed by CVD using chemicals including hexachlorodisilane (HCD or Si 2 Cl 6), dichlorosilane (DCS or SiH 2 Cl 2), bis(tertiary butylamino) silane (BTBAS or C 8 H 22 N 2 Si), and disilane (DS or Si 2 H 6).At operation 106, the method 100 (FIG. 1 ) forms a first material layer 206 over the hard mask layer 204. Referring to FIG. 2C, the first material layer 206 uses a different material from the hard mask layer 204. In various embodiments, the first material layer 206 and the hard mask layer 204 have high etch selectivity. The first material layer 206 may include silicon, hydrogen, oxygen, and / or carbon, such as spin-on-glass (SOG). In one embodiment, the first material layer 206 is an underlayer in a three-layer photolithography. The first material layer 206 may be formed using CVD, PVD, spin coating, or other suitable process.At operation 108, the method 100 (FIG. 1 ) forms a resist layer 210 over the first material layer. Referring to FIG. 2D, in the present embodiment, the method 100 forms a middle layer 208 on the first material layer 206 prior to forming the resist layer 210. The middle layer 208 may be an anti-reflective coating (ACR) layer comprising a polymeric material layer or a silicon-containing material layer, such as silicon oxide, silicon oxygen carbide, and plasma enhanced vapor phase deposited silicon oxide. In an alternative embodiment, the middle layer 208 includes carbon, hydrogen, and / or oxygen. The middle layer 208 may be formed by CVD, PVD, ALD, or other suitable methods. The resist layer 210 is formed on the middle layer 208. In an alternative embodiment, the resist layer 210 may be formed directly over the first material layer 206, without the middle layer 208. In various embodiments, the resist layer 210 is formed by a spin coating process followed by a smooth baking process.The resist layer 210 may be a positive resist or a negative resist. A positive resist is normally insoluble in a resist developer, but is solubilized by exposure to radiation such as a deep ultraviolet (DUV) beam, an extreme ultraviolet (EUV) beam, an electron beam (e-beam), an x-ray beam, or other suitable radiation. An exemplary positive resist material is chemically enhanced resist (CAR) containing an acid labile group (ALG) protected backbone polymer. A negative resist has the opposite behavior - is normally soluble in a resist developer, but is insolubilized by exposure to radiation such as a DUV beam, an EUV beam, an e-beam, an X-ray beam or other suitable radiation. An exemplary negative resist is a polymer that forms intramolecular and / or intermolecular crosslinks when irradiated, such as polymerization of ethyl (α-hydroxy)acrylate (EHMA) and methacrylic acid (MAA).In operation 110, the method 100 (FIG. 1 ) patterns the resist layer 210 and thereby forms a resist pattern 210'. Referring to FIG. 2E, in the present embodiment, the resist pattern 210' includes a trench 212, also referred to as resist trench 212. In further development of the present embodiment, the resist trench 212 has small dimensions to form a small island-shaped hard mask in the hard mask layer 204.An island-shaped hard mask (i.e., a hard mask feature isolated from the rest of the hard mask features) is regularly used in IC fabrication. For example, when forming a contact layer for SRAM cells, an end-of-line cut mask is used to determine the final feature. The line end cut mask is an island-shaped mask. However, it has been a rather challenge to form small island-shaped hard masks for photolithography as the semiconductor process gradually develops toward smaller nodes, such as 22 nm, 10 nm, or even smaller. One reason is that small paint patterns suffer from a paint peeling problem. When the resist layer 210 is patterned to form small resist pattern islands, similar to conventional photolithography processes, the small resist pattern islands do not adhere too well to the underlayer (e.g., the middle layer 208) and could easily fall off during the photolithography process. This is undesirable. One approach to counter the paint exfoliation problem uses a reverse patterning process. In the reverse patterning process, a resist is first patterned to have small resist trenches (such as resist trench 212). Then, the resist trenches are transferred to a hard mask layer (such as hard mask layer 204) to form hard mask trenches by etching the hard mask layer and any intervening layers between the hard mask layer and the resist. Next, the hard mask trenches are overfilled with a dielectric material and a chemical mechanical planarization (CMP) process is performed to remove excess dielectric material. Finally, the hard mask layer is removed by a selective etching process, leaving the dielectric material as a small island-shaped mask. The reverse patterning process addresses the paint exfoliation problem. However, it has its own disadvantages. First, it involves additional costs due to the use of the additional dielectric material and associated deposition, CMP, and etching processes. Second, due to the additional processing over the carrier layer (e.g., the hard mask layer is etched twice), it may cause more defects in the devices being fabricated. The provided article is superior to both conventional island-shaped resist patterning and the reverse patterning process, as will be discussed below.Still referring to FIG. 2E, in one embodiment, operation 110 (FIG. 1 ) patterns resist layer 210 using a photomask (or mask or reticle). Alternatively, operation 110 may use a maskless patterning technique, such as electron beam direct writing (EBDW). In an embodiment, patterning the resist layer 210 includes exposing the resist layer 210 to radiation, post exposure bakes, developing the resist layer 210 in a resist developer, and hard bake, thereby removing an exposed (or unexposed, in the case of a negative resist) portion of the resist layer 210 and leaving unexposed portions thereof on the middle layer 208 as the resist pattern 210'. The radiation may be a DUV beam, an EUV beam, an e-beam, an x-ray beam, an ion beam, or other suitable radiation. In embodiments where a photomask is used to pattern resist layer 210, the photomask may be of various types, such as a transmissive mask or a reflective mask, and may be formed in various technologies, such as binary mask or phase shift mask (PSM). In one example, a binary mask includes a transparent support layer (e.g., fused silica) and an opaque material (e.g., chromium) deposited in the opaque regions of the mask. In another example, a PSM includes various features designed to have a correct phase difference to improve resolution and image quality. In various embodiments, the resist layer 210 may be patterned to include any number of trench structures, and the trench patterns may be of any shape and size.At operation 112, the method 100 (FIG. 1 ) transfers the resist trench 212 to the first material layer 206, thereby forming a patterned first material layer 206'. In the present embodiment, the operation 112 includes etching the middle layer 208 and the first material layer 206 through the resist trench 212. The etching processes may include dry (plasma) etching, wet etching, and / or other etching processes. For example, a dry etching process may implement an oxygen-containing gas, a fluorine-containing gas (e.g., CF 4, SF 6, CH 2 F 2, CHF 3 and / or C 2 F 6), a chlorine-containing gas (e.g., Cl 2, CHCl 3, CCl 4 and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBR3), an iodine-containing gas, or other suitable gases and / or plasmas, and / or combinations thereof. For example, a wet etching process may use a dilute hydrofluoric acid (DHF) etchant, potassium hydroxide (KOH), ammonia, or other suitable wet etchant. The one or more etching process(s) form a trench 214 in the first material layer 206. After the first material layer 206 has been etched, the resist pattern 210' and the middle layer 208 are removed. The resist pattern 210' may be removed, for example, by a wet etching process using a resist remover, an aqueous alkali, an amine solvent mixture, or an organic solvent. The middle layer 208 may be removed by dry (plasma) etching, wet etching, and / or other etching methods that are selectively tuned to remove the middle layer 208 while the patterned material layer 206' remains substantially unchanged.In the present embodiment, the first material layer 206 and the hard mask layer 204 have high etch selectivity. In other words, when the first material layer 206 is etched in an etching process (e.g., a dry etching process) to form the trench 214, the hard mask layer 204 remains substantially unchanged in the etching process. As a result of operation 112, trench 214 is formed in first material layer 206 and exposes a portion of hard mask layer 204 as shown in FIG. 2F.At operation 114, the method 100 (FIG. 1 ) treats the hard mask layer 204 with an ion beam 216. Referring to FIG. 2G, the ion beam 206' is directed toward a top surface of the apparatus 200. Because the patterned first material layer 206' partially covers the hard mask layer 204, only a portion of the hard mask layer 204 corresponding to or exposed by the trench 214 is treated by the ion beam 216. In the present embodiment, the treated portion(s) of the hard mask layer 204 is labeled 204A, while the untreated portion(s) of the hard mask layer 204 is(are) labeled 204B. In the present embodiment, the ion beam 216 reduces the etching rate of the treated portion 204A with respect to a target etchant. In particular, the treated portion 204A achieves a lower etch rate (or higher etch resistance) with respect to the target etchant than the untreated portion 204B. In an embodiment, the hard mask layer 204 comprises amorphous silicon, the ion beam comprises B ions or BF 2- ions, and the target etchant comprises ammonium hydroxide or tetramethylammonium hydroxide. Experiments have shown that the etch rate of amorphous silicon in ammonium hydroxide or tetramethylammonium hydroxide decreases dramatically after being treated with a B ion beam or a BF 2- ion beam. In one example, the etch rate decreases from about 20 nm per minute (nm / min) to about 0 nm / min.In an embodiment, the ion beam 216 is generated by an ion implanter as a focused ion beam. In an embodiment, the ion beam 216 is a B ion beam or a BF 2- ion beam and is provided with an ion energy of about 1.0 keV to about 50 keV and an ion dose of about 1×10 13 ions / cm 2 to about 1×10 16 ions / cm 2. In non-claim examples, the ion beam 216 may include one of the following ion species: C, P, In, Ge, As, Si, and Yb. Further, the ion beam 216 may be directed toward the hard mask layer 204 at an angle of inclination ranging from 0 degrees (normal to the top surface of the device 200) to about 45 degrees (on both sides of the normal) and at an appropriate angle of rotation. In embodiments, the ion beam treatment of the hard mask layer 204 may be performed at temperatures ranging from -100 degrees Celsius to about 100 degrees Celsius and for about 3 seconds to about 600 seconds.The patterned first material layer 206' effectively blocks the ion beam 216 from reaching the hard mask layer 204 except through the trench 214. In an embodiment, the etch rate of the patterned first material layer 206' is substantially unaffected by the ion beam 216. Further, the patterned first material layer 206' and the hard mask layer 204 (including the treated and untreated portions) still have sufficient etch selectivity in an etching process.In one embodiment, it is desirable to leave the support layer 202 substantially unaffected by the ion beam 206. In further development of this embodiment, the thickness of the hard mask layer 204 and the characteristics of the ion beam 216 (such as ion energy, ion dose, beam tilt, and angle of rotation) are carefully designed so that the ion beam 216 thoroughly treats the hard mask layer portion 204A, but does not (or insignificantly) penetrate the support layer 202.In an embodiment, the operation 114 further includes an annealing process after the hard mask layer 204 is treated with the ion beam 216. For example, the annealing process may include a microsecond annealing (μSS) process, a microwave annealing (MWA) process, a rapid thermal annealing (RTA) process, and / or other suitable annealing processes. The anneal process may improve the critical dimension and profile of the treated portion 204 and, accordingly, the final small island-shaped hard mask.At operation 116, the method 100 (FIG. 1 ) removes the patterned first material layer 206' using an etching process, which may include dry (plasma) etching, wet etching, and / or other etching processes. For example, a dry etching process may implement an oxygen-containing gas, a fluorine-containing gas, a chlorine-containing gas, a bromine-containing gas, an iodine-containing gas, other suitable gases and / or plasmas, and / or combinations thereof. For example, a wet etching process may use a dilute hydrofluoric acid (DHF) etchant, potassium hydroxide (KOH), ammonia, or other suitable wet etchants. In the present embodiment, the etching process is adjusted to selectively remove the patterned first material layer 206' while the hard mask layer 204 including both the treated portion 204A and the untreated portion 204B remains substantially unchanged as shown in FIG. 2H.At operation 118, the method 100 (FIG. 1 ) removes the untreated portion 204B of the hard mask layer 204. The etching processes may include dry (plasma) etching, wet etching, and / or other etching processes. In the present embodiment, the hard mask layer 204 includes amorphous silicon, and the etching process uses ammonium hydroxide or tetramethylammonium hydroxide as an etchant. Due to the ion beam treatment in operation 114, the treated portion 204A and the untreated portion 204B have high etch selectivity in the etching process. As a result, the untreated portion 204B is removed by the etching process, while the treated portion 204A remains substantially unchanged and becomes a hard mask 204A' over the support layer 202. Depending on the etch selectivity between the treated and untreated portions 204A and 204B, the hard mask 204A' may be the same or substantially the same as the treated portion 204A. Referring to FIG. 21, therein is shown device 200 with hard mask 204' over support layer 202. In the present embodiment, the hard mask 204' is a small island-shaped hard mask for etching the substrate 202. Compared to conventional approaches for forming a small island-shaped hard mask, the provided article has many advantages. First, the provided subject matter overcomes the resist exfoliation problem because the mask feature is formed as a resist trench (e.g., resist trench 212). Second, the provided object forms the small island-shaped hard mask directly in the hard mask layer (e.g., the hard mask layer 204) and does not require any reversed material and associated process. Therefore, the provided subject matter is more cost effective in addition to other advantages.At operation 120, the method 100 (FIG. 1 ) etches the carrier layer 202 with the hard mask 204A' as an etch mask. Referring to FIG. 2J, the apparatus 200 is shown therein with the etched carrier layer 202. The hard mask layer 204A' serves as an etching mask and protects a portion 202A of the support layer 202 from being etched. In the present embodiment, portion 202A forms a small island-shaped feature on backing layer 202. The carrier layer 202 may be etched using dry etching, wet etching, reactive ion etching, and / or other etching methods. In another embodiment, the hard mask 204A' is used as a cut mask in a spindle cut process. In a spindle cut process, a spindle mask determines a spindle pattern in a first exposure and a cut mask determines a cut pattern (such as hard mask layer 204A') in a second exposure. For example, the spindle structure may be fins for FinFETs, contact lines in SRAM cells, etc. For example, the spindle structure defines areas to be removed from the spindle structure or its derivatives. The final structure includes the spindle structure plus the derivatives, but not the cut structure. Note that the provided object may be used in forming any kind of hard masks, and is not limited to small island-shaped hard masks. In this regard, the hard mask 204A' may be of any shape and size and may be used by the method 100 in forming various IC features, such as isolation features, source and drain features, gate blocks, contacts, vias, and metal interconnects. The hard mask 204A' may be removed after the carrier layer 202 has been etched, for example, by dry etching, wet etching, or other etching methods.At operation 122, the method 100 (FIG. 1 ) performs further steps to complete the manufacture of the device 200. For example, the method 100 may form active devices, such as transistors, in and on the substrate 202; form high dielectric metal gate blocks; form multi-layer interconnect structures; and form logic circuits and / or memory cells with various active and passive devices.Although not intended to be limiting, the present disclosure provides many advantages for the manufacture of an IC. For example, embodiments of the present disclosure may be advantageously used to form small island-shaped hard masks. Compared to conventional approaches for forming small island-shaped hard masks, the provided subject matter overcomes the resist exfoliation problem because the hard mask is first formed as a resist trench. Further, the provided article forms the small island-shaped hard mask directly in a hard mask layer without a need for a reverse material fill and associated processes (such as deposition, CMP, and etching). As a result, the provided article saves material costs and handling and helps reduce defects in the final IC device. The provided article can be easily integrated into an existing IC manufacturing process and used to form all kinds of etching masks without being limited to small island-shaped hard masks. Indeed, the specific embodiments discussed so far are only examples and do not limit the scope of the present disclosure beyond what is expressly recited in the claims.The invention is defined by the main claim and the subordinate claims. The dependent claims represent further embodiments of the invention.

Claims

A method of patterning a carrier layer (202), the method comprising: forming a hard mask layer (204) over the carrier layer (202), the hard mask layer (204) comprising amorphous silicon; forming a first material layer (206) over the hard mask layer (204), the material of the first material layer (206) being different from the material of the hard mask layer (204), and the first material layer (206) comprising silicon, hydrogen, oxygen, and / or carbon; forming a trench (214) in the first material layer (206), wherein forming the trench (214) in the first material layer (206) comprises: forming a resist layer (210) over the first material layer (206); patterning the resist layer (210) to form a trench (212) in the resist layer (210); transferring the trench (212) in the resist layer (210) to the first material layer (206) by etching the first material layer (206) through the trench (212) in the resist layer (210), and removing the resist layer (210); treating the hard mask layer (204) with an ion beam (216) through the trench (214) in the first material layer (206), wherein the ion beam (216) is a BF 2- ion beam, and an etching rate of a treated portion (204A) of the hard mask layer (204) with respect to an etching process decreases while an etching rate of untreated portions (204B) of the hard mask layer (204) remains unchanged with respect to the etching process, and the etching process uses tetramethylammonium hydroxide; after treating the hard mask layer (204) with the ion beam (216), annealing the hard mask layer (204); after annealing the hard mask layer (204), removing the first material layer (206); removing the untreated portions (204B) of the hard mask layer (204) with the etching process, thereby forming an island-shaped hard mask over the support layer (202); and etching the support layer (202) with the island-shaped hard mask as an etching mask.The method of claim 1, wherein the BF 2- ion beam is an ion beam having an ion energy of 1.0 keV to 50 keV and an ion dose of 1×10 13 ions / cm 2 to 1×10 16 ions / cm 2.The method of claim 1 or 2, wherein the ion beam (216) is provided at an inclination angle in a range of 0 degrees to 45 degrees.The method of any preceding claim, wherein removing the first material layer (206) uses an etching process that selectively removes the first material layer (206) while the hard mask layer (204) remains unchanged.The method of any preceding claim, wherein forming the trench (214) in the first material layer (206) further comprises: forming an anti-reflective coating layer (208) over the first material layer (206) prior to forming the resist layer (210).The method of any preceding claim, wherein forming the trench (214) in the first material layer (206) comprises a further process that selectively removes the first material layer (206) while the hard mask layer (204) remains unchanged.The method of any preceding claim, wherein the support layer (202) is unaffected by the ion beam (216).The method of any preceding claim, wherein an etch rate of the first material layer (206) is unaffected by the ion beam (216).A method of patterning a carrier layer (202), the method comprising: forming a hard mask layer (204) over the carrier layer (202), the hard mask layer (204) comprising amorphous silicon; forming a first material layer (206) over the hard mask layer (204), the material of the first material layer (206) being different from the material of the hard mask layer (204), and the first material layer (206) comprising silicon, hydrogen, oxygen, and / or carbon; forming a trench (214) in the first material layer (206), the trench (214) exposing a first portion (204A) of the hard mask layer (204), wherein forming the trench (214) in the first material layer (206) comprises: forming a resist layer (210) over the first material layer (206); patterning the resist layer (210) to form a trench (212) in the resist layer (210); and transferring the trench (212) in the resist layer (210) to the first material layer (206) by etching the first material layer (206) through the trench (212) in the resist layer (210), and removing the resist layer (210); treating the first portion (204A) with an ion beam (216), thereby reducing an etching rate of the first portion (204A) with respect to an etchant while leaving an etching rate of untreated portions (204B) of the hard mask layer (204) unchanged with respect to the etchant, wherein the ion beam (216) is a BF 2- ion beam, and the etchant is tetramethylammonium hydroxide; after treating the first portion (204A) with the ion beam (206), annealing the hard mask layer (204); after annealing the hard mask layer (204), removing the first material layer (206); removing the untreated portions (204B) of the hard mask layer (204) with the etchant, thereby forming an island-shaped hard mask over the support layer (202); and etching the support layer (202) with the island-shaped hard mask as an etch mask.The method of claim 9, wherein the support layer (202) is unaffected by the ion beam (216).The method of claim 9 or 10, wherein removing the first material layer (206) and forming the trench (214) in the first material layer (206) each comprises an etching process that selectively removes the first material layer (206) while the hard mask layer (204) remains unchanged.A method of patterning a carrier layer (202), the method comprising: forming a hard mask layer (204) over the carrier layer (202), the hard mask layer (204) comprising amorphous silicon; forming a first material layer (206) over the hard mask layer (204), the material of the first material layer (206) being different from the material of the hard mask layer (204), and the first material layer (206) comprising silicon, hydrogen, oxygen, and / or carbon; forming a trench (214) in the first material layer (206), the trench (214) in the first material layer (206) exposing a first portion of the hard mask layer (204), wherein forming the trench (214) in the first material layer (206) comprises: forming a resist layer (210) over the first material layer (206); patterning the resist layer (210) to form a trench (212) in the resist layer (210); and transferring the trench (212) in the resist layer (210) to the first material layer (206) by etching the first material layer (206) through the trench (212) in the resist layer (210), and removing the resist layer (210); treating the first portion with an ion beam (216), thereby reducing an etching rate of the first portion (204A) with respect to an etchant while leaving an etching rate of untreated portions (204B) of the hard mask layer (204) unchanged with respect to the etchant, wherein the ion beam (216) is a BF 2- ion beam, and wherein the etchant comprises tetramethylammonium hydroxide; after treating the first portion (204A) with the ion beam (216), annealing the hard mask layer (204); after annealing the hard mask layer (204), removing the first material layer (206); removing the untreated portions (204B) of the hard mask layer (204) with the etchant, thereby forming an island-shaped hard mask over the support layer (202); and etching the support layer (202) with the island-shaped hard mask as an etch mask.The method of claim 12, wherein removing the first material layer (206) and forming the trench (214) in the first material layer (206) each comprises an etching process that selectively removes the first material layer (206) while the hard mask layer (204) remains unchanged.

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