FinFET device and method for forming and controlling its quality

Abstract

A method of forming a FinFET device, comprising: Forming a plurality of fins (122) lying on a substrate having a central region and a peripheral region; Depositing a gate layer (154) on the fins (122); and Plasma etching the gate layer with an etching gas to form a first gate (170) in the central region (120) and a second gate (171) in the peripheral region, wherein the first and second gates (170, 171) each have two notch features in a first portion (172) and in a second portion (174), wherein the first portion (172) overlies a fin (122) and wherein the second portion (174) overlaps the sidewalls of the fin (122), wherein the etching gas is introduced at a ratio of the flow rate in the central region to the flow rate in the peripheral region between 0.2 and 1, and wherein the first gate (170) and the second gate (171) have a similar profile, wherein the first gate is located in a region of the substrate having a first fin density and wherein the second gate is located in a region of the substrate having a second fin density that is greater than the first fin density.

Description

BACKGROUND

[0001] Semiconductor devices are commonly used in many electronic devices, such as computers, mobile phones, and others. Semiconductor devices include integrated circuits, which are formed by depositing various types of thin material films on semiconductor wafers and patterning the thin material films to form the integrated circuits.

[0002] To address this increase in manufacturing complexity and the associated manufacturing process challenges, advances in IC processing and manufacturing are necessary. For example, a three-dimensional transistor, such as a fin field-effect transistor (FinFET), was introduced to replace a planar transistor. Continuous improvements in the FinFET device manufacturing process are needed to meet the performance requirements of the downscaling process.

[0003] Methods for forming FinFET devices are known, for example, from DE 102016 100 035 A1, DE 102015 105 856 A1, and US 2013 / 0 193 513 A1. US 2008 / 0 179 283 A1 describes a plasma etching process in which a process gas is supplied to a central region and an edge region of a substrate at different flow rates. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. Note that, in accordance with standard industry practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily exaggerated or reduced for clarity of description. Fig. 1 shows an example flowchart for fabricating a FinFET device in accordance with some embodiments. Fig. 2 shows a three-dimensional view of a FinFET device in accordance with some embodiments. Fig. 3A, Fig. 4A, Fig. 5A, Fig. 6A and Fig. 7A show different cross-sectional views of a FinFET device at line AA in Fig. 2 at various stages of the manufacturing process in accordance with some embodiments. Fig. 3B, Fig. 4B, Fig. 5B, Fig. 6B and Fig. 7A show different cross-sectional views of a FinFET device at line BB in Fig. 2 at various stages of the manufacturing process in accordance with some embodiments. Fig. 6C and Fig. 7C show different cross-sectional views of a FinFET device at line CC in Fig. 2 at various stages of the manufacturing process in accordance with some embodiments. Fig. 8 shows a cross-sectional view of a FinFET device in accordance with some embodiments. Fig. 9 shows an exemplary flowchart for controlling the quality of a FinFET device in accordance with some embodiments. DETAILED DESCRIPTION

[0005] The present invention provides a method of forming a FinFET device according to claim 1, as well as a FinFET device according to claim 11. Exemplary embodiments are set forth in the dependent claims. The following disclosure contemplates many different embodiments or examples for implementing various features of the intended subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting.For example, forming a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first and second features need not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, enforce any relationship between the various described embodiments and / or configurations.

[0006] The singular forms "a," "an," and "the" include plural referents unless the context dictates otherwise. Reference, for example, to a contact plug includes aspects having two or more such plugs unless the context dictates otherwise. Further, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to one or more other elements or features as shown in the figures.

[0007] When manufacturing a semiconductor device, it is very important that an integrated circuit operates under stable conditions so that any possibility of inducing a short circuit is eliminated. In a fin field-effect transistor (FinFET), such a short circuit can occur between a source / drain region in a fin structure and a gate structure surrounding the fin. In a normal situation, while forming the gate structure surrounding the fin structure, a removal process such as etching is controlled to remove a gate material layer to form a desired shape of the gate structure. However, in a conventional etching process, the gate structure in the central region of a substrate and the gate structure at the edge of the substrate are subjected to different etching rates. Such different etching rates can result in different profiles of the gate structures at the edge compared to the gate structures in the central region.For example, the gate structure in the edge region may be undercut, which may result in a pedestal (gate protrusion) extending from a lower portion of the gate structure. The pedestal may cause a short circuit between the gate structure and a source / drain region that will be formed later.

[0008] To solve the problem of short circuits between the gate structure and the source / drain region caused by the pedestal device of the gate structure, a method is provided for fabricating gate structures having two notch features in both the central region and the edge region. In this disclosure, a different flow rate of the etching gas is used in the central region versus the edge region during a plasma etching process to enhance the etching process in the edge region (i.e., increase the etch rate). In addition, by appropriately adjusting other etching parameters such as etch pressure, RF bias, and overetch time, gate structures in the central region and the edge region both have two notch features with the same profile. In particular, the dimensions (or a series of dimensions) of the notch features may be determined according to a predetermined criterion.Thus, the FinFET device has good electrical properties that can be measured by a WAT ​​(Wafer Acceptance Test) process.

[0009] Refer now to Fig. 1, which is an exemplary flowchart for fabricating a FinFET device according to an embodiment of the present disclosure. The flowchart shows only the relevant part of the overall fabrication process. It is understood that additional operations may be provided before, during, and after the operations described in Fig. 1, and some of the described operations may be substituted or omitted for further embodiments of the method. The order of the operations / methods may be changed.

[0010] As in Fig. 1, an embodiment of a method 1000 for forming two notch features in a gate structure of a FinFET is provided. In step 1002, a fin lying on a substrate is formed. In step 1004, an isolation structure is formed between the fins. In step 1006, a gate oxide layer and a gate material layer are deposited over the fin. In step 1008, a first hard mask layer and a second hard mask layer are deposited on the gate material layer. In step 1010, the first hard mask layer, the second hard mask layer, and the gate material layer are etched to form a gate structure with two notch features. In step 1012, epitaxy is formed in the fin.

[0011] With reference to Fig. 2, a three-dimensional view of a FinFET device with a gate structure having two notch features is provided to facilitate and better understand the present disclosure. In the following explanations relating to a method 1000 for forming the FinFET device, several cross-sectional views of the FinFET device are shown along line AA, line BB, and line CC in FIGS. Fig. 3A to 7A, the Fig. 3B to 7B or the Fig. 6C and Fig. 7C to better understand the present disclosure.

[0012] With reference to the Fig. 1, Fig. 2, Fig. 3A and Fig. 3B, the method 1000 begins at step 1002 by forming fins 122, 132, 134, 136, and 138 disposed on a substrate 110. The substrate 110 includes two regions: a central region 120 with the fin 122 thereon; and an edge region 130 with the fins 132, 134, 136, and 138 thereon. Note that the central region 120 and the edge region 130 may each be located in a dense region or an isolation region, where the dense region is defined to be a region with a high fin density, while the isolation region is defined to be a region with a low fin density. In other embodiments, the substrate 110 includes a dense region 130 and an isolation region. Furthermore, the dense region 130 and the insulating region 120 may both be located in a central region of the substrate 110 or an edge region of the substrate 110.

[0013] Substrate 110 may be a bulk silicon substrate. Alternatively, substrate 100 may comprise an elemental semiconductor such as silicon (Si) or germanium (Ge) in a crystal structure; a compound semiconductor such as silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb), or a combination thereof. Furthermore, substrate 110 may also comprise silicon-on-insulator (SOI) substrates. Generally, an SOI substrate comprises a layer of a semiconductor material such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon germanium-on-insulator (SGOI), or a combination thereof. The SOI substrate 100 will be fabricated by implanted oxygen separation (SIMOX), wafer bonding, and / or other suitable processes. Other substrates that may be used include multilayer substrates, gradient substrates, or hybrid orientation substrates.In the embodiment, substrate 110 is a bulk silicon substrate. This means that fins 122, 132, 134, 136, and 138 are physically connected to substrate 110.

[0014] Still referring to Fig. 1, Fig. 2, Fig. 3A and Fig. 3B, the method 1000 proceeds to step 1004, where an isolation structure 140 is formed between the fins 122, 132, 134, and 138. The isolation structure 140 serves as an insulating layer or insulating layer for separating two active regions, such as epitaxy 200 in the fins 122, 132, 134, and 138. The isolation structure 140 may comprise any suitable insulating materials, such as, but not limited to, silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), fluorine-doped silicate glass, a low-k dielectric, and a combination thereof. As used herein, the term "low-k dielectric" refers to a material having a dielectric constant k less than about 3.9, which is the k value of SiO2.The insulating structure 140 may also comprise flowable material such as silicate, siloxane, methylsilsesquioxane (MSQ), hydrogen silsesquioxane (HSQ), perhydrosilazane (TCPS), perhydropolysilazane (PSZ), a tetraethylorthosilicate (TEOS), or a silylamine such as trisilylamine (TSA).

[0015] With reference to the Fig. 1, Fig. 2, Fig. 4A and Fig. 4B, the method 1000 proceeds to step 1006 by depositing a gate oxide layer 152 on the fins and a gate material layer 154 on the gate oxide layer 152. The gate oxide layer 152 may comprise LaO, AlO, ZrO, TiO, SiO2, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), AlO3, Si3N4, oxynitrides (SiON), or other suitable materials. Meanwhile, the gate material layer 154 may comprise a conductive material, such as a metal (e.g., tantalum, titanium, molybdenum, tungsten, platinum, aluminum, hafnium, ruthenium), a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, tantalum silicide), a metal nitride (e.g., titanium nitride, tantalum nitride), doped polycrystalline silicon, other conductive materials, or a combination thereof.In some embodiments, the gate oxide layer 152 and the gate material layer 154 are formed by a deposition process such as chemical vapor deposition (CVD).

[0016] With reference to the Fig. 1, Fig. 2, Fig. 5A and Fig. 5B, the method 1000 proceeds to step 1008, where a first hard mask layer 162 is deposited on the gate material layer 154 and a second hard mask layer 164 is deposited on the first hard mask layer 162. The first hard mask layer 164 and the second hard mask layer may comprise the same material or a different material selected from SiC, SiCN, SiN, TaO, TiO2, SiO2, Si3N4, SiON, any suitable material, or a combination thereof. In some embodiments, the first hard mask layer 162 and the second hard mask layer 164 are formed by a deposition process, such as chemical vapor deposition (CVD). In other embodiments, the first hard mask layer 162 may have a multi-part structure. In still other embodiments, only one hard mask layer, such as the first hard mask layer 162, is formed on the gate material layer 154.

[0017] With reference to the Fig. 1, 2, and 6A-6C, the method 1000 proceeds to step 1010, in which the second hard mask layer 164, the first hard mask layer 162, and the gate material layer 154 are etched to form gate structures 170 and 171 having two notch features. Before performing the etching process of step 1006, the first hard mask layer 162 and the second hard mask layer 164 are patterned by a suitable photolithography process to form a pattern thereon. An etching process then follows to form the gate structures 170 and 171, as well as a first hard mask 180 and a second hard mask 190 on the gate structures 170 and 171.

[0018] The etching process may include dry etching, wet etching, plasma etching, reactive ion etching, a combination thereof, or other suitable processes. The etching gas used in the etching process may include HBr, CF4, CHF3, CH4, CH2F2, N2H2, BCl3, Cl2, N2, H2, O2, He, Ar, and a combination thereof. In order for the gate structure 170 in the central region 120 and the gate structure 171 in the edge region 130 to have two notch features with a similar profile, several etching parameters must be adjusted. The etching parameters of the plasma dry etching process include etching temperature, etching pressure, source power, RF bias voltage, RF bias power, gas flow, overetch time, and other suitable parameters. In the embodiment, the gas flow is not uniform in a central region 120 and a peripheral region 130. In the embodiment, the ratio of the gas flow in the central region to the gas flow in the peripheral region is in the range between about 0.2 and about 1.In some embodiments, the ratio is less than 0.2. This means that the gas flow in the edge region 130 is greater than in the central region 120, so that an etch rate of the gate material layer 154 in the edge region 130 is similar to that in the central region 120. Note that a higher etch rate of the gate material layer 154 in the edge region 130 improves the undercut conditions in the edge region 130 compared to the conventional etching method (i.e., that the gas flow in the edge region 130 and in the central region 120 is the same) and avoids a pedestal shape that could create a short-circuit problem.

[0019] Furthermore, other parameters of the plasma dry etching process may improve the etching process of the gate material layer 154. In the embodiment, the etching pressure ranges between about 1.7 Pa and about 2.7 Pa (about 13 mTorr and about 20 mTorr). In some embodiments, the etching pressure is higher than about 2.7 Pa (20 mTorr) or lower than about 1.7 Pa (13 mTorr). In the embodiment, the RF bias voltage ranges between about 160 V and about 180 V. In some embodiments, the RF bias voltage is higher than about 180 V or lower than about 160 V. In the embodiment, the overetch time ranges between about 30 seconds and about 32 seconds. By applying these etching parameters, underetch conditions that occur in the edge region 130 in the conventional process may be improved to prevent the socket device.

[0020] In addition, by appropriately selecting parameters of an etching process, the gate structures 170 and 171 may have two notch features in a first portion and a second portion of the gate structures 170 and 171, respectively, in either a dense region or an insulating region of the central region or the edge region.

[0021] With reference to Fig. 6A, the gate structure 170 in the central region 120 includes a first portion 172 above the fin 122 and a second portion 174 that overlaps sidewalls of the fin 122. That is, the gate structure 170 is separated into two parts that are connected to each other. And the bottom surface of the first portion 172 overlaps the top surface of the second portion 174. The notch feature in the first portion 172 has a series of dimensions that include a first width (W1) at a top surface of the first portion 172 and a first height (H1) from a first surface of the first portion 172 to the fin 122.On the other hand, the notch feature in the second portion 174 has a series of dimensions including a second width (W2) at a top surface of the second portion 174, a third width (W3) at a middle position of the second portion 174, a fourth width (W4) at a bottom surface of the second portion 174, a second height (H2) from a bottom surface of the second portion 174 to the fin 122, and a third height (H3) from a middle position of the second portion 174 to the fin 122. Note that each set of the above-mentioned dimensions refers to the second width (W2), and that a relative position between any two dimensions can be calculated and determined by the mentioned definitions of the series of dimensions.

[0022] With reference to Fig. 6C, the gate structure 171 in the edge region 130 includes a first portion 173 above the fin 132 and a second portion 175 that overlaps sidewalls of the fin 132. That is, the gate structure 171 is separated into two parts that are connected to each other. And the bottom surface of the first portion 173 overlaps the top surface of the second portion 175. The notch feature in the first portion 173 includes a series of dimensions including the first width (W11) at a top surface of the first portion 173 and a first height (H11) from a top surface of the first portion 173 to the fin 132.On the other hand, the notch feature in the second portion 175 includes a series of dimensions including a second width (W12) at a top surface of the second portion 175, a third width (W13) at a middle position of the second portion 175, a fourth width (W14) at a bottom surface of the second portion 175, a second height (H12) from a bottom surface of the second portion 175 to the fin 132, and a third height (H13) from a middle position of the second portion 175 to the fin 132.

[0023] In the embodiment, the gate structure 170 and the gate structure 171 have the notch feature with the same profile (or the same range of dimensions) in the first portions 172 and 173, respectively, and the second portions 174 and 175, respectively. Furthermore, the set of the above-mentioned notch features of the gate structures 170 and 171 can be used in comparison with a predetermined criterion to obtain a quality standard related to the electrical properties of the FinFET device, which will be described further below.

[0024] With reference to the Fig. 1, 2 and 7A-7C, the method 1000 proceeds to step 1002, in which an epitaxy 200 is formed in the fins 122 and 132, respectively. The epitaxy 200 may be formed by forming a crystal structure (not shown) in a recess of the fins 122 and 132. As in Fig. 7A, there is a distance D1 between the epitaxy 200 and the second portion 174 of the gate structure 170 and a distance D2 between the epitaxy 200 and the first portion 172 of the gate structure 170. On the other hand, as shown in Fig. 7C, a distance D11 between the epitaxy 200 and the second portion 175 of the gate structure 171 and a distance D12 between the epitaxy 200 and the first portion 173 of the gate structure 171. The distances D1, D2, D11, and D12 should be precisely set to prevent short circuits from occurring. In the embodiment, the notch feature in the second portions 174 and 175 of the gate structures 170 and 171 can provide larger distances D1 and D11, so that the process window can be increased and the stability of a semiconductor device can be increased. Furthermore, a notch feature in the first portions 172 and 173 of the gate structures 170 and 171 can also provide larger distances D2 and D12, so that a problem with short circuits caused by a socket device can also be avoided.

[0025] In other embodiments, as in Fig. 8, gate structures have different widths, so that different channel lengths can be formed under gate structures for specific design requirements. As shown in Fig. 8, gate structures including a short-channel gate 770, a mid-channel gate 870, and a long-channel gate 970 are formed on a fin 822 and a gate oxide layer 852. In addition, each of the gate structures 770, 870, and 970 includes a first hard mask 780, 880, and 980, respectively, and a second hard mask 790, 890, and 990, respectively. By using the etching process with the above-mentioned specific etching parameters, the short-channel gate 770, the mid-channel gate 870, and the long-channel gate 970 may have two notch features with the same profile. More specifically, a difference between each of the set of distances of the above-mentioned Fig. 6 mentioned notch features in the short channel gate 770, medium channel gate 870 and long channel gate 970 are of the same size. For example, the difference between a first width (W771) and a second width (W772) of the short channel gate 770 is equal to the difference between a first width (W871) and a second width (W872) of the medium channel gate 870. And the difference between a second width (W772) and a third width (W773) of the short channel gate 770 is equal to the difference between a second width (W872) and a third width (W873) of the medium channel gate 870. Furthermore, the difference between a second width (W872) and a third width (W783) of the medium channel gate 870 is equal to the difference between a second width (W972) and a third width (W973) of the long channel gate 970.And the difference between a first width (W871) and a second width (W872) of the center channel gate 870 is equal to the difference between a first width (W971) and a second width (W972) of the long channel gate 970. Thus, the above-mentioned etching process with certain parameters can be used to form the same differences between two dimensions of the series of dimensions when comparing gate structures with different gate widths.

[0026] Refer now to Fig. 9, which is an exemplary flowchart for controlling the quality of a FinFET device according to an embodiment of the present disclosure. The flowchart shows only a relevant part of the overall manufacturing process. It is understood that additional operations may be performed before, during, and after the operations described in Fig. 9, and that some of the operations described below may be substituted or omitted for additional embodiments of the method. The order of the operations / methods may be reversed.

[0027] With reference to Fig. 9, the method 2000 for controlling the quality of a FinFET device begins at step 2002, in which a FinFET device is provided that includes a gate structure having a notch feature. The FinFET device may be provided by the manufacturing method 100 described above in Fig. 1. Alternatively, the FinFET device may be obtained by other embodiments. The method 2000 described here refers only to a control method without considering a source of the FinFET device.

[0028] With reference to Fig. 9, the method 2000 continues with step 2004, in which a profile of the notch feature in the gate structure is measured. The measurement method of the profile of the notch feature may be an in-line inspection. The measurement method may use a TEM method, which includes cutting the substrate including the notch feature and then performing an electron microscope scan to measure the profile of the notch feature. By taking a TEM cross-sectional image of the notch feature, each dimension of the series of dimensions described above in Fig. 6 can be obtained directly and accurately. Alternatively, the measurement method may use optical feature width inspection (OCD). The OCD measurement method includes irradiating a notch feature with an incoming electromagnetic wave, receiving a radiated electromagnetic wave from the notch feature after an interaction between the incoming electromagnetic wave and the notch feature, and obtaining the profile of the notch feature by calculating a polarization change between the incoming electromagnetic wave and the radiated electromagnetic wave. OCD inspection can be used to provide a non-destructive measurement for determining the dimension of the above-mentioned series of dimensions.

[0029] With reference to Fig. 9, the method 2000 continues with step 2006, in which the profile of the notch feature is compared with a predetermined criterion for determining the quality of the FinFET device. After the profile and each dimension of the series of dimensions described above in Fig. 6A, were determined by the method described in step 2004, the dimension in the series of dimensions of the notch feature is compared with a predetermined criterion. It should be noted that each dimension of the series of dimensions of the notch feature in Fig. 6A is used to easily and clearly examine the predetermined criterion. The predetermined criterion includes the following conditions: the first width (W1) is greater than the second width (W2); the second width (W2) is greater than the third width (W3), wherein the difference between the second width (W2) and the third width (W3) is in the range between about 0.001 nm and about 15 nm; and the first height (H1) is greater than the second height (H2), wherein the second height (H2) is in the range between about 0.001 nm and about 50 nm. Since the third height (H3) is half the second height (H2), the third height (H3) is in the range between about 0.001 and about 25 nm. Note that the fourth width (W4) is not limited in the predetermined criterion, so that a fourth width (W4) may be greater than the third width (W3) or less than the third width (W3).In the embodiment, the second portion 174 includes smooth sidewalls with an equal slope such that the fourth width (W4) is smaller than the third width (W3). Note that the criterion is applied to the notch characteristics of all gate structures in a FinFET device. Note that a half upper portion of the second portion 174 has a particular profile having a second width (W2), a third width (W3), and a third height (H3), as shown in FIG. Fig.6A. Further, the second portion 174 has a slope on one of its sidewalls. The slope is defined as the ratio of the third height (H3) to a difference between the second width (W2) and the third width (W3), and a positive slope corresponds to a slope where the second portion 174 has a second width (W2) that is greater than the third width (W3), while a negative slope corresponds to the second portion 174 having a second width (W2) that is smaller than the third width (W3). In the embodiment, the slope is in the range between 0.000067 and 25000. In some embodiments, the slope is in the range between 0.067 and 25. By adjusting the slope of the second portion 174 of the gate structure 170, the gate structure 170 operates normally and passes a WAT ​​(Wafer Acceptance Test).

[0030] Furthermore, after the dimension of the notch feature's series of dimensions meets the aforementioned predetermined criteria, elements of a subsequent wafer acceptance test (WAT) also reach a predetermined benchmark, ensuring that the electrical properties and stability of a FinFET device are good or acceptable. The elements of a WAT ​​related to a gate structure may include Rc, Cgd, Cgg, Rg, drain-induced barrier lowering (DIBL), and other test elements.

[0031] As mentioned above, a method for forming gate structures having two notch features with a similar profile is very important to improve the electrical performance and stability of a semiconductor device. It is known that conventional methods of etching a gate material layer to form gate structures may result in uncontrollable dimensions in gate structures located in different regions (e.g., central / edge regions or dense / insulating regions) of a substrate. The uncontrollable dimension of a gate structure may lead to defects such as short circuits caused by a pedestal device of a gate structure in some under-etched gate structures. Therefore, a method is needed to improve the control of the dimensions of gate structures to prevent short circuits from occurring.

[0032] A method disclosed according to the embodiments to solve the above-described problem of controlling dimensions of gate structures during an etching process of a gate material layer provides different gas flows in a central region and a peripheral region of a substrate and adjusting etching parameters such as etching pressure, bias power, and overetch time. By appropriately adjusting a gas flow and other etching parameters, all formed gate structures have two notch features with a similar profile. Further, gate structures with different gate widths also have two notch features with an equal difference between each dimension of the series of notch feature dimensions. Additionally, the series of notch feature dimensions is associated with elements of a wafer acceptance test (WAT).In other words, a series of notch feature dimensions can provide information for determining the quality of a FinFET device. That is, once the dimensions of the series of notch feature dimensions meet a predetermined criterion, the corresponding WAT results become good and acceptable. In summary, the method of the disclosure can form two notch features with a similar profile in all gate structures. And the profile (or series of dimensions) of the notch features each meets a predetermined criterion, so that a good quality FinFET device can be achieved.

Claims

[1] A method of forming a FinFET device, comprising: Forming a plurality of fins (122) lying on a substrate having a central region and a peripheral region; Depositing a gate layer (154) on the fins (122); and Plasma etching the gate layer with an etching gas to form a first gate (170) in the central region (120) and a second gate (171) in the peripheral region, wherein the first and second gates (170, 171) each have two notch features in a first portion (172) and in a second portion (174), wherein the first portion (172) overlies a fin (122) and wherein the second portion (174) overlaps the sidewalls of the fin (122), wherein the etching gas is introduced at a ratio of the flow rate in the central region to the flow rate in the peripheral region between 0.2 and 1, and wherein the first gate (170) and the second gate (171) have a similar profile, wherein the first gate is located in a region of the substrate having a first fin density and wherein the second gate is located in a region of the substrate having a second fin density that is greater than the first fin density. [2] The method according to claim 1, wherein the plasma etching is carried out by introducing the etching gas at a pressure between 1.7 Pa and 2.7 Pa. [3] The method of claim 1 or 2, wherein the plasma etching is carried out by applying an RF bias voltage in the range between about 160 V and 180 V. [4] A method according to any one of the preceding claims, wherein the plasma etching is carried out by applying an overetching time in the range between 30 s and 32 s. [5] A method according to any one of the preceding claims, wherein after plasma etching, a step for controlling the quality of a FinFET device is carried out, comprising: Measuring a profile of at least one of the notch features; and Determining the quality of the FinFET device by comparing the profile of the measured notch feature with a predetermined criterion. [6] The method of claim 5, wherein measuring the profile of the notch feature comprises: Cutting the FinFET device including the notch feature; and Perform an electron microscope scan to determine the profile of the notch feature. [7] A method according to claim 5 or 6, wherein measuring the profile of the notch feature comprises: irradiating the notch feature with an incident electromagnetic wave; Receiving a radiated electromagnetic wave from the notch feature after an interaction between the incident electromagnetic wave and the notch feature; and Determining the profile of the notch feature by calculating a polarization change between the incident electromagnetic wave and the radiated electromagnetic wave. [8] A method according to any one of claims 5 to 7, wherein measuring the profile of the notch feature consists of measuring a series of dimensions comprising: a first width at an upper surface of the second portion; a second width at a middle position of the second section; and a first height from the first width to the second width. [9] The method of claim 8, wherein determining the quality of the FinFET device consists of comparing the profile of the notch feature with a predetermined criterion comprising: the first width is greater than the second width, wherein a difference between the first width and the second width is in the range between 0.001 nm and 15 nm; and the first height is in the range between 0.001 nm and 25 nm. [10] FinFET device comprising: several fins lying on a substrate that has a central area and has a border area; and a first gate structure (170) in the central region and a second gate structure (171) in the peripheral region, wherein the first and second gate structures each have two notch features in a first portion and a second portion, wherein the first portion (172) overlies the fins (122) and wherein the second portion (174) overlaps sidewalls of a fin, wherein a profile of the two notch features comprises: a first width W1 at an upper surface of the first portion; a second width W2 at an upper surface of the second section; a third width W3 at a middle position of the second section; a fourth width W4 at a lower surface of the second section; a first height H1 from the first width to the second width; a second height H2 from the second width to the third width; and a third height H3 from the third width to the fourth width, wherein the third width is smaller than the second width and a difference between the third width and the second width is in the range between 0.001 nm and 25 nm, and; wherein the notch features of the first gate structure and the second gate structure have the same inclined profile, wherein the first gate structure is located in a region of the substrate having a first fin density and wherein the second gate structure is located in a region of the substrate having a second fin density that is greater than the first fin density. [11] The FinFET device of claim 10, wherein the first height is greater than the combination of the second height and the third height. [12] The FinFET device of claim 10 or 11, wherein the third height is in the range between 0.001 nm and 25 nm. [13] The FinFET device of any one of claims 10 to 12, wherein the first width is greater than the second width. [14] The FinFET device of any one of claims 10 to 13, wherein the gate structure comprises a gate oxide layer and a gate electrode. [15] The FinFET device of claim 14, wherein the gate oxide layer comprises a material selected from a group consisting of hafnium oxide, titanium nitride, silicon dioxide, silicon nitride, silicon oxynitride, and a combination thereof. [16] The FinFET device of claim 14 or 15, wherein the gate electrode comprises a material selected from a group consisting of polycrystalline silicon (poly-Si), polycrystalline silicon germanium (poly-SiGe), silicon nitride, and a combination thereof. [17] The FinFET device of any one of claims 10 to 16, further comprising a hard mask on the gate structure. [18] The FinFET device of claim 17, wherein the hard mask comprises a material selected from a group consisting of SiC, SiCN, SiN, TaO, TiO2, SiO2, Si3N4, SiON, and a combination thereof. [19] The FinFET device of claim 17 or 18, wherein the hard mask has a two-layer structure.

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