Participants in a bus system, operating procedures and a bus system

Abstract

Participants (100) of a bus system (1), - with a timer (140), - with a transmit-receive circuit (170), - in which the transmit-receive circuit (170) is set up to receive a data packet (P) with a timestamp value (TS1) via a bus (800), - where the timer (140) is set up for synchronization based on the timestamp value (TS1), - where the timer (140) is set up to change the timestamp value (TS1), - in which the transmit-receive circuit (170) is set up to send the data packet (P) with a changed timestamp value (TS2) via the bus (800), - in which the data packet (P) has a plurality of data symbols (S1...S12), wherein a data symbol (S1...S12) has a particularly fixed number of bits, - where the timestamp value (TS1) of the data packet (P) has a plurality of data symbols (S1...S12), and - in which the transmit-receive circuit (170) is set up to receive and send the data packet (P) symbol by symbol, such that the sending of a data symbol (S1...S12) of the data packet (P) and the receiving of a subsequent data symbol (S1...S12) of the data packet (P) take place simultaneously.

Description

[0001] The invention relates to a participant in a bus system, a method for operating a bus system and a bus system.

[0002] Synchronization methods for bus systems are known in the state of the art.

[0003] German patent DE 10 2013 020 802 A1 relates to a method for reference message-based time synchronization in a CAN network of a motor vehicle, in which a time master transmits a sync message containing timestamp information to a time slave, followed by a message to transmit the sender's timestamp information. In a method that reduces the bus load, an existing, cyclically transmitted CAN message is used as the sync message.

[0004] From DE 199 17 354 A1, a synchronization method and a corresponding communication system, as well as the main unit and auxiliary unit of such a communication system, are known. Internal timers of a main unit and at least one auxiliary unit are to be synchronized. For this purpose, the main unit transmits time signals to the auxiliary unit via two communication channels. These signals require propagation times to reach the auxiliary unit via these two communication channels. The difference in propagation times is recorded, at least in the auxiliary unit. The propagation times are then determined from this difference. The timers then synchronize themselves, taking these propagation times into account.

[0005] EP 1 368 728 B1 concerns a synchronous, clocked communication system, such as a distributed automation system, whose participants can be any automation components and which are interconnected via a data network for mutual data exchange. Any bus system, such as fieldbus, Profibus, Ethernet, Industrial Ethernet, etc., is conceivable as the data network of the communication system. One participant in the communication system is designated as the clock master and ensures the distribution and adherence to the communication clock to and from all participants. Using the same mechanism, the clock master can also introduce a relative clock throughout the entire communication system at all participants. This participant is thus also the master of the relative clock and the prevailing relative time.All participants in the communication system are therefore permanently synchronized to the system-wide relative clock with the valid relative time and thus have the same understanding of time at all times. This should significantly improve, or even make possible, the implementation of application sequences, the synchronization of simultaneously occurring events, and the temporal accuracy in event detection and output switching.

[0006] German patent DE 10 2013 218 328 B3 discloses a method for locating a frequency deviation in a communication network and a corresponding communication network. EP 2 034 642 A1 discloses a method for transmitting synchronization messages in a communication network. EP 3 087 788 B1 relates to rollover solutions for time synchronization timers.

[0007] DE 197 26 763 C2 discloses a coupling arrangement for a master-slave bus system. This master-slave bus system has a ring topology with Byqass elements. DE 10 2004 055 105 A1 relates to a method for time synchronization in a centrally operating communication system. For initialization, absolute time information is simultaneously transmitted to all participants to be synchronized.

[0008] The present invention is based on the objective of specifying a participant in a bus system that is configured for the best possible synchronization.

[0009] This problem is solved by the features of claim 1 and the features of claim 2. Advantageous further developments are specified by features of the dependent claims.

[0010] Accordingly, a participant in a bus system is equipped with a timer and a transmit / receive circuit. This participant is configured to communicate with other participants in the bus system. The timer enables the participant to perform actions at specific times, such as outputting control data to output terminals or sampling measurement data.

[0011] The transmit / receive circuit is configured to receive a data packet containing a timestamp value via a bus. The device is advantageously configured to also receive and, if necessary, send additional data packets – for example, process data – using the transmit / receive circuit. The data packet containing the timestamp value is assigned to the timer, for example, by means of an identifier.

[0012] The timer is set up for synchronization based on the timestamp value. For synchronization, for example, a time value from a time counter is adjusted to the timestamp value, possibly including an offset value, and then continues to run like a clock.

[0013] The timer is configured to change the timestamp value. To change the timestamp value, it is overwritten, for example.

[0014] The transmit-receive circuit is configured to send the data packet with a modified timestamp value over the bus. The transmitted data packet is the same as the received data packet. The device is not configured to generate a data packet with a timestamp. The same data packet that was received is sent, but with modified data.

[0015] The data packet contains a plurality of data symbols. A data symbol has a fixed number of bits. For example, a data symbol may have 4, 8, 16, or 32 bits. Advantageously, the timestamp value of the data packet contains a plurality of data symbols. The transmit-receive circuit is configured to receive and send the data packet symbol by symbol. This symbol-by-symbol reception and transmission preferably involves receiving and immediately retransmitting a data symbol, so that preferably only a fixed subset of data symbols, and in particular only one data symbol, is available for processing at any given time at the receiving device. Preferably, the symbol-by-symbol reception and transmission of the data packet occurs such that the transmission of one data symbol and the reception of a subsequent data symbol of the data packet occur simultaneously.Preferably, the subscriber's transmit-receive circuit is configured to serially receive and transmit the bits of a data symbol.

[0016] According to an advantageous further development, the participant's timer is configured to change the data symbol first received from the timestamp value with the lowest place value of the timestamp value and send it to a subsequent participant before receiving the data symbol with the highest place value of the timestamp value.

[0017] According to a preferred embodiment, the timer includes a time counter. Advantageously, the timer includes a state machine. The state machine can also be referred to as a state automaton. The state machine is advantageously configured to synchronize the time counter based on the received timestamp value. The state machine is also advantageously configured to change the timestamp value.

[0018] According to a beneficial training course, the participant has access to a non-volatile memory for storing a correction value. The change in the timestamp value is based on the stored correction value.

[0019] The present invention also aims to provide a method for operating a bus system that achieves the best possible synchronization.

[0020] This problem is solved by the features of claim 5 and the features of claim 6. Advantageous further developments are specified by features of the dependent claims.

[0021] Accordingly, a procedure for operating a bus system with a first participant and a second participant is provided.

[0022] In this method, a data packet is received and sent by the first participant. It is not necessary for the data packet to be fully received before being sent. Preferably, a first, previously received part of the data packet is sent by the first participant before a second part of the data packet is received by the first participant.

[0023] In this process, a timer of the first participant is synchronized based on a timestamp value contained in the data packet.

[0024] In this process, the timestamp value is changed by the first participant.

[0025] In this process, the changed timestamp value is sent by the first participant to a second participant via the data packet.

[0026] According to a beneficial further development, a propagation delay caused by the first participant is determined before the data packet is received by the first participant. This propagation delay is determined, for example, by an external device, by the first participant itself, and / or by another participant in the bus system. Advantageously, a correction value is calculated based on the determined propagation delay. Advantageously, this correction value is stored. Advantageously, the change in the timestamp value is based on the stored correction value.

[0027] According to an advantageous further development, the modified timestamp value is determined by a function with the received timestamp value and the correction value. Advantageously, the modified timestamp value is determined by the sum of the received timestamp value and the correction value.

[0028] The present invention also aims to provide a bus system designed for the best possible synchronization.

[0029] This problem is solved by the features of claim 10 and the features of claim 11. Advantageous further developments are specified by features of the dependent claims.

[0030] Accordingly, a bus system is provided with a first participant trained as a first slave, a second participant trained as a second slave, a master and a bus.

[0031] The master, the first slave, and the second slave are connected via the bus for the transmission of a data packet in such a way that the data packet sent by the master connects the first slave and the second slave in a fixed

[0032] The sequence is repeated. For example, the data packet first passes through the first slave and then the second slave.

[0033] The master is configured to send a timestamp value in the data packet.

[0034] The first slave is set up to receive the data packet with the timestamp value.

[0035] The first slave is set up to synchronize its timer based on the timestamp value.

[0036] The first slave is set up to change the timestamp value and send the changed timestamp value in the data packet to the second slave.

[0037] The second slave is set up to receive the data packet with the changed timestamp value and to synchronize its timer based on the changed timestamp value.

[0038] According to an advantageous embodiment, the bus system comprises a first interface device. Advantageously, the first slave can be removed from the bus system by disconnecting it from the first interface device. Advantageously, the first interface device comprises a first switching device that creates a bypass to the second slave. Thus, when the first slave is removed, the first data packet is received not by the first slave but by the second slave with an unchanged timestamp value.

[0039] According to a beneficial further development, the bus system has a number of additional slaves. Advantageously, the data packet passes through all slaves of the bus system in a fixed sequence. Advantageously, each slave is configured to change the timestamp value in the data packet and forward the changed timestamp value to the next slave in the sequence via the bus. Advantageously, the last slave in the sequence is configured to send the data packet back to the master via the bus.

[0040] According to a beneficial training module, the master unit has a master timer. Advantageously, the master unit is configured to generate the data package and determine the timestamp value based on the master timer, then input it into the data package.

[0041] According to a beneficial further development, the master has a bus interface to a higher-level bus. Advantageously, the master is configured to synchronize its master timer based on a telegram received via the higher-level bus. The telegram and the data packet are different; for example, they may use different protocols.

[0042] The invention is not limited to the features and combinations of features described above. Further features, combinations of features, and advantageous embodiments will become apparent from the following description of the figures.

[0043] This shows Fig. 1 a schematic representation of a bus system, Fig. 2 a schematic representation of a data packet and a bus system, and Fig. 3 A schematic representation of a participant in a bus system configured as a slave.

[0044] In Fig. Figure 1 is a schematic representation of bus system 1. Bus system 1 comprises a master 900 configured as a coupler, a first slave 100, a second slave 200, and several further slaves 300, 400, 500, and 600. The master 900 can also be referred to as a controller or headend. The slaves 100, 200, 300, 400, 500, and 600 can also be referred to as I / O modules. The bus system 1 in the exemplary embodiment of the Fig. 1 is designed as a master-slave bus system, with the master 900 being connected via the bus 800 to the slaves 100, 200, 300, 400, 500, 600 for the transmission of a data packet P.

[0045] In the exemplary embodiment of the Fig. 1. The data packet P sent by master 900 passes through slaves 100, 200, 300, 400, 500, 600 in a fixed sequence. In the exemplary embodiment of the Fig. Figure 1 shows that the data packet P first passes through the first slave 100, then the second slave 200, then the third slave 300, then the fourth slave 400, then the fifth slave 500, and finally the sixth slave 600 in a fixed order. If a slave is added, or if one of the existing slaves is deactivated or removed from the bus, the order changes, and the data packet P would follow a new fixed sequence. The order remains fixed as long as all slaves participating in the bus communication (100, 200, 300, 400, 500, 600) remain in place and activated.

[0046] The master 900 has a master timer 940. The master 900 is configured to generate the data packet P using a transmit-receive circuit 970 and to send it on the bus 800. The master 900 is configured to send a timestamp value TS1 in the data packet P. In the exemplary embodiment of the Fig. Figure 1 shows a schematic representation of data packet P. Data packet P has a header P1, data fields P2 and P3, and a field P4 for a check value (CRC - Cyclic Redundancy Check). Data field P3 displays the timestamp value TS1 sent by master 900.

[0047] The first slave 100 has a transmit / receive circuit 170. Furthermore, the first slave 100 has a timer 140, a memory area 150, and an input / output circuit 190. The input / output circuit 190 is connected to terminals 191 and 192 for connecting cables, fiber optics, or the like to read and / or output analog and / or digital input and / or output signals for a process. The first slave 100 also has an electrical and mechanical interface device 180 for disconnecting and connecting to the bus 800.

[0048] The other slaves 200, 300, 400, 500, 600 can be similarly or identically constructed. Each slave 100, 200, 300, 400, 500, 600 accordingly has an interface device 180, 280, 380, 480, 580, 680, a transmit / receive circuit 170, 270, 370, 470, 570, 670, a timer 140, 240, 340, 440, 540, 640, a memory area 150, 250, 350, 450, 550, 650, an input / output circuit 190, 290, 390, 490, 590, 690 and, if applicable, inputs and / or outputs 191, 192, 291, 292, 391. 392, 491, 492, 591, 592, 691, 692 for connecting external devices. The invention is not limited to the in Fig. The number of slaves shown in Figure 1 is limited to 100, 200, 300, 400, 500, 600 in bus system 1. A smaller or larger number of slaves may be required depending on the application. Fig. The lines shown are between the first master 900, the first slave 100, the second slave 200 and the third slave 300, into which further slaves (not shown) can be inserted into the bus system 1.

[0049] The data packet P sent by the master 900 reaches the first slave 100 via bus 800. The first slave 100 is configured to receive the data packet P, containing the timestamp value TS1 sent by the master 900, using the transmit-receive circuit 170. The first slave 100 has a timer 140 connected to the transmit-receive circuit 170 and is configured to synchronize its timer 140 based on the timestamp value TS1.

[0050] In the exemplary embodiment of the Fig. 1. The first slave 100 forwards the data packet P to the second slave 200 in a fixed sequence. The same data packet P remains largely unchanged between receipt and transmission. The first slave 100 is configured to modify the received timestamp value TS1 and send the modified timestamp value TS2 in the data packet P to the second slave 200. Fig. 1 shows the changed timestamp value TS2.

[0051] The first slave 100 is configured to modify the received timestamp value TS1 by using a first correction value OS1. In the simplest case, the first correction value OS1 is added to the received timestamp value TS1; the sum of the first correction value OS1 and the received timestamp value TS1 is the modified timestamp value TS2. In the exemplary embodiment of the Fig. 1 is the first correction value OS1 stored in memory area 150 of the first slave 100. For example, the correction value OS1 is already determined at the factory and stored in memory area 150, where memory area 150 is advantageously part of non-volatile memory, for example, flash memory. In another embodiment, the correction value OS1 is determined during the operation of the bus system 1. In this case, a slave 100, 200, 300, 400, 500, 600 in the bus system 1 can acquire measured values, where the measured values ​​depend, for example, on a propagation delay d19 through a transmission path 810, as is the case in Fig. Figure 3 is shown schematically. Advantageously, the measured values ​​of several slaves 100, 200, 300, 400, 500, 600 of bus system 1 are evaluated by the master 900. The master 900 determines the correction value OS1 based on the measured values ​​and transmits the correction value OS1 to slave 100. Therefore, a factory-defined correction value OS1 is not strictly necessary. However, it is preferred that a factory-defined correction value OS1 is stored in memory area 150, which is then overwritten by the master 900 with a new, more accurate correction value OS1.

[0052] The data packet P shown is the same data packet P with only the timestamp value TS2 and the checksum changed. Data packet P is passed through the first slave 100 largely unchanged, meaning it is not regenerated and therefore retains its structure, length, and packet identification. Because the first slave 100 does not need to generate a new data packet P, latencies in the transmission of the timestamp values ​​TS1 and TS2 can be minimized.

[0053] The second slave 200 is configured to receive data packet P with the modified timestamp value TS2 and to synchronize its timer 240 based on the modified timestamp value TS2. The second slave 200 is configured to modify the received timestamp value TS2 based on a second correction value OS2 in its memory area 250 and to send the modified timestamp value TS3 in data packet P to the third slave 300. Fig. Figure 1 shows the changed timestamp value TS3. The same applies in the embodiment of the Fig. 1. This also applies to the third, fourth, fifth, and sixth slaves 300, 400, 500, and 600, each of which performs a timestamp value change. Accordingly, each slave 100, 200, 300, 400, 500, and 600 is configured to change the timestamp value TS... in data packet P and forward the changed timestamp value to the next slave in sequence 200, 300, 400, 500, and 600 via bus 800. The last slave, 600, in the sequence is configured to send the data packet P back to the master 900 via bus 800. Accordingly, the same data packet P is sent by the master 900, passes through all slaves 100, 200, 300, 400, 500, 600, and finally returns to the master 900, where it is received by the master 900 via the transmit-receive circuit 970. In the exemplary embodiment of the Fig. 1. Therefore, bus 800 is designed as a ring bus.

[0054] In the exemplary embodiment of the Fig. In diagram 1, a first interface device 180 is provided. The first slave 100 can be removed from the bus system 1 by detaching it from the interface device 180. For this purpose, the interface device 180 has, for example, electrical contacts and mechanical fastening means. The first interface device also has a first switching device 871, which effects a bypass from the master 900 to the second slave 200. When the first switching device 871 is closed and thus the bypass is activated, the first data packet P, when the first slave 100 is removed, is not received by the first slave 100 but by the second slave 200 with an unchanged timestamp value TS1 (in Fig. 1 not shown). In the exemplary embodiment of the Fig. Figure 1 shows that each slave 100, 200, 300, 400, 500, 600 is associated with a switching device 871, 872, 873, 874, 875, 876.

[0055] By synchronizing the timers 140, 240, 340, 440, 540, 640 in the slaves 100, 200, 300, 400, 500, 600, a bus system time can be achieved, whereby the individual times of the timers 140, 240, 340, 440, 540, 640 of the slaves 100, 200, 300, 400, 500, 600 differ from each other by only a small error. According to measurements by the applicant, the bus system 1 described above can achieve an error of less than 10 ns.

[0056] The bus system 1 according to the embodiment of the Fig. This is frequently used to control a process. Sensors or other acquisition devices are used to determine the process state at a given point in time. Ideally, all analog and digital values ​​belonging to the process should be acquired simultaneously via inputs 191, 291, 391, etc. Accordingly, a general sampling point (GSP) is defined for all slaves 100, 200, 300, 400, 500, 600. The more precisely the timers 140, 240, 340, 440, 540, 640 of slaves 100, 200, 300, 400, 500, 600 are synchronized, the smaller the timing error between the sampling points of different slaves 100, 200, 300, 400, 500, 600. The same applies to the control of actuators via outputs 192, 292, 392, etc., whereby the output times for analog or digital output signals are based on the timers 140, 240, 340, 440, 540, 640 of the slaves 100, 200, 300, 400, 500, 600.

[0057] One advantage of the exemplary embodiment of the Fig. The feature is that the bus system 1 can be modified during operation, whereby a bypass for bus communication can be activated by means of the switching device 871, 872, 873, 874, 875, 876 assigned to each slave 100, 200, 300, 400, 500, 600, so that the bus 800 is not interrupted when a slave, e.g., 100, is removed from the bus 800. If, for example, the first slave 100 is removed and the bypass is activated by closing the switching device 871, the data packet P with the timestamp value TS1 travels directly from the master 900 to the second slave 200. Thus, the data packet P reaches the second slave 200 earlier, almost completely eliminating the propagation delay for the data packet P caused by the first slave 100. At the same time, however, the change in the timestamp value TS1 by the first slave 100 is also eliminated, whereby the runtime delay and the change in the timestamp value TS1 ideally cancel each other out almost completely.Accordingly, even after the removal of the first slave 100 during operation, the second slave 200 receives the correct timestamp value, so that the Global Sampling Point remains unchanged for all remaining slaves 200, 300, 400, 500, and 600, minimizing errors and discontinuities in the process. When a slave is added to bus 800, the added slave causes a propagation delay of the data packet P. If a correction value corresponding to the propagation delay is stored in the memory area of ​​the added slave, the received timestamp value is immediately modified by the correction value, so that the propagation delay and the change in the timestamp value largely or ideally completely cancel each other out. In this case as well, errors and discontinuities in the process are minimized.

[0058] In the exemplary embodiment of the Fig. In the first embodiment, the master 900 has a master timer 940. The master 900 is configured to generate the data packet P and determine the timestamp value TS1 based on the master timer 940 and insert it into the data packet P. Since only the master 900 is configured to generate the data packet P, any delay caused by the start of the data packet P and, if applicable, the insertion of the timestamp value TS1 during the determination of the timestamp value TS1 can be directly taken into account by the master 900. If the master 900 also operates as a programmable logic controller (PLC) without being connected to a higher-level bus, the master 900 can independently set the bus system time in the master timer 940. In the exemplary embodiment of the Fig. However, it is provided that the master 900 has an additional transmit / receive circuit 980 for communication via a higher-level bus 700. The higher-level bus 700 can also be referred to as a fieldbus. The higher-level bus 700 is, for example, configured as ProfiNet, EthernetCAT, Industrial Ethernet, etc.

[0059] In the exemplary embodiment of the Fig. The master 900 is configured to synchronize its master timer 940 based on a telegram received via the higher-level bus 700 (not shown). The telegram is, for example, an Ethernet telegram and therefore independent of the data packet P. Accordingly, the telegram and the data packet P are different and are generated by different devices. The protocols of the telegram and the data packet P can also differ.

[0060] Fig. Figure 2 shows another embodiment of a bus system 1 with a schematic representation of a data packet P. The data packet P has a head P1 to be transmitted at the beginning, two data fields P2 and P3, and a tail P4, for example containing a CRC check value. The data packet P is transmitted in data symbols S1 to S12, each consisting of 16 bits. The data symbols S1 to S12 are transmitted in a fixed sequence, wherein in the embodiment the Fig. 2. The transmission begins with the first data symbol S1 and ends with the last data symbol S12. The data symbols S7, S8, S9, and S10 comprise a timestamp value, with data symbol S7 representing the least significant bit (LSB) and data symbol S10 representing the most significant bit (MSB) of the timestamp value.

[0061] It is shown in Fig. 2 also the bus system 1 with a master 900 with a transmit-receive circuit 970. The bus system 1 in the exemplary embodiment of the Fig. Figure 2 shows three slaves 100, 200, and 300. Each slave 100, 200, and 300 has a transmit-receive circuit 170, 270, and 370 for transmitting the data packet P over bus 800. For transmission, slaves 100, 200, and 300 are configured to forward the data packet P through them in a fixed sequence. In the exemplary embodiment of the Fig. 2 is the fixed sequence, first slave 100, then second slave 200, then third slave 300, shown as an example.

[0062] At any given moment, only a portion of the data packet P is in one of the slaves 100, 200, or 300, while a preceding portion of the data packet P is already in the subsequent slave. In this exemplary embodiment, the portions of the data packet P comprise... Fig. 2 a number of data symbols S1 to S12. In Fig. Figure 2 shows, as an example for a given moment, that the sixth data symbol S6 in the transmit-receive circuit 370 of the third slave 300, the following seventh data symbol S7 with the lowest place value (LSB) of the timestamp value in the transmit-receive circuit 270 of the second slave 200, and the eighth data symbol S8 in the transmit-receive circuit 170 of the first slave 100. Accordingly, each slave 100, 200, and 300 is configured to modify the first data symbol received from the timestamp value, S7, with the lowest place value (LSB), and send it to a subsequent participant, here the third slave 300, before receiving the data symbol S10 with the highest place value (MSB).

[0063] The data symbols S1 to S5 are already included in the following, in Fig. 2 slaves not shown. The ninth data symbol S9 is in the transmit-receive circuit 970 of the master 900. The remaining data symbols S10 to S12 are located in registers of the master 900 (not shown). For illustration, the aforementioned data symbols S6 to S9 are linked by dashed arrows to the data symbols S6 to S9 schematically represented in the transmit-receive circuits 970, 170, 270, and 370.

[0064] If the data packet P is subsequently transmitted, the ninth data symbol S9 travels from the transmit-receive circuit 970 of the master 900 to the transmit-receive circuit 170 of the first slave 100, the eighth data symbol S8 from the transmit-receive circuit 170 of the first slave 100 to the transmit-receive circuit 270 of the second slave 200, and so on. Each transmit-receive circuit 170, 270, 370 of the slaves 100, 200, 300 is thus configured to receive and transmit the data packet P symbol by symbol. The sending of a data symbol S1 ... S12 of the data packet P and the receiving of a subsequent data symbol of the data packet P occur in the exemplary embodiment of the Fig. 2 at the same time.

[0065] In the Fig. At the instantaneous point in time shown in Figure 2, the seventh data symbol S7 with the LSB is currently being changed by the timer 240 of the second slave 200. The change is based on the correction value OS2, which is stored in memory area 250 of the second slave. The seventh data symbol S7 was previously changed by the first slave 100 (in Fig. (2 not shown). The modified timestamp value is determined by a function using the received timestamp value and the correction value OS1, OS2, OS3, etc. In the simplest case, the modified timestamp value is determined by the sum of the received timestamp value and the correction value OS1, OS2, OS3. Of course, other, more complex functions are also possible in principle. In the exemplary embodiment of the Fig. 2. The data packet P has a plurality of data symbols S1 to S15, each data symbol S1 to S15 having a fixed number of 16 bits. Alternatively, the data symbols can also have another fixed number of, for example, 8 or 32 bits (in Fig. 2 not shown).

[0066] In Fig. Figure 3 schematically depicts a participant 100 of a bus system. Participant 100 has a timer 140 and a transmit / receive circuit 170. In the exemplary embodiment of the Fig. Participant 100 also has a plurality of computing circuits 110, 120, 130, in particular state machines for communication and / or for packet processing of data packets of different types, for example, to receive, process, or send process data. The transmit-receive circuit 170 is configured to receive a data packet P with a timestamp value TS1 via bus 800. The timer 140 is configured for synchronization based on the timestamp value TS1. In addition, the timer 140 is configured to change the timestamp value TS1 to a modified timestamp value TS2. The transmit-receive circuit 170 is configured to send the data packet P with the modified timestamp value TS2 via bus 800.

[0067] In the exemplary embodiment of the Fig. The timer 140 of participant 100 has a time counter 146. The time counter 146 outputs the time as a digital value, for example, in nanoseconds. Furthermore, the timer 140 has a state machine 145. The state machine 145 is connected to and configured with the time counter 146 to synchronize the time counter 146 based on the received timestamp value TS1. The data packet P also contains a speed value V, which is received with the data packet P and used by the state machine 145 of the timer 140 to set the speed of the time counter 146. For example, the speed value V can be used to set a counting increment of the time counter 146.

[0068] The state machine 145 is also connected to and configured with a memory area 150 to modify the received timestamp value TS1. In the exemplary embodiment, the memory area is... Fig. 3. Component of a non-volatile memory for storing a correction value OS1 on which the change of the received timestamp value TS1 is based. The state machine 145 is, in the exemplary embodiment of the Fig. The system is configured to add the correction value OS1 to the received timestamp value TS1. The sum of these additions is inserted into the data packet P to be sent as the modified timestamp value TS2, for example, by overwriting the received timestamp value TS1 with the modified timestamp value TS2.

[0069] In connection with participant 100, it is in Fig. Figure 3 shows a schematic timing diagram with time t and delays d10 and d19. When the data packet P arrives at the input of the transmit-receive circuit 170 of participant 100, it experiences a propagation delay d until the same data packet P arrives at an input of the subsequent participant 200. The total propagation delay d attributable to participant 100 is the sum of the propagation delay d10 caused by the processing of the data packet P by circuits of participant 100 and the propagation delay d19 caused by the physical transmission path 810 to the next participant 200.

[0070] The propagation delay d caused by participant 100 should be determined before the data packet P is received. For example, the propagation delay d is determined during manufacturing or factory configuration and stored in participant 100. Alternatively, the propagation delay d can be determined during operation or during setup of the bus system. For example, the propagation delay d is determined by the participant itself, by another participant in the bus system, or by a separate device (in Fig. (3 not shown). After determining the propagation delay d, a correction value OS1 is calculated based on this delay. In the simplest case, the correction value OS1 corresponds to the determined propagation delay d. Depending on the design of the physical transmission path 810, for example, a number of other values ​​or factors can be incorporated into the calculation of the correction value OS1. The correction value OS1 is stored in memory area 150 and can be read by the timer 140. Memory area 150 is, for example, a register within an ASIC or FPGA. If the correction value OS1 is stored in the memory area, the change in the timestamp value TS1 for each received data packet P with timestamp value TS1 is based on the stored correction value OS1.

[0071] In the case of a Slave 100 according to the embodiment of the Fig. Figure 1 proposes that the slave 100 has a clock synchronization unit (not shown) for clock synchronizing a clock generator (not shown) to the clock signal of the superior master 900. This clock synchronization unit is then configured to detect transitions in the downstream data stream received at the downstream data bus input, to regulate the frequency of the internal clock signal depending on the detected transitions, and to set a defined phase relationship between the internal clock signal and the detected transitions. A transition, as defined in the embodiment of Figure 1, is defined as... Fig. 1. A transition is defined as any characteristic signal change in the data stream that can be used to synchronize the clock generator with the clock signal of the higher-level master 900. In practice, these transitions are preferably signal edges of a digital signal when changing, for example, from a low signal level to a high signal level, i.e., when changing from a digital zero to a digital one or vice versa. However, other characteristic signal patterns can also be used as transitions, provided their signal timing can be determined with the accuracy required for synchronization.

[0072] This allows characteristic signal changes in a downstream data stream, which is passed from the higher-level master 900 to slave 100 and thus received by slave 100, to be detected. Based on the detected transitions, a defined phase angle of the internal clock signal is then set relative to the detected transitions. This means that the timing of a characteristic signal change in the downstream data stream provides the basis for clock synchronization of the clock generator, such that the detected time of a transition is taken as the clock synchronization point, to which the phase angle of the internal clock signal is adjusted.

[0073] The synchronization device measures the phase of the transitions in the downstream data stream relative to the slave's internal clock and adjusts the frequency of the slave's internal clock so that it corresponds as closely as possible to the clock signal embedded in the downstream data bus signal, resulting in a defined phase relationship between the edge transitions in the downstream data bus stream and the slave's internal clock. The transitions detected in the downstream data stream are thus used as clock synchronization information to adjust the slave's internal clock signal.

[0074] Compared to a separate synchronization message or synchronization line, the proposed clock synchronization based on the downstream data stream of a higher-level master 900 has the advantage that each slave 100, 200, 300, 400, 500, 600 of a more complex bus system 1 can synchronize its slave clock generators (in Fig. (1 not shown) then always synchronize their clocks with their adjacent preceding slaves 100, 200, 300, 400, 500, and as a result, all slaves 100, 200, 300, 400, 500, 600 in a network, regardless of the wiring configuration and without problems caused by propagation delays or a separate clock synchronization line, establish the exact same frequency of their internal clock generators. Only the phase relationship between the clocks is undefined due to propagation delays on lines 810 and latencies of slaves 100, 200, 300, 400, 500, 600. Since each slave 100, 200, 300, 400, 500, 600 synchronizes the clock of its receiver to the edges in the incoming data stream and the phase of the clock in the transmitter of the superior master 900 does not matter, a different phase of the clocks of the slaves 100, 200, 300, 400, 500, 600 in bus system 1 does not pose a problem.

[0075] It is particularly advantageous if the data bus interface is bidirectional and also has an upstream data bus output for sending data to a higher-level Master 900. The Slave 100, 200, 300, 400, 500, 600 is thus configured not only to receive data from a higher-level Master 900 in the downstream data stream but also to send data back to the higher-level Master 900 in the upstream data stream. For example, each Slave 100, 200, 300, 400, 500, 600 has a phase correction unit (in Fig. (1 not shown) for detecting transitions in the data stream received from the adjacent slave via the upstream data bus input (not shown) and for delaying this upstream data stream depending on the detection, such that a defined phase angle of the internal clock signal relative to the transitions of the delayed data stream is set. The phase correction unit can determine the phase angle of the data stream received at the upstream data bus input, e.g., using a delay line, and output the data stream after phase correction via its upstream data bus output to another slave or to the Master 900.

[0076] Since the clock frequency of the internal clock generator, i.e., the frequency and phase of the internal clock signal, is already set to the first downstream data stream, it is not possible to set the clock generator for the upstream data stream to match the upstream data stream. Therefore, it is proposed instead to use the phase correction unit to delay the received upstream data stream in the slave 100, 200, 300, 400, 500, 600 (i.e., in the receiver) so that a defined phase relationship is established between the internal clock signal set for the downstream data stream and the upstream data stream. This ensures that the upstream data stream received by the adjacent slave is also clock-synchronized with the downstream data stream received by the master 900, and that the clock frequency and phase are aligned.

[0077] The delay of the upstream data stream can be achieved, for example, by inserting delay elements (in Fig. (1 not shown) or data is transferred to the upstream data stream. It is advantageous if the data stream itself is not modified, but rather an electrical delay of the data signal is introduced, for example, using delay elements connected in series. Such delay elements can be, for example, look-up tables (LUTs) in an FPGA (Field Programmable Gate Array) or gates in an ASIC (Custom Integrated Circuit). The clock synchronization unit and the phase correction unit can be implemented as separate hardware circuits. However, it is also conceivable that the clock synchronization unit and the phase correction unit are implemented as software logic, running on shared or separate hardware platforms such as microcontrollers, processors, or FPGAs.

[0078] The clock synchronization unit and / or the phase correction unit are preferably configured to set a defined phase angle in the range of 90° to 270°, and preferably in the range of approximately 180°. The defined phase angle should be set such that the sampling of the data signal can be ensured as error-free as possible. In serial data transmission within a data stream, signal steepness, transient responses, and phase jitter often need to be considered, which prevent signal sampling immediately after a signal change. The most reliable sampling of a serial data signal is therefore ensured precisely between the activation and deactivation of a high and / or low data signal, i.e., exactly between the switching points or transitions of a data word; this corresponds to a phase angle of 180°.

[0079] The method for clock synchronization of participants 100, 200, 300, 400, 500, 600 of a bus system 1 has the following steps: - Receiving a downstream data stream from a preceding participant 100, 200, 300, 400, 500, 600 by a following participant 100, 200, 300, 400, 500, 600 via a downstream data bus input; - Detecting transitions in the downstream data stream received at the downstream data bus input; - Clock synchronization of an internal clock signal of a clock generator (in Fig. (1 not shown) of the subsequent participant 100, 200, 300, 400, 500, 600 depending on the detected transitions and - setting a defined phase angle of the clock-synchronized internal clock signal to the detected transitions. Preferably in the exemplary embodiment of the Fig. 1. It is therefore provided that both the clock synchronization of an internal clock signal of a clock generator of slaves 100, 200, 300, 400, 500, 600 is carried out, and a timer 140 can also be synchronized by a received timestamp value TS1. In the exemplary embodiment, this allows the Fig. 1. A particularly precise synchronization of the timers 140 in all slaves 100, 200, 300, 400, 500, 600 is achieved. Reference symbol list 1 bus system 100, 200, 300, 400, 500, 600 participants, Slave 110, 120, 130 State-Machine, computing circuit 140, 240, 340, 440, 540, 640 timers 145 State-Machine / Automat 146 time counters 150, 250, 350, 450, 550, 650 Memory area, registers 170, 270, 370, 470, 570, 670 Transceiver Circuit 180, 280, 380, 480, 580, 680 interface, electrical and mechanical 190, 290, 390, 490, 590, 690 Input-Output Circuit 191, 192, 291, 292, 391, 392, 491, 492, 591, 592, 691, 692 connection 700 main bus, fieldbus 800 bus, local bus 810 physical transmission path, line 871, 872, 873, 874, 875, 876 Switching device 900 Master, coupler 940 Master Timer 970, 980 Transceiver Circuit P data packet P1, P2, P3, P4 Data packet fields TS1, TS2, TS3 timestamp value OS1, OS2, OS3 Correction value S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12 data symbol V speed LSB Least Significant Bit MSB Highest Significant Bit d, d10, d19 propagation delay t time

Claims

[1] Participants (100) of a bus system (1), - with a timer (140), - with a transmit-receive circuit (170), - in which the transmit-receive circuit (170) is set up to receive a data packet (P) with a timestamp value (TS1) via a bus (800), - where the timer (140) is set up for synchronization based on the timestamp value (TS1), - where the timer (140) is set up to change the timestamp value (TS1), - in which the transmit-receive circuit (170) is set up to send the data packet (P) with a changed timestamp value (TS2) via the bus (800), - in which the data packet (P) has a plurality of data symbols (S1...S12), wherein a data symbol (S1...S12) has a particularly fixed number of bits, - where the timestamp value (TS1) of the data packet (P) has a plurality of data symbols (S1...S12), and - in which the transmit-receive circuit (170) is set up to receive and send the data packet (P) symbol by symbol, such that the sending of a data symbol (S1...S12) of the data packet (P) and the receiving of a subsequent data symbol (S1...S12) of the data packet (P) take place simultaneously. [2] Participants (100) of a bus system (1), - with a timer (140), - with a transmit-receive circuit (170), - in which the transmit-receive circuit (170) is set up to receive a data packet (P) with a timestamp value (TS1) via a bus (800), - where the timer (140) is set up for synchronization based on the timestamp value (TS1), - where the timer (140) is set up to change the timestamp value (TS1), - in which the transmit-receive circuit (170) is set up to send the data packet (P) with a changed timestamp value (TS2) via the bus (800), - in which the data packet (P) has a plurality of data symbols (S1...S12), wherein a data symbol (S1...S12) has a particularly fixed number of bits, - where the timestamp value (TS1) of the data packet (P) has a plurality of data symbols (S1...S12), and - in which the transmit-receive circuit (170) is configured to receive and transmit the data packet (P) symbol by symbol, in particular such that the sending of a data symbol (S1...S12) of the data packet (P) and the receiving of a subsequent data symbol (S1...S12) of the data packet (P) take place simultaneously, - wherein the participant (100) is configured to modify the data symbol (S7) first received from the timestamp value (TS1) with a lowest place value (LSB) of the timestamp value (TS1) and send it to a subsequent participant (200) before receiving the data symbol (S10) with a highest place value (MSB) of the timestamp value (TS1). [3] Participants (100) according to any of the preceding claims, - in which the timer (140) has a time counter (146), - in which the timer (140) has a state machine (145) which is set up to synchronize the time counter (146) based on the received timestamp value (TS1) and to change the timestamp value (TS1). [4] Participants (100) according to any of the preceding claims, - with a particularly non-volatile memory area (150) for storing a correction value (OS1) on which the change of the timestamp value (TS1) is based. [5] Method for operating a bus system (1) with a first participant (100) and a second participant (200), - in which a data packet (P) is received and sent by the first participant (100), - where a timer (140) of the first participant (100) is synchronized based on a timestamp value (TS1) contained in the data packet (P), - where the timestamp value (TS1) is changed by the first participant (100), and - where the changed timestamp value (TS2) is sent by the first participant (100) to a second participant (200) via the data packet (P), - in which the data packet (P) has a plurality of data symbols (S1...S12), wherein a data symbol (S1...S12) has a particularly fixed number of bits, - where the timestamp value (TS1) of the data packet (P) has a plurality of data symbols (S1...S12), and - in which the data packet (P) is received and sent symbol by symbol by symbol by the first participant (100), such that the sending of a data symbol (S1...S12) of the data packet (P) and the receiving of a subsequent data symbol (S1...S12) of the data packet (P) occur simultaneously. [6] Method for operating a bus system (1) with a first participant (100) and a second participant (200), - in which a data packet (P) is received and sent by the first participant (100), - where a timer (140) of the first participant (100) is synchronized based on a timestamp value (TS1) contained in the data packet (P), - where the timestamp value (TS1) is changed by the first participant (100), and - where the changed timestamp value (TS2) is sent by the first participant (100) to a second participant (200) via the data packet (P), - in which the data packet (P) has a plurality of data symbols (S1...S12), wherein a data symbol (S1...S12) has a particularly fixed number of bits, - where the timestamp value (TS1) of the data packet (P) has a plurality of data symbols (S1...S12), and - in which the data packet (P) is received and sent symbol by symbol by symbol by the first participant (100), in particular such that the sending of a data symbol (S1...S12) of the data packet (P) and the receiving of a subsequent data symbol (S1...S12) of the data packet (P) occur simultaneously, - wherein the first participant (100) is configured to modify the data symbol (S7) received first from the timestamp value (TS1) with a lowest place value (LSB) of the timestamp value (TS1) and send it to the second participant (200) before receiving the data symbol (S10) with a highest place value (MSB) of the timestamp value (TS1) [7] Method according to claim 5 or 6, - where a runtime delay (d10) caused by the first participant (100) is determined before the data packet (P) is received, - where a correction value (OS1) is determined based on the calculated runtime delay (d10), - where the correction value (OS1) is stored, and - where the change in the timestamp value (TS1) is based on the stored correction value (OS1). [8] Method according to claim 7, - in which, prior to the receipt of the data packet (P), a further propagation delay (d19) caused by a transmission path (810) between the first participant (100) and the second participant (200) is determined, and - where the correction value (OS1) is determined based on the runtime delay (d10) and the further runtime delay (d19). [9] Method according to claim 5, 6, 7 or 8, - where the modified timestamp value (TS2) is determined by a function with the received timestamp value (TS1) and the correction value (OS1), in particular by a sum of the received timestamp value (TS1) and the correction value (OS1). [10] Bus system (1) - with a first participant trained as the first slave (100), - with a second participant trained as a second slave (200), - with a Master (900) and - by bus (800), - in which the master (900) and the first slave (100) and the second slave (200) are connected via the bus (800) for the transmission of a data packet (P) such that the data packet (P) sent by the master (900) passes through the first slave (100) and the second slave (200) in a fixed order, - where the master (900) is configured to send a timestamp value (TS1) in the data packet (P), - where the first slave (100) is set up to receive the data packet (P) with the timestamp value (TS1), - where the first slave (100) is set up to synchronize its timer (140) based on the timestamp value (TS1), - where the first slave (100) is configured to change the timestamp value (TS1) and send the changed timestamp value (TS2) in the data packet (P) to the second slave (200), - where the second slave (200) is configured to receive the data packet (P) with the changed timestamp value (TS2) and to synchronize its timer (240) based on the changed timestamp value (TS2), - in which the data packet (P) has a plurality of data symbols (S1...S12), wherein a data symbol (S1...S12) has a particularly fixed number of bits, - where the timestamp value (TS1) of the data packet (P) has a plurality of data symbols (S1...S12), and - in which the data packet (P) is received and sent symbol by symbol by symbol by the first slave (100), such that the sending of a data symbol (S1...S12) of the data packet (P) and the receiving of a subsequent data symbol (S1...S12) of the data packet (P) occur simultaneously. [11] Bus system (1) - with a first participant trained as the first slave (100), - with a second participant trained as a second slave (200), - with a Master (900) and - by bus (800), - in which the master (900) and the first slave (100) and the second slave (200) are connected via the bus (800) for the transmission of a data packet (P) such that the data packet (P) sent by the master (900) passes through the first slave (100) and the second slave (200) in a fixed order, - where the master (900) is configured to send a timestamp value (TS1) in the data packet (P), - where the first slave (100) is set up to receive the data packet (P) with the timestamp value (TS1), - where the first slave (100) is set up to synchronize its timer (140) based on the timestamp value (TS1), - where the first slave (100) is configured to change the timestamp value (TS1) and send the changed timestamp value (TS2) in the data packet (P) to the second slave (200), - where the second slave (200) is configured to receive the data packet (P) with the changed timestamp value (TS2) and to synchronize its timer (240) based on the changed timestamp value (TS2), - in which the data packet (P) has a plurality of data symbols (S1...S12), wherein a data symbol (S1...S12) has a particularly fixed number of bits, - where the timestamp value (TS1) of the data packet (P) has a plurality of data symbols (S1...S12), and - in which the first slave (100) is configured to receive and send the data packet (P) symbol by symbol, in particular such that the sending of a data symbol (S1...S12) of the data packet (P) and the receiving of a subsequent data symbol (S1...S12) of the data packet (P) take place simultaneously, - wherein the first slave (100) is configured to modify the data symbol (S7) received first from the timestamp value (TS1) with a lowest place value (LSB) of the timestamp value (TS1) and send it to the second slave (200) before receiving the data symbol (S10) with a highest place value (MSB) of the timestamp value (TS1). [12] Bus system (1) according to claim 10 or 11, - with a first interface device (180), wherein the first slave (100) can be removed from the bus system (1) by detaching it from the interface device (180), - in which the first interface device (180) has a first switching device (871) which provides a bypass to the second slave (200) so that the data packet (P) is not received by the first slave (100) but by the second slave (200) with an unchanged timestamp value (TS1) when the first slave (100) is removed. [13] Bus system (1) according to any one of the preceding claims 10 to 12, - with a number of additional slaves (300, 400, 500, 600), - in which the data packet (P) passes through all slaves (100, 200, 300, 400, 500, 600) of the bus system (1) in a fixed sequence, - where each slave (100) is configured to change the timestamp value (TS1) in the data packet (P) and to forward the changed timestamp value (TS2) to the next slave (200-600) in sequence via the bus (800), - where the last slave (600) in the sequence is set up to send the data packet (P) back to the master (900) via the bus (800). [14] Bus system (1) according to any one of the preceding claims 10 to 13, - in which the master (900) has a master timer (940), - where the master (900) is set up to generate the data packet (P) and determine the timestamp value (TS1) based on the master timer (940) and enter it into the data packet (P). [15] Bus system (1) according to claim 14, - in which the master (900) has a transmit-receive circuit (980) to a higher-level bus (700), - in which the master (900) is set up to synchronize its master timer (940) based on a telegram received via the higher-level bus (700).

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