Planar and non-planar FET-based devices for protection against electrostatic discharge

Abstract

ESD protection device with: a source area (108, 118) that is connected to a first potential (VSS); a first drain area (110, 120) which is associated with a second potential that is different from the first potential; an extended drain area between the source area (108, 118) and the first drain area (110, 120), wherein the extended drain area has the following: N electrically floating doped regions (730, 734), and M gate areas (732, 736) connected to the second potential, wherein N and M are integers greater than 1, and one or more electrically floating doped regions of the N electrically floating doped regions (730, 734) alternate with one or more gate regions of the M gate regions (732, 736); a first tub area with a first conductivity type; and a second tub area with a second conductivity type that differs from the first conductivity type, wherein the source region, the first drain region and the N electrically floating doped regions have the second conductivity type, the source area is located in the first tub area, and the first drain area and an electrically floating doped area of ​​the N electrically floating doped areas are arranged in the second trough area.

Description

Background of the invention

[0001] This invention relates generally to electrostatic discharge protection devices for integrated circuits (ICs).

[0002] Electrostatic discharge (ESD) events can severely damage electronic components containing integrated circuits. During an ESD event, a large amount of heat is generated in a small area, requiring rapid dissipation to prevent damage to the IC. An ESD event is a momentary buildup of significant electrical potential, generally caused by direct or indirect contact with an electrostatic field. An ESD event harmful to an IC can be caused by various factors, such as contact with a person or machine, such as test fixtures or other electrical components that are not properly grounded. ESD protection devices are incorporated into various electronic devices to prevent damage to ICs.

[0003] The trend toward smaller and faster circuits has increased the vulnerability of an integrated circuit to ESD events and the complexity of designing effective ESD protection devices.

[0004] US 2015 / 0 348 967 A1 discloses semiconductor devices and manufacturing and design methods therefor.

[0005] US 2005 / 0 242 399 A1 discloses a semiconductor circuit comprising a semiconductor substrate, a semiconductor component having a drain region arranged in the substrate and a laterally adjacent and laterally contacting reverse-doped region, wherein the reverse-doped region has an opposite doping type from that of the drain region and a dopant concentration that is higher than that of the semiconductor substrate, the reverse-doped region and the drain can form a pn junction.

[0006] US 2014 / 0 139 957 A1 discloses: An electrical protection device for integrated circuits comprising a semiconductor substrate and first, second and third doped regions of a first polarity in the semiconductor substrate.

[0007] US 6 236 073 B1 discloses another electrostatic discharge protection circuit formed on a substrate.

[0008] The invention provides an ESD protection device according to claims 1 and 2. Embodiments are specified in the dependent claims. Short description of the drawings

[0009] Aspects of the present invention can best be understood from the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of various elements may be exaggerated or reduced as desired. The Fig. 1 and Fig. 2 are a plan view and a sectional view of an ESD protection device not according to the invention. Fig. 3 is an equivalent circuit diagram of the ESD protection device of the Fig. 1 and Fig. 2. Fig. 4 is a circuit diagram of a PMOS-based ESD protection device not according to the invention. The Fig. 5 and Fig. 6 are plan views of a FinFET-based ESD protection device not according to the invention. The Fig. 7 and Fig. 8 are a top view and a cross-sectional view, respectively, of an exemplary drain-extended NMOS-based ESD protection device. Fig. Figure 9 is a cross-sectional view of an exemplary drain-extended PMOS-based ESD protection device. Fig. Figure 10 is a top view of an exemplary drain-extended FinFET-based ESD protection device. The Fig. 11 and Fig. 12 are a top view and a cross-sectional view, respectively, of an exemplary drain-extended stacked NMOS-based ESD protection device. Fig. 13 is an equivalent circuit diagram of the exemplary ESD protection device of the Fig. 11 and Fig. 12. Fig. Figure 14 is a top view of an exemplary drain-extended stacked FinFET-based ESD protection device. The Fig. 15 and Fig. 16 are a top view and a cross-sectional view, respectively, of an exemplary drain-extended NMOS-based ESD protection device. The Fig. 17 and Fig. 18 are a top view and a cross-sectional view, respectively, of an exemplary drain-extended stacked NMOS-based ESD protection device. Fig. Figure 19 is a top view of an exemplary drain-extended FinFET-based ESD protection device. Fig. Figure 20 is a cross-sectional view of an exemplary drain-extended PMOS-based ESD protection device. Fig. Figure 21 is a circuit diagram of an exemplary NMOS-based ESD protection device. Fig. Figure 22 is a circuit diagram of an exemplary NMOS-based ESD protection device with ballast resistors. Fig. 23 is a top view of the exemplary NMOS-based ESD protection device of Fig. 22.

[0010] Illustrative embodiments are described below with reference to the accompanying drawings. In the drawings, similar reference symbols generally indicate identical, functionally similar, and / or structurally similar elements. Detailed description

[0011] The following description provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to facilitate the present invention. For example, in the following description, the fabrication of a first element over or on a second element may include embodiments in which the first and second elements are formed in direct contact, and it may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements are not in direct contact. Here, the fabrication of a first element on a second element means that the first element is fabricated in direct contact with the second element.Furthermore, reference numerals and / or letters may be repeated in the various examples throughout the present invention. This repetition does not, in itself, dictate any relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structure to one or more other elements or structures illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0013] It should be noted that in the specification, reference to "one embodiment," "an exemplary embodiment," "exemplary," etc., means that the described embodiment may include a particular element, structure, or characteristic, but not every embodiment necessarily includes that particular element, structure, or characteristic. Furthermore, such phrases may not necessarily refer to the same embodiment. In addition, one skilled in the art will appreciate that if a particular element, structure, or characteristic is described in connection with one embodiment, that element, structure, or characteristic will also be effected in connection with other embodiments, whether explicitly described or not.

[0014] It should be clear that the phraseology or terminology is for the purpose of description and not limitation, so that the phraseology or terminology of this description should be interpreted by persons skilled in the art in the light of the principles.

[0015] The term “approximately” used here indicates that the value of a given quantity varies by ±10% of the value unless otherwise stated.

[0016] The term "substrate" as used herein refers to a material onto which successive layers of material are applied. The substrate itself can be patterned, and the materials applied to it can also be patterned or not. Furthermore, a "substrate" can encompass a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be electrically non-conductive, such as a glass or sapphire wafer.

[0017] The term “vertical” as used here means nominally perpendicular to the surface of a substrate.

[0018] The p-wells described here can be fabricated by doping a substrate with p-dopants, unless otherwise stated.

[0019] The n-wells described here can be fabricated by doping a substrate with n-dopants, unless otherwise stated. overview

[0020] This invention provides various exemplary configurations of planar and non-planar FET-based ESD protection devices that have improved performance over conventional FET-based ESD protection devices. For example, the ESD protection devices disclosed herein offer higher turn-on uniformity, higher drive current, larger volume for faster heat dissipation during an ESD event, and lower leakage current in the off-state of the ESD protection devices compared to conventional ESD protection devices. Furthermore, the FinFET-based ESD protection devices disclosed herein have extended drain areas that meet the minimum poly-poly spacing requirement in the restrictive design rules (RDRs) in semiconductor manufacturing technology. Examples of ESD protection devices, hereinafter also referred to as ESD-protected components

[0021] Fig. 1 is a top view of an exemplary NMOS device 100 with ESD protection (NMOS: n-channel metal oxide semiconductor) in an IC. Fig. 2 is a sectional view of the device 100 with ESD protection of Fig. 1. Fig. 1-14 serve to explain the invention, but are not themselves according to the invention.

[0022] The ESD protection device 100 includes a p-well 104 on a p-substrate 102, shallow trench isolation (STI) regions 106, NMOS transistors M1 and M2 connected in parallel, parasitic npn transistors Q1 and Q2, and parasitic resistors R1 and R2. Transistor M1 includes n+-doped regions 108 and 110 formed in the p-well 104 and a gate 112 formed on the p-well 104. In some embodiments, the p-well 104 is optional, and the n+-doped regions 108 and 110 are formed in the p-substrate 102. The n+-doped region 108 can be configured as a source region and connected to a supply voltage line VSS, and the n+-doped region 110 can be configured as a drain region and connected to a pad of the IC. In some embodiments, the pad of the IC is a bond pad that attaches to one or more I / O pads or pins of an ESD-protected circuit.Gate 112 can be connected to a voltage source or to the operating voltage line VSS. In some embodiments, the operating voltage line VSS is at a ground potential.

[0023] The parasitic NPN transistor Q1 includes the N+-doped region 110 as a collector, the P-well 104 as a base, and the N+-doped region 108 as an emitter. The base of the NPN transistor Q1 is connected to a P+-doped region 114 via the parasitic resistor R1, which represents the intrinsic resistance of the P-well 104 (or via the P-substrate 102 if the transistor M1 is fabricated in the P-substrate 102). The P+-doped region 114 can be connected to the supply voltage line VSS. The ESD-protected device 100 further includes electrically isolated dummy gates 116.

[0024] Transistors M2 and Q2 and resistor R2 may be similar in structure and operation to transistors M1 and Q1 and resistor R1, respectively, and may form a mirror image of the arrangement of transistors M1 and Q1 and resistor R1. Transistor M2 has n+-doped regions 118 and 120 fabricated in p-well 104 and a gate 122 fabricated on p-well 104. N+-doped region 118 may be configured as a source region and connected to the operating voltage line VSS, and n+-doped region 120 may be configured as a drain region and connected to a pad of the IC. Gate 122 may be connected to a voltage source or to the operating voltage line VSS. The parasitic npn transistor Q2 has the n+-doped region 120 as a collector, the p-well 104 as a base, and the n+-doped region 118 as an emitter.The base of NPN transistor Q2 is connected to a P+-doped region 124 via parasitic resistor R2, which represents the intrinsic resistance of P-well 104 (or via P-substrate 102 if transistor M2 is fabricated in P-substrate 102). P+-doped region 124 may be connected to the supply voltage line VSS. In some embodiments, transistors M1 and M2 are separated by a gate 125 connected to the same potential as N+-doped regions 110 and 120 (e.g., the potential of the pad).

[0025] The arrangement of transistors M1, M2, Q1, and Q2 and resistors R1 and R2 along STI regions 106, p+-doped regions 112 and 124, and dummy gates 116 can be repeated as often as necessary depending on the desired properties for ESD protection device 100. Note that ESD protection device 100 may be based on only one arrangement of transistors M1 and Q1 and resistor R1.

[0026] The p-substrate 102 and the p-well 104 comprise a semiconductor material, which may include, but is not limited to: silicon, germanium; a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide; an alloy semiconductor such as silicon germanium carbide, silicon germanium, gallium arsenophosphide, gallium indium phosphide, gallium indium arsenide, gallium indium arsenide, aluminum indium arsenide, aluminum gallium arsenide; or a combination thereof. Furthermore, the p-substrate 102 and the p-well 104 are doped with p-dopants such as boron, indium, aluminum, or gallium. In some embodiments, the p-substrate 102 may have a material and doping concentration similar to or different from those of the p-well 104. The STI regions 106 consist of a dielectric material.In some embodiments, the STI regions 106 comprise silicon oxide, silicon nitride, silicon oxynitride, fluorosilicate glass (FSG), a low-k dielectric material, and / or another suitable insulating material. The n+-doped regions 108, 110, 118, and 120 may be doped with n-type dopants, such as phosphorus, arsenic, or a combination thereof, and may have a doping concentration greater than 1 × 10 19 atoms / cm 3 The p+-doped regions 114 and 124 may be doped with p-dopants, such as boron, indium, aluminum, gallium, or a combination thereof, and they may have a doping concentration of more than 1 × 10 19 atoms / cm 3 have.

[0027] Gates 112 and 122 each include a gate electrode and a dielectric layer (not shown). In some embodiments, the dielectric layer includes one or more layers of silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectric materials, such as hafnium oxide (HfO2), TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, or a combination thereof. Alternatively, the high-k dielectric materials may include metal oxides. Examples of metal oxides used for the high-k dielectrics are oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and / or mixtures thereof. The dielectric layer can be produced by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), electron beam evaporation or another suitable process.

[0028] The gate electrode may include a gate work function metal layer and a gate metal fill layer. In some embodiments, the gate work function metal layer comprises a suitable material, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), silver (Ag), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), tantalum carbide nitride (TaCN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tungsten nitride (WN), metal alloys, and / or combinations thereof. The gate work function metal layer may be formed using a suitable method, such as ALD, CVD, PVD, or combinations thereof. In some embodiments, the gate metal fill layer comprises a suitable conductive material, such as Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, WN, Cu, W, Co, Ni, TiC, TiAlC, TaAlC, metal alloys and / or combinations thereof.The gate metal fill layer 124 may be formed using ALD, PVD, CVD, or other suitable conductive material deposition process.

[0029] In some embodiments, gate 125 and dummy gates 116 include a gate electrode and dielectric layer similar to those of gates 112 and 122. In some embodiments, gate 125 and dummy gates 116 have a polysilicon structure.

[0030] Fig. Figure 3 shows an exemplary equivalent circuit diagram of the ESD-protected device 100 connected to an ESD-protected circuit. NMOS transistors M1 and M2 are connected in parallel, with their drain and source regions connected to the pad and the supply voltage line VSS, respectively. NPN transistors Q1 and Q2 are connected in parallel, with their collectors and emitters connected to the pad and the supply voltage line VSS, respectively, and their bases connected to the supply voltage line VSS via the parasitic resistors R1 and R2, respectively.

[0031] The ESD protected device 100 operates in two modes of operation, on state and off state, which will be described later with reference to the Fig. 1 to 3. The device 100 is in the on state during an ESD event, which may be a momentary buildup of a significant electrical potential at the pad, generally caused by direct or indirect contact with an electrostatic field. During the ESD event, the device 100 with ESD protection provides low-impedance discharge paths 326 and 328 ( Fig. 3) so that the ESD charging current can be discharged without damaging the ESD-protected circuit. The discharge path 326 is in the Fig. 1 and Fig. 2 by a path a from an n+-doped region 110 to the p-well 104 and a path b from the p-well 104 to an n+-doped region 108. Similarly, the discharge path 328 in the Fig. 1 and Fig. 2 by a path c from an n+-doped region 120 to the p-well 104 and a path d from the p-well 104 to an n+-doped region 118.

[0032] During the ESD event, path a, which is a junction between the n+-doped region 110 and the p-well 104, is reverse biased and can induce a leakage current, and path b, which is a junction between the p-well 104 and the n+-doped region 108, is forward biased. Thus, the parasitic transistor Q1 is turned on, and at least a portion of the ESD charging current flows from the pad via path a ( Fig. 1 and Fig. 2), ie its equivalent discharge path 326 ( Fig. 3), to the operating voltage line VSS without flowing through the ESD-protected circuit. Another part of the ESD charging current flows via path b ( Fig. 1 and Fig. 2), ie its equivalent discharge path 328 ( Fig. 3) when the parasitic transistor Q2 is turned on in a similar manner to the parasitic transistor Q1 during the ESD event.

[0033] The off state occurs during normal operation of the ESD-protected circuit, i.e., without ESD events. During normal operation, the ESD-protected device 100 presents a high impedance with respect to the ESD-protected circuit, thus causing no current to flow to the ESD-protected circuit.

[0034] Fig. Figure 4 shows a circuit diagram of an ESD protection device 100* of an IC connected to an ESD-protected circuit. The ESD protection device 100* has a similar arrangement to the ESD protection device 100, but it is based on p-type transistors. The ESD protection device 100* includes PMOS transistors M1* and M2* connected in parallel, with their source and drain regions connected to a supply voltage line VDD and a pad of the IC, respectively. PNP transistors Q1* and Q2* are connected in parallel, with their collectors and emitters connected to the supply voltage line VDD and the pad, respectively, and their bases connected to the supply voltage line VDD via a parasitic resistor R1* and R2*, respectively. The parasitic resistors R1* and R2* represent the intrinsic resistance of an n-well (not shown) in which the transistors Q1* and Q2* are fabricated.The parasitic PNP transistors Q1* and Q2* have the drain regions of transistors M1* and M2* as collectors, an N-well fabricated on a P-type substrate as a base, and the source regions of transistors M1* and M2* as emitters. The ESD protection device 100* can operate similarly to the ESD protection device 100, but with reversed polarities. During an ESD event, the ESD charging current is discharged from the supply voltage line VDD to the pad via discharge paths 326* and 328*.

[0035] Fig. 5 is a top view of an exemplary ESD protection device 500, which may be similar to ESD protection device 100 in terms of structure and operation. The differences between ESD protection devices 100 and 500 are discussed below. ESD protection device 500 is implemented using multi-fin FinFETs FF1 and FF2 instead of the planar NMOS transistors M1 and M2 of ESD protection device 100. FinFETs FF1 and FF2 may have one or more fins and are not limited to the four fins shown in Fig. 5. FinFETs FF1 and FF2 are connected in parallel. FinFETs FF1 and FF2 each have gates 512 and 522, n+-doped regions 508 and 518 configured as source regions, and n+-doped regions 510 and 520 configured as drain regions. FinFETs FF1 and FF2 are connected to the pad and the supply voltage line VSS in a manner similar to transistors M1 and M2 of device 100 with ESD protection. The ESD protection device 500 also includes parasitic NPN transistors fabricated between N+-doped regions of the FinFETs FF1 and FF2 and the P-well 104 as the parasitic NPN transistors Q1 and Q2 of the ESD protection device 100.For example, a parasitic transistor is fabricated with an n+-doped region 510 as the collector, an n+-doped region 508 as the emitter, and the p-well 104 as the base, which is connected to a p+-doped region 514 via a parasitic resistor representing the intrinsic resistance of the p-well 104 (or via the p-substrate 102 if the FinFET FF1 is fabricated in the p-substrate 102). Similar to the ESD protection device 100, the parasitic npn transistors of the ESD protection device 500 provide the discharge paths during an ESD event.

[0036] The ESD-protected device 500 also includes dummy gates 516 and a gate 525, which are similar in functionality and material composition to dummy gates 116 and gate 125. The material composition of the n+-doped regions 508, 510, 518, and 520, the p+-doped regions 514 and 524, and the gates 512 and 522 is similar to the material composition of the n+-doped regions 108, 110, 118, and 120, the p+-doped regions 114 and 124, and the gates 112 and 122, respectively.

[0037] The n+-doped regions 508, 510, 518, and 520 are epitaxial fin regions of the FinFETs FF1 and FF2, which comprise a semiconductor material epitaxially grown on the p-type substrate 102 or the p-type well 104. The epitaxially grown semiconductor material may include the following semiconductor materials: germanium or silicon; or a compound semiconductor, such as gallium arsenide or aluminum gallium arsenide; or an alloy semiconductor, such as silicon germanium or gallium arsenide phosphide. In some embodiments, the epitaxial fin regions of the FinFETs FF1 and FF2 are grown using the following methods: CVD, e.g., low-pressure CVD (LPCVD), atomic layer CVD (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced-pressure CVD (RPCVD), or another suitable CVD method. Molecular beam epitaxy (MBE) or another suitable epitaxial growth technique; or a combination thereof.In some embodiments, the epitaxial fin regions are grown using a process of epitaxial deposition and partial etching that is repeated at least once. This repeated process of epitaxial deposition and partial etching is also referred to as a cyclic deposition and etching (CDE) process. The epitaxial fin regions of the FinFETs FF1 and FF2 can be doped in situ during the epitaxial growth process. In various embodiments, the epitaxial regions can be doped with n-type dopants, such as phosphorus or arsenic, and / or combinations thereof, or using n-type doping precursors, such as phosphine (PH3) or arsenic (AsH3), but other n-type doping precursors can also be used. Through in situ doping, the doping concentration of the epitaxially grown semiconductor material can be controlled and achieved as desired.In some embodiments, the epitaxial fin regions are not doped in situ, and an ion implantation process is performed to dope the epitaxial fin regions of FinFETs FF1 and FF2. The doping concentration of the n+-doped regions 508, 510, 518, and 520 may be greater than 1 × 10 19 atoms / cm 3 be.

[0038] Fig. 6 is a top view of an exemplary ESD-protected device 600, which may be similar to ESD-protected device 500 except for extended n+ drain regions 510* and 520* of FinFETs FF1* and FF2*. The extended n+ drain regions 510* and 520* may contribute to reducing leakage currents during normal operation and thus reducing power consumption, both of which are of significant importance, for example, in FinFET technology or submicrometer technology nodes. Due to the formation of extended drain regions, such as 510*, by forming longer drain regions than the non-extended drain regions, such as 510 ( Fig. 5), however, the distance between adjacent gates, such as gates and 525, is increased beyond the target value specified in the poly-poly pitch requirement in the constraining design rules (RDRs) in semiconductor manufacturing technology. The poly-poly pitch can be defined as the minimum distance between adjacent gate structures specified by the RDRs. For example, the distance between adjacent gates and 525 can be referred to as the poly-poly pitch.

[0039] Various embodiments of ESD protection devices with extended drain regions that meet the poly-poly spacing requirement in RDRs in semiconductor manufacturing technology are described below. Example ESD protection device with extended drain regions, hereinafter also referred to as ESD protection device with extended drain regions

[0040] Fig. 7 is a top view of an exemplary drain-extended NMOS device 700 with ESD protection in an IC. Fig. Figure 8 is a cross-sectional view of the exemplary drain-extended NMOS device 700 with ESD protection of Fig. 7. ESD protection device 700 is similar to ESD protection device 100 in terms of structure, composition, and operation. The differences between ESD protection devices 100 and 700 are discussed below.

[0041] The ESD protection device 700 includes drain-extended NMOS transistors M3 and M4, including: n+-doped regions 108 and 118 configured as source regions; n+-doped regions 110 and 120 configured as drain regions; gates 112 and 122; and extended drain regions between regions 108 and 110 and between regions 118 and 120, respectively. The extended drain regions include n+-doped floating regions 730 and 734 and three gates 732 and 736 connected to the same potential (e.g., the potential of the pad) as the n+-doped regions 110 and 120. The spacing between adjacent gates among the three gates 732 and among the three gates 736 satisfies the poly-poly spacing requirement in the RDRs.Thus, extending the drain regions 110 and 120 of transistors M3 and M4 by adding pairs of a doped region with a similar doping to drain regions 110 and 120 and a gate connected to the same potential as drain regions 110 and 120 helps increase the drain resistances of NMOS transistors M3 and M4 while maintaining the poly-poly spacing requirement in the RDRs. Higher drain resistances, in turn, can help improve the turn-on uniformity of ESD protection device 700, promoting the simultaneous turn-on of all discharge paths of ESD protection device 700. The extended drain regions of transistors M3 and M4 may include one or more n+-doped floating regions 730 and 734 and one or more gates 732 and 736, respectively, and are not limited to the number of doped floating regions 730 and 734 and gates 732 and 736 in the . Fig. 7 and Fig. 8. The n+-doped regions 730 and 734 may be fabricated in a similar manner to the n+-doped region 110, and the gates 732 and 736 may be fabricated in a similar manner to the gate 112 and the dummy gates 116.

[0042] The ESD protection device 700 may optionally include further n+-doped regions 740 and 742 configured as drain regions of transistors M3 and M4, respectively, and connected to the pad. These further drain regions 740 and 742 are separated from each other and from neighboring n+-doped regions by gates 744 connected to the same potential as the drain regions 110 and 120. The gates 744 may be fabricated in a similar manner to the gate 112 and the dummy gates 116. These further drain regions 740 and 742 provide further discharge paths in the ESD protection device 700 in addition to the discharge paths a and b of transistor M3 and the discharge paths c and d of transistor M4. The discharge of the ESD charging current via paths a, b, c and d is similar to the discharge described above with reference to the Fig. 2 and Fig. 3. The further discharge paths of transistor M3 may extend from the n+-doped region 740 to the p-well 104 (path a*) and from the p-well to the n+-doped region 108 (path b). The further discharge paths of transistor M4 may extend from the n+-doped region 742 to the p-well 104 (path c*) and from the p-well to the n+-doped region 118 (path d). The further discharge paths contribute to increasing the amount of heat dissipation during an ESD event and thereby improving the discharge current management of the device with ESD protection. For example, an ESD-protected device with a single multi-drain transistor, i.e., with only one additional discharge path, can handle twice the current level during an ESD event as a device with ESD protection without a multi-drain transistor. In another example, an ESD-protected device with two multi-drain transistors, i.e.,with two additional discharge paths, can handle 2.5 times the current level of a device with ESD protection without a multi-drain transistor during an ESD event.

[0043] Fig. 9 shows a cross-sectional view of an exemplary drain-extended PMOS device 900 with ESD protection. Fig. Figure 9 shows that ESD protection device 700 is not limited to NMOS transistors and can be implemented using PMOS transistors M5 and M6. The differences between ESD protection devices 700 and 900 are discussed below.

[0044] The ESD protection device 900 includes drain-extended PMOS transistors M5 and M6, including p+-doped regions 908 and 918 configured as source regions; p+-doped regions 910 and 920 configured as drain regions; gates 912 and 922; and extended drain regions between regions 908 and 910 and between regions 918 and 920, respectively. The extended drain regions include p+-doped floating regions 930 and 934 and three gates 732 and 736 connected to the same potential (e.g., the potential of the pad) as the p+-doped regions 910 and 920.

[0045] The ESD protection device 900 also includes parasitic PNP transistors Q5 and Q6. The parasitic PNP transistors Q5 and Q6 have drain regions of transistors M5 and M6 as collectors, an N-well 904 fabricated on the P-type substrate 102 as bases, and the source regions of transistors M5 and M6 as emitters. The bases of transistors Q5 and Q6 are connected to the supply voltage line VDD via N+-doped regions 914 and 924 and parasitic resistors R5 and R6, respectively. The parasitic resistors R5 and R6 represent the intrinsic resistance of the N-well 904. The ESD protection device 900 can operate in a similar manner to the ESD protection device 700, but with reversed polarities. For example, during an ESD event, the charging current flows through discharge paths e and f of transistor Q5 and through discharge paths g and h of transistor Q6 in a direction opposite to the direction through discharge paths a and b, respectively.the discharge paths c and d are opposite. The discharge paths e and f of the transistor Q5 can extend from the p+-doped region 908 to the n-well 904 and from the n-well 904 to the p+-doped region 910. The discharge paths g and h of the transistor Q6 can extend from the p+-doped region 918 to the n-well 904 and from the n-well 904 to the p+-doped region 920.

[0046] The ESD protection device 900 may optionally include further p+-doped regions 940 and 942 configured as drain regions of transistors M5 and M6, respectively, and connected to the pad. Similar to the ESD protection device 700, these further drain regions provide further discharge paths in the ESD protection device 900 in addition to the discharge paths e and f of transistor M5 and the discharge paths g and h of transistor M6. The further discharge paths of transistor M5 may extend from the p+-doped region 908 to the n-well 904 (path e) and from the n-well 904 to the p+-doped region 940 (path f*). The further discharge paths of the transistor M6 can extend from the p+-doped region 918 to the n-well 904 (path g) and from the n-well 904 to the p+-doped region 942 (path h*).

[0047] Fig. 10 is a top view of an exemplary drain-extended FinFET device 1000 with ESD protection. The differences between the ESD protection devices 500, 700, and 1000 are discussed below. The ESD protection device 1000 is similar to the ESD protection device 500, but it has additional extended drain regions of transistors FF3 and FF4 between regions 508 and 510 and between regions 518 and 520, respectively. The extended drain regions include n+-doped epitaxial fin floating regions 1030 and 1034 and gates 1032 and 1036 connected to the same potential (e.g., the potential of the pad) as the n+-doped regions 510 and 520. The spacing between adjacent gates among the three gates 1032 and among the three gates 1036 satisfies the poly-poly spacing requirement in the RDRs.Thus, extending the drain regions 510 and 520 of transistors FF3 and FF4 by adding pairs of a doped region with a similar doping to drain regions 510 and 520 and a gate connected to the same potential as drain regions 510 and 520 helps increase the drain resistances of NMOS transistors M3 and M4, thereby meeting the poly-poly spacing requirement in the RDRs. The design of the drain-extended ESD-protected FinFET device 1000, which meets the poly-poly spacing requirement, also helps achieve high-quality epitaxial fin regions in the extended drain regions of FinFETs FF3 and FF4. The ESD-protected device 1000 is similar to the ESD-protected device 700 in terms of its material composition and operation. A person skilled in the art will recognize that the device 1000 with ESD protection can also be implemented with a p-FinFET.

[0048] The ESD protection device 1000 may optionally include further n+-doped regions 1040 and 1042 configured as drain regions of the FinFETs FF3 and FF4, respectively, and connected to the pad. Similar to the ESD protection device 700, these further drain regions 1040 and 1042 provide further discharge paths in the ESD protection device 1000 in addition to the discharge paths via the FinFETs FF3 (e.g., from the n+-doped region 510 to the p-well 104 to the n+-doped region 508) and the FinFETs FF4 (e.g., from the n+-doped region 520 to the p-well 104 to the n+-doped region 518). The further discharge paths of the FinFET FF3 can extend from the n+-doped region 1040 to the p-well 904 and from the p-well 104 to the n+-doped region 508. The further discharge paths of the FinFET FF4 can extend from the n+-doped region 1042 to the p-well 104 and from the p-well 104 to the n+-doped region 518.

[0049] Fig. 11 is a top view of an exemplary drain extended device 1100 with ESD protection with stacked NMOS transistors in an IC. Fig. 12 is a sectional view of the device 1100 with ESD protection of Fig. 11. Fig. 13 is an exemplary equivalent circuit diagram of the ESD protection device 1100. The differences between the ESD protection devices 700 and 1100 are discussed below. The ESD protection device 1100 is similar to the ESD protection device 700 in terms of its structure, composition, and operation, but it has additional pairs of an n+-doped region 1146 and a gate 1148 and of an n+-doped region 1150 and a gate 1152. The pair of the n+-doped region 1146 and the gate 1148, together with the source and drain regions 108 and 110, form stacked NMOS transistors M7 and M8, which are Fig. 13. Likewise, the pair of n+-doped region 1150 and gate 1152 together with source and drain regions 118 and 120 form stacked NMOS transistors M9 and M10, which are Fig. 13. The n+-doped regions 1146 and 1150 and the gates 1148 and 1152 can be connected to a potential. The ESD protection device 1100 can include two or more transistors stacked on top of each other. The ESD protection device 1100, like the ESD protection device 700, also includes parasitic npn transistors Q1 and Q2 between the source and drain regions 108 and 110 and between the source and drain regions 118 and 120.

[0050] Fig. 14 is a top view of an exemplary drain-extended FinFET device 1400 with ESD protection in an IC. The differences between the ESD protection devices 1000 and 1400 are discussed below. The ESD protection device 1400 is similar in structure, composition, and operation to the ESD protection device 1000, but it has additional pairs of an n+-doped epitaxial fin region 1146 and a gate 1448 and of an n+-doped epitaxial fin region 1450 and a gate 1452. The pair of region 1146 and gate 1148, together with the source and drain regions 508 and 510, form stacked FinFETs as transistors M7 and M8 in Fig. 13. Likewise, the pair of region 1150 and gate 1152 together with source and drain regions 518 and 520 form stacked FinFETs as transistors M9 and M10 in Fig. 13.

[0051] Fig. 15 is a top view of an exemplary drain-extended NMOS device 1500 with ESD protection in an IC. Fig. 16 is a sectional view of the device 1500 with ESD protection of Fig. 15. The differences between ESD protection devices 700 and 1500 are discussed below. ESD protection device 1500 is similar to ESD protection device 700, but it has drain regions 110 and 120 along with further drain regions 740 and 742 and extended drain regions including n+-doped regions 730 and 732 of transistors M3 and M4, respectively, formed in an n-well 1504. In some embodiments, n+-doped regions 730 and 732 are formed entirely or partially in n-well 1504. That is, one or more of the n+-doped regions of regions 730 and 732 may be formed in p-well 104. In some embodiments, the p-well 104 is the p-substrate 102.

[0052] Fig. 17 is a top view of an exemplary NMOS device 1700 with ESD protection having stacked NMOS transistors in an IC. Fig. 18 is a sectional view of the 1700 device with ESD protection of Fig. 17. ESD protection device 1700 is similar to ESD protection device 1100, but it has drain regions 110 and 120 along with further drain regions 740 and 742 and extended drain regions having n+-doped regions 730 and 732 formed in n-well 1504. In some embodiments, n+-doped regions 730 and 732 are formed entirely or partially in n-well 1504. That is, one or more of the n+-doped regions of regions 730 and 732 may be formed in p-well 104. In some embodiments, p-well 104 is p-substrate 102.

[0053] Fig. 19 is a top view of an exemplary drain-extended FinFET device 1900 with ESD protection in an IC. The ESD protection device 1900 is similar to the ESD protection device 1000, but it has drain regions 510 and 520 along with further drain regions 1040 and 1042 and extended drain regions having n+-doped regions 1030 and 1032 formed in the n-well 1504. In some embodiments, the n+-doped regions 1030 and 1032 are formed entirely or partially over the n-well 1504. That is, one or more of the n+-doped regions of regions 730 and 732 may be formed over the p-well 104. In some embodiments, the p-well 104 is the p-substrate 102.

[0054] Fig. 20 is a top view of an exemplary drain-extended PMOS device 2000 with ESD protection in an IC. The ESD protection device 2000 is similar to the ESD protection device 900, but it has a deep n-well 2005 formed on the p-type substrate 102. In addition, drain regions 910 and 920, along with further drain regions 940 and 942 and extended drain regions having p+-doped regions 930 and 934, are formed in a p-well 104 formed on the deep n-well 2005. In some embodiments, the p+-doped regions 930 and 934 are formed entirely or partially over the p-well 104. That is, one or more of the p+-doped regions of regions 930 and 934 can be fabricated in the n-well 1504, which is fabricated on the deep n-well 2005.The ESD protected device 2000 also includes a deep n-well 2005 formed between the p-substrate 102 and the wells 104 and 1504.

[0055] The above-described fabrication of the n+-doped extended drain regions of the 1500, 1700, and 1900 ESD-protected devices in an n-well and the fabrication of the p+-doped extended drain regions of the 2000 ESD-protected device in a p-well can help to further increase the drain resistances and thereby improve the turn-on uniformity of these ESD-protected devices.

[0056] Fig. 21 is a circuit diagram of an exemplary NMOS device 2100 with ESD protection, which may have a structure similar to one of the structures described with reference to FIGS. Fig. 1 and 2, 5, 7 and 8, 10 to 12, and 14 to 19. Similar to the operation of the various embodiments of the ESD protection devices discussed above, during an ESD event, the ESD charge current may be discharged from the pad through one or more of the parasitic NPN transistors Q11-Q14 to the supply voltage line VSS. For efficient performance of the ESD protection device 2100, it is desirable for all NPN transistors Q11-Q14 to turn on simultaneously. Due to different values ​​of the parasitic resistors R11 to R14 and the presence of a parasitic resistor R pHowever, in the metal trace from transistors M11 to M14, transistors Q11 and Q12 may have a turn-on voltage V1 that is different from the turn-on voltage V2 that transistors Q13 and Q14 may have. And if V1 > V2, transistors Q13 and Q14 may turn on earlier than transistors Q11 and Q12 during an ESD event, and the ESD charge current can only be discharged through transistors Q13 and Q14. This would result in inefficient performance of the 2100 device with ESD protection.

[0057] Fig. Figure 22 is a circuit diagram of an exemplary NMOS device 2200 with ESD protection using ballast resistors R15 and R16. Ballast resistors R15 and R16 contribute to increasing the drain resistances of transistors M11 through M14 and reducing the influence of the parasitic resistance R pon the turn-on voltages V1 and V2 and thus to a reduction in the difference between the voltages V1 and V2 for turn-on uniformity.

[0058] Fig. Figure 23 is a top view of the exemplary device 2200 with ESD protection of Fig. 22. The ESD protection device 2200 can be implemented by repeating the structure of the ESD protection device 700 and connecting them in parallel between the pad and the supply voltage line VSS, as shown in the equivalent circuit of Fig. 22. Each pair of transistors M11 / M12 and M13 / M14 may be similar to transistors M3 and M4 of ESD protection device 700. For clarity, the additional drain regions 750 and 742 in ESD protection device 2200 are not shown, but these regions may be present in device 2200. The ballast resistors R15 and R16 may be increased in ESD protection device 2200 by increasing the metal routing distances (e.g., distances 2254 and 2256) between drain regions 110 and 120 and the pad.

[0059] Although the ESD protection device 2200 is shown with a structure similar to that of the ESD protection device 700, the ESD protection device 2200 may also have a structure similar to one of the structures described with reference to the Fig.7 and 8, 10 to 12, and 14 to 19. The 2200 device with ESD protection can also be implemented using PMOS transistors. Exemplary embodiments and advantages

[0060] In one embodiment, an ESD protection device comprises: a source region connected to a first potential; a first drain region connected to a second potential different from the first potential; and an extended drain region between the source region and the first drain region. The extended drain region has N doped floating regions and M gate regions connected to the second potential, where N and M are integers greater than 1, and N is equal to M. The doped floating regions of the N doped floating regions each alternate with gate regions of the M gate regions.

[0061] In another embodiment, an ESD protection device comprises a first well region having a first conductivity type and a source region having a second conductivity type different from the first conductivity type. The source region is disposed in the first well region. The ESD protection device further comprises a first drain region having the second conductivity type and an extended drain region having electrically floating doped regions and gate regions. A first portion of the extended drain region is disposed in the first well region.

[0062] In yet another embodiment, an integrated circuit comprises: an I / O pad; a power line; an ESD protection device connected to the I / O pad and the power line; and a circuit with an ESD protection device connected in parallel with the ESD protection device. The ESD protection device comprises: a source region connected to the power line; a drain region connected to the I / O pad; and an extended drain region between the source region and the drain region. The extended drain region has electrically floating doped regions and gate regions connected to the I / O pad. The electrically floating doped regions alternate with the gate regions.

Claims

[1] ESD protection device with: a source region (108, 118) connected to a first potential (VSS); a first drain region (110, 120) connected to a second potential different from the first potential; an extended drain region between the source region (108, 118) and the first drain region (110, 120), the extended drain region comprising: N electrically floating doped regions (730, 734), and M gate regions (732, 736) connected to the second potential, wherein N and M are integers greater than 1, and one or more electrically floating doped regions of the N electrically floating doped regions (730, 734) alternate with one or more gate regions of the M gate regions (732, 736); a first well region having a first conductivity type; and a second well region having a second conductivity type different from the first conductivity type, wherein the source region, the first drain region and the N electrically floating doped regions have the second conductivity type, the source region is arranged in the first well region, and the first drain region and an electrically floating doped region of the N electrically floating doped regions are arranged in the second well region. [2] ESD protection device with: a source region (108, 118) connected to a first potential (VSS); a first drain region (110, 120) connected to a second potential different from the first potential; an extended drain region between the source region (108, 118) and the first drain region (110, 120), the extended drain region comprising: N electrically floating doped regions (730, 734), and M gate regions (732, 736) connected to the second potential, where N and M are integers greater than 1, and one or more electrically floating doped regions of the N electrically floating doped regions (730, 734) alternate with one or more gate regions of the M gate regions (732, 736); a first well region having a first conductivity type; and a second well region having a second conductivity type different from the first conductivity type, wherein the N electrically floating doped regions have the second conductivity type, and an electrically floating doped region of the N electrically floating doped regions is arranged partly in the first well region and partly in the second well region. [3] ESD protection device according to one of the preceding claims, comprising: a gate between the source region and the first drain region, the gate being coupled to a voltage source; where the N electrically floating doped regions (730, 734) alternate with the M gate regions (732, 736). [4] ESD protection device according to one of the preceding claims, wherein the source region (108, 118), the first drain region (110, 120) and the electrically floating doped regions (730, 734) are epitaxial fin regions. [5] An ESD protection device according to any preceding claim, further comprising a gate electrode (112, 122) connected to the first potential (VSS) between the source region (108, 118) and the extended drain region (110, 120). [6] An ESD protection device according to any preceding claim, wherein distances between adjacent gate regions of the M gate regions (732, 736) are nominally equal. [7] ESD protection device according to one of the preceding claims, wherein distances between adjacent gate regions of the M gate regions (732, 736) meet requirements of restrictive design rules (RDRs). [8] An ESD protection device according to any preceding claim, further comprising a second drain region (740, 742) connected to the second potential. [9] An ESD protection device according to any preceding claim, further comprising a parasitic transistor (Q3, Q4) connected to the source region (108, 118) and the first drain region (110, 120). [10] An ESD protection device according to claim 9, further comprising: a doped region (114, 124) connected to the first potential (VSS) and having a conductivity type different from that of the source region (108, 118) and the first drain region (110, 120); and a parasitic resistor (R3, R4) connected to the parasitic transistor (Q3, A4) and the doped region. [11] ESD protection device according to one of the preceding claims, further comprising: a discharge path with: a first path (a, c) from the first drain region to the first well region, and a second path (b, d) from the first well region to the source region. [12] ESD protection device according to one of claims 1 to 10, further comprising: a second drain region connected to the second potential; a first discharge path with: a first path (a) from the first drain region to the first well region, and a second path (b) from the first well region to the source region; and a second discharge path with: a third path (c) from the second drain region to the second well region, and a fourth path (d) from the second well region to the source region. [13] ESD protection device according to one of the preceding claims, further comprising: an electrically floating gate region (116); and an isolation region (106), wherein the source region (108, 118) is separated from the isolation region by the electrically floating gate region.

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