Device for controlling electrical and / or electronic components of a vehicle module and such a vehicle module with automatic module addressing and bus shunt bypass switches

Abstract

Bus junction (BK) j ), which is capable of carrying out a procedure for assigning bus addresses to bus nodes of a serial, bidirectional, differential two-wire communication bus (DB), - wherein the procedure for assigning bus addresses to bus nodes ((BK1) (BK2), (BK3), ...... [BK n-1 ], [BK n ]) of a serial, bidirectional, differential two-wire communication bus (DB) using first bus shunt resistors (R2) and second bus shunt resistors (R2') in the individual bus nodes ((BK1), (BK2), (BK3), ...... [BK n-1 ], [BK n ]) is carried out within a procurement period and - whereby, after the execution of the procedure for assigning bus addresses to the bus nodes ((BK1), (BK2), (BK3), ...... [BK n-1 ], [BK n ]) of the serial, bidirectional, differential two-wire communication bus (DB) connects an operating period during the award period and - wherein the serial, bidirectional, differential two-wire communication bus (DB) comprises a first single-wire bus (DB1) and a second single-wire bus (DB2) and - where the bus junction (BK) j ) has such a first bus shunt resistor (R2) and such a second bus shunt resistor (R2') and - wherein the first bus shunt resistor (R2) is inserted into the first single-wire bus (DB1) and - wherein the second bus shunt resistor (R2') is inserted into the second single-wire bus (DB2) and - which includes a first bus shunt bypass switch (S4), • which is open before a bus address is assigned to the bus hub during the allocation period and • which is closed after a bus address has been assigned to the bus hub during the allocation period and • which is closed during the operating period, and - having a second bus shunt bypass switch (S4'), • which is open before a bus address is assigned to the bus hub during the allocation period and • which is closed after a bus address has been assigned to the bus hub during the allocation period and • which is closed during the operating period.

Description

[0001] The invention relates to a device for controlling electrical and / or electronic components of a vehicle module, in particular an interior light and / or exterior light such as a rear light module of a vehicle. Furthermore, the invention relates to a vehicle module with several electrical and / or electronic components, in particular an interior light and / or exterior light such as a rear light module of a vehicle.

[0002] The electrical and electronic components of vehicle modules, such as the various lighting modules, are becoming increasingly complex. Particularly in the area of ​​lighting, there has been a recent trend towards the use of dynamic functions, such as sweeping turn signals or the "coming home" function. This approach takes advantage of the fact that the individual exterior and interior lighting functions of a vehicle are each implemented using multiple LEDs or OLEDs. Dynamic effects can now be achieved in a relatively simple way from a hardware perspective by controlling the numerous light sources within such a vehicle lighting module in different ways.

[0003] The numerous components of a vehicle module, such as the many LEDs or OLEDs assigned to the individual lighting functions of, for example, a taillight module, are advantageously connected to a control unit of the module via a communication bus, or rather, they communicate with the control unit via this bus. Typically, the control unit also includes a voltage converter to supply power, in particular, to the LED drivers of a lighting module.

[0004] Differential two-wire communication bus systems have proven effective in terms of transmission speed and robustness. Information signals are transmitted between the control unit and the devices as a voltage difference between the two bus lines, resulting in greater signal reliability, higher transmission speed, and reduced susceptibility to interference. Such two-wire bus systems are generally known.

[0005] The problem is that the hardware requirements for such two-wire bus systems and their components are considerable. A particular disadvantage in terms of cost is the fact that the components must have relatively precise clocks that operate synchronously. Furthermore, the light modules must be able to determine their physical position during installation and connection at the vehicle factory and convert it into a logical address. This allows identical light modules to be used without pre-programming a bus node address for each module, which significantly reduces the potential for errors and logistical challenges in production.

[0006] From NN: “High-Brightness LED Matrix Manager for Automotive Headlight Systems”, February 1, 2016 (2016-02-01), pages 1-53, XP055348745, Dallas, Texas (found on the Internet: URL:http: / / www.ti.com / lit / ds / symlink / tps92661-q1.pdf on 2017-02-23) a vehicle headlight control system is known whose bus has two lines to which no differential signals are applied.

[0007] In MONAL GIRADKAR ET AL: “Design and Implementation of Adaptive Front Light System of Vehicle Using FPGA Based LIN Controller”, EMERGING TRENDS IN ENGINEERING AND TECHNOLOGY (ICETET), 2011 4TH INTERNATIONAL CONFERENCE ON, IEEE, November 18, 2011 (2011-11-18), pages 258-261, XP032087461, DOI: 10.1109 / ICETET.2011.67; ISBN: 978-1-4577-1847-2, a bit timing logic for a CAN bus is described.

[0008] A device for controlling an adaptive automotive front light with an FPGA-based LIN controller is described in GUO JINYAN ET AL: “The design and realization of CAN bit timing logic”, MICROELECTRONICS AND ELECTRONIS (PRIMEASIA), 2010 ASIA PACIFIC CONFERENCE ON POSTGRADUATE RESEARCH IN, IEEE, PISCATAWAY, NJ, USA, September 22, 2010 (2010-09-22), pages 333-337, XP031777603, ISBN: 978-1-4244-6735-8.

[0009] Finally, ZENG WEIYING ET AL: “In-Vehicle Networks Outlook: Achievements and Challenges”, IEEE COMMUNICATIONS SURVEYS & TUTORIALS, Vol. 18, No. 3, February 27, 2016 (2016-02-27), pages 1552-1571, XP011620858, DOI: 10.1109 / COMST.2016.2521642; [accessed 2016-08-19] provides an overview of vehicle communication systems.

[0010] Devices and methods for addressing and operating an LED chain using a JTAG protocol are disclosed in German patent applications DE 10 2016 125 290 A1 and DE 10 2017 100 718 A1. One problem is that the clock signal must be transmitted together with the data using a multi-level signal. However, there is a market need to be able to use existing protocols. In this case, the bus nodes must be synchronized with sufficient precision to avoid transmitting the clock signal as described in DE 10 2016 125 290 A1 and DE 10 2017 100 718 A1. In the CAN protocol, for example, this is solved using complex timing synchronization, which, however, generally results in excessively complex bus nodes.

[0011] Bus nodes are known from DE 10 2013 201 106 B4. The bus nodes of DE 10 2013 201 106 B4 have a communication unit that can be connected to at least one data line of a communication bus (CB) for communication. Furthermore, the bus nodes of DE 10 2013 201 106 B4 have a bus node controller that is operationally connected to the communication unit. In addition, the bus nodes of DE 10 2013 201 106 B4 have an identification unit that is operationally connected to the bus node controller. This identification unit allows for the optional use of a two-port interface instead of a direct connection between an IDT input and an IDT output of an identification line. The identification line of DE 10 2013 201 106 B4 can be connected with a predetermined voltage level.The two-port device of DE 10 2013 201 106 B4 is typically a symmetrical two-port device in the form of a T-circuit consisting of three T-shaped connected resistors, of which a first resistor and a second resistor can be connected in series with the identification line and a third resistor can be connected between a connection point of the first with the second resistor and a reference potential. The identification unit of DE 10 2013 201 106 B4 is configured, in an initialization state with an interposed two-port bus node controller, to signal a time for a message exchange between the bus node and a bus master by comparing a first voltage at the IDT input with a predetermined threshold value. This message exchange is then used by the bus master of DE 10 2013 201 106 B4 to assign a unique identifier to the bus node. However, the auto-addressing method of DE 10 2013 201 106 B4 requires three lines.

[0012] The object of the invention is to create a device for controlling electrical and / or electronic components of a vehicle module and such a vehicle module which is reduced in terms of hardware effort.

[0013] The scope of the work claimed is determined by the claims themselves. The description specifies the claims and places them in an overall context.

[0014] Abbreviations, unlike reference symbols, are marked in the text with square brackets "[]" and are listed in the accompanying abbreviation list. Reference symbols that appear in any of the figures are marked in the text with parentheses "()" and are listed in the accompanying reference symbol list. The terms are always listed with their respective reference symbols, even if they are used elsewhere in the description besides the figure description.

[0015] The indices j and n each correspond to a positive integer.

[0016] This problem is solved by the subject matter of claim 1.

[0017] The proposed approach combines the advantages of a differential two-wire communication bus with auto-addressing capability with the advantages of using asynchronous digital serial interfaces to connect individual participants or components to the two-wire communication bus. The use of Universal Asynchronous Receiver Transmitters (UARTs) requires that the bitstream received via such a digital serial interface contains synchronization information for the clock of the bus participant (the respective bus node). However, such synchronization information (e.g., synchronization bits) can now also be easily integrated via a differential two-wire communication bus, for example, in the header of a data frame representing the bitstream.Thus, the protocol of the differential two-wire communication bus used according to the invention includes elements such as those known from single-wire buses whose participants have standardized and cost-effective UARTs.

[0018] The invention is particularly applicable in the context of digital interfaces for robust and high-speed data transmission via a two-wire cable connection between circuit boards equipped with LEDs, for example, for the rear light and interior light within a luminaire, at a data rate of up to 500 kbit / s. Symmetrical transmission using a differential high-speed two-wire bus system is employed for the purpose of transmitting a simple serial protocol, thereby reducing the hardware digital complexity. Figure 1

[0019] The Fig. Figure 1 shows an example of a taillight module (BLM) of a vehicle. The taillight module (BLM) has a bus master (ECU) and a serial, bidirectional, differential two-wire communication bus (DB). The serial, bidirectional, differential two-wire communication bus (DB) consists of a first single-wire bus (DB a ) and a second single-wire bus (DB bThe TXD and RXD lines of the bus master (ECU) lead to a level converter (TR) to convert the signal level for operation of the two-wire communication bus DB. The bus master (ECU) receives various control commands externally, for example, for the functions of the taillights, turn signals, rear fog light, dynamic effects, etc., and / or information via a digital bus. The bus master (ECU) converts these commands into bit streams, which include bits of a synchronization field for the corresponding data frames (bit stream packet (BP)). The level converter and bus master (ECU) are subsequently considered as a single unit and referred to collectively as the bus master (ECU).

[0020] Various components or devices are connected to the communication bus (DB) as bus nodes BK1 to BK6. For example, the first and second bus nodes (BK1 and BK2) are responsible for the turn signal function, the third bus node (BK3) for the taillight function, the fourth and sixth bus nodes (BK4 and BK6) for the brake light function, and the fifth bus node (BK5) for the reverse light function. Each of these devices or components has a number of LEDs (LED1 to LED6) controlled by their respective LED drivers.

[0021] Each bus node is also equipped with a digital interface (IF1 to IF6) in the form of a UART. Furthermore, each bus node may have a microcontroller (µC) as required. 1]up to [µC6]) and furthermore a clock generator ([CLKG1] to [CLKG6]) to be able to read messages on the differential two-wire communication bus (DB) synchronously with the transmission of the bits of the bit streams or to be able to place such bit streams on the two-wire communication bus (DB) synchronously for reading by other participants or the bus master (ECU).

[0022] Furthermore, simplifying the hardware of the inventive control system for the components of a vehicle module is facilitated by the use of fixed sampling points at the component or two-wire communication bus participant level, instead of dynamic adjustment of the sampling points. The latter is considerably more complex. Clock signal acquisition for each participant is achieved by reading the synchronization information from the bit streams, which is advantageously transmitted at the beginning of a bit stream.

[0023] Fig. Figure 2 shows a two-wire communication bus (DB), such as those known from the prior art. The serial, bidirectional, differential two-wire communication bus (DB) consists of a first single-wire bus (DB). a ) and a second single-wire bus (DB b ).

[0024] The serial, bidirectional, differential two-wire communication bus (DB) connects the bus master (ECU) to several bus nodes ((BK1) to [BK n ]). Figure 3

[0025] The bus master (ECU) has a first driver [TR a ] with which he built the first single-wire bus (DB a ) can bring into a first state (Z1) or a second state (Z2) or a third state (Z3).

[0026] A first driver, acting as a CAN driver, can preferably assume two of the three allowed states: In a first state, it places a first logical level (Z1) on the first single-wire bus (DB). aIn a second state, it applies a third logical level (Z3) to the first single-wire bus (DB). a The first driver of the bus master (ECU) also operates in the addressing state of the data bus system and the bus nodes ((BK1) to [BK n' ]) as the first current sink for the first addressing currents of the first addressing current sources ((Iq1) to [Iq n ]) the bus junction ((BK1) to [BK n ]) and their first quiescent currents. Preferably, the first driver of a bus node ((BK1) to [BK n ]) or the bus master (ECU) indicates the first state (Z1) when the second driver [TR b ] of the relevant bus junction ((BK1) to [BK n ]) assumes the second state (Z2). This differentially induces a first differential level (z1) in the signal. Preferably, the first driver of a bus node ((BK1) to [BK n ]) or the bus master (ECU) indicates the third state (Z3) when the second driver [TR b] of the relevant bus junction ((BK1) to [BK n ]) assumes the third state (Z3). This causes the signal to be differentially impressed with a third differential level (z3).

[0027] The first driver, also known as an RS485 driver, can preferably assume two of the two allowed states: In a first state, it places a first logical level (Z1) on the first single-wire bus (DB). a In a second state, it applies a second logical level (Z2) to the first single-wire bus (DB). a The first driver of the bus master (ECU) also operates in the addressing state of the data bus system and the bus nodes ((BK1) to [BK n ]) as the first current sink for the first addressing currents of the first addressing current sources ((Iq1) to [Iq n ]) the bus junction ((BK1) to [BK n ]) and their first quiescent currents. Preferably, the first driver of a bus node ((BK1) to [BK n]) or the bus master (ECU) indicates the first state (Z1) when the second driver [TR b ] of the relevant bus junction ((BK1) to [BK n ]) assumes the second state (Z2). This differentially induces a first differential level (z1) in the signal. Preferably, the first driver of a bus node ((BK1) to [BK n ]) or the bus master (ECU) indicates the second state (Z2) when the second driver [TR b ] of the relevant bus junction ((BK1) to [BK n ]) assumes the first state (Z1). This causes the signal to be differentially impressed with a second differential level (z2).

[0028] Furthermore, the first driver typically has a sub-device for detecting and avoiding a bus collision in the event of simultaneous access to the first single-wire bus (DB). a ) by a first driver of another bus node ((BK1) to [BK n ]) or the bus master (ECU).

[0029] A second driver, acting as a CAN driver, can preferably assume two of the three allowed states: In a first state, it places a second logical level (Z2) on the second single-wire bus (DB). b In a second state, it applies a third logical level (Z3) to the second single-wire bus (DB). b The second driver of the bus master (ECU) also operates in the addressing state of the data bus system and the bus nodes ((BK1) to [BK n ]) as the second current sink for the second addressing currents of the second addressing current sources ((Iq'1) to [Iq' n ]) the bus junction ((BK1) to [BK n ]) and their second quiescent currents. Preferably, the second driver of a bus node ((BK1) to [BK n ]) or the bus master (ECU) indicates the second state (Z2) when the first driver [TR a ] of the relevant bus junction ((BK1) to [BK n]) assumes the first state (Z1). This differentially induces the signal with a first differential level (z1). Preferably, the second driver of a bus node ((BK1) to [BK n ]) or the bus master (ECU) indicates the third state (Z3) when the first driver [TR a ] of the relevant bus junction ((BK1) to (BK n ]) assumes the third state (Z3). This causes the signal to be differentially impressed with a third differential level (z3).

[0030] The second driver can also be configured as an RS485 driver and preferably assume two of the two allowed states: In a first state, it places a second logical level (Z2) on the first single-wire bus (DB). a In a second state, it applies a first logical level (Z1) to the second single-wire bus (DB). b The second driver of the bus master (ECU) also operates in the addressing state of the data bus system and the bus nodes ((BK1) to [BK n]) as the second current sink for the second addressing currents of the second addressing current sources ((Iq'1) to [Iq' n ]) the bus junction ((BK1) to [BK n ]) and their second quiescent currents. Preferably, the second driver of a bus node ((BK1) to [BK n ]) or the bus master (ECU) indicates the second state (Z2) when the first driver [TR a ] of the relevant bus junction ((BK1) to [BK n ]) assumes the first state (Z1). This differentially induces the signal with a first differential level (z1). Preferably, the second driver of a bus node ((BK1) to [BK n ]) or the bus master (ECU) indicates the first state (Z1) when the first driver [TR a ] of the relevant bus junction ((BK1) to [BK n ]) assumes the second state (Z2). This causes the signal to be differentially impressed with a second differential level (z2). Furthermore, the second driver typically has a sub-device for detecting and avoiding a bus collision in the event of simultaneous access to the first single-wire bus (DB). a ) by a second driver of another bus node ((BK1) to [BK n ]) or the bus master (ECU). Figure 2

[0031] Each of the bus junctions ((BK1) to [BK nThe controller and bus master (ECU) preferably have a receiver (Rec). The receiver (Rec) extracts the data (DATA) contained in the bit stream packets (BP) on the serial, bidirectional, differential two-wire communication bus (DB) and preferably outputs this data, along with error information, via an output (out) of the receiver (Rec). The receiver (Rec) typically checks whether check information (CHKD) within the data information (DATA) of a bit stream packet (BP) indicates error-free reception by the receiver (Rec). If a bit stream packet (BP) was not received correctly by the receiver (Rec), the receiver (Rec) preferably signals this. The actual user circuitry at the receiver output (out) is described in the Fig. 2 not shown for clarity. These process the information received by the receiver (Rec) (out) and control the drivers [TR]. a , TR b] for the respective transmission process of a bus node ((BK1) to [BK n ]) or the bus master (ECU).

[0032] The data bus system has a common supply voltage line (V bat ) and typically a common reference potential [GND] that is in Fig. 2 is not shown.

[0033] Note that the Fig. 2 despite serial arrangement of the bus nodes ((BK1) to [BK n ]) exhibits a star structure of the data bus. The representation of the Fig. Route 2 breaks off at the third bus junction (BK3) for better clarity.

[0034] In one embodiment, a device for controlling electrical and / or electronic bus nodes ((BK1) to [BK] is provided. n]), in particular within a vehicle module, an interior light and / or exterior light such as a rear light module of a vehicle, which proposes a serial, bidirectional, differential two-wire communication bus (DB) with n bus nodes (BK1 to [BK n ]) has a . where n is a positive integer greater than 1. Furthermore, the proposed device has a bus master (ECU). The serial, bidirectional, differential communication bus (DB) consists of a first single-wire bus (DB a ) and a second single-wire bus (DB b ). Each bus hub (BK j ) the n bus nodes ((BK1) to [BK n ]) has a differential serial interface [IF j ] suitable for the serial, bidirectional, differential communication bus (DB). Each bus node (BK) j ) the n bus nodes ((BK1) to [BK n ]) preferably has a clock generator [CLKG j ], a scanning device [AT j], an address identification unit [ADR j ] and a bus node address register [BKADR j ] on. The serial, bidirectional, differential communication bus (DB) is designed so that it can preferably be in at least a first logical state (High, Z1) and in a second logical state (Low, Z2) and possibly in a third logical state (Idle, Z3).

[0035] Firstly, levels of the high-speed CAN protocol [HS-CAN] can be used. This will be explained first.

[0036] For this purpose, the serial, bidirectional, differential communication bus (DB) in the transmitters (TX) is used. a , TX b ) the respective bus hub (BK j ) each preferably via a high-impedance voltage divider per transmitter (TX) a , TX b ) preferably on a preferably vanishing differential voltage difference between the first single-wire bus (DB) a) and the second single-wire bus (DB b ) clamped according to the third logical state (Idle, Z3). Each of the transmitters (TX) a , TX b ) preferably includes one switch each, which, when activated, switches on the first single-wire bus (DB) a ) of the serial, bidirectional, differential communication bus (DB) by the first driver [TR a ] is brought to the first logical state (High, Z1) and the second single-wire bus (DB) b ) of the serial, bidirectional, differential communication bus (DB) by the second driver [TR b ] can be brought into a second logical state (Low, Z2). This is in Fig. 3 shown below. If the driver switches [TR a , TR b ] switched off (IDLE), the serial, bidirectional, differential communication bus (DB) again assumes the third logical state (Idle, Z3).

[0037] Secondly, levels from the RS484 protocol can be used. This will be explained second.

[0038] For this purpose, the serial, bidirectional, differential communication bus (DB) in the transmitters (TX) is used. a , TX b ) the respective bus hub (BK j ) each preferably via a high-impedance voltage divider per transmitter (TX) a , TX b ) preferably clamped to a differential voltage difference corresponding to the third logic state (Idle, Z3). Each of the transmitters (TX) a , TX bThe system preferably comprises a half-bridge, which, by inversely controlling the serial, bidirectional, differential communication bus (DB), can be brought to the first logical state (High, Z1) and to a second logical state (Low, Z2). When the half-bridges are switched off (IDLE), the serial, bidirectional, differential communication bus (DB) again assumes the third logical state (Idle, Z3). Figure 3

[0039] The serial interface (IF) j ) of at least one bus hub (BK) j ) the n bus nodes ((BK1) to [BK n Each [ ]) is connected to the serial, bidirectional, differential communication bus (DB) to send and / or receive data via this serial, bidirectional, differential communication bus (DB). It typically comprises [ ] per bus node (BK ). j ) the transmitters already mentioned (TX) a , TX b) and a receiver (Rec). Clock and data extraction within the bus nodes ((BK1) to [BK n The bit packets (BP) are not shown in the diagrams for simplification, as they can be found in the prior art. The bus master (ECU) receives control commands externally for the n bus nodes ((BK1) to [BK1]. n ]) and sends these control commands via the serial, bidirectional, differential communication bus (DB) to the bus nodes ((BK1) to [BK n The bus master (ECU) transmits the bit streams to be sent via the serial, bidirectional, differential communication bus (DB), depending on a clock signal (CLK) within the bus master (ECU). The bus master (ECU) receives data in the opposite direction from the bus nodes ((BK1) to [BK1]. n ]) generated bitstreams via the serial, bidirectional, differential communication bus (DB). Clock generator [CLKG j] within each bus hub (BK j ) the n bus nodes ((BK1) to [BK n ]) generate within each bus node (BK j ) this bus junction ((BK1) to [BK n ]) a respective sampling signal [CLKA j ]. The scanning device [AT j ] of this respective bus junction (BK) j ) the n bus nodes ((BK1) to [BK n ]) then samples depending on the sampling signal [CLKA j ] this bus junction (BK) j ) the bit streams transmitted via the serial, bidirectional, differential communication bus (DB). These can be bit streams from the bus master (ECU) to the bus nodes ((BK1) to [BK n ]) as well as bit streams from the other bus nodes ((BK1) to [BK n ]) to the bus master (ECU) or to other bus nodes ((BK1) to [BK n ]) act. The relevant bus junction (BK) j) thus extracts a local bitstream within this bus node (BK) from the signals on the serial, bidirectional, differential communication bus (DB). j ), from the output of the receiver (Rec) by sampling the output signal of the receiver (Rec) or a signal derived from it. The bus master (ECU) sends the bitstreams to be transmitted as sequences of bits in bitstream packets (frames, BP). The bus nodes also preferably transmit their bitstreams to be transmitted as sequences of bits in bitstream packets (frames, BP), which preferably correspond in structure to those of the bus master (ECU). For the sake of simplicity, only the bitstream packets (frames, BP) of the bus master (ECU) are discussed here. For the bitstream packets (BP) of the bus nodes ((BK1) to [BK n ]) The same applies.

[0040] As explained previously, this setup means that the serial, bidirectional, differential two-wire communication bus (DB) is used when neither the bus master (ECU) nor any of the n bus nodes ((BK1) to [BK n ]) transmits data via the serial, bidirectional, differential two-wire communication bus (DB), the first logical state (Z1) (dashed in Fig. 3) or assumes the third logical state (Z3) - which is preferred.

[0041] The proposed preferred structure of the bit stream packets (BP) sent by the bus master (ECU) is determined using Fig. 3 explained. The one with V diff The signal is intended to represent the differential level on the serial, bidirectional, differential communication bus (DB), i.e., the voltage difference between the first single-wire bus (DB). a ) and the second single-wire bus (DB b ).

[0042] The diagram labeled HS-CAN describes the corresponding levels when CAN drivers [TR a , TR b ] be used.

[0043] The diagram labeled RS485 represents the corresponding levels when RS485 drivers [TR a , TR b ] be used.

[0044] The drivers [TR a , TR b ] deliver three voltage levels in the HS-CAN scheme, but only two differential voltage levels.

[0045] The drivers [TR a , TR b In the RS485 scheme, they provide two voltage levels and only two differential voltage levels.

[0046] It is proposed here that at least some of the bitstream packets (BP) sent by the bus master (ECU) contain the following: 1. a start signal (START) in the form of i bits with i as a positive integer with i-1≤m / 3 of the m bits of the respective bit stream packet (BP) with a second logical differential state (z2) on the serial, bidirectional, differential two-wire communication bus (DB), 2. a synchronization information (SYNC), for synchronizing the sampling signal [CLKA j ] the clock generator [CLKG j ] the bus hub (BK j ) with the clock (CLK) of the bus master (ECU), 3. Data information (DATA) in the form of k bits with k

[0047] The address identification units ([Adr1] to [Adr n ]) the bus junction ((BK1) to [BK n ​]) and possibly also the bus master (ECU) evaluate the address information (ADRD) of the bit stream packets (BP). The address recognition units ([Adr1] to [Adr n ]) the bus junction ((BK1) to [BK n ]) only allow the use of the contained user information (INFO) if the content of the address information (ADRD) matches the content of the bus node address register [BKADR]. j ] of the bus junction (BK) j ) corresponds. Preferably, the bus junctions (BK) j ) the n bus nodes ((BK1) to [BK n ]) Means to perform an auto-addressing procedure for a two-wire data bus to use the bus node address register [BAKDR j ] to fill with a logical bus node address that corresponds to the physical position of this bus node (BK) j ) the n bus nodes ((BK1) to [BK n]) within the serial, bidirectional, differential two-wire communication bus (DB). This is a crucial step that is not yet resolved in the current state of the art.

[0048] In a refinement of the procedure, each bus junction (BK) j ) the n bus nodes ((BK1) to [BK n ]) a microcontroller [µC j ] on, which performs some of the previously mentioned tasks, such as those of the address identification unit [ADR] j ] of the respective bus junction (BK j ) and / or the scanning device [AT j ] of the respective bus junction (BK j ) can be handled by a software program. It is now proposed that preferably at least one additional bus node (BK) should be added. j ) the n bus nodes ((BK1) to [BK n ]) at least one light source [LED j ] has and at least one energy supply means [EV j ] exhibits. That at least one energy supply means [EV] j] of at least one bus junction (BK) j ) the n bus nodes ((BK1) to [BK n ]) is then responsible for the energy supply of at least one light source [LED]. j ] of at least one bus junction (BK) j ) the n bus nodes ((BK1) to [BK n ]) provided.

[0049] As before, the clock generator [CLKG] j ] of each bus hub (BK j ) the n bus nodes ((BK1) to [BK n ]) a sampling signal [CLKA j within the respective bus hub (BK) j ) the n bus nodes ((BK1) to [BK n ]). The scanning device [AT j ] one preferably every bus hub (BK j ) the n bus nodes ((BK1) to [BK n ]) samples again depending on the sampling signal [CLKA j ] this bus junction [BK j] Bitstreams sent via the serial, bidirectional, differential two-wire communication bus (DB) to create a local bitstream within this bus node (BK) j to obtain. The bit stream packets (BP) preferably consist of a temporal sequence of m individual bits of the same time length t. B with m as a positive integer, whose time length t B by no more than a factor of + / - (0.4 / m)*t B and / or better + / - (0.2 / m)*t B and / or better + / - (0.1 / m)*t B and / or better + / - (0.05 / m)*t B within a bitstream packet (BP) varies. At least some of the bitstream packets (BP) sent by the bus master (ECU) preferentially contain the following (see Fig. 3): 1. A start signal (START) in the form of i bits with i as a positive integer with i-1≤m / 3 with a second differential logic state (z2) on the serial, bidirectional, differential two-wire communication bus (DB); 2. A synchronization information (SYNC) consisting of k-bits, where k is a positive integer, in particular k j ) the clock generator [CLKG j ] the bus hub (BK j ) on the phase of the clock (CLK) of the bus master (ECU) and for frequency synchronization of the sampling signal [CLKA j ] the clock generator [CLKG j ] the bus hub (BK j ) to the frequency of the clock (CLK) of the bus master (ECU); 3. Data information (DATA) from the remaining bits of the mik bits of the m bits of the respective bit stream packet (BP), wherein the data information (DATA) includes address information (ADRD), user information (INFO), and check information (CHKD).​

[0050] At least some of the user information (INFO) includes lighting information (ILD) for controlling the power supply of the light sources [LED]. j ] of the bus junction (BK) j ) through the energy supply medium [EV j ] of the bus junction (BK) j ) depending on this lighting information. For this purpose, a lighting register is typically used within the power supply unit [EV]. j ] described with a value depending on the received illumination information (ILD), which describes the emission characteristics such as color, color temperature and brightness of the connected light sources [LED]. j ] determined. So that this data passes through the relevant bus node (BK) j ) to be accepted, the logical content of the address information (ADRD) must match the content of the bus node address register [BKADR]. j ] of the bus junction (BK) j). If this is not the case, the data information (DATA) is ignored. The same applies if the integrity check of the received data information (DATA) using the also received check data (CHKD) reveals that the reception was faulty. The respective address identification unit [ADR] j ] of the respective bus junction (BK j ) evaluates the address information (ADRD) of a received bit stream packet (BP) and only then allows the use of the contained payload information (INFO) by the rest of the bus node devices of the bus node (BK). j ) if the content of the received address information (ADRD) matches the content of the bus node address register [BKADR j ] of the bus junction (BK) j ) corresponds and is error-free. In contrast to the state of the art, bus nodes ((BK1) to [BK n]) Means to perform an auto-addressing procedure for a serial, bidirectional, and differential communication bus (DB). As a result of such an auto-addressing procedure, the bus node address register [BAKDR] is created. j ] this bus junction ((BK1) to [BK n ]) filled with a logical bus node address that corresponds to the physical position of this bus node (BK) j ) the n bus nodes ((BK1) to [BK n ]) within the serial, bidirectional, differential two-wire communication bus (DB).

[0051] The tests described above can still be used. In a first variant of the device, the bus master (ECU) and / or bus node ((BK1) to [BK n ]) equipped with means to detect a malfunctioning clock generator [CLKG] based on the evaluation of the test information (CHKD). j ] one or more bus hubs (BK) j ) close.

[0052] The following describes various exemplary auto-addressing methods and other variants that can be used as examples: ASYMMETRIC AUTOADDRESSING WITH BUS SHUNT RESISTORS NOT FLOWED THROUGH THE ADDRESSING CURRENT Figure 4

[0053] It is now typically desired that the bus nodes ((BK1) to [BK n ]) independently determine their physical position within the data bus system in the serial, bidirectional, differential two-wire communication bus (DB) and receive a bus node address based on this position, so that the logical address corresponds to the physical address. This has the advantage that with identically constructed bus nodes ((BK1) to [BK n]) only one type of bus node needs to be maintained in production, which prevents potential errors and improves logistics. To implement such auto-addressing, one might consider incorporating auto-addressing. This is in Fig. 4 is shown here. The first single-wire bus (DB) is shown as an example. a ) a first bus shunt resistor (R2) per bus node ((BK1) to [BK n ]) inserted. A second differential amplifier (D2) is used to measure the first current through the first single-wire bus (DB). a ) by means of the first shunt resistor (R2). The output of the second differential amplifier (D2), which is used to measure the first current through the first single-wire bus (DB) a ) is connected to a third comparator (D3), which compares the output value of the second differential amplifier (D2) with a first reference value (Ref). This is equivalent in effect to a comparison of the first current in the first single-wire bus (DB).a ) through the first bus shunt resistor (R2) with a first reference current [I ref The data bus system with its bus nodes ((BK1) to [BK n The bus can now be switched between an addressing state and a normal state by the bus master (ECU) using a special bus signal. During the addressing state, an auto-addressing procedure is performed. When the data bus system is in the addressing state, the bus nodes ((BK1) to [BK] are in the addressing state. n ]), which can perform the auto-addressing procedure in a corresponding addressing state of the bus nodes. The first addressing current source (Iq) j ) (with 1≤j≤n) of the respective bus junction (BK) j ) is switched off in the normal state or fulfills another function such as supplying power to a light source [LED]. j The first addressing current source (Iq) j ) (with 1≤j≤n) of the respective bus junction (BK) j) is switched off in addressing state when the respective bus node (BK) j ) using these first means (R2, D2, D3) detects a first current through its first bus shunt resistor (R2) which is above a threshold corresponding to the first reference current [I Ref ] lies. In the example of the Fig. 4 feeds the respective first addressing current source (Iq). j ) of a bus hub (BK j ) their first addressing stream from the bus master (ECU) before the respective first bus shunt resistor (R2) of the respective bus node (BK) j ) into the first single-wire bus (DB a ) if the bus junction (BK) j ) using the previously described first means (R2, D2, D3), it determines that only a first current below this threshold flows through its first bus shunt resistor (R2) towards the bus master (ECU). This has the disadvantage that a self-test of the bus node (BK) j) is not possible at this injection point of the first addressing current. Furthermore, the first driver [TR] may be overloaded during the power-on process. a ] of the bus master (ECU). Therefore, the first addressing current of the first addressing current sources ((Iq1) to [Iq] must be n ]) be limited to an nth part of the maximum current value that the first driver [TR a ] can still absorb. This limits the resistance value of the first bus shunt resistor (R2) from below, since otherwise the level of the voltage drop across the first bus shunt resistor (R2) of a bus node (BK) would be too high. j ) too small for detection by the first means (R2, D2, D3) of this bus junction (BK) j ). This leads to increased sensitivity to electromagnetic interference, which should actually be avoided. Furthermore, the asymmetry between the first single-wire bus (DB) a ) the Fig. 4 and the second single-wire bus (DB) b ) the Fig. 4. This concerns the coupling of common-mode interference into the differential signal on the serial, bidirectional, differential two-wire communication bus (DB), which should also be avoided. If a bus node (BK) represents j ) in the addressing state, after a certain predetermined waiting time after entering the addressing state, it determines that its first addressing current source (Iq) j If it is not yet switched off, it is the last bus node (BK) that has not yet been assigned a valid bus node address. j It then adopts a bus node address typically offered by the bus master (ECU) as its new valid bus node address. Since it then has a valid bus node address, it switches its addressing current source (Iq). j ) and then waits for the end of the addressing state of the data bus system without its addressing current source (Iq). j) to reactivate the data bus system's addressing state before this point. The bus node [BK j-1] , which, as the next bus node in the next initialization run, then determines that its addressing stream source (Iq) j If the bus node address is not switched off, it then adopts the next available bus node address offered by the bus master (ECU) as its valid bus node address, and so on. This continues until all bus nodes ((BK1) to [BK] have been assigned. n ]) of the data bus system have thus obtained a valid bus node address. The bus master then typically reassigns the data bus system and its bus nodes ((BK1) to [BK n ]) back to the normal state, retaining the valid bus node addresses. This recommended retention of valid bus node addresses during the transition from the addressing state to the normal state is preferred for the entire document. Symmetrical auto-addressing with bus shunt resistors not carried by the addressing current (Figure 5)

[0054] One problem that arises with auto-addressing, as mentioned, is that of symmetry. Since the serial, bidirectional, differential two-wire communication bus (DB) is a differential bus, the two single-wire buses (DB) should be a and DB b The data bus system should therefore be constructed as symmetrically as possible to avoid providing a point of attack for common-mode interference. j) for the serial, bidirectional, differential two-wire communication bus (DB), consisting of a first single-wire bus (DB1) and a second single-wire bus (DB2), featuring a first bus shunt resistor (R2) inserted into the first single-wire bus (DB1) and a second bus shunt resistor (R2') inserted into the second single-wire bus (DB2). A corresponding proposal based on Fig. 4 is in Fig. 5 shown. The two bus shunt resistors (R2, R2') per bus node (BK) j ) the bus junction ((BK1) to [BK n ]) are preferably integrated monolithically and matching, with a relative resistance value deviation within the respective bus node (BK). j ) manufactured with less than 10% and / or better less than 5% and / or better less than 2% and / or better less than 1% and / or better less than 0.5%.

[0055] Each bus hub (BK) j ) the bus junction ((BK1) to [BK n]) is now in addition to the first means (R2, D2, D3) for detecting the first current through the first bus shunt resistor (R2) in the first single-wire bus (DB) a ) with second means (R2', D2', D3') for detecting the second current through the second bus shunt resistor (R2') in the second single-wire bus (DB) b ) equipped.

[0056] The second single-wire bus (DB) is now also an example of this. b ) a second bus shunt resistor (R2') per bus node ((BK1) to [BK n ]) inserted. A further second differential amplifier (D2') is used to measure the second current through the second single-wire bus (DB). b ) by means of the second shunt resistor (R2') of the relevant bus node (BK) j ). The output of the further second differential amplifier (D2'), which is used to measure the second current through the second single-wire bus (DB) b) is connected to a further third comparator (D3'), which compares the output value of the further second differential amplifier (D2') with a further reference value (Ref'), which is typically equal to the first reference value (Ref). This is equivalent in effect to a comparison of the second current in the second single-wire bus (DB). b ) through the second bus shunt resistor (R2') with a second reference current [I' ref ], which is typically equal to the previously mentioned first reference current [I ref ] is selected. The second addressing current source (Iq') j ) (with 1≤j≤n) of the respective bus junction (BK) j ) is switched off when the respective bus node (BK) j ) using these second means (R2', D2', D3') detects a first current through its second bus shunt resistor (R2') which is above a threshold corresponding to the first reference current [I Ref ] lies. In the example of the Fig. 5 feeds the respective second addressing current source (Iq' j ) of a bus hub (BK j ) the second addressing stream from the bus master (ECU) also before the respective second bus shunt resistor (R2') of the respective bus node (BK) j ) into the second single-wire bus (DB) b ) if the bus junction (BK) j ) using the previously described second means (R2', D2', D3') determines that only a second current below this threshold flows through its second bus shunt resistor (R2') towards the bus master (ECU). As before, this has the disadvantage that a self-test of the bus node (BK) j ) is not possible. Furthermore, the second driver [TR] can also be overloaded during the power-on process. b ] of the bus master (ECU). Therefore, the second addressing stream must come from the second addressing stream sources ((Iq'1) to [Iq' n]) be limited to an nth part of the maximum current value that the second driver [TR b ] can still absorb. This limits the resistance value of the second bus shunt resistor (R2') downwards, since otherwise the level of the voltage drop across the second bus shunt resistor (R2') of a bus node (BK) would be too high. j ) too small for detection by the second means (R2', D2', D3'). This leads to increased sensitivity to electromagnetic interference, which should be avoided. The symmetry between the first single-wire bus (DB) a ) the Fig. 5 and the second single-wire bus (DB) b ) the Fig. However, 5 now leads to a reduced coupling of common-mode interference into the differential signal on the serial, bidirectional, differential two-wire communication bus (DB), which is an advantage.

[0057] Both addressing current sources (Iq) are always preferred. j , Iq'j ) of a bus hub (BK j ) switched off when the bus node (BK) j ) determines, using the first means described above (R2, D2, D3), that a first current above the threshold flows through its first bus shunt resistor (R2) towards the bus master (ECU), or determines, using the second means described above (R2', D2', D3'), that only a second current above this threshold flows through its second bus shunt resistor (R2') towards the bus master (ECU). Symmetrical auto-addressing with bus shunt resistors flowing through the addressing current (Figure 6)

[0058] Fig. 6 now shows a different proposal based on the Fig. 5. Key difference to Fig. 5 is now that the respective first addressing stream sources ((Iq1) to [Iq n]) from the perspective of the bus master (ECU), the first addressing current behind the first bus shunt resistors (R2) in the addressing phase in which the respective bus node (BK) j ) is in an addressing state, feed in when the respective bus node (BK) j ) using the first means (R2, D2, D3) determines a current value of the first current through the first bus shunt resistor (R2) that is smaller than a predetermined first reference current value [I ref ] is. The third comparator (D3) is preferably now a third differential amplifier (D3). In contrast to the proposal of the Fig. 5 becomes the first addressing stream of the respective first addressing stream source (Iq). j ) of the respective bus junction (BK) j ) however, it is now readjusted until the first current through the first bus shunt resistor (R2) matches the specified first reference current [I ref ] corresponds. Similarly, in deviation from Fig. 5 the respective second addressing current sources ((Iq'1) to [Iq' n ]) from the perspective of the bus master (ECU), the respective second addressing stream is also behind the corresponding second bus shunt resistors (R2') in the addressing phase in which the respective bus node (BK) j ) is in an addressing state, if the respective bus node (BK) j ) using the second means (R2', D2', D3') determines a current value of the second current through the second bus shunt resistor (R2) that is smaller than a predetermined second reference current value [I' ref ] is, which is preferably equal to the first reference current value [I ref ] is. The further third comparator (D3') is preferably now another third differential amplifier (D3'). In contrast to the proposal of the Fig. 5 becomes the second addressing stream of the respective second addressing stream source (Iq' j ) of the respective bus junction (BK) j) however, it is now also readjusted until the second current through the second bus shunt resistor (R2') matches the specified second reference current [I' ref ] corresponds.

[0059] Of course, it is possible to configure the Fig. 6 the addressing current sources ((Iq1) to [Iq n ], (Iq'1) to [Iq' n ]) to switch instead of to regulate.

[0060] The proposed bus junction (BK) j ) is thus connected to a first addressing current source (Iq) j ) to determine the bus position of the bus junction (BK) j ) in the serial, bidirectional, differential two-wire communication bus (DB), which provides a first addressing stream in the manner of the first single-wire bus (DB) a ) of the serial, bidirectional, differential two-wire communication bus (DB) can additionally feed in such a regulated manner that the first total current (i j) through the first bus shunt resistor (R2) of the bus junction (BK) j ) a predetermined or calculated or otherwise determined first total flow [I ref ] corresponds. Preferably, the first addressing current flows through the first bus shunt resistor (R2). Preferably, the respective bus node (BK) j ) now with a second addressing current source (Iq' j ) to determine the bus position of the bus junction (BK) j ) in the serial, bidirectional, differential two-wire communication bus (DB), which provides a second addressing stream in the manner of the second single-wire bus (DB) b ) of the serial, bidirectional, differential two-wire communication bus (DB) can additionally feed in regulated current so that the second total current (i j ) through the second bus shunt resistor (R2') of the bus junction (BK) j ) a predetermined or calculated or otherwise determined second total current [I' ref] corresponds. The second addressing current now flows through the second bus shunt resistor (R2'). For symmetry, it is helpful if the two addressing current sources (Iq) j , Iq' j ) are executed in a matching manner. Furthermore, all measuring and controlling components of the control loop should be configured for these two addressing current sources (Iq). j , Iq' j ) must be executed matching to achieve full symmetry. Figures 7 to 9

[0061] The Fig. Figures 7 to 9 describe the proposed advantageous properties of the control system. The control system is illustrated using the example of controlling the first addressing current sources ((Iq1) to [Iq]. n ]) explained, but also applies to the second addressing stream sources ([Iq'1] to [Iq' n ]) in an analogous manner. The control characteristic for the first addressing current source (Iq) j ) of a bus junction (Bk j) is preferably generated by a first filter (F) that produces a first control signal [rw] from the output signal of the third differential amplifier (D3). j ] of the relevant bus junction (BK) j ) generated, with which the first addressing current source (Iq) j ) of the relevant bus junction (BK) j ) is controlled. The control characteristic for the second addressing current source (Iq') j ) of a bus junction (Bk j ) is preferably generated by a second filter or a second controller (F') which derives a second control signal (rw') from the output signal of the further third differential amplifier (D3'). j ) of the relevant bus junction (BK) j ) generated, with which the second addressing current source (Iq') j ) of the relevant bus junction (BK) j ) is controlled. Figure 7

[0062] Fig. Figure 7 shows, as an example, the waveform of the output current (i1) of the first bus node (BK1), the output current (i2) of the second bus node (BK2), and the output current (i3) of the third bus node (BK3) in an exemplary data bus system with n=3 bus nodes (BK1 to BK3). It also shows the first addressing current (I). 1_intern ) the first addressing current source (Iq1) of the first bus node (BK1), the first addressing current (I2_ intern ) the first addressing current source (Iq2) of the second bus node (BK2) and the first addressing current (I3_ intern ) of the first addressing current source (Iq3) of the third bus node (BK3). Here, the time constants for the ramp-up and ramp-down of the first addressing current of the first addressing current sources are approximately the same. This results in an overshoot. It is clearly visible that the first addressing current (I 1_intern) the first addressing current source (Iq1) of the first bus node (BK1) and the first addressing current (I2_ intern ) of the first addressing current source (Iq2) of the second bus node (BK2) are regulated down by the controllers of these first auto-addressing bus nodes, while the first addressing current (I3_ intern ) of the first addressing current source (Iq3) of the third bus node (BK3) to the reference value [I ref ] is regulated. The settling time is determined by a first time constant [t1] for ramping up the first addressing current of the first addressing current sources (Iq1 to Iq3). Figure 8

[0063] Fig. Figure 8 shows the waveform of the output current (i1) of the first bus node (BK1), the output current (i2) of the second bus node (BK2), and the output current (i3) of the third bus node (BK3). It also shows the current (I 1_intern) of the first addressing current source (Iq1) of the first bus node (BK1), the current (I2_ intern ) of the first addressing current source (Iq2) of the second bus node (BK2) and the current (I3_ intern ) of the first addressing current source (Iq3) of the third bus node (BL3). Here, the first time constants [t1] for the ramp-up of the first addressing current of the first addressing current sources are approximately ten times as long as the second time constants [τ]. 2] for reducing the first addressing current of the first addressing current sources. Only a minimal overshoot occurs. Figure 9

[0064] Fig. Figure 9 shows the waveform of the output current (i1) of the first bus node (BK1), the output current (i2) of the second bus node (BK2), and the output current (i3) of the third bus node (BK3). Here, the first time constants [τ1] for ramping up the first addressing current of the first addressing current sources are approximately one hundred times longer than the second time constants [τ 2] for the reduction of the first addressing current of the first addressing current sources. No overshoot occurs.

[0065] The bus junction (BK) preferably includes j ) first means (R2, D2) to detect the current through the first bus shunt resistor (R2) and / or second means (R2', D2') to detect the current through the second bus shunt resistor (R2').

[0066] If the data bus system is designed such that the first and second addressing streams of the two addressing stream sources (Iq) j , Iq' jSince the current is always injected downstream of the bus shunt resistors (R2, R2') from the bus master (ECU), the current detected through the first bus shunt resistor (R2) and / or through the second bus shunt resistor (R2') can be used for a self-test. With perfect symmetry, the voltage drops across both bus shunt resistors (R2, R2') should ideally be equal. A cold solder joint, for example, can therefore be easily detected in this way. Figure 10

[0067] For error detection, it is advantageous to use the bus node (BK). j ) to provide with a first detection device (DET) that detects the internal signals (ds1, ds3) of the bus node (BK) j ) checks for plausibility. The internal signals are preferably control signals within the bus node (BK). jIn the case of bus symmetry, the symmetry of these signals can be checked, for example. However, checks per channel are also possible. Reference is made to the as yet unpublished German patent application DE 10 2017 122 365 B3. Fig. Figure 10 shows the principle of such a detection. Fig. Figure 10 shows the control loop of a bus node (BK). j ). Here, j represents a position in the bus chain of bus nodes ((BK1) to [BK n ]) in the form of a positive, integer, natural number. It is a j-th bus node (BK). j ), who is able to • Firstly, to recognize a swapping of his bus entrances with his bus exits and • Secondly, in this case as an exemplary countermeasure ◯ the injection point for the first addressing current of its regulated first addressing current source (Iq) j) to position it in front of or behind its first bus shunt resistor (R2) so that auto-addressing is possible depending on the circuit configuration and ◯ the injection point for the second addressing current of its regulated second addressing current source (Iq' j ) to position it in front of or behind its second bus shunt resistor (R2') so that auto-addressing is possible depending on the circuit configuration.

[0068] In the Fig. 10 will only exemplify the repositioning of the feed-in point of the first addressing current of the first addressing current source (Iq). j ) of the bus junction under consideration (BK j ) demonstrated. For the repositioning of the feed point of the second addressing current of the second addressing current source (Iq') j ) of the bus junction under consideration (BK j The same applies.

[0069] The in Fig. 10 exemplary j-th auto-addressing bus nodes (BK) j) indicates for the repositioning of the feed point of the first addressing current of the first addressing current source (Iq j ) of the bus junction under consideration (BK j ) a first detection device (DET) capable of detecting a swap of the bus input of the j-th bus node (BK) j ) for the first single-wire bus (DB a ) with the bus exit of the j-th bus junction (BK) j ) for the first single-wire bus (DB a ) to determine. For this purpose, the exemplary first detection device (DET) checks internal signals of the j-th bus node (BK). j ) for plausibility. Do the internal signals of the j-th bus node (BK) allow j ) on a swap of the bus entrance of the j-th bus node (BK) j ) for the first single-wire bus (DB a ) with the bus exit of the j-th bus junction (BK) j ) for the first single-wire bus (DB a) close securely, the first detection device (DET) can potentially take various exemplary measures: a. Signaling the error to a user; b. Signaling of the fault to the bus master (ECU) by means of a response to a diagnostic request (broadcast message) or by means of an interrupt line; c. Use of a predetermined error address as a valid bus node address; d. Reconfiguration of the internal topology to neutralize the error; e. Reparameterization of internal sub-devices such as power sources to neutralize the fault; Further measures are conceivable.

[0070] In the example of the Fig. 10. A reconfiguration of the internal topology is provided to neutralize the error. In the Fig. 10 For example, the first detection device (DET) changes the injection point for the first addressing current of the regulated first addressing current source (Iq). j ) of the j-th bus junction (BK j ) for example using a first analog demultiplexer (X3) and reverses the polarity of the inputs or output of the second differential amplifier (D2) using the polarity signal (pol). Figure 11

[0071] For better clarity, the analog device for the second single-wire bus (DB) b ) not shown, as it is structured analogously. The one in Fig. 11 simplified examples of j-th auto-addressing bus nodes (BK) j ) indicates for the repositioning of the feed point of the second addressing current of the second addressing current source (Iq') j ) of the bus junction under consideration (BK j) a second detection device (DET') capable of detecting a swap of the bus input of the j-th bus node (BK) j ) for the second single-wire bus (DB b ) with the bus exit of the j-th bus junction (BK) j ) for the second single-wire bus (DB b ). To this end, the exemplary second detection device (DET') checks further internal signals of the j-th bus node (BK). j ) for plausibility. Do the internal signals of the j-th bus node (BK) allow j ) on a swap of the bus entrance of the j-th bus node (BK) j ) for the second single-wire bus (DB b ) with the bus exit of the j-th bus junction (BK) j ) for the second single-wire bus (DB b ) close securely, so the second detection device (DET') can potentially take various exemplary measures: a. Signaling the error to a user; b. Signaling of the fault to the bus master (ECU) by means of a response to a diagnostic request (broadcast message) or by means of an interrupt line; c. Using an error address as a bus node address; d. Reconfiguration of the internal topology to neutralize the error; e. Reparameterization of internal sub-devices such as power sources to neutralize the fault; Further measures are conceivable.

[0072] Here too, a reconfiguration of the internal topology can be provided to neutralize the error. For example, the second detection device (DET') can also be the injection point for the second addressing current of the regulated second addressing current source (Iq'). j ) of the j-th bus junction (BK j) for example, by using a second analog demultiplexer (X3') and by using a second polarity signal (pol') to change the polarity of the inputs or output of the further second differential amplifier (D2').

[0073] As an alternative to the previous example of the Fig. 10 and Fig. 11. Is it possible to reparameterize internal sub-devices such as current sources to neutralize the error if, instead of a first addressing current source (Iq), j ) of the j-th bus junction (BK j ) and a first multiplexer (X3) a first addressing current source [Iq j1 ] of the j-th bus junction (BK j ) and, for example, another first addressing current source [Iq j2 ] of the j-th bus junction (BK j ) are used, of which the first addressing current source [Iq j1 ] of the j-th bus junction (BK j) injects its first addressing current before the first bus shunt resistor (R2) and the next first addressing current source [Iq j2 ] of the j-th bus junction (BK j ) injects its further first addressing current behind the first bus shunt resistor (R2). In that case, the first detection device (DET) would receive the first addressing current from one of the two first addressing current sources ([Iq]). j1 ], [Iq j2 ]) set to zero, so that the equivalent effect is the same as when combining a first addressing current source (Iq) j ) of the j-th bus junction (BK j ) is achieved by switching through a first demultiplexer (X3).

[0074] For the second single-wire bus (DB) b ) would then instead of a second addressing current source (Iq' j ) of the j-th bus junction (BK j ) and a second multiplexer (X3') a second addressing current source [Iq' j1] of the j-th bus junction (BK j ) and, for example, another second addressing current source [Iq' j2 ] of the j-th bus junction (BK j ) are used, of which the second addressing current source [Iq' j1 ] of the j-th bus junction (BK j ) feeds its second addressing current in front of the second bus shunt resistor (R2') and the further second addressing current source [Iq' j2 ] of the j-th bus junction (BK j ) feeds its second addressing current behind the second bus shunt resistor (R2'). In that case, the second detection device (DET') would detect the second addressing current from one of the two second addressing current sources ([Iq'). j1 ], [Iq' j2 ]) set to zero, so that the equivalent effect is the same as when combining a second addressing current source (Iq' j ) of the j-th bus junction (BK j) is achieved by switching through a further second demultiplexer (X3').

[0075] For example, the first detection device (DET) can detect that the first control value of the first control signal (rw) j ) of the j-th bus junction (BK j ) the first addressing stream of the first addressing stream source (Iq j ) maximized. This can be achieved, for example, with a suitable design by comparing the first control value of the first control signal (rw). j ) with a tenth threshold (Ref10). Is the derivative of the first addressing current of the first auto-addressing current source (Iq) j ) after the first control value of the first control signal (rw j ) positive, this means that the first control value of the first control signal (rw) j) above the tenth threshold (Ref10). Furthermore, the first detection device (DET) can simultaneously compare the output (ds2) of the second differential amplifier (D2) with an eleventh threshold (Ref11). If the value of the output (ds2) of the second differential amplifier (D2) is below the eleventh threshold (Ref11), the first detection device (DET) can infer a negative voltage drop across the first bus shunt resistor (R2) or a voltage drop across the first bus shunt resistor (R2) close to zero. This state is illegal because the first auto-addressing current source (Iq) j ) yes, it provides a positive first addressing current, which, if correctly installed, should flow through the first bus shunt resistor (R2), but this obviously does not happen.

[0076] For example, the second detection device (DET') can also detect that the second control value of the second control signal (rw') j ) of the j-th bus junction (BK j ) the second addressing stream of the second addressing stream source (Iq' j ) maximized. This can be achieved, for example, with a suitable design by comparing the second control value of the second control signal (rw'). j ) with a further tenth threshold (Ref10'), which is preferably equal to the tenth threshold (Ref10). Is the derivative of the second addressing current of the second auto-addressing current source (Iq') j ) after the second control value of the second control signal (rw' j ) positive, this means that the second control value of the second control signal (rw') j) above the further tenth threshold (Ref10'), which is preferably equal to the tenth threshold (Ref10). Furthermore, the second detection device (DET') can simultaneously compare the further output (ds2') of the further second differential amplifier (D2') with a further eleventh threshold (Ref11'). The further eleventh threshold (Ref11') is preferably equal to the eleventh threshold (Ref11). If the value of the further output (ds2') of the further second differential amplifier (D2') is below the further eleventh threshold (Ref11), the second detection device (DET') can conclude that there is a negative voltage drop across the second bus shunt resistor (R2') or that the voltage drop across the second bus shunt resistor (R2') is close to zero. This condition is illegal because the second auto-addressing current source (Iq') j) yes, it provides a positive second addressing current, which, if correctly installed, should flow through the second bus shunt resistor (R2'), but this obviously does not happen.

[0077] Preferably, the first detection device (DET) and the second detection device (DET') form a unit.

[0078] A change in bus direction, as described above, preferably only occurs if both detection devices (DET, DET') detect a reversal of the bus connections.

[0079] The detection devices (DET, DET') can signal a detected error, for example, via a respective error signal (er, er') to a bus node, internal computer, or suitable control system.

[0080] The test results can be accessed via the bus hub (BK). j ) or a sub-device (DET, DET') of the bus node (BK j) are used to initiate and take predetermined actions when one or more of the detection devices (DET, DET') receive implausible internal signals within the bus node (BK). j ) determine. For example, the bus junction (BK) j ) assume a swapping of input and output. To compensate for this, it is advantageous if the bus node (BK) j ) a first sub-device (X3) comprising the injection point of the first addressing current of the first addressing current source (Iq) j ) can change and / or if the bus node (BK) j ) a second sub-device (X3') which has the injection point of the second addressing current of the second addressing current source (Iq') j ) can be changed. The changes are preferred for controlling the first single-wire bus (DB). a) and the first bus shunt resistor (R2) synchronously with the analog changes for controlling the second single-wire bus (DB) b ) and the second bus shunt resistor (R2'). Instead of switching the injection point of the addressing current sources (iq) j and iq' j ) using the aforementioned demultiplexers (X3, X3') also allows the use of two different first addressing current sources instead of a single first addressing current source (Iq). j ) conceivable, which transforms the switching via the demultiplexer (X3) into a switching between these two first addressing current sources. Such a bus node (BK) j ) therefore has instead of a first addressing current source (Iq) j) a first addressing current source and a second first addressing current source, wherein the first addressing current source injects its first addressing current into a node connected to the first terminal of the first bus shunt resistor (R2) when it injects current, and wherein the second first addressing current source injects its first addressing current into a node connected to the second terminal of the first bus shunt resistor (R2) when it injects current. The two first addressing current sources preferentially inject their addressing currents such that the resulting total addressing current flows through the first bus shunt resistor (R2), thus ensuring self-test capability. The bus node (BK) jIn contrast to the prior art, this design features a second addressing current source and a further second addressing current source instead of a single second addressing current source. The second addressing current source injects its addressing current into a node connected to the first terminal of the second bus shunt resistor (R2') when it injects current, and the further second addressing current source injects its addressing current into a node connected to the second terminal of the second bus shunt resistor (R2') when it injects current. These two second addressing current sources also preferably inject their addressing currents such that the addressing current flows through the second bus shunt resistor (R2') to ensure self-test capability.

[0081] When multiple bus nodes are connected to a data bus, it must be ensured that dangerous overcurrent situations do not occur due to overshoot of the bus sum current. Therefore, it has proven advantageous if the first addressing current source (Iq) j ) increases the first addressing current with a first time constant [τ1] and decreases it with a second time constant [τ2] that is smaller than the first time constant [t1] and / or when the second addressing current source (Iq' jThe second addressing stream is incremented by a third time constant [τ3] and decremented by a fourth time constant [τ4] that is smaller than the third time constant [τ3]. Preferably, the third time constant [τ3] and the first time constant [τ1] are chosen to have the same magnitude to ensure bus symmetry dynamically. For the same reason, the fourth time constant [τ4] and the second time constant [τ2] are preferably chosen to have the same magnitude to also ensure bus symmetry dynamically. Reference is made here again to the Fig. 7 to 9 referred. REDUCTION OF BUS RESISTANCE IN NORMAL OPERATION Figure 12

[0082] It will be here on Fig. 12 referred. It has now been shown that the bus shunt resistors (R2, R2') determine the properties of the single-wire buses (DB). a , DB b) and thus degrade the serial, bidirectional, differential two-wire communication bus (DB). Therefore, it was recognized that it is beneficial to use a first bus shunt bypass switch (S4) at each bus node (BK). j ) the associated first bus shunt resistor (R2) of the bus junction (BK) j ) in normal operation, i.e., in the normal state of the bus node (BK) j ), to bridge and to open this first bus shunt bypass switch (S4) only in the addressing state, thus allowing the first bus shunt resistor (R2) to become effective only in the addressing state. To avoid disturbing the bus symmetry, it is therefore also advisable to use a second bus shunt bypass switch (S4') for each bus node (BK). j ) the associated second bus shunt resistor (R2') of the bus junction (BK) j ) in normal operation, i.e., in the normal state of the bus node (BK) j), to bridge and to open this second bus shunt bridging switch (S4') only in the addressing state, thus allowing the second bus shunt resistor (R2') to become effective only in the addressing state.

[0083] At the bus junction (BK) described above j ) it is therefore a bus hub (BK) j ), which is capable of carrying out a procedure for assigning bus addresses to bus nodes of a serial, bidirectional, differential two-wire communication bus (DB). The procedure for assigning bus addresses to bus nodes ((BK1), (BK2), (BK3), ...... [BK n-1 ], [BK n ]) of a serial, bidirectional, differential two-wire communication bus (DB) using first bus shunt resistors (R2) and using second bus shunt resistors (R2') in the individual bus nodes ((BK1), (BK2), (BK3), ...... [BK n-1 ], [BK a]) in a tender period in which the bus hubs ((BK1) to [BK n ]) are in an addressing state, which significantly distinguishes this method from the prior art. After the procedure for assigning bus addresses to the bus nodes ((BK1), (BK2), (BK3), ...... [BK n-1 ], [BK n Following the allocation period of the serial, bidirectional, differential two-wire communication bus (DB), an operating period ensues in which the bus nodes operate normally, i.e., are in a normal state. The bus node (BK) j The system is thus preferably characterized, compared to the prior art, by such a first bus shunt resistor (R2) and such a second bus shunt resistor (R2'). Preferably, the bus node (BK) j ) each equipped with a first bus shunt bypass switch (S4) which is used before a bus address is assigned to the bus node (BK) j) is open during the allocation period and is closed after a bus address has been assigned to the bus hub during the allocation period and is closed during the operating period. Similarly, for reasons of symmetry, the following occurs at the bus hub (BK): j ) preferably a second bus shunt bypass switch (S4') is provided, which is used before a bus address is assigned to the bus node (BK) j ) is open during the allocation period and after the allocation of a bus address to the bus hub (BK) j ) is closed during the allocation period and is closed during the operating period. These bus shunt bridging switches (S4, S4') significantly reduce the bus resistance and decrease sensitivity to electromagnetic interference. They therefore improve EMC performance.

[0084] Differential symmetrical common-mode and differential-mode based auto-addressing Instead of a first addressing current of a first addressing current source (Iq) j ) of a bus hub (BKj ) and a second addressing stream from a second addressing stream source (Iq' j ) of a bus hub (BK j ) can also be a common-mode current source [GLlq j ] of a bus hub (BK j ) with two outputs, both of which supply the same common-mode current to the first single-wire bus (DB) a ) and the second single-wire bus (DB b ) of the serial bidirectional differential communication bus (DB) with the same sign. The first output of these two outputs thus corresponds to the first addressing current source (Iq). j The second output then corresponds to the second addressing current source (Iq'). j ). The first addressing stream of the first addressing stream source (Iq) j ) is then equal in magnitude to the second addressing stream of the second addressing stream source (Iq') j The use of a single common-mode addressing current source [GLlqj This has the advantage that only one control loop is needed.

[0085] Instead of a first addressing stream from a first addressing stream source (Iq) j ) of a bus hub (BK j ) and a second addressing stream from a second addressing stream source (Iq' j ) of a bus hub (BK j ) can also be a push-pull current source [GGlq j ] of a bus hub (BK j ) with two outputs, both of which supply the same magnitude of push-pull current to the first single-wire bus (DB) a ) and the second single-wire bus (DB b ) of the serial bidirectional differential communication bus (DB) but now with opposite signs. The first output of these two outputs therefore corresponds to the first addressing current source (Iq). j The second output then corresponds again to the second addressing current source (Iq'). j). The first addressing stream of the first addressing stream source (Iq) j ) is then equal in magnitude but not in sign to the second addressing current of the second addressing current source (Iq'). j ). The use of a single differential-mode addressing current source [GLIq j This also has the advantage that only one control loop is needed.

[0086] Mixed solutions using common-mode and differential-mode addressing current sources are conceivable.

[0087] Accordingly, a bus hub (BK) will also be built here. jA serial, bidirectional, differential two-wire communication bus (DB) with a bus master (ECU) is proposed, wherein the serial, bidirectional, differential two-wire communication bus (DB) comprises a first single-wire bus (DB1) and a second single-wire bus (DB2). A first bus shunt resistor (R2) inserted into the first single-wire bus (DB1) and a second bus shunt resistor (R2') inserted into the second single-wire bus (DB2) are part of the bus node (BK). j The bus node also includes a differential first common-mode addressing current source [GLlq]. j ] to determine the bus position of the bus junction (BK) j ) in the serial, bidirectional, differential two-wire communication bus (DB). The differential first common-mode addressing current source [GLlq j ] can introduce a first common-mode addressing current component in the manner described in the first single-wire bus (DB). a) of the serial, bidirectional, differential two-wire communication bus (DB) additionally regulates the feed-in so that the first total current (i j ) through the first bus shunt resistor (R2) of the bus junction (BK) j ) a predetermined or calculated or otherwise determined first total flow [I ref ] corresponds. At the same time, the differential first common-mode addressing current source [GLlq j ] a second common-mode addressing current component of the same magnitude and sign is additionally fed into the second single-wire bus (DB) b ) of the serial, bidirectional, differential two-wire communication bus (DB) is regulated with the same sign as the sign of the first push-pull addressing current component, so that the second total current (i' j ) through the second bus shunt resistor (R2') of the bus junction (BK) j) the specified or calculated or otherwise determined first total flow [I ref ] also corresponds. The first common-mode addressing current component of the common-mode addressing current source [GLlq j ] of the bus junction (BK) j ) flows through the first bus shunt resistor (R2) of the bus junction (BK) j ) towards the bus master (ECU). The second common-mode addressing current component of the common-mode addressing current source [GLlq j ] of the bus junction (BK) j ) flows through the second bus shunt resistor (R2') of the bus node (BK) j ) towards the bus master (ECU).

[0088] Complementary to common-mode control, differential-mode control is also possible. Therefore, a bus node (BK) is used. j) for a serial, bidirectional, differential two-wire communication bus (DB) with a bus master (ECU), wherein the serial, bidirectional, differential two-wire communication bus (DB) comprises a first single-wire bus (DB1) and a second single-wire bus (DB2), and wherein a first bus shunt resistor (R2) is inserted into the first single-wire bus (DB1) and a second bus shunt resistor (R2') is inserted into the second single-wire bus (DB2). The bus node (BK j ) then has a differential first push-pull addressing current source [GGlq j ] to determine the bus position of the bus junction (BK) j ) in the serial, bidirectional, differential two-wire communication bus (DB), which has a first push-pull addressing current component in the form of the first single-wire bus (DB) a) of the serial, bidirectional, differential two-wire communication bus (DB) can additionally feed in regulated current so that the first total current (i j ) through the first bus shunt resistor (R2) of the bus junction (BK) j ) a predetermined or calculated or otherwise determined first total flow [I ref ] corresponds. The differential-mode addressing current source [GGlq j] of the bus junction (BK) j ) feeds the second push-pull addressing current component, which is of the same magnitude, into the second single-wire bus (DB) in the same way. b ) of the serial, bidirectional, differential two-wire communication bus (DB) is regulated with the opposite sign to the sign of the first push-pull addressing current component, so that the second total current (i' j ) through the second bus shunt resistor (R2') of the bus junction (BK) j ) the specified or calculated or otherwise determined first total flow [Iref ] also corresponds. The first differential-mode addressing current component of the differential-mode addressing current source [GGlq j ] of the bus junction (BK) j ) flows through the first bus shunt resistor (R2) of the bus junction (BK) j ) towards the bus master (ECU). The second differential-mode addressing current component of the differential-mode addressing current source [GGlq j] of the bus junction (BK) j ) flows through the second bus shunt resistor (R2') of the bus node (BK) j ) towards the bus master (ECU).

[0089] The bus hub (BK) has the regulation j ) preferably via first means (R2, D2) to detect the current through the first bus shunt resistor (R2), and / or via second means (R2', D2') to detect the current through the second bus shunt resistor (R2').

[0090] As explained previously, the ability to detect the voltage drop across the respective bus shunt resistor (R2, R2') can also be used for a self-test. Therefore, a bus node (BK) is used. j ) is proposed, in which the detected current through the first bus shunt resistor (R2) is used for a self-test and / or in which the detected current through the second bus shunt resistor (R2') is used for a self-test. Here, the detected voltage drop across the bus shunt resistor is compared with an expected value. If the detected voltage deviates from the expected value by more than a predefined amount, an error has occurred, which can be signaled.

[0091] The proposed bus hub (BK) preferably includes j ) for this purpose at least a detection device (DET) that detects internal signals (ds1, ds3) of the bus node (BK) j ) checks for plausibility. Preferably, the bus node (BK) takes over.j ) or a sub-device (DET) of the bus node (BK) j ) Measures if the detection device (DET) does not detect implausible internal signals within the bus node (BK) j ) determines. One possible measure can be achieved by a first sub-device (X3) of the bus node (BK). j ) and a second sub-device (X3') of the bus node (BK j ) are initiated in such a way that the feed points of the first common-mode addressing currents of the common-mode addressing current source [GLlq j ] through the first sub-device (X3) of the bus node (BK) j ) and the second sub-device (X3') of the bus node (BK j ) will be changed upon detection of a predetermined error.

[0092] Another possible measure can be implemented by a first sub-device (X3) of the bus node (BK). j ) and a second sub-device (X3') of the bus node (BK j) are initiated in such a way that the feed points of the first differential-mode addressing currents of the differential-mode addressing current source [GGlq j ] through the first sub-device (X3) of the bus node (BK) j ) and the second sub-device (X3') of the bus node (BK j ) will be changed upon detection of a predetermined error.

[0093] Here too, regulating the addressing streams with specific time constants is desirable and recommended. Therefore, a bus node (BK) is used. j ) proposed, in which the common-mode addressing current source [GLlq j ] the common-mode addressing current is increased by a first time constant [t1] and decreased by a second time constant [τ2] that is smaller than the first time constant [τ1].

[0094] Analogously, a bus node (BK) is therefore j ) proposed, in which the differential-mode addressing current source [GGlq j] the push-pull addressing current is increased with a first time constant [t1] and decreased with a second time constant [τ2] that is smaller than the first time constant [τ1]. AUTO ADDRESSING VIA INTERRUPT LINE Figure 13

[0095] Fig. 13 is based on Fig. 2. In addition to the addressing method described above, the bus node (BK) described above can be used j ), which is intended for a data bus system with a serial, bidirectional, differential two-wire communication bus (DB), for a different auto-addressing method (see Fig. 13) be prepared. The relevant bus junction (BK) j ) is then again intended to be used in a procedure for assigning logical bus node addresses to the bus nodes ((BK1) to [BK n ]) of the data bus system. The corresponding data bus system then assigns a bus master (ECU) with an address input (Adr i0) on. The data bus system should again have n bus nodes ((BK1) to [BK n ]) including this bus junction (BK) j ) even with n being a positive integer. The bus junction (BK) j ) is transmitted via a data line section ((DB1) to [DB n ]) or the serial, bidirectional, differential two-wire communication bus (DB) consisting of data line sections ((DB1) to [DB n ]) and further bus junctions ((BK2) to [BK n ]) is connected to the bus master (ECU) for data transmission. Within the data bus system, there is a line [L1 to L1]. n ] from an address input (address i0 ) of the bus master (ECU) of the data bus system, starting through all bus nodes ((BK1) to [BK n ]) of the data bus system including this bus node (BK) j ) itself looped through so that it passes through the individual bus nodes ((BK1) to [BK n ]) including this bus junction (BK) j ) even in n line sections [L1 to Ln ] is subdivided. Each of the bus hubs (BK) j ) includes an associated address input [Adr ij ] and one of these bus hubs (BK) j ) associated address output [Adr oj Each of the bus hubs (BK) j ) with 1≤j≤ n-1, if it is not the n-th bus node [BK n ] is, is each intended to be used with its address input [Adr ij ] with the address output [Adr o(j+1) ] of a subsequent bus junction [BK j+1 ] with 1≤j≤n-1 through a bus junction following the next one [BK j+1 ] associated (j+1)-th line section [L j+1 ] from the (j+1)th bus junction [BK j+1 ] to the j-th bus junction (BK) j ) to be connected. Each of the bus hubs (BK) j ), if it is not the first bus node (BK1), its address output [Adr oj ] with the address input [Adr i(j-1) ] of a preceding bus junction [BK j-1 ] with 2≤j≤n through a bus junction (BK) j) associated j-th line section [L j ] from the j-th bus junction (BK j ) to the (j-1)th bus junction [BK j-1 ] connected. The first bus node (BK1) is (j=1) connected to its address output (Adr o1 ) with the address input (Adr i0 ) of the bus master (ECU) by one of the bus nodes (BK) j ) associated line section [L1]. The bus node address of the bus node (BK) j ) in its bus station address register [BKADR j ] can be valid or invalid, as is the case throughout this entire document. The proposed bus node now provides means and methods to set its bus node address and to make its bus node address valid or invalid. These can be, for example, specific data contents (DATA) from bit packets (BP) of the bus master (ECU), with which the bus master (ECU) can address individual, multiple, or all bus nodes ((BK1) to [BK1]). n]) can force the invalidation of the addresses in their bus stop address registers. The proposed bus stop (BK j The bus node (BK) can assume an addressing state and a second operating state (or normal state) that differs from the addressing state. j The bus node (BK) preferably has means to switch between the addressing state and the second operating state depending on instructions from the bus master (ECU). j ) then has means to, when it is in the addressing state and its bus node address is invalid, in this case the logical state at the address input [Adr i(j-1) ] of a preceding bus junction [BK j-1 ] to set a first logical value by overwriting, or then, if it is in the addressing state and if its bus node address is invalid, to set the logical state at the address input (Adr i0) of a preceding bus master (ECU) to a first logical value by overwriting. The bus node (BK) j ) furthermore preferably has means to display the logical state at its address input [Adr] in the addressing state. ij ] to set to a second logical value if this second logical value is not provided by a subsequent bus node [BK j+1 ] is overwritten with a first logical value, and provides a means to adopt a bus node address signaled by the bus master (ECU) as its valid future bus node address if its bus node address is invalid and if it is in the addressing state and if its address input [Adr ij ] has a second logical value, and in this case mark this future bus node address as "valid".

[0096] In a refinement of this proposal, the address input [Adr ij ] of the bus junction (BK) j) in the second operating state as the input of an interrupt signal of a subsequent bus node [BK j-1 ] can be used. In this way, an interrupt line can be used for the auto-addressing of bus nodes of a serial, bidirectional, differential two-wire communication bus (DB). Preferably, the address output [Adr oj ] of the bus junction (BK) j ) in the second operating state as the output of an interrupt signal from a subsequent bus node [BK j-1 ] and / or the bus hub (BK) j ) can be used by themselves. Figure 14

[0097] Fig. Section 14 describes the basic procedure of the preferred address allocation method described here. After the address allocation method is started (START), the bus master (BM) signals in a first procedure step (1) by means of a preferred first broadcast command preferably to one bus node or preferably to all or at least a part of the set of bus nodes ((BK1) to [BK1]). n ]), that such a procedure for assigning bus node addresses to these bus nodes is initiated. This preferably results in all these bus nodes ((BK1) to [BK n ]) possibly invalidate or delete valid bus node addresses already present in these bus nodes. If addressing is to be done using an interrupt line [L1 to L] looped through all bus nodes, n ] as in Fig. 13, then in this preferred version of the proposal this interrupt line [L1 to L] is lost n] for the duration of the addressing process, this function is used and is integrated into the aforementioned point-to-point connections between the bus nodes ((BK1) to [BK n ]) and splits the point-to-point connection between the first LED bus node (BK1) and the bus master (BM). In a second process step (2), the bus master (ECU) splits the bus node ((BK1) to [BK n ]) with the information that a bus node address is to be assigned and which logical bus node address this is. The bus node in question, here arbitrarily the j-th bus node (BK), is an example for clarity. j ), whose address inbox [Adr ij If the output has a second logical value, it then takes the bus address offered by the bus master (BM) in this process step and sets its address output [Adr oj ] in such a way that it receives the address [Adr i(j-1) ] of a preceding bus junction [BK j-1] no longer overwrites to the first logical value, but to a second logical value at the address input [Adr i(j-1) ] of a preceding bus junction [BK j-1 ] allows. This second logical value is then preferentially assigned by the preceding bus node [BK]. j-1 ] even at his address [Adr i(j-1) ] imprinted. In a further third step (3), the bus master (ECU) checks whether the logical value at its address input (Adr) i0 ) corresponds to a second logical value or not. If it does not correspond (N), the bus master (ECU) repeats the second procedure step (2). If it corresponds to this logical value (Y), the bus master (ECU) terminates the procedure by performing a fourth procedure step (4). If necessary, it first checks the correct assignment. Preferably, if all bus addresses are successfully assigned, the bus master (ECU) sends a message to all bus nodes ((BK1) to [BK1]). n]), that the bus node addresses have been assigned. This results in bus nodes ((BK1) to [BK n ]) transitions from the addressing state assumed in the first process step (1) to another operating state, preferably the normal operating state or normal state. In particular, the bus nodes ((BK1) to [BK n ]) After completing this fourth step, any interrupt line that may have been used for point-to-point connections is repurposed as an interrupt line. This concludes the proposed procedure (END). Symmetrical auto-addressing method via bus shunt resistors

[0098] Here, a procedure for addressing the bus nodes ((BK1) to [BK] is described. n ]) of a data bus system using a symmetrical method was discussed.

[0099] This is an auto-addressing procedure for addressing the bus nodes ((BK1) to [BKn ]) of a data bus system based on a serial, bidirectional, differential two-wire communication bus (DB). The data bus system comprises a bus master (ECU), a serial, bidirectional, differential two-wire communication bus (DB) radiating from the bus master (ECU), and several addressable bus nodes ((BK1) to [BK2]. n ]), which are connected to the serial, bidirectional, differential two-wire communication bus (DB). The serial, bidirectional, differential, two-wire communication bus (DB) consists of the aforementioned first single-wire bus (DB). a ) and the aforementioned second single-wire bus (DB b ). Each unaddressed bus node (BK) j ) the bus junction ((BK1) to [BK n ]) does not have a valid bus node address and therefore feeds a first addressing stream into the first single-wire bus (DB) for identification purposes. a ) one and a second addressing stream into the second single-wire bus (DB) b). All of these addressing streams flow through the serial, bidirectional, differential two-wire communication bus (DB) towards the bus master (ECU). Each unaddressed bus node (BK) j ) detects the one through the first single-wire bus (DB) a ) the first current flowing through the serial, bidirectional, differential two-wire communication bus (DB) and the current flowing through the second single-wire bus (DB) b ) the second current flowing in the serial, bidirectional, differential two-wire communication bus (DB). Only the bus node that has not yet been addressed (BK) jA bus node that does not detect a first current, or only detects a first current lower than a predefined first threshold, and simultaneously does not detect a second current, or only detects a second current lower than a predefined second first threshold, is identified as an unaddressed bus node. An address is assigned to this identified bus node, thus giving it a valid bus node address. The aforementioned steps are performed without the most recently addressed bus node until all unaddressed bus nodes have been addressed. Preferably, the first threshold is equal to the second first threshold, and the value of the first addressing current within a bus node is equal to the value of the second addressing current within that bus node.

[0100] In addition to addressed bus nodes (i.e., those with a valid bus node address), unaddressed bus nodes without a valid bus node address can also be connected to the serial, bidirectional, differential two-wire communication bus (DB). The unaddressed bus node feeds into the first single-wire bus (DB). a ) a first quiescent current and into the second single-wire bus (DB) b ) a second quiescent current. Each unaddressed bus node detects the current supplied by the first single-wire bus (DB) before the addressing currents are injected. a ) flowing first quiescent current and the one through the second single-wire bus (DB) b ) flowing second quiescent current. Only the bus nodes that have not yet been addressed and have an invalid bus node address feed the first addressing currents into the first single-wire bus (DB). a ) and the second addressing streams into the second single-wire bus (DB) bOnly those unaddressed bus nodes that, when addressing currents are injected by all unaddressed bus nodes, detect no current difference between the first and second currents compared to the previous current detection, or only a current difference between the first and second currents that is smaller than a predefinable second threshold, are identified as unaddressed bus nodes. An address is assigned to the bus node thus identified, thereby giving it a valid bus node address. The aforementioned steps are performed without the most recently addressed bus node until all unaddressed bus nodes have been addressed. The second threshold is preferably equal to the first threshold or the subsequent first threshold.

[0101] In another variant of the procedure, each addressable bus node feeds into the first single-wire bus (DB). a) a first quiescent current, which can be zero, and into the second single-wire bus (DB) b ) a second quiescent current, which can be zero. Every unaddressed bus node without a valid bus node address feeds a first quiescent current into the first single-wire bus (DB). a ) one and a second quiescent current into the second single-wire bus (DB) b ) one. Each unaddressed bus node detects the one connected by the first single-wire bus (DB). a ) due to the quiescent current feed-in, the first current flowing and the one through the second single-wire bus (DB) b) due to the quiescent current injection. This determines which of the unaddressed bus nodes detects a first current above a predefined third threshold, and which of the unaddressed bus nodes detects a second current above a predefined further third threshold. Only those unaddressed bus nodes that detect a first current less than or equal to the third threshold when the quiescent currents are injected feed first addressing currents into the first single-wire bus (DB). a ) and only those bus nodes that are not yet addressed and that detect a second current when the quiescent currents are injected, which is less than or equal to the further third threshold, preferentially feed second addressing currents into the second single-wire bus (DB). b) one. It is preferred at this point if only those bus nodes not yet addressed that detect a first current less than or equal to the third threshold when the quiescent currents are injected, and that simultaneously detect a second current less than or equal to the next third threshold when the quiescent currents are injected, send first addressing currents into the first single-wire bus (DB). a ) and second addressing streams into the second single-wire bus (DB) b feed in.

[0102] From the group of unaddressed bus nodes injecting these addressing streams, only the node that detects no first stream, or only a first stream lower than a predefined fourth threshold, and that detects no second stream, or only a second stream lower than a predefined fourth threshold, is identified as an unaddressed bus node. An address is assigned to the identified bus node for addressing purposes. The aforementioned steps are performed without the most recently addressed bus node until all unaddressed bus nodes have been addressed. Preferably, the third and / or fourth threshold, and / or the further third and / or fourth threshold, and the first threshold are the same.

[0103] In one variant of the method, in addition to the addressable bus nodes, non-addressable bus nodes are also connected to the serial, bidirectional, differential two-wire communication bus (DB). Such a non-addressable bus node feeds into the first single-wire bus (DB). a ) a first quiescent current and into the second single-wire bus (DB) b ) introduces a second quiescent current. Each unaddressed bus node determines the address before the first addressing currents are fed into the first single-wire bus (DB). a ) the one in the first single-wire bus (DB a ) Due to the quiescent current input of all non-addressable bus nodes, the first current flowing is detected by a first current detection. Each unaddressed bus node determines the current before the second addressing currents are injected into the second single-wire bus (DB). b ) the one in the second single-wire bus (DB b) due to the quiescent current feed-in from all non-addressable bus nodes, a second current flows through a second current detection. Subsequently, each addressable bus node feeds into the first single-wire bus (DB). a ) a first quiescent current and into the second single-wire bus (DB) b ) a second quiescent current. This determines which of the unaddressed bus nodes has a first current in the first single-wire bus (DB). a ) detected, which is above a predefinable fifth threshold, and / or a second current in the second single-wire bus (DB) b ) detected, which lies above a predefinable fifth threshold. Only those bus nodes not yet addressed, which are fed into the first single-wire bus (DB) when the first quiescent currents are fed in a ) detecting a first current that is less than or equal to the fifth threshold, feed first addressing currents into the first single-wire bus (DB).a ) one. Only those bus nodes not yet addressed, which are fed into the second single-wire bus (DB) when the second quiescent currents are fed in. b ) detect a second current that is less than or equal to the further fifth threshold, feed second addressing currents into the second single-wire bus (DB). b ) one. However, it is particularly preferred if only those bus nodes not yet addressed, which are fed into the first single-wire bus (DB) when the first quiescent currents are fed in, are included. a ) detect a first current that is less than or equal to the fifth threshold, and which simultaneously triggers the injection of the second quiescent currents into the second single-wire bus (DB). b ) detect a second current that is less than or equal to the further fifth threshold, first addressing currents into the first single-wire bus (DB) a) and second addressing streams into the second single-wire bus (DB) b feed in.

[0104] From the group of unaddressed bus nodes feeding in these addressing streams, only those nodes that detect no current difference of the first current, or only a current difference of the first current less than a predefined sixth threshold, and that detect no current difference of the second current, or only a current difference of the second current less than a predefined sixth threshold, are identified as unaddressed. An address is then assigned to each of these identified bus nodes for addressing purposes. The aforementioned steps are performed without the most recently addressed bus node until all unaddressed bus nodes have been addressed.The fifth threshold and / or the sixth threshold and / or the further fifth threshold and / or the further sixth threshold and / or the first threshold are preferably the same.

[0105] The first current detection preferably takes place in the bus nodes via the first bus shunt resistors (R2) of the first single-wire bus (DB) assigned to the addressable bus node. a ) and the second current detection preferably takes place in the bus nodes via the second bus shunt resistors (R2') of the second single-wire bus (DB) assigned to the addressable bus nodes b The first bus shunt resistors (R2) assigned to an addressable bus node preferably correspond, at least in value, to the second bus shunt resistors (R2') assigned to the respective addressable bus node. All first bus shunt resistors (R2) are preferably located in the first single-wire bus (DB). a ) along the first single-wire bus (DB) a) connected in series and all second bus shunt resistors (R2') are preferably in the second single-wire bus (DB) b ) along the second single-wire bus (DB) b ) connected in series.

[0106] Instead of current detection, voltage detection can also be performed in the bus nodes.

[0107] The assignment of an address typically occurs by transmitting an address to the identified bus node by transmitting the same address to all unaddressed bus nodes before the identification of a bus node, and only the subsequently identified bus node accepts this address as its bus node address.

[0108] Preferably, an address is assigned after the initial identification of a bus node and / or the bus node address is verified after the identification of a bus node.

[0109] Verification of the identification of a bus node can be carried out, for example, by re-identifying the bus node and / or by identifying the bus node using the other single-wire bus and comparing the second identification with the first identification.

[0110] Verification of a participant's identification can also be achieved by re-identifying the participant using a different auto-addressing method and comparing the second identification with the first. Any errors that occur during this process are signaled. ASYMMETRIC AUTOADDRESSING METHOD VIA BUS SHUNT RESISTORS

[0111] The data bus system has a bus master (ECU), a serial, bidirectional, differential two-wire communication bus (DB) radiating from the bus master (ECU), and several addressable bus nodes ((BK1) to [BK n]) which are connected to the serial, bidirectional, differential two-wire communication bus (DB). The serial, bidirectional, differential, two-wire communication bus (DB) again consists of a first single-wire bus (DB a ) and a second single-wire bus (DB b In the first auto-addressing method discussed here, each unaddressed bus node (BK) feeds in j ) the bus junction ((BK1) to [BK n ]) to identify an addressing stream in at least ONE single-wire bus of the single-wire buses (DB) a , DB b ). Each unaddressed bus node feeds the addressing current into at least one single-wire bus, hereinafter referred to as the addressing single-wire bus. However, it is preferred if this addressing current is fed into both single-wire buses (DB). a , DB b) is fed in. All other unaddressed bus nodes also feed their respective addressing streams into the addressing single-wire bus. All addressing streams flow through the serial, bidirectional, differential two-wire communication bus (DB) towards the bus master (ECU). Each unaddressed bus node (BK) j ) detects the current flowing through the addressing single-wire bus of the serial, bidirectional, differential two-wire communication bus (DB). This detection preferably occurs via the bus shunt resistors (R2, R2') already mentioned above. Only the bus node that has not yet been addressed (BK) jA bus node that detects no current or only a current lower than a predefined initial threshold is identified as an unaddressed node. This identified node is then assigned an address, thus receiving a valid bus node address. This address is preferably determined by the bus master (ECU). The aforementioned steps are then repeated without the most recently addressed bus node, resulting in another initialization cycle, until all unaddressed bus nodes have been addressed.

[0112] It can happen that, in addition to the addressed bus nodes, one or more unaddressed bus nodes are connected to the serial, bidirectional, differential two-wire communication bus (DB), and these unaddressed nodes inject a quiescent current into the addressing single-wire bus. In this case, the previously described procedure must be modified. This modification requires that each unaddressed bus node detects the quiescent current flowing through the addressing single-wire bus before injecting the addressing currents. Only the unaddressed bus nodes then inject the addressing currents into the addressing single-wire bus.Only the unaddressed bus node that, when addressing currents are injected by all unaddressed bus nodes, detects no current difference compared to the previous current detection, or only a current difference smaller than a predefined second threshold, is identified as an unaddressed bus node. An address is assigned to this identified bus node for addressing purposes, thus giving it a valid bus node address. The aforementioned steps are performed without the most recently addressed bus node until all unaddressed bus nodes have been addressed. Preferably, the second threshold is equal to the first threshold.

[0113] It can also happen that every addressable bus node injects a quiescent current into the addressing single-wire bus, and that every unaddressed bus node injects a quiescent current into the addressing single-wire bus. The procedure is then modified similarly to the one described above: Each unaddressed bus node again detects the current flowing through the addressing single-wire bus due to the quiescent current injection. A circuit within the bus nodes (BK) jThe system then determines which of the unaddressed bus nodes detects a current above a predefined third threshold. Only those unaddressed bus nodes that detect a current less than or equal to the third threshold when quiescent currents are applied feed addressing currents into the addressing single-wire bus. From this group of unaddressed bus nodes feeding addressing currents, only the node that detects no current or only a current less than a predefined fourth threshold is identified as an unaddressed bus node. An address is then assigned to this identified bus node, thus giving it a valid bus node address.The aforementioned steps are repeated without the last addressed bus node until all unaddressed bus nodes have been addressed. Here too, the third and / or fourth threshold is preferably the same as the first threshold.

[0114] It can again occur that, in addition to the addressable bus nodes, at least one non-addressable bus node is connected to the serial, bidirectional, differential two-wire communication bus (DB), which injects a quiescent current into the addressing single-wire bus. Again, the procedure is appropriately modified: Before injecting the addressing currents, each unaddressed bus node determines the current flowing in the addressing single-wire bus due to the quiescent current injection from all non-addressable bus nodes by means of an initial current detection. Subsequently, each addressable bus node injects a quiescent current into the addressing single-wire bus. The system then determines which of the unaddressed bus nodes detects a current above a predefined fifth threshold.Only those unaddressed bus nodes that detect a current less than or equal to the fifth threshold when quiescent currents are injected feed addressing currents into the addressing single-wire bus. From this group of unaddressed bus nodes injecting addressing currents, only the node that detects no current difference compared to the first current detection, or only a current difference less than a predefined sixth threshold, is identified as an unaddressed bus node. An address is assigned to this identified bus node for addressing purposes, thus giving it a valid bus node address. The aforementioned steps are then repeated without the most recently addressed bus node until all unaddressed bus nodes have been addressed.Again, the fifth threshold and / or sixth threshold is preferably equal to the first threshold.

[0115] Current detection in the bus nodes is preferably performed via the shunt resistors of the addressing single-wire bus assigned to the addressable bus nodes. In the other single-wire bus, which is not the addressing single-wire bus, further bus shunt resistors assigned to the addressable participants are preferably, but not necessarily, arranged in the participants. These additional shunt resistors preferably correspond in value to the shunt resistors in the addressing single-wire bus. Most preferably, the bus shunt resistors (R2, R2') in the two single-wire buses (DB) match. a , DB bAll shunt resistors in the addressing single-wire bus along the addressing single-wire bus are preferably connected in series. All shunt resistors in the other single-wire bus along this other single-wire bus are also preferably connected in series.

[0116] It is possible to perform voltage detection instead of current detection in the bus nodes.

[0117] One variant of the procedure provides that the assignment of an address is carried out by transmitting an address to the identified bus node or by transmitting the same address to all bus nodes that have not yet been addressed before the identification of a bus node, and that only the subsequently identified bus node accepts this address as its bus node address.

[0118] Another variant of the proposed procedure provides that the assignment of an address takes place after the initial identification of a bus node, or that verification of the bus node address takes place after the identification of a bus node.

[0119] Another variant of the proposed procedure provides that the verification of the identification of a bus node is carried out by re-identifying the bus node and / or by identifying the bus node using the other single-wire bus and comparing the second identification with the first identification.

[0120] Another variant of the proposed procedure involves verifying a participant's identification by re-identifying the participant using a different auto-addressing method and comparing the second identification with the first. Preferably, the bus node and / or the bus master then signal an error. Symmetrical auto-addressing method via bus shunt resistors with self-test capability and addressing current control

[0121] Furthermore, a self-testable auto-addressing procedure for assigning bus node addresses within a data bus system is proposed. The data bus system comprises a serial, bidirectional, differential two-wire communication bus (DB) with a chain of n bus nodes ((BK1), (BK2), (BK3), ..... [BK n-1 ], [BK n]), with n as a positive integer greater than zero, and a bus master (ECU). The serial, bidirectional, differential two-wire communication bus (DB) is connected to the bus master (ECU). Each bus node ((BK2), (BK3), ..... [BK n-1 ], [BK n ]) indicates a preceding bus node ((BK1), (BK2), (BK3), ..... [BK n-1 ]) if it is not the first bus stop (BK1) and each bus stop ((BK2), (BK3), ..... [BK n-1 ], [BK n ]) is with its preceding bus node ((BK1), (BK2), (BK3), ..... [BK n-1 ]) via the serial, bidirectional, differential two-wire communication bus (DB) by means of a connecting section of the serial, bidirectional, differential two-wire communication bus (DB), if it is not the first bus node (BK1). The serial, bidirectional, differential two-wire communication bus (DB) consists of a first single-wire bus (DB a ) and a second single-wire bus (DBb The first bus node (BK1) is connected to the bus master (ECU) via the serial, bidirectional, differential two-wire communication bus (DB) by means of a connecting section of the serial, bidirectional, differential two-wire communication bus (DB). Each bus node ((BK2), (BK3), ..... [BK n-1 ], [BK n ]) sends a first bus node output stream ((i2), (i3), ...[I (n-1) ], [i n ]) via section (DB1) of the first single-wire bus (DB a ), the part of the connecting section between this bus junction ((BK2), (BK3), ..... [BK n-1 ], [BK n ]) and its preceding bus junction ((BK1), (BK3), ..... [BK n-1 ], [BK n-1 ]) is, at its preceding bus hubs ((BK1), (BK2), (BK3), ..... [BK n-1 ]), if it is not the first bus stop (BK1). Each bus stop ((BK2), (BK3), ..... [BK n-1 ], [BK n]) sends a second bus node output stream ((i'2), (i'3),...[i' (n-1) ], [i' n ]) via section (DB2) of the second single-wire bus (DB b ), the part of the connecting section between this bus junction ((BK2), (BK3), ..... [BK n-1 ], [BK n ]) and its preceding bus junction ((BK1), (BK3), ..... [BK n-1 ], [BK n-1 ]) is, at its preceding bus hubs ((BK1), (BK2), (BK3), ..... [BK n-1 ]), if it is not the first bus node (BK1). The first bus node (BK1) sends a first bus node output current (i1) over the section (DB1) of the first single-wire bus (DB). a ), which is part of the connection section between the first bus node (BK1) and the bus master (ECU), to the bus master (ECU). The first bus node (BK1) sends a second bus node output current (i2) via the section (DB2) of the second single-wire bus (DB). b), which is part of the connection section between the first bus node (BK1) and the bus master (ECU), to the bus master (ECU). The bus master (ECU) receives a first bus node input current (i1) via the section (DB1) of the first single-wire bus (DB). a ), which is part of the connection section between the first bus node (BK1) and the bus master (ECU), from its subsequent first bus nodes (BK1). The bus master (ECU) receives a second bus node input current (i'1) via the section (DB2) of the second single-wire bus (DB). b ), which is part of the connection section between the first bus node (BK1) and the bus master (ECU), from its subsequent first bus nodes (BK1). Each bus node ((BK1), (BK2), ..... [BK n-1 ]) receives a first bus node input stream ((i2), (i3), ...[i( n-1 )], [i n ]) via section (DB1) of the first single-wire bus (DB a), the part of the connecting section between this bus junction ((BK2), (BK3), ..... [BK n-1 ], [BK n ]) and its preceding bus junction ((BK1), (BK3), ..... [BK n-1 ], [BK n-1] ) is, from its subsequent bus hubs ((BK2), (BK3), ..... [BK n-1 ], [BK n ]), if it is not the last bus stop [BK n ] is. Each bus stop [(BK1), (BK2), ..... [BK n-1 ]) receives a second bus node input stream ((i2), (i3), ...[i (n-1) ], [i n ]) via the section of the second single-wire bus (DB b ), the part of the connecting section between this bus junction ((BK2), (BK3), ..... [BK n-1 ], [BK n ]) and its preceding bus junction ((BK1), (BK3), ..... [BK n-1 ], [BK n-1 ]) is, from its subsequent bus hubs ((BK2), (BK3), ..... [BK n-1 ], [BK n ]), if it is not the last bus stop [BK nThis method, unlike the one described previously, therefore uses both single-wire buses (DB). a and DB b ) for the transmission of the addressing streams. First, a maximum addressing stream [I ] is determined. amax ] determined. This is followed by the execution of an initialization sequence, which has the following steps, for each auto-addressing bus node of the n bus nodes ((BK1), (BK2), ..... [BK n-1 ], [BK n ]), which does not yet have a valid bus node address, until all auto-addressing bus nodes of the n bus nodes ((BK1), (BK2), ..... [BK n-1 ], [BK n ]) have a valid bus stop address: • Signaling of a bus address to be assigned to all auto-addressing bus nodes of the n bus nodes ((BK1), (BK2), ..... ]BK n-1 ], [BK n ]); • Perform the following steps for each auto-addressing bus node (BK) j) the auto-addressing bus node of the n bus nodes ((BK1), (BK2), ..... ]BK n-1 ], [BK n ]), hereinafter referred to as the relevant auto-addressing bus node (BK) j ) designated: • Reception of the said auto-addressing command from the bus master (ECU) by the relevant auto-addressing bus node (BK); • Receipt of the bus address to be assigned from the bus master (ECU) by the relevant auto-addressing bus node (BK); • Receipt of a start signal for the assignment of the bus address to be assigned from the bus master (ECU) by the relevant auto-addressing bus node (BK) j ) and start of a timer by the relevant auto-addressing bus node (BK;); • Feeding in the data from the following bus nodes ([BK j+1 ], [BK j+2 ] ... [BK n-1 ], [BK n ]) received first bus input stream [i (j+1) ] via section (DB1) of the first single-wire bus (DB a), the part of the connection section of the serial, bidirectional, differential two-wire communication bus (DB) between the relevant auto-addressing bus node (BK) j ) and the preceding (j-1)th bus junction [BK j-1 ] is, as part of the first bus output stream [i j ] of the relevant auto-addressing bus node (BK j ); • Feeding in the data from the following bus nodes ([BK j+1 ], [BK j+2 ] ...) received second bus input stream [i' (j+1) ] via section (DB2) of the second single-wire bus (DB b ), the part of the connection section of the serial, bidirectional, differential two-wire communication bus (DB) between the relevant auto-addressing bus node (BK) j ) and the preceding (j-1)th bus junction [BK j-1 ] is, as part of the second bus output stream (i' j ) of the relevant auto-addressing bus node (BK) j ); • Capturing the first value of the first bus node output stream (i j ) of the relevant auto-addressing bus node (BK) j ) using first measuring instruments (R2, D2, D3); • Capturing the second value of the second bus node output current (i') j ) of the relevant auto-addressing bus node (BK) j ) using second measuring instruments (R2', D2', D3'); • Generation of a first control signal (rw) j ) from the captured first value of the first bus node output current (i j ) of the relevant auto-addressing bus node (BK) j ) by means of first means of regulation (F); • Generation of a second control signal (rw') j ) from the captured second value of the second bus node output current (i' j ) of the relevant auto-addressing bus node (BK) j ) by means of second means of regulation (F'); • Regulating the first bus node output current (i j) through the relevant auto-addressing bus node (BK) j ), by means of a first regulated auto-addressing current source (Iq j ), whose first addressing stream is a portion of the first bus output stream (i j ) represents, to a first predetermined total current value [I ref ] depending on the generated first control signal (rw) j ), where an increase in the first addressing current of the first regulated auto-addressing current source (Iq) j ) of the relevant auto-addressing bus node (BK) j ) with a first time constant [τ1] and wherein a reduction of the first addressing current of the first regulated auto-addressing current source (Iq j ) of the relevant auto-addressing bus node (BK) j ) with a second time constant [τ2] and where the second time constant [τ2] is smaller than the first time constant [τ1]; • Regulating the second bus node output stream (i')j ) through the relevant auto-addressing bus node (BK) j ), by means of a second regulated auto-addressing current source (Iq') j ), whose second addressing stream is a portion of the second bus output stream (i' j ) represents, to a second predetermined total flow value [l' ref ] depending on the generated second control signal (rw' j ), wherein an increase in the second addressing current of the second regulated auto-addressing current source (Iq') j ) of the relevant auto-addressing bus node (BK) j ) with a third time constant [τ3] and wherein a reduction of the second addressing current of the second controlled auto-addressing current source (Iq' j ) of the relevant auto-addressing bus node (BK) j ) with a fourth time constant [τ4] and where the fourth time constant [τ4] is smaller than the third time constant [τ3]; • Comparing the first rule value [r j ] of the first control signal (rw j ) of the relevant auto-addressing bus node (BK) j ) with a first threshold [SW j ] of the relevant auto-addressing bus node (BK;); • Comparing the second rule value [r' j ] of the second control signal (rw' j ) of the relevant auto-addressing bus node (BK) j ) with a second threshold [SW' j ] of the relevant auto-addressing bus node (BK j ); • Freezing the control of the first addressing current source (Iq) j ) of the relevant auto-addressing bus node (BK) j ) at a first time point t1 after the start of the timer; • Freezing the control of the second addressing current source (Iq') j ) of the relevant auto-addressing bus node (BK) j ) at a second time t2 after the start of the timer; • Adoption of the bus node address to be assigned from the bus master (ECU) as the valid bus node address of the relevant auto-addressing bus node (BK). j ), if a minimum time has elapsed since the start of the timer and if the comparison of the first rule value [r j ] with the first threshold [SW j ] shows that the first addressing stream of the first addressing stream source (Iq j ) of the relevant auto-addressing bus node (BK) j ) is above a current threshold in magnitude and / or if the comparison of the second control value [r' j ] with the second threshold [SW' j ] results in the second addressing stream of the second addressing stream source (Iq) j ) of the relevant auto-addressing bus node (BK) j ) is above a current threshold in amount and configuration of the relevant auto-addressing bus node (BK) j) as a bus node without auto-addressing capability with the bus node address to be assigned as the valid bus node address of the relevant auto-addressing bus node (BK) j ) at a third time t3 after the first time t1 and after the second time t2, whereby this auto-addressing bus node (BK) j ) will no longer participate in the following initialization sequences until further notice. • Verification of successful address assignment by the bus master (ECU); • If necessary, deletion of the validity of the last assigned bus node address, thereby invalidating the relevant auto-addressing bus nodes (BK). j ) again like auto-addressing bus nodes (BK) j ) behave without a valid bus node address; • Verification that all auto-addressing bus nodes have received a valid bus node address; • Execution of another initialization sequence if not all auto-addressing bus nodes have received a valid bus node address.

[0122] This basic procedure can be supplemented with an additional step after or in conjunction with the acquisition of the bus node address to be assigned. It then includes bridging the first bus shunt resistor (R2) using a first bus shunt bypass switch (S4) and / or bridging the second bus shunt resistor (R2') using a second bus shunt bypass switch (S4') when transitioning from the addressing state with an invalid bus node address of the respective bus node (BK). j ) into the addressing state with a valid bus node address of the respective bus node (BK) j ) or when switching to the normal state. This approach has the advantage that the bus resistance is reduced during operation (normal state after address assignment).

[0123] During the transition to auto-addressing mode (addressing state), the bridging of the bus shunt resistors (R2, R2') is reversed. The procedure then involves opening the first bus shunt bridging switch (S4) when the bus node address of the relevant auto-addressing bus node (BK) j ) is not valid, and / or the opening of the second bus shunt bypass switch (S4') if the bus node address of the relevant auto-addressing bus node (BK) j ) is not valid.

[0124] The third time constant [τ3] is preferably chosen to be smaller than the first time constant [τ1] and the second time constant [τ2] by a factor greater than 10. The third time constant τ3 is preferably located within the relevant auto-addressing bus node (BK) in a specific method variant. j ) from the first value of the first bus node output current (i) recorded by means of first measuring instruments (R2, D2, D3) j) of the relevant auto-addressing bus node (BK) j ) and / or from the second value of the second bus node output current (i') detected by means of second measuring instruments (R2', D2', D3'). j ) of the relevant auto-addressing bus node (BK) j ) away.

[0125] Preferably, the first time constant [τ1] is located within the relevant auto-addressing bus node (BK). j ) from the first value of the first bus node output current (i) recorded by means of first measuring instruments (R2, D1, D3) j ) of the relevant auto-addressing bus node (BK) j ) and / or the second time constant [τ2] within the relevant autoaddressing bus node (BK) j ) from the second value of the second bus node output current (i') recorded by means of second measuring instruments (R2', D1', D3') j ) of the relevant auto-addressing bus node (BK) j ) away.

[0126] The first time constant [τ1] within the relevant auto-addressing bus node (BKj) can be determined from the value of the first bus node output current (i) detected by first measuring instruments (R2, D2, D3). j ) of the relevant auto-addressing bus node (BK) j ) depend in such a way that the value of the first time constant [τ1] has a first value below a threshold and a second value above this threshold, and / or depends on the value of the second bus node output current (i') detected by means of second measuring devices (R2', D2', D3'). j ) of the relevant auto-addressing bus node (BK) j ) depend in such a way that the value of the second time constant τ2 has a third value below a threshold and a fourth value above this threshold.

[0127] It is important that the technology disclosed here enables a self-test. Therefore, it is advantageous to additionally verify the recorded first value of the first bus node output current (i). j ) and / or the captured second value of the second bus node output current (i') j ) of the relevant auto-addressing bus node (BK) j ) plausibility check and, if necessary, measures are initiated if the recorded first value of the first bus node output stream (i j ) of the relevant auto-addressing bus node (BK) j ) and / or the captured second value of the second bus node output current (i') j ) of the relevant auto-addressing bus node (BK) j ) or whose combination is not plausible.

[0128] Preferably, the injection point of the first addressing stream is redefined (i j ) if the first recorded value of the first bus node output current (i j) of the relevant auto-addressing bus node (BK) j ) is not plausible. Likewise, a re-determination of the injection point of the first addressing current (i) is preferably carried out analogously. j ) and the injection point of the second addressing stream (i' j ), if the captured first value of the first bus node output current (i j ) and / or the captured second value of the second bus node output current (i') j ) of the relevant auto-addressing bus node (BK) j ) and / or their combination is not plausible.

[0129] In one variant, a fault is preferably signaled via the serial bidirectional differential communication bus (DB) upon request by a bus master (ECU) if the detected first value of the first bus node output current (i) j ) of the relevant auto-addressing bus node (BK) j ) and / or the captured second value of the second bus node output current (i')j ) of the relevant auto-addressing bus node (BK) j ) or whose combination is not plausible.

[0130] In one variant of the procedure, the step of capturing the first value of the first bus node output current (i) is carried out. j ) of the relevant auto-addressing bus node (BK) j ) using first measuring instruments (R2, D1, D3) to detect the first value of the first bus node output current (i j ) of the relevant auto-addressing bus node (BK) j ) using first measuring instruments (R2, D1, D3) with a first sign, if the detected first value of the first bus node output current (i j ) of the relevant auto-addressing bus node (BK) j ) is plausible, and capturing the first value of the first bus node output stream (i j ) of the relevant auto-addressing bus node (BK) j) using first measuring instruments (R2, D1, D3) with a second sign that is inverted to the first sign, if the detected first value of the first bus node output current (i j ) of the relevant auto-addressing bus node (BK) j ) is not plausible.

[0131] In another variant of the procedure, which relates to the other single-wire bus, the step of capturing the second value of the second bus node output current (i') is carried out j ) of the relevant auto-addressing bus node (BK) j ) using second measuring instruments (R2', D1', D3') as follows: The step includes capturing the second value of the second bus node output current (i') j ) of the relevant auto-addressing bus node (BK) j ) using second measuring instruments (R2', D1', D3') with a first sign, if the detected second value of the second bus node output current (i' j) of the relevant auto-addressing bus node (BK) j ) is plausible, and capturing the second value of the second bus node output stream (i') j ) of the relevant auto-addressing bus node (BK) j ) using second measuring instruments (R2', D1', D3') with a second sign that is inverted to the first sign, if the detected second value of the second bus node output current (i' j ) of the relevant auto-addressing bus node (BK) j ) is not plausible.

[0132] Another method variant additionally includes capturing the second value of the second bus node output current (i'). j ) of the relevant auto-addressing bus node (BK) j ) using second measuring instruments (R2', D1', D3') in the following manner: This step first involves capturing the second value of the second bus node output current (i') j ) of the relevant auto-addressing bus node (BK) j) using second measuring instruments (R2', D1', D3') with a first sign, if the previously recorded first value of the first bus node output current (i j ) of the relevant auto-addressing bus node (BK) j ) is plausible and if the previously recorded second value of the second bus node output current (i') j ) of the relevant auto-addressing bus node (BK) j ) is plausible, and capturing the second value of the second bus node output stream (i') j ) of the relevant auto-addressing bus node (BK) j ) using second measuring instruments (R2', D1', D3') with a second sign that is inverted to the first sign, if the previously recorded first value of the first bus node output current (i j ) of the relevant auto-addressing bus node (BK) j ) is not plausible or if the previously recorded second value of the second bus node output current (i') j ) of the relevant auto-addressing bus node (BK)j ) is not plausible.

[0133] For the purposes of this disclosure, two values ​​are plausible if they are the result of two different tests which, by design, should produce a similar, though not necessarily identical, result, and which are equal to each other. Equality here means a deviation of the magnitude of the norm of the results by less than a predetermined threshold. For the purposes of this disclosure, two values ​​are not plausible if they are the result of two different tests which, by design, should produce a similar, though not necessarily identical, result, and which are not equal to each other.

[0134] Furthermore, this variant includes performing the step of capturing the first value of the first bus node output stream (i j ) of the relevant auto-addressing bus node (BK) j) using first measuring instruments (R2, D1, D3) in the following manner: The step includes capturing the first value of the first bus node output current (i j ) of the relevant auto-addressing bus node (BK) j ) using first measuring instruments (R2, D1, D3) with a first sign, if the previously recorded first value of the first bus node output current (i j ) of the relevant auto-addressing bus node (BK) j ) is plausible and if the previously recorded second value of the second bus node output current (i') j ) of the relevant auto-addressing bus node (BK) j ) is plausible, and capturing the first value of the first bus node output stream (i j ) of the relevant auto-addressing bus node (BK) j ) using first measuring instruments (R2, D1, D3) with a second sign that is inverted to the first sign, if the previously recorded first value of the first bus node output current (i j) of the relevant auto-addressing bus node (BK) j ) is not plausible or if the previously recorded second value of the second bus node output current (i') j ) of the relevant auto-addressing bus node (BK) j ) is not plausible.

[0135] One variant of the plausibility check procedure involves using an error address as the valid bus node address of the relevant auto-addressing bus node (BK). j ), if the captured first value of the first bus node output current (i j ) of the relevant auto-addressing bus node (BK) j ) not plausible or if the detected second value of the second bus node output current (i') j ) of the relevant auto-addressing bus node (BK) j ) is not plausible. AUTO ADDRESSING PROCEDURE VIA INTERRUPT LINE

[0136] In addition to these address assignment methods supported by bus shunt resistors (R2, R2'), the following procedure for auto-addressing via an interrupt line is proposed: This is a procedure for assigning logical bus node addresses to the bus nodes ((BK1) to [BK n ]) of a data bus system with a serial, bidirectional, differential two-wire communication bus (DB), in which the data bus system has a bus master (ECU) with an address input (Adr i0 ) and n bus nodes ((BK1) to [BK n ]) (with n as a positive integer). Each of the n bus nodes ((BK2) to [BK n ]) is via a data line section (DB1 to DB n) or a serial, bidirectional, differential two-wire communication bus (DB) is connected to the bus master (ECU) for data transmission. A line, which is used here to signal the auto-addressing information and is typically an interrupt line, is now connected to an address input (Adr i0 ) of the bus master (ECU) starting through all bus nodes ((BK1) to [BK n ]) so that they pass through the individual bus nodes ((BK1) to [BK n ]) in n line sections ([L1] to [L n ]) is subdivided. Each of the bus nodes, hereinafter referred to as the j-th bus node (BK) for clarity, is j ) denoted by 1≤j≤ n, now has one of these j-th bus nodes (BK). j ) associated address input [Adr ij ] and one of these j-th bus junctions (BK) j ) associated address output [Adr ojThese are used as inputs and outputs to stimulate and transmit auto-addressing information. Each of the bus nodes (BK) j ), if it is not the nth bus stop [BK n ] is, is with its address input [Adr ij ] (with 1≤j≤ n-1) with the address output [Adr o ( j+1 )] of a subsequent bus junction [BK j+1 ] with 1≤j≤ n-1 through a bus junction following the next one [BK j+1 ] associated (j+1)-th line section [L j+1 ] connected. Each of the bus hubs (BK) j ) with 2≤j≤ n is with its address output [Adr oj ] with the address input (Address (j-1) ) of a preceding bus junction [BK j-1 ] with 2≤j≤ n through a bus junction (BK) j ) associated j-th line section [L j ] connected. The first bus node (BK1) is connected to its address output (Adr o1 ) with the address input (Adr i0) of the bus master (ECU) is connected by a line section (L1) belonging to the first bus node (BK1). The respective bus node address of each bus node ((BK1) to [BK n ]) can be valid or invalid. As a first step in this procedure, all or at least some of the respective bus node addresses of bus nodes ((BK1) to [BK] are invalidated. n ]) and a relocation of at least this part of the bus junctions ((BK1) to [BK n ]) e.g., from a normal state to an addressing state. The first is intended to establish a defined initial state. The second is intended to configure address assignment in all bus nodes ((BK1) to [BK n ]) to start. As long as the bus node is in the addressing state, the line in question is not used for its normal function, e.g. as an interrupt request line, but for transporting the auto-addressing function.

[0137] During this addressing state, the first step is to set the level of the address input (Adr). i0 ) of the bus master (ECU) to a second logical value when the level of this address input (Adr i0 ) this bus master (ECU) not through the address output (Adr o1 ) of the first bus junction (BK1) of the bus junctions ((BK1) to [BK n ]) is overwritten. It is a characteristic that both the bus master (ECU) with its address input (Adr i0 ), as well as the bus junctions ((BK1) to [BK n-1 ]) with their address inputs ((Adr i1 ) to [Adr in ]) through the address outputs ((Adr o1 ) to [Adr on ]) the following bus junctions ((BK1) to [BK n ]) can be overwritten, as these are designed with a lower impedance than the corresponding driver stages in the address inputs ((Adr i1 ) to [Adr in ]) the bus junction ((BK1) to [BK n]). Only the last bus stop [BK n ] is connected to its address input [Adr in ] is not connected to any other subsequent bus hub. Therefore, at this last bus hub [BK], the bus is determined n ] the driver stage within the address input [Adr in ] of the last bus junction [BK n ] the logical state at the address input [Adr in This allows the last bus node to recognize that it is the last in the sequence of bus nodes that does not yet have a valid bus node address, and can therefore accept the address offered by the bus master as a new valid bus node address if it does not have a valid bus node address, provided it does not possess one by any means whatsoever. Since it has thus obtained and now possesses a valid bus node address, this bus node (BK) switches j ) then its address output [Adr oj ] off, thereby the driver stage of the preceding address input [Adr i(j-1)] of the previous bus junction [BK j-1 ] no longer through the address output [Adr oj ] of the bus junction (BK) j ) is overwritten and the preceding bus node [BK j-1 ] can then identify itself as the last bus node without a valid bus node address in the sequence of unaddressed bus nodes and thus, in the next initialization process, the preceding bus node [BK j-1 ] then the newly assigned bus node address offered by the bus master (ECU) can be adopted in the same way as its valid bus node address.

[0138] Since the preceding bus junction [BK j-1 ]In this way, a valid bus node address is obtained in the subsequent initialization run and then has access to it, this preceding bus node [BK] switches j-1 ] then its address output [Adr o(j-1) ] off, whereby the driver stage of the next-but-one preceding address input [Adr i(j-2)] of the next-but-one preceding bus junction [BK j-2 ] no longer through the address output [Adr o(j-1) ] of the previous bus junction [BK j-1 ] is overwritten and the next-but-one preceding bus stop [BK j-2 ] can then identify itself as the last bus node without a valid bus node address in the sequence of unaddressed bus nodes and thus, in the next-but-one initialization process, the next-but-one preceding bus node [BK j-2 ] then the newly assigned bus node address offered by the bus master (ECU) can be adopted in the same way as its valid bus node address.

[0139] This process continues bus node by bus node. Therefore, while the addressing state exists, this occurs at each bus node (BK). j ) the bus junction ((BK2) to [BK n ]) excluding the first bus node (BK1), overwriting the level at the address input [Adr i(j-1)] of the respective bus hub (BK j ) preceding bus junction [BK j-1 ] through this respective bus junction (BK) j ) with a first logical level when the bus node address of this respective bus node (BK) j ) is invalid and the level at the address input [Adr ij ] of this respective bus junction (BK) j ) has a first logical value and a setting of the level of the address input [Adr ij ] this bus junction (BK) j ) to a second logical value when the level of this address input [Adr ij ] this bus junction [BK j ] not through the address output [Adr o(j+1) ] of the respective bus hub (BK j ) possibly following bus junction [BK j+1 ] the bus junction ((BK3) to [BK n ]) is overwritten. Likewise, while the addressing state exists in the first bus node (BK1), the level at the address input (Adr) is overwritten. i0) of the bus master (ECU) through the first bus node (BK1) with a first logical level if the bus node address of the first bus node (BK1) is invalid and the level at the address input (Adr o1 ) this first bus node (BK1) has a first logical value and a setting of the level of the address input (Adr i1 ) this first bus node (BK1) to a second logical value when the level of this address input (Adr i1 ) this first bus node (BK1) not through the address output (Adr o2 ) of the bus node (BK2) following the first bus node (BK1) the bus nodes ((BK2) to [BK n ]) is overwritten. Furthermore, while the addressing state exists, a bus node address is signaled to all bus nodes ((BK1) to [BK1]. n ]) by the bus master (ECU) and the adoption of the signaled bus node address as a valid bus node address by that bus node (BK) j) the bus junction ((BK1) to [BK n ]), whose bus node address is invalid and whose address input [Adr ij ] has a second logical value and the repetition of this signaling by the bus master (ECU) until the address input (Adr i0 The bus master (ECU) has a second logical value, meaning it is not overwritten. This addressing is repeated until the bus master (ECU) is the last in the chain of unaddressed bus nodes. Therefore, the bus nodes ((BK1) to [BK] are shifted. n ]) into a second operating state different from the addressing state - which is typically the normal state when the address input (Adr i0 ) of the bus master (ECU) has a second logical value.

[0140] As already mentioned, in some cases it is advantageous if the line ([L1] to [L n ]) is used as an interrupt line in the second operating state. AUTO ADDRESSING METHOD VIA BUS SHUNT RESISTORS IN THE SUPPLY VOLTAGE LINE Figure 15

[0141] Finally, an auto-addressing method for assigning bus node addresses within a data bus system with a communication bus, in particular a serial, bidirectional, differential two-wire communication bus (DB), with n bus nodes ((BK1), (BK2), (BK3), ..... [BK n-1 ], [BK n ]), with n as a positive integer greater than zero, and a bus master (ECU) in which the bus nodes are connected via a supply voltage line (V bat ) are supplied with electrical energy, the communication bus (DB) is connected to the bus master (ECU), each bus node ((BK1), (BK2), ..... [BK n-1 ], [BK n ]) is connected to the communication bus (DB) and within the bus nodes ((BK1) to [BK n ]) each one at the respective bus hub (BK) j ) the n bus nodes ((BK1) to [BK n]) assigned measuring resistance [Rm j ] into the supply voltage line (V bat ) is inserted. This case corresponds to the Fig. 15. Thus, the data bus system proposed here has n measuring resistors ((Rm1) to [Rm n ]). The measuring resistances ((Rm1) to [Rm n ]) the bus junction ((BK1) to [BK n ]) thus divide the supply voltage line (V bat ) in n supply voltage line sections. Figure 16

[0142] Especially in the case of data bus systems for controlling multiple groups of lights ((LED1) to [LED n ]) (see also Fig. 16) significant currents via the supply voltage line (V bat ) to allow flow, the measuring resistances ((Rm1) to [Rm n ]) should preferably be chosen with the lowest possible resistance to minimize losses. It is therefore conceivable to use dedicated measuring resistors ((Rm1) to [Rm) instead of dedicated ones. n]) only conductor track constrictions or even just conductor sections of predefined length, width and thickness of the same material and with a specific conductor resistance deviating from 0 Ω / m as measuring resistors ((Rm1) to [Rm n ]) to use. These are only examples of how to implement the measuring resistors ((Rm1) to [Rm n Other implementations, such as thick-film technology, etc., are conceivable. Each bus junction (BK) j ) the bus junction ((BK1) to [BK n ]) has an addressing stream source (Iq j ). As such addressing stream sources (Iq j ) power sources can also be used that, in the normal state of the bus node, for example, serve as a power source for a light-emitting diode or other light source [LED]. j ] can be used. Each bus hub (BK) j ) the bus junction ((BK1) to [BK n ]) preferentially has means ((D2), (D3), [Rm j]), to measure the current through the measuring resistor [Rm j ] this bus junction (BK) j ) the bus junction ((BK1) to [BK n ]) to capture. The second differential amplifier (D2) of a bus node (BK) j ) detects the voltage drop across the respective measuring resistor [Rm j 9 of the relevant bus junction (BK j A third differential amplifier (D3) compares the value of the output signal of the second differential amplifier (D2) with a reference value (Ref) by calculating the difference. The third differential amplifier (D3) of the bus node (BK) j ) generates, depending on the result of this comparison, together with a controller or filter (F) of the bus node (BK). j ) a control signal (rw j ), which is specific to this bus junction (BK) j ) is. The value of this control signal (rw) j ) depends on the value of the addressing current of the addressing current source (Iq). j ) of the relevant bus junction (BK) j) assumes when the bus junction (BK) j ) has been previously switched from the normal state to the addressing state by the bus master (ECU). If the bus node is in the normal state, the addressing current source (Iq) is typically j ) is switched off if it has no other task in this normal state. For example, it is also possible for a power source that in normal operation is used to supply energy to consumers, such as light bulbs and / or LEDs [LED]. j ], is used in the addressing state of the bus node (BK) j ) as an addressing current source (Iq j ) of the bus junction (BK) j ) to use. This is in Fig. 16 shown, which differ except for the light sources ((LED1) to [LED n ]) not from the Fig. 15 distinguishes. A command from the bus master (ECU) causes the relevant bus node (BK) to go j) into the addressing state, thereby its addressing current source (Iq) j ) is switched on. This switching on of its addressing current source (Iq) j ) preferably leads to a bus junction (BK) j ) only proceeds if it does not have a valid bus node address, which is typically stored in a bus node address register (BKADR) and marked as "valid" or "invalid" with a corresponding flag. This flag is then typically also used to mark it as "invalid". If its bus node address is invalid, a bus node (BK) j It therefore preferentially participates in an auto-addressing sequence when it is initiated by the bus master (ECU). This also applies to other auto-addressing methods. The addressing current source (Iq) j ) of each bus hub (BK j ) the bus junction ((BK1) to [BK n]) then in this case feeds an addressing current towards the power supply (SUP) into the supply voltage line (V bat ) into the terminal of the measuring resistor [Rm j ] this bus junction (BK) j ) one that runs along the supply voltage line (V bat ) is furthest from the power supply (SUP). The bus nodes ((BK1) to [BK j-1 ]), which are located less far from the power supply (SUP), measure with their respective measuring instruments ((Rm1) to [Rm j-1 ], (D2), (D3)) each the additional voltage drop across their respective measuring resistors (Rm1 to Rm j-1 ) and regulate their addressing stream sources ((Iq1) to [Iq j-1 ]) down or switch them, depending on the implementation of the procedure, in this addressing state of the bus nodes ((BK1) to [BK n ]) off. This shutdown can be triggered by a threshold comparison, e.g., of the respective control signal (rw). j) of a bus hub (BK j ) can be identified. This allows the respective bus node (BK) to be recognized. j ) then determine that it is not the last bus node in the bus node sequence without a valid bus node address, or that it is the last bus node in the bus node sequence without a valid bus node address. In this latter case, the bus node adopts the bus node address offered by the bus master as its valid bus node address. Thus, this bus node—assuming it is the j-th bus node (BK)—possesses j ) - now a valid bus node address and switches its addressing current source (Iq) j ) for the duration of the addressing procedure. The addressing procedure is, as always in this disclosure, typically terminated by a command from the bus master (ECU), which preferentially addresses all bus nodes ((BK1) to [BK1]. n ]) typically causes the system to exit the addressing state and, for example, enter the normal state.

[0143] The proposed method for addressing via voltage drops along the supply voltage line (V bat ) therefore now specifically envisages the following steps: • Signaling of an addressing state, hereinafter referred to as power line addressing state, to all bus nodes ((BK1) to [BK n ]), thereby establishing an addressing state for performing an auto-addressing procedure using the supply voltage line (V bat ) assume; • If necessary, signaling to at least one bus node or part of it, preferably to all of the bus nodes ((BK1) to [BK n ]) to invalidate their bus node addresses; • Performing an initialization sequence, comprising the following steps, for each bus node (BK) j ) the n bus nodes ((BK1), (BK2), ..... [BK n-1 ], [BK n ]), which does not yet have a valid bus node address until all bus nodes of the n bus nodes ((BK1), (BK2), ..... [BKn-1 ], [BK n ]) have a valid bus stop address: ◯ Signaling of a bus address to be assigned to all bus nodes of the n bus nodes ((BK1), (BK2), ..... [BK n-1 ], [BK n ]) (Typically, this signaling also sends the bus master (ECU) a command to the bus nodes to assume or, if necessary, maintain the addressing state.); ◯ Perform the following steps in parallel for each bus junction (BK) j ) the bus node of the n bus nodes ((BK1), (BK2), ..... [BK n-1 ], [BK n ]), hereinafter referred to as the relevant bus junction (BK) j ) refers to someone who does not have a valid bus stop address: • Reception of the said auto-addressing command from the bus master (ECU) by the relevant bus node (BK); • Receipt of the bus address to be assigned from the bus master (ECU) by the relevant bus node (BK); • Receipt of a start signal for the assignment of the bus address to be assigned from the bus master (ECU) by the relevant bus node (BK) j ) and start of a timer at a start time t0=0s by the relevant bus node (BK) j ); • Detecting the voltage drop across the measuring resistor (Rm) j ) of the relevant bus junction (BK) j ) as the base voltage value [V m0 ] using measuring instruments ([Rm j ], (D2), (D3)); • At a fourth time [t4] after the start time [t0]: Switching on the addressing current source (Iq j ) of the relevant bus junction (BK) j ) and regulation of the voltage drop across the measuring resistor [Rm j ] of the relevant bus junction (BK) j ) using the addressing current source (Iq) j ) depending on the voltage drop across the measuring resistor [Rm j ] by means of a control signal (rw j), which is measured by measuring instruments ((D2), (D3), [Rm j ]) and / or control means (F) of the bus junction (BK) j ) is generated, to a total target voltage value, which is a target voltage value plus the previously measured base voltage value [V m0 ] corresponds to an increase in the addressing current of the auto-addressing current source (Iq). j ) of the relevant bus junction (BK) j ) with a first time constant [τ1] and wherein a reduction of the addressing current of the autoaddressing current source (Iq) j ) of the relevant bus junction (BK) j ) with a second time constant [τ2] (Note that no statement is yet made about the numerical ratio of the first time constant [τ1] compared to the second time constant [τ2].); • At a fifth time point [t5] after the start time [t0] and after the fourth time point [t4]: recording the value of the control signal (rw) j) or a signal derived therefrom and comparison of this value with a threshold value and • Use of the bus node address to be assigned as the valid bus node address of the bus node (BK) j ), if the magnitude of this value exceeds the threshold and switching off the addressing current source (Iq) j ) at the latest when the bus node (BK) leaves the addressing state j );

[0144] It is advisable to perform a check of the successful address assignment by the bus master (ECU) after a bus node address has been assigned to a bus node (BK). j ). If this results in an error, for example, if several bus nodes report a bus collision, it is advisable to delete the validity of the last assigned bus node address, thereby invalidating the affected bus nodes (BK). j ) again like bus hubs (BK) j) without a valid bus node address. After all bus node addresses have been assigned to all bus nodes ((BK1) to [BK n ]), which should receive a bus node address, it should be checked whether all bus nodes ((BK1) to [BK n ]), which should have received a bus node address, have received a valid bus node address. If all bus nodes have received a valid bus node address, the bus master (ECU) preferentially signals to all bus nodes ((BK1) to [BK n ]), that they should leave the addressing state and enter another state, preferably the normal state. In the normal state, the bus nodes ((BK1) to [BK] switch n ]) their addressing stream sources ((Iq1) to [Iq n ]) from or operate them in the function that is for these addressing current sources ((Iq1) to [Iq n]) in this operating state, here the normal state. Performing a further initialization sequence is advisable if not all bus nodes ((BK1) to [BK n ]), which should have received a bus node address, have received a valid bus node address. Generally, it is advantageous if the second time constant [τ2] is smaller than the first time constant [τ1] by a factor greater than 10. At the very least, however, the first time constant [τ1] should be larger than the second time constant [τ2]. It is beneficial if the first time constant [τ1] is within the relevant auto-addressing bus node (BK). j ) from the measuring instruments ([Rm j ], (D2), (D3)) measured value of the voltage drop across the measuring resistor [Rm j ] of the relevant auto-addressing bus node (BK j ) depends and / or the second time constant [τ2] within the relevant auto-addressing bus node (BK) j) from the measuring instruments ([Rm j ], (D2), (D3)) measured value of the voltage drop across the measuring resistor [Rm j ] of the relevant auto-addressing bus node (BK j ) depends. This allows for faster control of the voltage drop across the measuring resistor [Rm]. j ] of the relevant bus junction (BK) j ). Figure 17

[0145] In the Fig. 17 now also include second addressing current sources (Iq') j ) the relevant bus junction (BK j ) for auto-addressing via the power supply line (V bat ). Second measuring instruments (D2', D3') are also used in addition to the first measuring instruments ((Rm1) to [Rm n], (D2), (D3)). This redundancy can be used for testing and monitoring purposes, as each auto-addressing run should lead to the same result for both branches. If this is not the case, the offered bus node address is preferably not accepted, but instead, for example, a specially reserved and predetermined error address is assumed. If the bus master (ECU) addresses this error address using its data bus protocol, the bus node where the error occurred responds to the bus master (ECU), which it should not do if no error had occurred in the bus node. The test can, for example, look like this: the difference between the value of the first control signal (rw) j ) of a bus hub (BK j ) and the value of the second control signal (rw' j ) this bus junction (BK) j) is generated. If the magnitude of this difference exceeds a predetermined limit, at least one of the circuits is malfunctioning. This can be detected and used to prevent the bus node address offered by the bus master (ECU) from being accepted as a valid bus node address. Instead, the predetermined error address is used as the valid bus node address, which can then be verified by the bus master (ECU) by addressing this address. Simultaneous use of different auto-addressing methods Figure 18

[0146] It is advantageous to be able to use several of the auto-addressing methods described here, as each method can confirm the success of correct identification through redundancy. Furthermore, using more than two auto-addressing methods allows for fail-operational capability. This means that auto-addressing is usually successful, but an error is detected and can then be signaled. This is potentially of particular importance for safety-critical applications. Fig. Figure 18 shows such a proposed device, which allows the execution of several auto-addressing procedures and thus offers increased security. Fig. 18 is a combination of Fig. 17, Fig. 13, Fig. 6 and Fig. 5. To the bus junction ((BK1) to [BK n ]) becomes a first multiplexer (X1) of the respective bus node (BK). j) and a second multiplexer (X2) of this bus node (BK) j ) used to connect the inputs of the second differential amplifier (D2) of this bus node (BK) j ) to the first bus shunt resistor (R2) of this bus junction (BK) j ) or to the measuring resistor [Rm j ] this bus junction (BK) j ) to switch. In the bus nodes ((BK1) to [BK n ]) In addition, another first multiplexer (X1') of the respective bus node (BK) will be j ) and another second multiplexer (X2') of this bus node (BK) j ) used to control the inputs of the second differential amplifier (D2') of this bus node (BK) j ) to the second bus shunt resistor (R2') of this bus junction (BK) j ) or to the measuring resistor (Rm j ) this bus junction (BK) j ) to switch. Accordingly, the first addressing current source (Iq) is j ) this bus junction (BK) j) either with a reference potential (GND) or with the first single-wire bus (DB) a ) through a third demultiplexer (X3) of this bus node (BK) j ) connected. The third demultiplexer (X3) of this bus node (BK) then establishes j ) also determines whether the first addressing stream of the first addressing stream source (Iq) j ) this bus junction (BK) j ) before or after the first bus shunt resistor (R2) of this bus junction (BK) j ) into the first single-wire bus (DB a ). is fed in. Analogously, the second addressing current source (Iq') is j ) this bus junction (BK) j ) either with a reference potential (GND) or with the second single-wire bus (DB) b ) by a further third demultiplexer (X3') of this bus node (BK) j ) connected. The third demultiplexer (X3') of this bus node (BK) then establishes a connection. j) also determines whether the second addressing stream of the second addressing stream source (Iq' j ) this bus junction (BK) j ) before or after the second bus shunt resistor (R2') of this bus junction (BK) j ) into the second single-wire bus (DB) b ) is fed in. Low-impedance normal operation Figure 19

[0147] It is now useful if only in the addressing state of the bus nodes ((BK1) to [BK n ]) the bus shunt resistors (R2, R2') in the first single-wire bus (DB a ) and the second single-wire bus (DB b ) are effective. Therefore, it is advisable, as soon as the addressing state is exited, preferably in all bus nodes ((BK1) to [BK n ]) by a first bridging switch (S4) in preferably each bus node (BK) j ) the first bus shunt resistor (R2) of this bus junction (BK) j ) and by a second bridging switch (S4') in this bus node (BK) j) the second bus shunt resistor (R2') of this bus junction (BK) j ) to short-circuit. This is in Fig. 19 shown.

[0148] Of course, this approach would also be suitable for the measuring resistor [Rm j ] of a bus hub (BK j ) conceivable. However, the corresponding switches would generally take up too much chip area. Furthermore, the voltage drop across the normal supply voltage line is usually sufficient, so a dedicated measuring resistor [Rm] is not necessary in these cases. j ] into the supply voltage line (V bat ) is inserted, but a section of the supply voltage line (V bat ) as measuring resistor [Rm j ] this bus junction (BK) j ) can be used. Swap detection Figure 20

[0149] Fig. 20 now additionally shows in the exemplary bus nodes ((BK1) to [BK n]) one fourth multiplexer (X4) per bus node (BK) j ), with which a control system within this bus node (BK) j ) the two inputs of the second differential amplifier (D2) of this bus node (BK) j ) can be swapped. Furthermore, the Fig. 20 additionally in the exemplary bus junctions ((BK1) to [BK n ]) one further fourth multiplexer (X4') per bus node (BK) j ), with which the control within this bus node (BK) j ) the two inputs of the further second differential amplifier (D2') of this bus node (BK) j ) can be swapped. Figure 21

[0150] This can be due to Fig. 21 will now be explained for the error case shown there: The second bus node (BK2) is installed incorrectly. This can be easily detected by controlling the second bus node (BK2) in a self-test, which is preferably performed at the beginning of the initialization procedure. Preferably, for example, the bus master (ECU) signals to the bus nodes ((BK1) to [BK n ]), that they should perform such a self-test. Other start scenarios, e.g., during a power-on phase, are conceivable. For example, the bus node (BK) j ) using its measuring instruments (R2, R2', D2, D2', D3, D3', Iq j , Iq' j , X1, X1', X2, X2', X3, X3') determine whether the first addressing current of its first addressing current source (Iq j) flows through its first bus shunt resistor (R2) when it is supposed to flow through its first bus shunt resistor (R2), and whether the second addressing current of its second addressing current source (Iq' j The signal flows through its second bus shunt resistor (R2') when it is supposed to flow through the second bus shunt resistor (R2'). If this is exactly the opposite, the bus node's controller can determine this based on the corresponding measurement results and use a fourth multiplexer (X4) of this bus node (BK) to j ) and the third multiplexer (X3) of this bus node (BK) j ) firstly, the inputs of the second differential amplifier (D2) of this bus node (BK) j ) swap and secondly the injection point for the first addressing current of the first addressing current source (Iq) j ) this bus junction (BK) j ) to the other side of the first bus shunt resistor (R2) of this bus junction (BK) j). In this case, the control of the bus node can be achieved by means of a further fourth multiplexer (X4') of this bus node (BK). j ) and the further third multiplexer (X3') of this bus node (BK) j ) firstly, the inputs of the second differential amplifier (D2') of this bus node (BK) j ) also swap and, secondly, the feed-in point for the second addressing current of the second addressing current source (Iq') j ) this bus junction (BK) j ) to the other side of the second bus shunt resistor (R2') of this bus junction (BK) j ). Then the auto-addressing procedure using the bus shunt resistors (R2, R2') can be carried out again. Also possible, but not shown here for clarity, is to move the feed point of the first addressing current source (Iq). j ) this bus junction (BK) j ) into the supply voltage line (V bat) to the other side of the measuring resistor (Rm j ) by means of a fifth multiplexer (X5) not shown. However, this is only useful if the first addressing current source (Iq) j ) does not need to supply too large a current under normal conditions. However, this is precisely the case when the first auto-addressing current source (Iq) j ) in the normal state of the bus junction (BK) j ) for example, the energy source of light bulbs (LED) j ) of the bus node. In that case, the transistors of the fifth multiplexer (X5), which is not shown, would be too large and therefore too expensive. Similarly, relocating the feed point of the second addressing current source (Iq') is not possible. j ) this bus junction (BK) j ) into the supply voltage line (V bat ) to the other side of the measuring resistor (Rm j ) by means of a further fifth multiplexer (X5') that is not shown. The same considerations apply here.

[0151] It was also not shown that the entrance to the address (address) ij ) of the relevant bus junction (BK) j ) (here, for example, the second bus node (BK2)) with the output of the address output (Adr oj ) of the relevant bus junction (BK) j ) can be swapped using two multiplexers (X6, X7), if such a swap as in Fig. 21 by controlling the bus node (BK j ) e.g., as described above.

[0152] These are examples of measures to compensate for the insertion of a bus node with connector swapping. List of characters Fig. Figure 1 shows an example of a rear light module (BLM) of a motor vehicle. Fig. Figure 2 shows a two-wire communication bus (DB), such as is known from the state of the art. Fig. Figure 3 shows the preferred structure of the bit stream packets (BP) sent by the bus master (ECU). Fig. Figure 4 shows a data bus system in which a first bus shunt resistor (R2) is inserted into the first single-wire bus (DBa) at each bus node ((BK1) to [BK n ]) is inserted. Fig. 5 shows based on Fig. 4 a serial, bidirectional, differential two-wire communication bus (DB) with a first bus shunt resistor (R2) inserted into the first single-wire bus (DB1) and a second bus shunt resistor (R2') inserted into the second single-wire bus (DB2). Fig. 6 corresponds to the Fig. 5 with the difference that the respective first addressing current sources ((Iq1) to [Iq n ]) from the perspective of the bus master (ECU), the first addressing current behind the first bus shunt resistors (R2) in the addressing phase in which the respective bus node (BK) j) is in an addressing state, feed in. Fig. Figure 7 shows, by way of example, the output current (i1) of the first bus node (BK1), the output current (i2) of the second bus node (BK2) and the output current (i3) of the third bus node (BK3) in an exemplary data bus system with n=3 bus nodes (BK1 to BK3). Fig. Figure 8 shows the output current (i1) of the first bus node (BK1), the output current (i2) of the second bus node (BK2) and the output current (i3) of the third bus node (BK3). Fig. Figure 9 shows the output current (i1) of the first bus node (BK1), the output current (i2) of the second bus node (BK2) and the output current (i3) of the third bus node (BK3). Fig. Figure 10 shows the control loop of a bus node (BK). j ) to provide with a first detection device (DET) that detects internal signals (ds1, ds3) of the bus node (BK) j ) checks for plausibility.. Fig. Figure 11 shows a simplified representation of a j-th auto-addressing bus node (BK). j ), which is responsible for repositioning the injection point of the second addressing current of the second addressing current source (Iq') j ) of the bus junction under consideration (BK j ) has a second detection device (DET'). Fig. 12 shows auto-addressing bus node (BK) 1, BK2, BK3) with a second bus shunt bypass switch (S4') per bus node (BKj) to bridge the associated second bus shunt resistance (R2') of the bus node (BKj) in normal operation, i.e. in the normal state of the bus node (BKj), and to open this second bus shunt bypass switch (S4') only in the addressing state. Fig. 13 is based on the Fig. 2 and shows a data bus system with auto-addressing via interrupt line. Fig. Section 14 describes the basic procedure of the preferred address allocation method described here, using an interrupt line. Fig. Figure 15 shows a serial, bidirectional, differential two-wire communication bus (DB), with n bus nodes ((BK1), (BK2), (BK3), ..... [BK n-1 ], [BK n ]), with n as a positive integer greater than zero, and a bus master (ECU) in which the bus nodes are connected via a supply voltage line (V bat ) are supplied with electrical energy, the communication bus (DB) is connected to the bus master (ECU), each bus node ((BK1), (BK2), ..... [BK n-1 ], [BK n ]) is connected to the communication bus (DB) and within the bus nodes ((BK1) to [BK n ]) each one at the respective bus hub (BK) j ) the n bus nodes ((BK1) to [BK n ]) assigned measuring resistance (Rm j ) into the supply voltage line (V bat ) is inserted Fig. 16 shows Fig. 15 with light sources (LED1 to LED n ). Fig. 17 is based on Fig. 15, where now also second addressing current sources (Iq' j ) the relevant bus junction (BK) j ) for auto-addressing via the power supply line (V bat ) be used. Fig. Figure 18 shows a device that allows the execution of several auto-addressing procedures. Fig. 18 is a combination of Fig. 17, Fig. 13, Fig. 6 and Fig. 5. Fig. 19 corresponds to the Fig. 18 with a bypass switch (S4). Fig. 20 shows the exemplary bus junctions ((BK1) to [BK n ]) one fourth multiplexer (X4) per bus node (BK) j ), with a controller within this bus node (BK) j ) and one further fourth multiplexer (X4') per bus node (BK) j), with a controller within this bus node (BK) j ) with which the control within this bus node (BK) j ) the two inputs of the further second differential amplifier (D2') of this bus node (BK) j ) can be swapped. Fig. 21 shows Fig. 20 with a twisted bus junction (BK2). List of abbreviations ADR1 Address recognition unit of the first bus node (BK1); ADR2 Address Recognition Unit of the Second Bus Node (BK2); ADR3 Address Recognition Unit of the Third Bus Node (BK3); ADR4 Address Recognition Unit of the fourth bus node (BK4); ADR5 Address Recognition Unit of the Fifth Bus Node (BK5); ADR6 Address Recognition Unit of the sixth bus node (BK6); ADR j Address recognition unit of the j-th bus node [BK j ]; ADR n Address recognition unit of the nth bus node [BK n ]; Address i(j-1) Address input of the (j-1)th bus node [BK (j-1) ]; Address ij Address input of the j-th bus node (BK) j ); Address i(j+1) Address input of the (j+1)th bus node [BK (j+1) ]; Address in Address input of the nth bus node [BK n ]; Address o(j-1) Address output of the (j-1)th bus node [BK (j-1) ]; Address oj Address output of the j-th bus node (BK) j ); Address o(j+1) Address output of the (j+1)th bus node [BK (j+1) ]; Address on Address output of the nth bus node [BK n ]; AT1 scanning device of the first bus node (BK1); AT2 scanning device of the second bus node (BK2); AT3 scanning device of the third bus node (BK3); AT4 scanning device of the fourth bus node (BK4); AT5 fifth bus node scanning device (BK5); AT6 scanning device of the sixth bus node (BK6); AT j scanning device of the j-th bus node [BK j ]; AT n Sampling device of the nth bus node [BK n ]; In English: “arbitrary units”, relative units; BKADR1 Bus node address register of the first bus node (BK1); BKADR2 Bus node address register of the second bus node (BK2); BKADR3 Bus node address register of the second bus node (BK3); BKADR4 Bus node address register of the second bus node (BK4); BKADR5 Bus node address register of the second bus node (BK5); BKADR6 Bus node address register of the second bus node (BK6); BKADR j Bus node address register of the jth bus node [BK j ]; BKADR n Bus node address register of the nth bus node [BK n ]; BK j-2 (j-2)-th bus junction; BK j-1(j-1)th bus junction; BK j+1 (j+1)th bus junction; BK j+2 (j+2)th bus junction; BK n-2 (n-2)th bus junction; BK n-1 (n-1)th bus stop; BK n nth bus stop; BLM rear light module; CLKA1 sampling signal within the first bus node (BK1); CLKA2 sampling signal within the second bus node (BK2); CLKA3 sampling signal within the third bus node (BK3); CLKA4 sampling signal within the fourth bus node (BK4); CLKA5 sampling signal within the fifth bus node (BK5); CLKA6 sampling signal within the sixth bus node (BK6); CLKA j Sampling signal within the j-th bus node [BK j ]; CLKA n Sampling signal within the nth bus node [BK n ]; CLKG1 Clock generator of the first bus node (BK1); CLKG2 Clock generator of the second bus node (BK2); CLKG3 Clock generator of the third bus node (BK3); CLKG4 Clock generator of the fourth bus node (BK4); CLKG5 Clock generator of the fifth bus node (BK5); CLKG6 Clock generator of the sixth bus node (BK6); CLKG j Clock generator of the j-th bus node [BK j ]; CLKG n Clock generator of the nth bus node [BK n ]; DB j j-th, bidirectional, differential data line section of the bidirectional differential two-wire communication bus between the j-th bus node (BK) j ) and the (j-1)th bus junction [BK j-1 It comprises one corresponding section of the first single-wire bus (DB). a ) and the second single-wire bus (DB b ); DB nnth, bidirectional, differential data line section of the bidirectional differential two-wire communication bus between the nth bus node [BK n] and the (n-1)th bus stop [BK n-1 It comprises one corresponding section of the first single-wire bus (DB). a ) and the second single-wire bus (DB b ); EV1 Energy supply means of the first bus node (BK1), which is intended for the energy supply of the first light source (LED1) of the first bus node (BK1). EV2 Energy supply unit of the second bus node (BK2), which is intended for the energy supply of the second light source (LED2) of the second bus node (BK2). EV3 Energy supply unit of the third bus node (BK3), which is intended for the energy supply of the third light source (LED3) of the third bus node (BK3). EV4 Energy supply unit of the fourth bus node (BK4), which is intended for the energy supply of the fourth light source [LED4] of the fourth bus node (BK4). EV5 Energy supply unit of the fifth bus node (BK5), which is intended for the energy supply of the fifth light source [LED5] of the fifth bus node (BK5). EV6 Energy supply unit of the sixth bus node (BK6), which is intended for the energy supply of the sixth light source [LED6] of the sixth bus node (BK6). EV j Energy supply means of the j-th bus junction (BK) j ), which is responsible for the energy supply of the j-th light source [LED j ] of the j-th bus junction (BK j ) is planned. EV n Energy supply means of the nth bus node [BK n ], which is responsible for the energy supply of the nth light source [LED n ] of the nth bus junction [BK n ] is planned. GGlq jPush-pull power source; GLlq j Common-mode addressing current source of the bus node (BK) j ); GND second supply voltage line (complementary to V) bat ) also referred to as reference potential; HS-CAN High-Speed ​​CAN Protocol; I amax maximum addressing current; Iq j1 first addressing stream source of the j-th bus node (BK) j ) when splitting the first addressing current source [Iq j1 ] of the j-th bus junction (BK j ) into a first addressing current source that feeds in before the first bus shunt resistor (R2) and another first addressing current source that feeds in after the first bus shunt resistor (R2); Iq j2 further first addressing current source of the j-th bus node (BK) j ) when splitting the first addressing current source [Iq j1 ] of the j-th bus junction (BK j) into a first addressing current source that feeds in before the first bus shunt resistor (R2) and a first addressing current source that feeds in after the first bus shunt resistor (R2); Iq' j1 second addressing current source of the j-th bus node (BK) j ) when splitting the second addressing current source [Iq j1 ] of the j-th bus junction (BK j ) into a second addressing current source that feeds in before the second bus shunt resistor (R2') and another second addressing current source that feeds in after the second bus shunt resistor (R2'); Iq' j2 further second addressing current source of the j-th bus node (BK) j ) when splitting the second addressing current source [Iq j1 ] of the j-th bus junction (BK j) into a second addressing current source that feeds in before the second bus shunt resistor (R2') and another second addressing current source that feeds in after the second bus shunt resistor (R2'); I ref first predefined total current value within a bus node (BK) j ) for the first bus node output stream (i j The initial total flow value should preferably be the same for all bus nodes. However, it can also vary from bus node to bus node. I' ref second predefined total current value within a bus node (BK) j ) for the second bus node output stream (i' j The second total flow value should preferably be the same for all bus nodes. However, it can also vary from bus node to bus node. L1 to L n Line from line sections L1 to L n ; L4 fourth line section from the fourth bus junction [BK4] to the third bus junction (BK3); L j-1 (j-1)th line section from (j-1)th bus junction [BK j-1 ] to the (j-2)th bus junction [BK j-2 ]; L j j-th line section from the j-th bus junction (BK) j ) to the (j-1)th bus junction [BK j-1 ]; L j+1 (j+1)th line section from (j+1)th bus node [BK j+1 ] to the j-th bus junction (BK) j ); L n-1 (n-1)th line section from (n-1)th bus junction [BK n-1 ] to the (n-2)th bus stop [BK n-2 ]; L n nth line section from the nth bus node [BK n ] to the (n-1)th bus stop [BK n-1 ]; LED j Light source of the j-th bus junction (BK) j This includes groups of light sources and circuits. (These can be, for example, series and parallel circuits of several LEDs.) LED n Light source of the nth bus junction [BK n This includes groups of light sources and circuits. (These can be, for example, series and parallel circuits of several LEDs.) µC1 Microcontroller of the first bus node (BK1); µC2 Microcontroller of the second bus node (BK2); µC3 Microcontroller of the third bus node (BK3); µC4 microcontroller of the fourth bus node (BK4); µC5 microcontroller of the fifth bus node (BK5); µC6 microcontroller of the sixth bus node (BK6); microcontroller j microcontroller of the j-th bus node (BK) j ); microcontroller n Microcontroller of the nth bus node [BK n ]; rw n first control signal of the nth bus node [BK n The first control signal of the nth bus node [BK] n ] is done using means, preferably a first filter (F) of the nth bus node [BKn ], which is connected to the third comparator (D3) of the nth bus node [BK n ] can also form a unit from the output signal of the third comparator (D3) of the nth bus node [BK n ] formed and serves to control the first auto-addressing current source [Iq n ] of the nth bus junction [BK n ]; rw' n second control signal of the nth bus node [BK n The second control signal of the nth bus node [BK] n ] is done using means, preferably a second filter (F) of the nth bus node [BK n ], which is connected to the corresponding third comparator (D3') of the nth bus node [BK n ] can also form a unit from the output signal of the corresponding third comparator (D3') of the nth bus node [BK n ] formed and serves to control the second auto-addressing current source [Iq' n ] of the nth bus junction [BK n ]; SUP power supply; SW1 is the first threshold value for comparison with the first rule value (r1) of the first bus node (BK1) for the decision as to whether the address data should be adopted as a valid bus node address; SW'1 second threshold for comparison with the second rule value (r'1) of the first bus node (BK1) for the decision as to whether the address data should be adopted as a valid bus node address; SW2 is the first threshold value for comparison with the first rule value (r2) of the second bus node (BK2) for the decision as to whether the address data should be adopted as a valid bus node address; SW'2 second threshold for comparison with the second rule value (r'2) of the second bus node (BK2) for the decision as to whether the address data should be adopted as a valid bus node address; SW3 is the first threshold value for comparison with the first rule value (r3) of the third bus node (BK3) for the decision as to whether the address data should be adopted as a valid bus node address; SW'3 second threshold for comparison with the second rule value (r'3) of the third bus node (BK3) for the decision as to whether the address data should be adopted as a valid bus node address; SW j first threshold value for comparison with the first control value (r) j ) of the j-th bus junction (BK j ) for the decision whether the address data should be accepted as a valid bus stop address; SW' j second threshold for comparison with the second control value (r') j ) of the j-th bus junction (BK j ) for the decision whether the address data should be accepted as a valid bus stop address; SW n first threshold for comparison with the first control value [r n] of the nth bus junction [BK n ] for the decision as to whether the address data should be accepted as a valid bus stop address; SW' n second threshold for comparison with the second control value [r' n ] of the nth bus junction [BK n ] for the decision as to whether the address data should be accepted as a valid bus stop address; τ1 first time constant with which the increase of the first addressing current of the first regulated auto-addressing current source (Iq) j ) of the relevant bus junction (BK) j ) is done; τ2 second time constant, with which the reduction of the first addressing current of the first regulated auto-addressing current source (Iq) j ) of the relevant auto-addressing bus node (BK) j ) is τ3 third time constant, with which the increase of the second addressing current of the second regulated auto-addressing current source (Iq') j) of the relevant bus junction (BK) j ) is done; τ4 fourth time constant, with which the reduction of the second addressing current of the second regulated auto-addressing current source (Iq') j ) of the relevant auto-addressing bus node (BK) j ) is done; τ ref Device-specific, undefined temporal reference quantity; t time; t1 first time point after the start of the timer at which a freeze of the control of the first addressing current source (Iq) j ) of the relevant auto-addressing bus node (BK) j ) is done; t2 second time point after the start of the timer at which a freeze of the control of the second addressing current source (Iq') j ) of the relevant auto-addressing bus node (BK) j ) is done; t3 third point in time at which, under certain conditions, the bus node address to be assigned is accepted by the bus master (ECU) as the valid bus node address of the relevant auto-addressing bus node (BK). j ) is done; TR driver; TR a first driver in the bus master (ECU) or in a bus node ((BK1) to [BK n ]). Preferably, the driver is implemented as a CAN driver or RS485 driver. A first driver, preferably a CAN driver, can assume two of the three allowed states: In a first state, it sets a first logical level (Z1) on the first single-wire bus (DB). a In a second state, it applies a third logical level (Z3) to the first single-wire bus (DB). a The first driver of the bus master (ECU) also operates in the addressing state of the data bus system and the bus nodes ((BK1) to [BK n]) as the first current sink for the first addressing currents of the first addressing current sources ((Iq1), (Iq2) to [Iq n ]) the bus junction ((BK1) to [BK n ]) and their first quiescent currents. Preferably, the first driver of a bus node ((BK1) to [BK n ]) or the bus master (ECU) indicates the first state (Z1) when the second driver [TR b ] of the relevant bus junction ((BK1) to [BK n ]) assumes the second state (Z2). This differentially induces a first differential level (z1) in the signal. Preferably, the first driver of a bus node ((BK1) to [BK n ]) or the bus master (ECU) indicates the third state (Z3) when the second driver [TR b ] of the relevant bus junction ((BK1) to [BK n]) assumes the third state (Z3). This differentially induces a third differential level (z3) in the signal. The first driver, also known as an RS485 driver, can preferentially assume two of the two allowed states: In a first state, it applies a first logic level (Z1) to the first single-wire bus (DB). a In a second state, it applies a second logical level (Z2) to the first single-wire bus (DB). a The first driver of the bus master (ECU) also operates in the addressing state of the data bus system and the bus nodes ((BK1) to [BK n ]) as the first current sink for the first addressing currents of the first addressing current sources ((Iq1), (Iq2) to [Iq n ]) the bus junction ((BK1) to [BK n ]) and their first quiescent currents. Preferably, the first driver of a bus node ((BK1) to [BK n ]) or the bus master (ECU) indicates the first state (Z1) when the second driver [TR b] of the relevant bus junction ((BK1) to [BK n ]) assumes the second state (Z2). This differentially induces a first differential level (z1) in the signal. Preferably, the first driver of a bus node ((BK1) to [BK n ]) or the bus master (ECU) indicates the second state (Z2) when the second driver [TR b ] of the relevant bus junction ((BK1) to [BK n ]) assumes the first state (Z1). This differentially induces a second differential level (z2) in the signal. Furthermore, the first driver typically has a sub-device for detecting and preventing a bus collision in the event of simultaneous access to the first single-wire bus (DB). a ) by a first driver of another bus node ((BK1) to [BK n ]) or the bus master (ECU). TR b second driver in the bus master (ECU) or in a bus node ((BK1) to [BK n]). Preferably, the second driver is implemented as a CAN driver or RS485 driver. A second driver, if implemented as a CAN driver, can preferably assume two of the three allowed states: In a first state, it places a second logical level (Z2) on the second single-wire bus (DB). b In a second state, it applies a third logical level (Z3) to the second single-wire bus (DB). b The second driver of the bus master (ECU) also operates in the addressing state of the data bus system and the bus nodes ((BK1) to [BK n ]) as the second current sink for the second addressing currents of the second addressing current sources ((Iq'1) to [Iq' n ]) the bus junction ((BK1) to [BK n ]) and their second quiescent currents. Preferably, the second driver of a bus node ((BK1) to [BK n ]) or the bus master (ECU) indicates the second state (Z2) when the first driver [TR a ] of the relevant bus junction ((BK1) to [BK n]) assumes the first state (Z1). This differentially induces the signal with a first differential level (z1). Preferably, the second driver of a bus node ((BK1) to [BK n ]) or the bus master (ECU) indicates the third state (Z3) when the first driver [TR a ] of the relevant bus junction ((BK1) to [BK n ]) assumes the third state (Z3). This differentially induces a third differential level (z3) in the signal. The second driver, also an RS485 driver, can preferentially assume two of the two allowed states: In a first state, it applies a second logic level (Z2) to the first single-wire bus (DB). a In a second state, it applies a first logical level (Z1) to the second single-wire bus (DB). b The second driver of the bus master (ECU) also operates in the addressing state of the data bus system and the bus nodes ((BK1) to [BK n]) as the second current sink for the second addressing currents of the second addressing current sources ((Iq'1) to [Iq' n ]) the bus junction ((BK1) to [BK n ]) and their second quiescent currents. Preferably, the second driver of a bus node ((BK1) to [BK n ]) or the bus master (ECU) indicates the second state (Z2) when the first driver [TR a ] of the relevant bus junction ((BK1) to [BK n ]) assumes the first state (Z1). This differentially induces the signal with a first differential level (z1). Preferably, the second driver of a bus node ((BK1) to [BK n ]) or the bus master (ECU) indicates the first state (Z1) when the first driver [TR a ] of the relevant bus junction ((BK1) to [BK n]) assumes the second state (Z2). This differentially induces a second differential level (z2) in the signal. Furthermore, the first driver typically has a sub-device for detecting and preventing a bus collision in the event of simultaneous access to the first single-wire bus (DB). a ) by a first driver of another bus node ((BK1) to [BK n ]) or the bus master (ECU). UART Universal Asynchronous Receiver Transmitter; V m0 Base voltage value; X5 multiplexer for swapping the connections of the measuring resistor [Rm j ] of a bus hub (BK j ); X6 first multiplexer for swapping the connections of the address input [Adr ij ] and the address output [Adr oj ] of a bus hub (BK j ); X7 second multiplexer for swapping the connections of the address input [Adr ij] and the address output [Adr oj ] of a bus hub (BK j ); Reference symbol list ADRD address information within the data information (DATA) of a bit stream packet (BP); Address io Address input of the bus master (ECU); Address i1 Address input of the first bus junction (BK1); Address i2 Address input of the second bus junction (BK2); Address i3 Address input of the third bus junction (BK3); Address o1 Address output of the first bus node (BK1); Address o2 Address output of the second bus node (BK2); Address o3 Address output of the third bus node (BK3); BK1 first bus junction; BK2 second bus junction; BK3 third bus junction; BK4 fourth bus junction; BK5 fifth bus junction; BK6 sixth bus junction; BK jj-th bus node, also referred to in this disclosure as the bus node in question, when making statements about a single bus node of the bus nodes (BK1, BK2, .....BK n-1 , BK n ) be carried out; BP Bitstream packet (English: frame), also referred to as data packet; CHKD verification information within the data information (DATA) of a bit stream packet (BP). This preferably consists of a CRC checksum and / or parity bits, etc.; CLK clock within the bus master (ECU); CLKA j Sampling signal within the j-th bus node (BK) j ); D2 second differential amplifier for measuring the first current through the first single-wire bus (DB) a ) using the first shunt resistor (R2) or to measure the current through the supply voltage line (V bat ) using the measuring resistor [Rm j within the relevant bus junction (BK) jFor clarity, the second differential amplifiers are not labelled with indices for the respective bus nodes. D2' second differential amplifier for measuring the second current through the second single-wire bus (DB) b ) using the second shunt resistor (R2') or to measure the current through the supply voltage line (V bat ) using the measuring resistor [Rm j within the relevant bus junction (BK) j For clarity, the second differential amplifiers are not labelled with indices for the respective bus nodes. D3 third comparator or third differential amplifier for comparing the output of the second differential amplifier (D2), which is used to measure the current through the first single-wire bus (DB). a ) by means of the first shunt resistor (R2) or through the supply voltage line by means of the measuring resistor [Rm j] serves, with a threshold value (Ref) within the relevant bus node (BK) j The third comparators and differential amplifiers are not labeled with indices for the respective bus nodes (BK) for clarity. j ) provided. D3' third comparator or third differential amplifier for comparing the output of the second differential amplifier (D2'), which is used to measure the current through the second single-wire bus (DB) b ) via the second shunt resistor (R2') or via the supply voltage line using the measuring resistor [Rm j ] serves, with a further threshold (Ref') within the relevant bus node (BK) j The third comparators and differential amplifiers are not labeled with indices for the respective bus nodes (BK) for clarity. j ) provided. DATA: Data information within a bit stream packet; DB serial, bidirectional, differential two-wire communication bus; DB a first single-wire bus of the serial, bidirectional, differential two-wire communication bus (DB); DB b second single-wire bus of the serial, bidirectional, differential two-wire communication bus (DB); DB1 is the first bidirectional, differential data line section of the bidirectional differential two-wire communication bus between the first bus node (BK1) and the bus master (ECU). It comprises one corresponding section of the first single-wire bus (DB). a ) and the second single-wire bus (DB b ); DB2 is the second, bidirectional, differential data line section of the bidirectional differential two-wire communication bus between the second bus node (BK2) and the first bus node (BK1). It comprises a corresponding section of the first single-wire bus (DB1). a) and the second single-wire bus (DB b ); DB3 is the third, bidirectional, differential data line section of the bidirectional differential two-wire communication bus between the third bus node (BK3) and the second bus node (BK2). It comprises a corresponding section of the first single-wire bus (DB3). a ) and the second single-wire bus (DB b ); DET first detection device within a bus node (BK) j ); DET' second detection device within a bus node (BK) j ); ds2 output of the second differential amplifier (D2). This is an internal signal within a bus node (BK). j ); ds2' Output of the second differential amplifier (D2'). This is an internal signal within a bus node (BK). j ); ds3 internal signal within a bus node (BK) j ); ds3' further internal signal within a bus node (BK) j ); ECU bus master, also referred to here as control unit; the first fault signal of the first detection device (DET); er' second fault signal of the second detection device (DET'); F first filter; F' second filter; i1 first bus node output current, which the first bus node (BK1) sends to the bus master (ECU) via the section of the first single-wire bus (DB1), which is part of the connection section of the serial, bidirectional, differential two-wire communication bus (DB) between the first bus node (BK1) and the bus master (ECU), and which the bus master receives as the first bus master input current; i'1 second bus node output current which the first bus node (BK1) sends to the bus master (ECU) via the section of the second single-wire bus (DB2), which is part of the connection section of the serial, bidirectional, differential two-wire communication bus (DB) between the first bus node (BK1) and the bus master (ECU), and which the bus master receives as the second bus master input current; i2 first bus node output current that the second bus node (BK2) sends to the first bus node (BK1) via the section of the first single-wire bus (DB1), which is part of the connection section of the serial, bidirectional, differential two-wire communication bus (DB) between the second bus node (BK2) and the first bus node (BK1), and which the first bus node (BK1) receives as the first bus node input current; i'2 second bus node output current which the second bus node (BK2) sends to the first bus node (BK1) via the section of the second single-wire bus (DB2), which is part of the connection section of the serial, bidirectional, differential two-wire communication bus (DB) between the second bus node (BK2) and the first bus node (BK1), and which the first bus node (BK1) receives as the second bus node input current; i3 first bus node output current that the third bus node (BK3) sends to the second bus node (BK2) via the section of the first single-wire bus (DB1), which is part of the connection section of the serial, bidirectional, differential two-wire communication bus (DB) between the third bus node (BK3) and the second bus node (BK2), and which the second bus node (BK2) receives as the first bus node input current; i'3 second bus node output current, which the third bus node (BK3) sends to the second bus node (BK2) via the section of the second single-wire bus (DB2), which is part of the connection section of the serial, bidirectional, differential two-wire communication bus (DB) between the third bus node (BK3) and the second bus node (BK2), and which the second bus node (BK2) receives as the second bus node input current; i j first bus node output stream that the j-th bus node (BK) j ) via the section of the first single-wire bus (DB1), which is part of the connection section of the serial, bidirectional, differential two-wire communication bus (DB) between the j-th bus node (BK) j ) and the (j-1)th bus junction [BK j-1 ] is, at the (j-1)th bus junction [BK j-1 ] sends and the (j-1)th bus node [BK (j-1) ] as the first bus node input stream; i' jsecond bus node output stream, which the j-th bus node (BK) j ) via the section of the second single-wire bus (DB2), which is part of the connection section of the serial, bidirectional, differential two-wire communication bus (DB) between the j-th bus node (BK) j ) and the (j-1)th bus junction [BK j-1 ] is, at the (j-1)th bus junction [BK j-1 ] sends and the (j-1)th bus node [BK (j-1) ] as the second bus node input stream; i j+1 first bus node output stream that the (j+1)th bus node [BK j+1 ] via the section of the first single-wire bus (DB1), which is part of the connection section of the serial, bidirectional, differential two-wire communication bus (DB) between the (j+1)th bus node [BK j+1 ] and the j-th bus junction (BK j ) is, at the j-th bus junction (BK j ) sends and the j-th bus node (BK) j ) receives as the first bus node input stream; i' j+1 second bus node output stream, which the (j+1)th bus node [BK j+1 ] via the section of the second single-wire bus (DB2), which is part of the connection section of the serial, bidirectional, differential two-wire communication bus (DB) between the (j+1)th bus node [BK j+1 ] and the j-th bus junction (BK j ) is, at the j-th bus junction (BK j ) sends and the j-th bus node (BK) j ) receives as a second bus node input stream; i n-1 first bus node output stream that the (n-1)th bus node [BK n-1] via the section of the first single-wire bus (DB1), which is part of the connection section of the serial, bidirectional, differential two-wire communication bus (DB) between the (n-1)th bus node [BK n-1] and the (n-2)th bus stop [BK n-2 ] is, at the (n-2)th bus junction [BK n-2 ] sends and the (n-2)th bus node [BK n-2] as the first bus node input stream; i' n-1 second bus node output stream, which the (n-1)th bus node [BK n-1] via the section of the second single-wire bus (DB2), which is part of the connection section of the serial, bidirectional, differential two-wire communication bus (DB) between the (n-1)th bus node [BK n-1] and the (n-2)th bus stop [BK n-2 ] is, at the (n-2)th bus junction [BK n-2 ] sends and the (n-2)th bus node [BK n-2 ] as the second bus node input stream; i n first bus node output stream that the nth bus node [BK n] via the section of the first single-wire bus (DB1), which is part of the connection section of the serial, bidirectional, differential two-wire communication bus (DB) between the nth bus node [BK n] and the (n-1)th bus stop [BK n-1] is at the (n-1)th bus junction [BK n-1]sends and the (n-1)th bus node [BK n-1] as the first bus node input stream received; i' n second bus node output stream, which the nth bus node [BK n] via the section of the second single-wire bus (DB2), which is part of the connection section of the serial, bidirectional, differential two-wire communication bus (DB) between the nth bus node [BK n] and the (n-1)th bus stop [BK n-1] is at the (n-1)th bus junction [BK n-1] sends and the (n-1)th bus node [BK n-1] as a second bus node input stream; IF1 differential serial interface of the first bus node (BK1); IF2 differential serial interface of the second bus node (BK2); IF3 differential serial interface of the third bus node (BK3); IF4 differential serial interface of the fourth bus node (BK4); IF5 differential serial interface of the fifth bus node (BK5); IF6 differential serial interface of the sixth bus node (BK6); IF (j-1) differential serial interface of the (j-1)th bus node [BK j-1 ]; IF j differential serial interface of the j-th bus node (BK j ); IF (j+1) differential serial interface of the (j+1)th bus node [BK j+1 ]; IF (n-1) differential serial interface of the (n-1)th bus node [BK n-1 ]; IF n differential serial interface of the nth bus node [BK n ]; ILD lighting information for controlling the energy supply of the light sources (LEDs) j ) of the bus junction (BK) j ) through the energy supply medium (EV j ) of the bus junction (BK) j ) depending on this lighting information; INFO: Useful information within the data information (DATA) of a bit stream packet (BP). Preferably, this is lighting data for the respective bus node (BK). j ); Iq1 first addressing current source of the first bus node (BK1); Iq1' second addressing current source of the first bus node (BK1); Iq2 first addressing current source of the second bus node (BK2); Iq2' second addressing current source of the second bus node (BK2); Iq3 first addressing current source of the third bus node (BK3); Iq3' second addressing current source of the third bus node (BK3); Iq j first addressing stream source of the j-th bus node (BK) j ); lq j ' second addressing current source of the j-th bus node (BK) j ); Iq n first addressing current source of the nth bus node [BK n ]; Iq n' second addressing current source of the nth bus node [BK n ]; L1 first line section from the first bus node (BK1) to the bus master (ECU); L2 second line section from the second bus junction (BK2) to the first bus junction (BK1); L3 third line section from the third bus junction (BK3) to the second bus junction (BK2); µC microcontroller; LED1 is the light source of the first bus node (BK1). Light source groups and circuits are included here. (These can be, for example, series and parallel circuits of several LEDs.) LED2 light source of the second bus node (BK2). Light source groups and circuits are included here. (These can be, for example, series and parallel circuits of several LEDs.) LED3 light source of the third bus node (BK3). Light source groups and circuits are included here. (These can be, for example, series and parallel circuits of several LEDs.) LED4 light source of the fourth bus junction (BK4). Light source groups and circuits are included here. (These can be, for example, series and parallel circuits of several LEDs.) LED5 is the lighting element of the fifth bus node (BK5). This includes groups of lights and their interconnections. (These can be, for example, series and parallel circuits of multiple LEDs.) LED6 light source of the sixth bus junction (BK6). Light source groups and circuits are included here. (These can be, for example, series and parallel circuits of several LEDs.) pol first polarity signal, which preferentially controls the multiplexer (X4); pol' second polarity signal, which preferentially controls the further multiplexer (X4'); R2 is the first shunt resistor for measuring the current through the first single-wire bus (DB). a ) within the relevant bus junction (BK) j The first shunt resistor is used here as part of the bus junction (BK). j ) considered. It is in each of the auto-addressable bus nodes ((BK1) to [BK n ]) preferably present in each case. The first shunt resistors were not labeled with indices for the respective bus nodes for clarity. R2' second shunt resistor for measuring the current through the second single-wire bus (DB) b ) within the relevant bus junction (BK) j The second shunt resistor is used here as part of the bus junction (BK). j ) considered. It is in each of the auto-addressable bus nodes ((BK1) to [BK n]) preferably present in each case. The second shunt resistors were not labeled with indices for the respective bus nodes for clarity. Rec receiver. Each bus node ((BK1) to [BK n The bus master (ECU) and the data processing unit (DPU) preferably have a receiver. A receiver extracts the data (DATA) contained in the bit stream packets (BP) and outputs it, preferably along with error information, via an output (out). The receiver typically checks whether the check information (CHKD) within the data information (DATA) of a bit stream packet (BP) indicates error-free reception. If a bit stream packet (BP) was not received without errors, the receiver signals this. Ref10 tenth threshold; Ref10' further tenth threshold; Ref11 eleventh threshold; Ref11' further eleventh threshold; Rm1 measuring resistor in the supply voltage line for the first bus node (BK1); Rm2 measuring resistor in the supply voltage line for the second bus node (BK2); Rm3 measuring resistor in the supply voltage line for the third bus node (BK3); Rm j Measuring resistor in the supply voltage line for the j-th bus node (BK) j ); Rm n Measuring resistor in the supply voltage line for the nth bus node [BK n ]; rw1 first control signal of the first bus node (BK1). The first control signal of the first bus node (BK1) is generated from the output signal of the third comparator (D3) of the first bus node (BK1) by means, preferably a first filter (F) of the first bus node (BK1), which can also form a unit with the third comparator (D3) of the first bus node (BK1), and serves to control the first auto-addressing current source (Iq1) of the first bus node (BK1); rw'1 second control signal of the first bus node (BK1). The second control signal of the first bus node (BK1) is generated from the output signal of the corresponding third comparator (D3') of the first bus node (BK1) by means of, preferably a second filter (F) of the first bus node (BK1), which can also form a unit with the corresponding third comparator (D3') of the first bus node (BK1), and serves to control the second auto-addressing current source (Iq'1) of the first bus node (BK1); rw2 first control signal of the second bus node (BK2). The first control signal of the second bus node (BK2) is generated from the output signal of the second comparator (D3) of the second bus node (BK2) by means, preferably a first filter (F) of the second bus node (BK2), which can also form a unit with the third comparator (D3) of the second bus node (BK2), and serves to control the first auto-addressing current source (Iq2) of the second bus node (BK2); rw'2 second control signal of the second bus node (BK2). The second control signal of the second bus node (BK2) is generated from the output signal of the corresponding third comparator (D3') of the second bus node (BK2) by means, preferably a second filter (F) of the second bus node (BK2), which can also form a unit with the corresponding third comparator (D3') of the second bus node (BK2), and serves to control the second auto-addressing current source (lq'2) of the second bus node (BK2); rw3 first control signal of the third bus node (BK3). The first control signal of the third bus node (BK3) is generated from the output signal of the third comparator (D3) of the third bus node (BK3) by means, preferably a first filter (F) of the third bus node (BK3), which can also form a unit with the third comparator (D3) of the third bus node (BK3), and serves to control the first auto-addressing current source (Iq3) of the third bus node (BK3); rw'3 second control signal of the third bus node (BK3). The second control signal of the third bus node (BK3) is generated from the output signal of the corresponding third comparator (D3') of the third bus node (BK3) by means, preferably a second filter (F) of the third bus node (BK3), which can also form a unit with the corresponding third comparator (D3') of the third bus node (BK3), and serves to control the second auto-addressing current source (Iq'3) of the third bus node (BK3); rw j first control signal of the j-th bus node (BK) j ). The first control signal of the j-th bus node (BK) j ) is done using means, preferably a first filter (F) of the j-th bus node (BK) j ), which is connected to the third comparator (D3) of the j-th bus node (BK) j )can also form a unit from the output signal of the third comparator (D3) of the j-th bus node (BK) j)formed and serves to control the first auto-addressing current source (Iq) j ) of the j-th bus junction (BK j ); rw' j second control signal of the j-th bus node (BK) j The second control signal of the j-th bus node (BK) j ) is achieved using means, preferably a second filter (F) of the j-th bus node (BK) j ), which is connected to the corresponding third comparator (D3') of the j-th bus node (BK) j ) can also form a unit from the output signal of the corresponding third comparator (D3') of the j-th bus node (BK) j ) formed and serves to control the second auto-addressing current source (Iq') j ) of the j-th bus junction (BK j ); S4 first bypass switch - also called first bus shunt bypass switch - for bypassing the first shunt resistor (R2) within a bus node (BK) jThe first bypass switch can also be implemented as a transistor and / or as a more complex circuit of various electronic and other components, if the functionality of a switch results in the operating range; S4' second bypass switch - also called second bus shunt bypass switch - for bypassing the second shunt resistor (R2') within a bus node (BK) j The second bypass switch can also be implemented as a transistor and / or as a more complex circuit of various electronic and other components, if the functionality of a switch results in the operating range; START Start signal; SYNC synchronization information; t B Length of a single bit within a bit stream packet (BP); TX a Transmitter that the first driver [TR a ] includes; TX b Transmitter that connects the second driver [TRb ] includes; V bat Power supply line; X1 first multiplexer for connecting a first input of the second differential amplifier (D2) for measuring the current through the first single-wire bus (DB) a ) with a first connection of the first shunt resistor (R2) on the side of the bus master (ECU) or optionally with a second connection of the measuring resistor [Rm j ] in the supply voltage line within the relevant bus node (BK) j ); X1' second multiplexer for connecting a first input of the second comparator (D2') for measuring the current through the second single-wire bus (DB) b ) with a first connection of the second shunt resistor (R2') on the side of the bus master (ECU) or optionally with a second connection of the measuring resistor [Rm j ] in the supply voltage line within the relevant bus node (BK) j ); X2 is the first multiplexer for connecting a second input of the second differential amplifier (D2) for measuring the current through the first single-wire bus (DB). a ) with a second connection of the first shunt resistor (R2) on the opposite side from the bus master (ECU) or with a first connection of the measuring resistor [Rm j ] in the supply voltage line within the relevant bus node (BK) j ); X2' second multiplexer for connecting a second input of the second comparator (D2') for measuring the current through the second single-wire bus (DB) b ) with a second connection of the second shunt resistor (R2') on the opposite side from the bus master (ECU) or with a first connection of the measuring resistor [Rm j ] in the supply voltage line within the relevant bus node (BK) j ); X3 first demultiplexer for connecting one terminal of the first addressing current source (Iq)j ) of the bus junction (BK) j ) with a first connection of the first shunt resistor (R2) or with a second connection of the first shunt resistor (R2) or with a reference potential within the relevant bus node (BK) j ); X3' second demultiplexer for connecting one terminal of the second addressing current source (Iq' j ) of the bus junction (BK) j ) with a first connection of the second shunt resistor (R2') or with a second connection of the second shunt resistor (R2') or with a reference potential within the relevant bus node (BK) j ); X4 first multiplexer for swapping the inputs of the second differential amplifier (D2) of the bus node (BK) j ); X4' second multiplexer for swapping the inputs of the further second differential amplifier (D2') of the bus node (BK) j ); Z1 first logical state in which the first single-wire bus (DB) a ) or the second single-wire bus (DB) b ). This may be located. In this disclosure, it is also referred to as High. z1 is the first differential state in which the serial, bidirectional, differential two-wire communication bus (DB) can be. This is also referred to as "High" in this disclosure. Z2 second logical state in which the first single-wire bus (DB) a ) or the second single-wire bus (DB) b ). This may be located. In this disclosure, it is also referred to as Low. z2 is the second differential state in which the serial, bidirectional, differential two-wire communication bus (DB) can be located. This is also referred to as "Low" in this disclosure. Z3 third logical state in which the first single-wire bus (DB) a ) or the second single-wire bus (DB) b). This is also referred to as Idle in this disclosure. Preferably, but not necessarily, the corresponding physical level of the first single-wire bus (DB) a ) or the second single-wire bus (DB) b ) a value around a common mean. z3 is the third differential state in which the serial, bidirectional, differential two-wire communication bus (DB) can be located. This is also referred to as Idle in this disclosure. Preferably, but not necessarily, the corresponding differential physical level has a value around zero.

Claims

[1] Bus node (BK j ) capable of carrying out a procedure for assigning bus addresses to bus nodes of a serial, bidirectional, differential two-wire communication bus (DB), - the method for assigning bus addresses to bus nodes ((BK1) (BK2), (BK3), ...... [BK n-1 ], [BK n ]) of a serial, bidirectional, differential two-wire communication bus (DB) by means of first bus shunt resistors (R2) and by means of second bus shunt resistors (R2') in the individual bus nodes ((BK1), (BK2), (BK3), ...... [BK n-1 ], [BK n ]) is carried out in a procurement period and - where, after the procedure for assigning bus addresses to the bus nodes ((BK1), (BK2), (BK3), ...... [BK n-1 ], [BK n ]) of the serial, bidirectional, differential two-wire communication bus (DB) in the allocation period is followed by an operating period and - wherein the serial, bidirectional, differential two-wire communication bus (DB) comprises a first single-wire bus (DB1) and a second single-wire bus (DB2) and - where the bus node (BK j ) has such a first bus shunt resistor (R2) and such a second bus shunt resistor (R2') and - wherein the first bus shunt resistor (R2) is inserted into the first single-wire bus (DB1) and - wherein the second bus shunt resistor (R2') is inserted into the second single-wire bus (DB2) and - comprising a first bus shunt bypass switch (S4), • which is open before a bus address is assigned to the bus node during the allocation period and • which is closed after a bus address has been assigned to the bus node during the allocation period and • which is closed during the operating period, and - comprising a second bus shunt bypass switch (S4'), • which is open before a bus address is assigned to the bus node during the allocation period and • which is closed after a bus address has been assigned to the bus node during the allocation period and • which is closed during the operating period.

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