Methods for forming semiconductor devices

Abstract

A method (100) for forming a semiconductor device (300), the method (100) comprising: Forming (110) a mask layer having a first implantation window on a semiconductor substrate (310); Implanting (120) dopants with a first implantation energy into the semiconductor substrate (310) through the first implantation window to form a first section of a doping region (320) of the semiconductor device (300); Adjusting (130) the mask layer to form a second implantation window of the mask layer; and Implanting (140) dopants with a second implantation energy into the semiconductor substrate (310) through the second implantation window to form a second section of the doping region (320) of the semiconductor device (300), wherein the second implantation energy differs from the first implantation energy, and wherein a lateral dimension of the first implantation window differs from a lateral dimension of the second implantation window, wherein, taking into account the implantation energy-dependent lateral scatter, a difference between the lateral dimension of the second implantation window and the lateral dimension of the first implantation window depends on a difference between the second implantation energy and the first implantation energy, wherein a maximum lateral dimension of the first section of the doping region (320) differs from a maximum lateral dimension of the second section of the doping region (320) by less than 5% of the maximum lateral dimension of the second section of the doping region (320).

Description

AREA

[0001] The following examples relate to semiconductor devices and methods for forming semiconductor devices. BACKGROUND

[0002] The formation of semiconductor devices can involve ion implantation. For example, dopants with different implantation energies can be implanted into a semiconductor substrate. A doping region formed by dopant implantation can have varying lateral extent, which may depend on its distance from a surface of the semiconductor substrate. This varying lateral extent can lead to, for example, a non-uniform vertical boundary of the doping region. There is a need for improved concepts for implanting dopants into semiconductor substrates.

[0003] Die Dokumente DE 10 2007 052 220 A1, US 2014 / 0 273 370 A1, DE 10 2015 120 272 A1, US 2015 / 0 372 075 A1, DE 39 20 585 A1, US 5 198 692 A, „BARTOLF, H. [et al.]: Development of a 60µm Deep Trench and Refill Process for Manufacturing Si-Based High-Voltage Super-Junction Structures. In: IEEE Trans. on Semicond. Manuf., Vol. 26, 2013, No. 4, S. 529-541“ und „ZHONG, X. ; WANG, B. ; SHENG, K.: Design and experimental demonstration of 1.35 kV SiC super junction Schottky diode. In: 2016 28th International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2016, S. 231-234“ beschreiben bekannte Halbleiterbauelemente. ZUSAMMENFASSUNG

[0004] One example relates to a method for forming a semiconductor device. The method involves forming a mask layer, which has a first implantation window, on a semiconductor substrate. The method further involves implanting dopants with a first implantation energy through the first implantation window into the semiconductor substrate to form a first section of a doped region of the semiconductor device. The mask layer is adapted to form a second implantation window, and the dopants are implanted with a second implantation energy through the second implantation window into the semiconductor substrate to form a second section of the doped region of the semiconductor device.The second implantation energy differs from the first implantation energy, and a lateral dimension of the first implantation window differs from a lateral dimension of the second implantation window.

[0005] Another example relates to a method for forming a semiconductor device, comprising forming a first mask layer on a semiconductor substrate. The first mask layer includes a first implantation window. The method further comprises implanting dopants into the semiconductor substrate with a first implantation energy through the first implantation window to form a first section of a doped region of the semiconductor substrate. A second mask layer is formed on the semiconductor substrate. The second mask layer includes a second implantation window, which differs from the first implantation window. Dopants are implanted into the semiconductor substrate with a second implantation energy through the second implantation window to form a second section of the doped region of the semiconductor substrate.A difference between a lateral dimension of the second implantation window and a lateral dimension of the first implantation window is selected depending on a difference between the second implantation energy and the first implantation energy.

[0006] An example relates to a semiconductor device comprising a semiconductor substrate and a doping region positioned within the semiconductor substrate. The vertical extent of a vertical section of the doping region is greater than 300 nm. A minimum lateral dimension of the doping region within the vertical section of the doping region in a vertical cross-sectional area of ​​the doping region is at least 90% of an average lateral dimension within the vertical section of the doping region, and a maximum lateral dimension of the doping region within the vertical section of the doping region is at most 110% of an average lateral dimension of the doping region within the vertical section of the doping region. BRIEF DESCRIPTION OF THE FIGURES

[0007] The following are some examples of devices and / or methods, described solely by way of example and with reference to the accompanying figures, in which the following applies: Fig. Figure 1 shows a flowchart of a process for forming a semiconductor device, comprising providing a mask layer on a semiconductor substrate and fitting the mask layer; Fig. Figure 2 shows a flowchart of a process for forming a semiconductor device, comprising forming two mask layers on the semiconductor substrate. Fig. Figure 3 shows a schematic cross-section of a semiconductor device with a doping region that has a minimum and a maximum lateral extent; Fig. Figure 4 shows a schematic cross-section of a semiconductor device with a tapered lateral extent of a doping region of the semiconductor device; Fig. Figures 5a-c show an example of forming a doping region using back-etching of an implantation mask; Fig. Figure 6 shows a schematic cross-section of a semiconductor device comprising a transistor; and Fig. Figure 7 shows a schematic cross-section of a semiconductor device comprising a diode. DETAILED DESCRIPTION

[0008] Several examples will now be described in more detail with reference to the accompanying drawings, which illustrate some of these examples. The thickness of lines, layers, and / or areas in the figures may be exaggerated for clarity.

[0009] While further examples of various modifications and alternative forms are suitable, some specific examples are shown in the figures and are described in detail below. Throughout the description of the figures, "same" or "similar" reference symbols refer to identical or similar elements that, when compared, may be implemented identically or in a modified form, while providing the same or a similar function.

[0010] It is understood that when an element is described as "connected" or "coupled" to another element, the elements may be connected or coupled directly or via one or more intermediate elements. When two elements A and B are combined using "or," this is to be understood as revealing all possible combinations, i.e., only A, only B, and A and B, unless explicitly or implicitly stated otherwise. An alternative formulation for the same combinations is "at least one of A and B" or "A and / or B." The same applies, mutatis mutandis, to combinations of more than two elements. Furthermore, when an element (e.g., a layer or a mask) is "on" (e.g., positioned "on") another element, this does not necessarily mean that this element is positioned "directly on" that other element. Rather, another component (e.g.,(another layer) should be positioned between this element and this other element.

[0011] The terminology used herein to describe certain examples is not intended to be limiting for other examples. Where a singular form, such as "a" and "the," "a," or "a," is used, and the use of only a single element is neither explicitly nor implicitly defined as mandatory, further examples may also use plural elements to implement the same function. Similarly, where a function is subsequently described as being implemented using multiple elements, further examples may implement the same function using a single element or a single processing entity.It is further understood that the terms “include”, “comprehensive”, “exhibit” and / or “exhibit” when used specify the presence of the indicated features, integers, steps, operations, processes, elements and / or components thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, processes, elements, components and / or a group thereof.

[0012] Unless otherwise defined, all terms (including technical and scientific terms) are used here in their usual meaning within the field to which examples belong.

[0013] When dopants are implanted into a wide-bandgap semiconductor substrate, particularly a silicon carbide substrate, via a mask layer using ion implantation, foreign atoms within the semiconductor may no longer be able to move by diffusion, unlike in a silicon substrate. Therefore, multiple implantations may be necessary to create a homogeneous implantation (e.g., a quasi-box profile perpendicular to the semiconductor surface). Furthermore, diffusion may not occur with some dopants (e.g., nitride (N), aluminum (Al)) when activated at a temperature of 1800°C.

[0014] Ion implantation in semiconductor materials can cause lateral scattering (straggling). The lateral expansion of a doped region can increase with increasing implantation energy. If implantation is performed with several different implantation energies via the same mask, e.g., with the same implantation window, straggling can occur within the semiconductor substrate (as, for example, in...). Fig. (as shown in 4) a slightly bulbous implantation profile will result.

[0015] Therefore, in some embodiments, it is proposed to implant the individual implantations via a specifically adapted mask layer (e.g., a resist mask), depending on their implantation energy, so that the mask layer can compensate for the lateral scattering, which increases, for example, with deeper implantations. Consequently, sharper-edged implantation profiles can be achieved.

[0016] Fig. Figure 1 shows a flowchart of a process 100 for forming a semiconductor device, comprising the provision of a mask layer and the fitting of the mask layer. The process 100 may include the formation 110 of a mask layer on a semiconductor substrate. The semiconductor substrate may comprise at least one of the following: a semiconductor wafer and an epitaxially grown semiconductor layer. The semiconductor substrate extends along a principal extension plane in lateral directions. Perpendicular to the principal extension plane, in a vertical direction, the semiconductor substrate may have a thickness that is small compared to the extension of the semiconductor substrate in the lateral directions.

[0017] The mask layer can include a first implantation window. For example, the mask layer can be provided on a front surface of the semiconductor substrate. The mask layer can include a resist layer (e.g., photoresist), an oxide layer, a metal layer, and / or a nitride layer, or the mask layer can consist of any one of these layers. Forming the mask layer can involve forming a layer on the semiconductor substrate and removing part of the layer, for example, by etching, to create the first implantation window.

[0018] The procedure 100 can include the implantation 120 of dopants. The dopants can be implanted into the semiconductor substrate through the first implantation window using a first implantation energy. The dopants can be implanted 120 while the mask layer is positioned on the semiconductor substrate after the mask layer has been formed 110. The dopants can be implanted 120 to form a first section of a doping region of the semiconductor device. For example, a maximum lateral extent of the first section of the doping region can be greater than a maximum vertical extent of the first section of the doping region.

[0019] Procedure 100 may further include an adjustment 130 of the mask layer. The mask layer may be adjusted 130 to form a second implantation window. A midpoint of the first implantation window may be the same as a midpoint of the second implantation window. The second implantation window may differ from the first implantation window with respect to its lateral extent. For example, the adjustment 130 of the mask layer may involve increasing or decreasing a lateral dimension of the first implantation window. For instance, all edges of the implantation window may be altered or modified equally.

[0020] For example, a lateral dimension of the first implantation window may differ from a lateral dimension of the second implantation window. The two lateral dimensions may represent the same geometric parameter of the implantation window, such as its length or width. For instance, the lateral dimension of the first and / or second implantation window may be the width or length of a border of the first and / or second implantation window if the first and / or second implantation window has a rectangular or square lateral cross-section. Alternatively, the first and / or second implantation window may have an elliptical or circular lateral cross-section, and the lateral dimension of the first and / or second implantation window may be its radius.The lateral dimension of the first implantation window and the lateral dimension of the second lateral dimension can be measured in the same direction parallel to a front face of the semiconductor substrate (that is, along at least one of the lateral directions). For example, the first and second implantation windows are rectangular, and the width and / or length of the second implantation window can differ from the width and / or length of the first implantation window.

[0021] Method 100 can further include implanting dopants 140 into the semiconductor substrate with a second implantation energy after fitting the mask layer. The dopants can be implanted with a second implantation energy through the second implantation window of the mask layer 140. The dopants can be implanted 140 to form a second section of the doping region of the semiconductor device, for example, adjacent to the first section of the doping region. In at least one example of Method 100, the dopants implanted 140 to form the second section can be implanted through the first section of the doping region.

[0022] Both the dopants implanted with the first implantation energy and those implanted with the second implantation energy can be of a first conductivity type, which can be either n-type or p-type. Generally, any implanted dopant, e.g., one implanted with a third implantation energy, etc., can be of the first conductivity type. Alternatively, at least one of the dopants implanted with a different energy can be of a second conductivity type, opposite to the first. For example, the dopants implanted with the first implantation energy can be of the first conductivity type, and the dopants implanted with the second implantation energy can be of the second conductivity type.The first conductivity type can be an n-type, and the second conductivity type can be a p-type, or vice versa.

[0023] The doping region can be formed by at least the two implantations used to create the first and second sections, but more implantation processes through multiple implantation windows of varying sizes can be used to create the entire doping region. If multiple implantation processes are implemented, each process can involve the implantation of dopants with a corresponding implantation energy and / or through a corresponding implantation window.

[0024] In the case of at least three implantation processes, the respective implantation energies and / or the respective implantation windows are different for at least two subsequent implantation processes. However, it is possible that at least two implantation energies are the same or substantially the same. Furthermore, at least two implantation windows can be the same. In a typical embodiment, in the case of at least three implantation processes, each of the respective implantation energies of an implantation process can be greater (or alternatively, less) than the implantation energy of the immediately following implantation process. This applies, mutatis mutandis, to the size of the implantation window.

[0025] If the dopants are all of the first conductivity type, the doping region, after implantation of all doping region segments, can be a continuous region of the first conductivity type in the semiconductor substrate, comprising at least the first and second segments formed by implantation through the first and second implantation windows. If dopants of opposite conductivity types are implanted, the doping region can include at least one continuous region of the first conductivity type and at least one continuous region of the second conductivity type.

[0026] For example, the second implantation energy can differ from the first. Consequently, the vertical distance between the second portion of the doping region and the surface of the semiconductor substrate can differ from the vertical distance between the first portion of the doping region and the surface of the semiconductor substrate. By using different implantation energies, a doping region with a large vertical extent can be achieved. For example, the first and second portions can be vertically adjacent, or they can partially overlap vertically.

[0027] Implanting dopants into the semiconductor substrate at different implantation energies can cause varying degrees of lateral scattering. For example, higher implantation energies may result in greater lateral scattering of the implanted dopants compared to lower implantation energies. By providing adapted implantation windows with different lateral dimensions for implanting dopants at varying energies, the lateral extent of the implanted regions can be controlled, for example, by taking the lateral scattering into account as a function of the implantation energy. Adjusting the implantation window of the mask layer can also increase the homogeneity of the sidewalls or vertical boundaries of the doping region.

[0028] For example, the second implantation energy can be lower than the first. In this case, the lateral dimension of the second implantation window can be larger than the lateral dimension of the first. With lower implantation energy, the implantation depth of the dopants can be reduced. For example, the second section of the doping region can be closer to the surface of the semiconductor substrate than the first section. The vertical distance of the first section of the doping region to the front surface of the semiconductor substrate can be greater than the vertical distance of the second section of the doping region to the front surface of the semiconductor substrate.Due to the lower implantation energy, the lateral scatter of the dopants implanted with the second implantation energy (140) may be smaller than the lateral scatter of the dopants implanted with the first implantation energy (120).

[0029] Accordingly, the mask layer can be adjusted to achieve a more uniform lateral extent of the doping region, for example, due to a similar lateral extent of the first and second sections of the doping region. The mask layer can be adjusted such that the lateral dimension of the second implantation window is larger than the lateral dimension of the first implantation window. The larger lateral dimension of the second implantation window can compensate for the lower lateral dispersion of the dopants implanted with the lower second implantation energy.

[0030] In another example, the second implantation energy may be higher than the first. In this case, the lateral dimension of the second implantation window may be smaller than the lateral dimension of the first. Implanting with sequentially higher energies can lead to differential canalization due to disturbances in the crystal structure of the lower-energy implantations.

[0031] For example, adapting 130 of the mask layer may involve etching the mask layer to increase the lateral dimension of the first implantation window in order to obtain the second implantation window. This can provide a larger lateral dimension of the second mask window compared to the first mask window. For example, a portion of the mask layer may be back-etched to increase a lateral area of ​​the mask layer's implantation window. For example, isotropic etching may be used to adapt 130 of the mask layer. For example, oxygen (O2) plasma may be used to etch the mask layer, e.g., if the mask layer is a photoresist layer. In particular, treatment with oxygen plasma can result in combustion (also called ashing), which is equivalent to etching. Adapting 130 of the mask layer may result in a reduction of the mask layer's thickness.For example, the thickness of the mask layer prior to the adjustment of the mask layer 130 can be at least 1 µm (or at least 1.5 µm or at least 2 µm or at least 3 µm or at least 5 µm) and / or at most 10 µm (or at most 7 µm or at most 5 µm) in order to maintain the second implantation window.

[0032] Alternatively, the mask layer can be adapted so that the lateral dimension of the second implantation window is smaller than the lateral dimension of the first implantation window. Accordingly, the second implantation energy can be higher than the first. By providing a smaller implantation window at higher implantation energies, it may be possible to compensate for greater lateral scattering of the implanted dopants.

[0033] In another example, adjusting the mask layer 130 can involve forming a spacer at one edge of the first implantation window. This allows for the provision of a second implantation window with a smaller lateral dimension than the first. Forming the spacer makes it possible to reduce the lateral dimension of the first implantation window to maintain the second. For example, to form the spacer, an auxiliary layer can be deposited onto the mask layer. The auxiliary layer can be back-etched such that the spacer remains at the edges of the first implantation window. By controlling the thickness of the auxiliary layer and / or the etching, the width of the spacer and the size or lateral dimension of the second implantation window can be adjusted.

[0034] For example, the difference between the lateral dimension of the second implantation window and the lateral dimension of the first implantation window can be selected based on a difference between the second and first implantation energies. This difference can be based on, correlate with, and / or be proportional to the difference between the first and second implantation energies. For instance, if the difference between the first and second implantation energies is increased, the difference between the lateral dimension of the first and second implantation windows can also be increased.

[0035] However, the required lateral dimension of each implantation window can be inversely proportional to the implantation energy used. This means that if the first implantation energy is greater than the second implantation energy, the lateral dimension of the first implantation window can be smaller than the lateral dimension of the second implantation window, and vice versa.

[0036] The relationship between the difference in implantation energies and the difference in lateral dimensions can be nonlinear. By adjusting the mask layer or the lateral dimension of the mask layer's implantation window according to a difference in implantation energies, the effect of lateral scatter on the lateral extent of the doping region can be reduced; for example, a more uniform lateral extent of the doping region can be achieved. For instance, the maximum lateral dimension of the first section of the doping region can differ from the maximum lateral dimension of the second section of the doping region by less than 10% (or less than 5%, or less than 3%).

[0037] For example, the difference between the lateral dimension of the first implantation window and the lateral dimension of the second implantation window can be at least 10 nm (or at least 20 nm, at least 50 nm or at least 100 nm) and / or at most 500 nm (or at most 300 nm, and at most 200 nm, at most 100 nm or at most 50 nm).

[0038] For example, a lateral portion of the second implantation window may encompass a lateral portion of the first implantation window. The first and second implantation windows may overlap, at least partially. For instance, the second implantation window may be larger than the first and may completely encompass the first. Alternatively, the first implantation window may be larger and encompass the second, for example, if the first implantation energy is lower than the second.

[0039] Method 100 can further include adapting the mask layer to form a third implantation window. Dopants can be implanted into the semiconductor substrate through this third implantation window using a third implantation energy to form a third section of the doped region of the semiconductor device, for example, in a third implantation process following the second implantation process. The dopants implanted using the third implantation energy can be of the first conductivity type or the second conductivity type.

[0040] A difference between the lateral dimension of the third implantation window and the lateral dimension of the first (or second) implantation window can be selected based on, or derived from, a difference between the third and first (and / or second) implantation energies, and / or be based on the same, and / or correlate with the same, and / or be proportional to the same. By creating the third section, the vertical extent of the doping region can be increased. For example, the third implantation energy can differ from the first and second implantation energies.

[0041] The lateral dimension of the third implantation window may be selected and / or adjusted in the same or a similar manner as for the second implantation window. This means that the disclosure herein relating to the second implantation window applies, mutatis mutandis, to the third implantation window and vice versa. For example, the lateral dimension of the third implantation window may differ from the lateral dimensions of the first and second implantation windows. For example, the lateral dimension of the third implantation window may be larger or smaller than both the lateral dimensions of the first and second implantation windows. Alternatively, the lateral dimension of the third implantation window may be larger than the lateral dimension of the first implantation window and smaller than the lateral dimension of the second implantation window.In the latter case, the third implantation energy can be smaller than the second implantation energy and larger than the first implantation energy. In another example, the lateral dimension of the third implantation window can be smaller than the lateral dimension of the first implantation window, but larger than the lateral dimension of the second implantation window.

[0042] By providing multiple implantation processes to form corresponding doping regions, a doping region with a greater vertical extent can be created while maintaining homogeneity of the vertical boundary of the doping region. For example, at least two (or at least four) and / or at most eight (or at most six) implantation processes can be performed to form the doping region. In a typical example, at least three and at most seven implantation processes are performed. For example, at higher implantation energies, more implantation windows can be used than at lower implantation energies (e.g., within a predefined implantation energy range) because lateral scattering increases at higher implantation energies.For example, the number of lateral minima and / or lateral maxima of the doping region may correlate with the number of implantation procedures performed. By performing more implantation procedures for a doping region of a predefined vertical extent, the homogeneity of the vertical boundary of the doping region can be increased. The difference between lateral maxima and lateral minima can be reduced because the effect of lateral variation on the lateral extent of the doping region can be better compensated for with a smaller difference between the lateral dimensions of the implantation windows.

[0043] The doping region can extend to the surface of the semiconductor substrate or be buried within the semiconductor substrate. For example, a minimum vertical distance between a boundary of the doping region (e.g., a pn junction to an adjacent doping region) and the front surface of the semiconductor substrate can be at least 200 nm (or at least 300 nm or at least 400 nm) and / or at most 600 nm (or at most 500 nm). For example, a maximum vertical distance between the boundary of the doped section of the doping region and the front surface of the semiconductor substrate is at most 2.5 µm (or at most 2 µm or at most 1.5 µm).

[0044] The front side of the semiconductor substrate can be used to implement more sophisticated and complex structures than the back side, because process parameters (e.g., temperature) and handling may be limited on the back side, for example, if structures are already formed on one side of the semiconductor substrate. For instance, the vertical dimension or vertical distance and thickness of layers can be measured orthogonally to the front surface of the semiconductor substrate, while lateral direction and lateral dimensions can be measured parallel to the front surface.

[0045] For example, a scattering layer can be positioned within the first implantation window during dopant implantation through the first implantation window. The scattering layer thickness can be less than the mask layer thickness; for example, the scattering layer thickness can be at most 70% (or at most 50% or at most 20%) of the mask layer thickness. The scattering layer can either include an oxide layer or consist entirely of one. Alternatively, the implantation window can be a region of the semiconductor substrate exposed by the mask layer.

[0046] Procedure 100 may further include removal of the mask layer after implantation of the dopants through the second implantation window. For example, the mask layer may be removed after a final implantation process performed to form the doping region.

[0047] For example, Method 100 may further include removing a surface layer of the semiconductor substrate after implantation of dopants through the second implantation window. The surface layer may be removed after removal of the mask layer. Alternatively, the surface layer may be removed before removal of the mask layer, for example, to facilitate removal of the surface layer. The surface layer may be a vertical layer of the semiconductor substrate at the front face of the semiconductor substrate. The surface layer may have a thickness of at most 30 nm (or at most 50 nm, 70 nm, or 100 nm) and / or at least 200 nm (or at least 150 nm or 100 nm). Removing the surface layer may result in a more uniform doping region; for example, uneven portions of the vertical boundary of the doping region may be removed.

[0048] The first implantation energy can differ from the second implantation energy by at least 30 keV (or at least 50 keV, at least 100 keV, or at least 200 keV) and / or by at most 1.8 MeV (or at most 1.5 MeV, at most 1.0 MeV, or at most 0.5 MeV). For example, if multiple implantation processes are used, the implantation energy of the first implantation process (e.g., performed after mask layer deployment) can differ by at least 0.2 MeV (or at least 0.5 MeV) and / or by at most 2 MeV from the implantation energy of the last implantation process (e.g., before mask layer removal).

[0049] According to at least one example of the method, the doping region is at least one of the following regions of a semiconductor device (in particular a transistor or a diode) or it consists of at least one of the following regions of a semiconductor device: an anode region, a cathode region, a base region, an emitter region, a source region, a drain region, a collector region, a body region, a gate region, a current propagation region, a shielding region, and an edge termination region.

[0050] Furthermore, the doping region can be at least part of a superjunction structure of a semiconductor device, in particular a transistor. The superjunction structure can be encompassed by a drift region of the semiconductor device. The drift region can be n-doped, and the superjunction structure can be p-doped. The superjunction structure can, for example, include at least one p-pillar.

[0051] In general, the fabrication of doping regions can comprise the following steps: (a) epitaxial growth of at least a portion of the semiconductor substrate, (b) formation of a doping region using the method described herein (in particular with at least two implantation processes), and (c) removal of the mask layer from the portion of the semiconductor substrate. At least some of steps (a) to (c) can then be repeated. For example, another portion of the semiconductor substrate can be epitaxially grown onto the first portion, and further implantation processes can follow. Using such a method, a deep doping region, e.g., a superjunction structure, can be formed in the semiconductor substrate.

[0052] For example, the doping region can be an anode region of a diode and / or a cathode region of a diode. The doping region can be a base region of a transistor and / or an emitter region of a transistor and / or a source region of a transistor and / or a drain region of a transistor. For example, a metal-oxide-semiconductor field-effect transistor (MOSFET) can be formed using Method 100, which has six implantation processes.

[0053] The semiconductor device to be formed can be a field-effect transistor, e.g., a metal-oxide-semiconductor field-effect transistor (MOSFET), or an insulated-gate bipolar transistor (IGBT). For example, the proposed method 100 can be used to form a semiconductor device or a wide-bandgap semiconductor device comprising at least one transistor or transistor assembly, for example, a MOSFET and / or an IGBT. A gate of the transistor can be formed by a gate insulating layer and a gate electrode. The gate can be positioned in a gate trench extending into the semiconductor substrate or can be positioned on a lateral surface of the semiconductor substrate. For example, the semiconductor substrate can comprise one or more source regions, one or more body regions, and a drift region of the transistor assembly.The one or more source regions and the drift region can each have the same conductivity type. The one or more body regions can each have the same conductivity type, which is opposite to the conductivity type of the source regions or the drift region. The one or more source regions and the drift region can each be n-type. The one or more body regions can be p-type. Furthermore, the semiconductor substrate may include a diode region, which can have the same conductivity type as the body region, and / or a current propagation region, which can have the same conductivity type as the drift region and / or the source region. The gate insulating layer can be directly adjacent to the semiconductor substrate.In particular, it is possible that the gate insulating layer is directly adjacent to regions of the semiconductor substrate that have a different conductivity type, for example, the source region, the drift region, the body region, the current propagation region and / or the diode region.

[0054] The first conductivity type can be p-doping (e.g., caused by the introduction of aluminum ions or boron ions) or n-doping (e.g., caused by the introduction of nitrogen ions, phosphorus ions, or arsenic ions).

[0055] The transistor arrangement can be a vertical transistor structure that conducts current between a front surface of the semiconductor substrate and a back surface of the semiconductor substrate. For example, the transistor arrangement of the semiconductor device can include multiple source doped regions connected by a source wiring structure, multiple gate electrodes or a gate electrode grid connected by a gate wiring structure, and a back-drain metallization.

[0056] For example, the semiconductor substrate can be either a semiconductor base substrate, a semiconductor base substrate with a semiconductor epitaxial layer grown on the semiconductor base substrate, or a semiconductor epitaxial layer. In one example, the semiconductor substrate can be a semiconductor wafer or a semiconductor die.

[0057] For example, the semiconductor substrate can be a wide-bandgap semiconductor substrate with a bandgap greater than that of silicon (1.1 eV). Specifically, the wide-bandgap semiconductor substrate has a bandgap greater than 2 eV, for example, greater than 3 eV. For example, the wide-bandgap semiconductor substrate can be a silicon carbide (SiC) substrate, diamond (C), or a gallium nitride (GaN) semiconductor substrate.

[0058] The semiconductor device to be formed can be a power semiconductor device. A power semiconductor device or an electrical structure (e.g., transistor array of the semiconductor device and / or diode array of the semiconductor device) of the power semiconductor device can, for example, have a breakdown voltage or reverse voltage of more than 10 V (e.g., a breakdown voltage of 10 V, 20 V, or 50 V), more than 100 V (e.g., a breakdown voltage of 200 V, 300 V, 400 V, or 500 V), more than 500 V (e.g., a breakdown voltage of 600 V, 700 V, 800 V, or 1 kV), or more than 1 kV (e.g., a breakdown voltage of 1.2 kV, 1.5 kV, 1.7 kV, 2 kV, 3.3 kV, or 6.5 kV).

[0059] Fig. Figure 2 shows a flowchart of a process 200 for forming a semiconductor device. The process 200 can include forming at least two mask layers on a semiconductor substrate. For example, a first mask layer can be formed on the semiconductor substrate 210. The first mask layer can include a first implantation window, for example, of a first lateral dimension.

[0060] The method 200 can include the implantation 220 of dopants into the semiconductor substrate with a first implantation energy. The dopants can be implanted through the first implantation window 220 while the mask layer is positioned on the semiconductor substrate, e.g., to form a first section of a doping region of the semiconductor substrate.

[0061] A second mask layer can be formed on the semiconductor substrate 230. For example, the second mask layer can include a second implantation window that differs from the first implantation window. For example, the second implantation window can be larger than the first implantation window. It may be possible to change the mask layer after the implantation of dopants 220. For example, the mask layer encompassing the first implantation window can be removed after the implantation of dopants 220, and the second mask layer, e.g., a different mask layer encompassing the second implantation window, can be formed on the semiconductor substrate 230 such that a lateral area of ​​the second implantation window covers an area of ​​the former first implantation window.For example, the first implantation window and the second implantation window can have the same central position on the semiconductor substrate.

[0062] The method 200 can further include the implantation 240 of dopants into the semiconductor substrate using a second implantation energy. The dopants can be implanted through the second implantation window 240 while the second mask layer is positioned on the semiconductor substrate to form a second section of the doping region of the semiconductor substrate.

[0063] For example, the difference between a lateral dimension of the second implantation window and a lateral dimension of the first implantation window can be selected based on a difference between the second and first implantation energies. The difference can be chosen such that the maximum lateral dimension of the first section differs from the maximum lateral dimension of the second section by less than 5%. The implantation windows can be selected according to the implantation energies used, for example, to reduce the effect of lateral scatter on the lateral extent of the doping region.

[0064] For example, multiple doping regions can be formed, e.g., by alternating with the formation of corresponding mask layers with appropriate implantation windows. To form the entire doping region, at least two and / or at most seven different implantation processes can be performed using appropriate mask layers with different implantation windows and different implantation energies. Using Method 200, a semiconductor device can be formed that has at least one doping region with a more uniform vertical boundary.

[0065] Further details and aspects are mentioned in connection with the exemplary embodiments described above or below. Fig. The embodiments shown in Figure 2 may have one or more optional additional features corresponding to one or more aspects mentioned in connection with the proposed concept or one or more embodiments described above or below (e.g., Fig. 1 or 3-7).

[0066] Fig. Figure 3 shows a schematic cross-section of a semiconductor device 300 with a doping region 320. The doping region 320 may have been formed by a method described herein. This means that all features described in connection with examples of the method may also be disclosed for the semiconductor device 300, and vice versa.

[0067] The semiconductor device 300 can comprise a semiconductor substrate 310. The doping region 320 can be positioned within the semiconductor substrate 310. A vertical extent 330 of a vertical section of the doping region 320 can be at least 200 nm (or at least 350 nm, at least 500 nm, or at least 750 nm) and / or at most 1200 nm (or at most 900 nm, at most 600 nm, or at most 400 nm). A minimum lateral dimension 340 of the doping region 320 within the vertical section of the doping region 320 in a vertical cross-sectional area of ​​the doping region 320 can be at least 80% (or at least 90%, or at least 95%) and / or at most 98% (or at most 95%) of an average lateral dimension within the vertical section of the doping region 320.A maximum lateral dimension 350 of the doping region 320 within the vertical section of the doping region 320 can be at most 120% (or at most 110%, or at most 105%) and / or at least 102% (or at least 105%) of the average lateral dimension of the doping region 320 within the vertical section of the doping region 320.

[0068] For example, the difference between the maximum lateral dimension and the minimum lateral dimension of the doping region can be at most 100 nm (or at most 50 nm, at most 30 nm, at most 20 nm or at most 10 nm).

[0069] The vertical boundary of doping region 320 can be more uniform, e.g., compared to the vertical boundaries of other doping regions. Doping region 320 can be formed by multiple implantation processes, while, for example, an implantation mask layer is fitted between implantation processes. Doping region 320 can comprise multiple doping sections of similar lateral dimensions, resulting in reduced variation in the lateral extent of doping region 320, for example, within the vertical section. The lateral, uniform doping region 320 can be positioned laterally close to another doping region, e.g., closer compared to other doping regions, and the lateral size of a semiconductor device encompassing doping region 320 can be reduced.

[0070] For example, the semiconductor device 300 can comprise a plurality of doping regions 320 within a semiconductor substrate, wherein the conductivity of the doping regions 320 can be opposite to the conductivity of the semiconductor substrate. For example, a lateral dimension of the doping regions can be at least 0.5 µm (or at least 1 µm) and / or at most 2 µm (or at most 1.5 µm). A lateral distance between any two of the plurality of doping regions can, for example, be at least 0.5 µm (or at least 1 µm) and / or at most 2 µm (or at most 1.5 µm). By providing doping regions with more uniform vertical boundaries, the distance between the doping regions within the semiconductor device can be reduced.

[0071] For example, the semiconductor substrate 310 of the semiconductor device can be a wide bandgap semiconductor substrate, e.g. a silicon carbide substrate.

[0072] Further details and aspects are mentioned in connection with the exemplary embodiments described above or below. Fig. The three embodiments shown may have one or more optional additional features corresponding to one or more aspects mentioned in connection with the proposed concept or one or more embodiments described above or below (e.g. Fig. 1-2 or 4-7).

[0073] Fig. Figure 4 shows a schematic cross-section of a semiconductor device 400 with a tapered lateral extent of a doping region 420 of the semiconductor device. The semiconductor device 400 can be a silicon carbide (SiC) semiconductor device with a SiC semiconductor substrate or a SiC semiconductor body, for example. A second lateral extent 450 of the doping region 420 may, for example, differ from a first lateral extent 440 of the doping region 420 by more than 10%. For example, a mask layer 430 (e.g., a resist mask) may not have been fitted during the implantation processes to form the doping region 420, so that the lateral profile of the doping region 420 may be relatively uneven or irregular. The doping region 420 may, for example, be formed by triple implantation via the mask layer 430.Lateral dispersion is schematically represented by the increasing lateral extent of the doping region with increasing implantation depth or implantation dose, for example.

[0074] Fig. Figures 5a-c show an example of creating a doping region using back-etching of an implantation mask (which may correspond to the mask layer described herein). By adjusting the implantation mask, deviations in the lateral extent of the doping region can be reduced.

[0075] For example, by implanting dopants through an implantation window of an implantation mask 510 into a semiconductor substrate 500, e.g. a SiC semiconductor body, a first doping section 520 (shown in Fig. 5a) of a doping region. To form the first doping section 520, a first implantation energy and an implantation window of a first lateral dimension 522 can be used. The first doping section 520 can have a first lateral extent 524. The first lateral extent 524 can be an average lateral extent of the first doping section 520. For example, the implantation mask 510 can have a thickness sufficient to provide an adequate span for subsequent re-etching.

[0076] Fig. Figure 5b shows the semiconductor substrate 500 after the formation of a second doping region 530. The second doping region 530 can be formed using a second implantation energy that is lower than the first implantation energy. The distance from the second doping region 530 to a front surface of the semiconductor substrate 500 can be less than the distance from the first doping region 520 to the front surface of the semiconductor substrate 500. The lateral extent (e.g., the average lateral extent) of the second doping region 530 can differ from the first lateral extent 524 by less than 10% (or less than 5%). In other words, the first and second doping regions can have similar lateral extents.The similar lateral extent can be achieved by isotropic etching of the implantation mask 510 prior to the formation of the second doping section 530. By adapting the implantation mask, an implantation window of a second lateral dimension 532, which is larger than the first lateral dimension 522, can be provided, e.g., to compensate for lateral dispersion depending on the respective implantation energies.

[0077] For example, to form the doping region of the semiconductor substrate 500, a third doping section 540 (shown in Fig. 5c) with a third implantation energy lower than the second implantation energy through the implantation window of a third lateral dimension 542, which is larger than the second lateral dimension 532, into the semiconductor substrate 500. The doping region of the semiconductor substrate 500 can include the doping sections 520, 530, 540. For example, after removing the implantation mask (e.g., a resist mask), an upper SiC layer can be removed to obtain a quasi-cuboid typical implantation profile, e.g., of the doping region.

[0078] Further details and aspects are mentioned in connection with the exemplary embodiments described above or below. Fig. The embodiments shown in 5a-5c may have one or more optional additional features corresponding to one or more aspects mentioned in connection with the proposed concept or one or more embodiments described above or below (e.g. Fig. 1-4 or 6-7).

[0079] Fig. Figure 6 shows a schematic cross-section of a semiconductor device 600 comprising a transistor. The semiconductor device 600 can include a first electrode 602 and a second electrode 604. The first electrode 602 can be a source connection S of the semiconductor device 600, and the second electrode 604 can be a drain connection D of the semiconductor device 600. A drift structure 610 can be positioned between the electrodes, the drift structure 610 comprising a drift section 612 and a contact layer 614 that connects the drift section and the second electrode 604, for example. P-doped regions 616, 618 can be positioned between the n-doped drift section 612 and the first electrode 602, for example, shielding regions 616 and body regions 618. The p-doped regions 616, 618 can separate a source region 640 from the drift structure 610.A maximum doping concentration p12 within the shielding regions 616 can be higher, e.g. at least 2 times (or at least 5 times) higher than a maximum doping concentration p11 within the body regions 618.

[0080] For example, the p-doped body region 618 and the n-doped source region 640 could have been implanted using a method described herein, employing the same mask layer for implantation. At least two implantation processes can be used for this purpose. For example, the n-doped source region 640 can be implanted in a first implantation process, wherein dopants of a first conductivity type (here: n-type dopants) are implanted with a first implantation energy through a first implantation window. The p-doped body region 618 can be implanted in at least a second implantation process, wherein dopants of a second conductivity type (here: p-type dopants) are implanted with at least a second implantation energy through at least one corresponding second implantation window.

[0081] Transistor cells TC of the semiconductor device 600 can be provided along gate structures 620 with a gate electrode 622 and a gate dielectric 624, for example. The gate structures 620 can be trench-gate structures, e.g., a lateral extension of the gate structures 620 along a first direction can be greater than a lateral extension of the gate structures 620 along a second direction orthogonal to the first direction. For example, the gate structures 620 can be long trenches with a length of more than 100 µm, more than 1 mm, or up to 5 cm. A right sidewall 626 and a left sidewall 628 can be adjacent to p-doped regions of the semiconductor device 600. The transistor cell TC can include an intermediate layer 630, e.g., between the gate electrode 622 and the first electrode 602.

[0082] The source region 640 can be (e.g., highly) n-doped and positioned between the first electrode 602 and the body region 618. For example, the source region 640 can be adjacent to the left side wall 628 of the gate structure 620. For example, a highly n-doped section n + between the shielding region 616 and the first electrode 602, e.g. adjacent to the right side wall 626 of the gate structure 620. For example, a lateral extension of the highly n-doped section n + be lower than a lateral extension of the shielding region, e.g. the highly n-doped section n + may not extend to the source region 640. A transition pn1 indicates a pn transition from the body region 618 to the drift structure 610, and a transition pn2 indicates a pn transition from the body region 618 to the source region 640, for example.

[0083] For example, the shielding regions 616 and / or the body regions 618 can be protected by a proposed method (e.g., as in conjunction with Fig. 1, 2 or 5a-5c) are formed and / or they can be a suggested structure (e.g. as described in connection with Fig. 3 described) include.

[0084] Further details and aspects are mentioned in connection with the examples described above or below. The in Fig. The 6 examples shown may have one or more optional additional features corresponding to one or more aspects mentioned in connection with the proposed concept or one or more examples described above or below (e.g. Fig. 1-5c or 7).

[0085] Fig. Figure 7 shows a schematic cross-section of a semiconductor device 700 comprising a merged-PIN Schottky diode. The semiconductor device 700 can comprise a semiconductor substrate 710, comprising an n-doped cathode region 712 extending to a back surface of the semiconductor substrate 710, and p-doped anode regions 714 on a front surface of the semiconductor substrate 710, for example. A contact metallization 720 can be in contact with the p-doped anode regions 714 on the front surface. An ohmic contact can exist between the contact metallization 720 and the p-doped anode regions 714. Furthermore, a Schottky metallization layer 730 can be in contact with the n-doped cathode region 712 on the front surface of the semiconductor substrate between the p-doped anode regions 714. A Schottky contact can exist between the Schottky metallization layer 730 and the n-doped cathode region 712.A power metallization layer 740 can be positioned on the Schottky metallization layer 730. The contact metallization 720, the Schottky metallization layer 730, and the power metallization layer 740 can form an anode metallization within an active region 750 of the semiconductor device 700.

[0086] For example, the p-doped anode regions 714 can be modified by a proposed method (e.g., as in conjunction with Fig. 1, 2 or 5a-5c) are formed and / or they can be a suggested structure (e.g. as described in connection with Fig. 3 is described) include.

[0087] Further details and aspects are mentioned in connection with the examples described above or below. The in Fig. The 7 examples shown may have one or more optional additional features corresponding to one or more aspects mentioned in connection with the proposed concept or one or more examples described above or below (e.g. Fig. 1-6).

[0088] For example, when aluminum (Al) atoms are implanted into a SiC semiconductor substrate, lateral scattering (straggle) can increase with increasing implantation energy. A maximum lateral scatter at an implantation energy of 80 keV might be 35 nm, a maximum lateral scatter at an implantation energy of 200 keV might be 70 nm, a maximum lateral scatter at an implantation energy of 700 keV might be 180 nm, and a maximum lateral scatter at an implantation energy of 1800 keV might be 300 nm, for example. The maximum lateral scatter can be calculated, for example, using Transport of Ions in Matter (TRIM) simulations. The implantation window can then be adjusted based on the calculated lateral scatter, for example.

[0089] One example involves laterally sharpening the implantation profile in SiC by subsequent etching of the mask layer (e.g., a resist mask). Etching the mask layer can prevent an inhomogeneous profile, and consequently, an inhomogeneous extent of the implantation profile may not need to be accommodated in the layout.

[0090] With some implantation concepts, the lateral extent can depend on the implantation energies (e.g., dopant depths) and may vary. For example, inhomogeneous potential conditions can occur along the implantation pathways when using some concepts. For instance, current filamentation can occur with some concepts, e.g., in the case of horizontal current flow, because the cross-section can vary due to the different dopant extent.

[0091] For example, the semiconductor device could be a SiC Schottky diode. Fabrication of the semiconductor device could involve, for example, triple ion implantation in a cell array. After completion of a mask layer, the deepest implantation can occur. The average lateral scattering can be known, for example, from TRIM calculations. The mask layer can be etched back by the calculated amount. For example, the mask layer might be large enough that the resulting edge rounding might not affect the implantation profile in the semiconductor. For example, a second implantation can take place. Here, too, lateral scattering can occur, which, due to the reduced ion energy, may exhibit a reduced extent. The resist can be etched back by this extent to complete the implantation in a third implantation process, for example.In this way, a more homogeneous implantation profile can be achieved, with regard to an average extent of lateral dispersion.

[0092] Alternatively, for example, a first dopant (e.g., p-doping) can be introduced in its entirety, followed by dry chemical etching of the structure. A second dopant (e.g., n-doping) can then be grown over the etched trenches.

[0093] The aspects and features mentioned and described along with one or more of the previously detailed examples and figures can also be combined with one or more of the other examples to replace an identical feature of the other example or to additionally introduce the feature into the other example.

[0094] The description and drawings illustrate only the principles of the revelation. Furthermore, all examples presented here are expressly intended for illustrative purposes only, to assist the reader in understanding the principles of the revelation and the concepts contributed by the inventor(s) to the advancement of technology.

[0095] It is understood that the disclosure of multiple actions, processes, operations, steps, or functions in the description or in the claims is not to be construed as existing within a specific sequence, unless explicitly or implicitly stated otherwise, for example, for technical reasons. Therefore, the disclosure of multiple steps or functions does not restrict them to a particular sequence unless these steps or functions are not interchangeable for technical reasons. Furthermore, in some examples, a single step, function, process, or operation may include and / or be broken down into multiple sub-steps, sub-functions, sub-processes, or sub-operations. Such sub-steps may be included and form part of the disclosure of that single step unless explicitly excluded.

Claims

[1] A method (100) for forming a semiconductor device (300), comprising the method (100): Forming (110) a mask layer having a first implantation window on a semiconductor substrate (310); Implanting (120) dopants with a first implantation energy into the semiconductor substrate (310) through the first implantation window to form a first section of a doping region (320) of the semiconductor device (300); Adjusting (130) the mask layer to form a second implantation window of the mask layer; and Implanting (140) dopants with a second implantation energy into the semiconductor substrate (310) through the second implantation window to form a second section of the doping region (320) of the semiconductor device (300), wherein the second implantation energy differs from the first implantation energy, and wherein a lateral dimension of the first implantation window differs from a lateral dimension of the second implantation window, wherein, taking into account the implantation energy-dependent lateral scatter, a difference between the lateral dimension of the second implantation window and the lateral dimension of the first implantation window depends on a difference between the second implantation energy and the first implantation energy, wherein a maximum lateral dimension of the first section of the doping region (320) differs from a maximum lateral dimension of the second section of the doping region (320) by less than 5% of the maximum lateral dimension of the second section of the doping region (320). [2] The method (100) according to claim 1, wherein the second implantation energy is lower than the first implantation energy, and / or wherein the lateral dimension of the second implantation window is larger than the lateral dimension of the first implantation window. [3] The method (100) according to claim 1, wherein the second implantation energy is higher than the first implantation energy, and / or wherein the lateral dimension of the second implantation window is smaller than the lateral dimension of the first implantation window. [4] The method (100) according to one of the preceding claims, wherein the dopants of the first implantation energy and the dopants of the second implantation energy are of a first conductivity type. [5] The method (100) according to one of the preceding claims, wherein the difference between the lateral dimension of the first implantation window and the lateral dimension of the second implantation window is at least 20 nm and at most 200 nm. [6] The method (100) according to one of the preceding claims, wherein a lateral region of the second implantation window has a lateral region of the first implantation window. [7] The method (100) according to claim 1 or 2, wherein an adjustment (130) of the mask layer comprises etching the mask layer to increase the lateral dimension of the first implantation window in order to obtain the second implantation window. [8] The method (100) according to claim 1 or 3, wherein an adjustment (130) of the mask layer comprises forming a spacer at an edge of the first implantation window to reduce the lateral dimension of the first implantation window in order to obtain the second implantation window. [9] The method (100) according to one of the preceding claims, wherein a scattering layer is positioned within the first implantation window during the implantation of the dopants through the first implantation window. [10] The method (100) according to any one of the preceding claims, further comprising Adjusting the mask layer to form a third implantation window of the mask layer; and Implanting dopants with a third implantation energy into the semiconductor substrate through the third implantation window to form a third section of the doping region (320) of the semiconductor device (300), wherein the third implantation energy differs from the first implantation energy and the second implantation energy, and wherein a lateral dimension of the third implantation window differs from a lateral dimension of the first implantation window and the second implantation window. [11] The method (100) according to one of the preceding claims, wherein the mask layer has a thickness of at least 1.5 µm before the mask layer is adapted to obtain the second implantation window. [12] The method (100) according to one of the preceding claims, wherein the first implantation energy differs from the second implantation energy by at least 50 keV and at most 2.5 MeV. [13] The method (100) according to any one of the preceding claims, wherein the semiconductor substrate (310) is a silicon carbide substrate, a gallium arsenide substrate or a gallium nitride substrate. [14] The method (100) according to any one of the preceding claims, wherein the doping region (320) is at least one of or part of the following: an anode region of a semiconductor device (300), a cathode region of a semiconductor device (300), a base region of a semiconductor device (300), an emitter region of a semiconductor device (300), a source region of a semiconductor device (300), a drain region of a semiconductor device (300), a collector region of a semiconductor device (300), a body region of a semiconductor device (300), a gate region of a semiconductor device (300), a current propagation region of a semiconductor device (300), a shielding region of a semiconductor device (300) and an edge termination region of a semiconductor device (300). [15] A method (200) for forming a semiconductor device (300), comprising the method (200): Forming (210) a first mask layer on a semiconductor substrate (310), wherein the first mask layer comprises a first implantation window; Implanting (220) dopants with a first implantation energy into the semiconductor substrate (310) through the first implantation window to form a first section of a doping region (320) of the semiconductor substrate (310); Forming (230) a second mask layer on the semiconductor substrate (310), wherein the second mask layer comprises a second implantation window; and Implanting (240) dopants into the semiconductor substrate (310) through the second implantation window with a second implantation energy to form a second section of the doping region (320) of the semiconductor substrate (310), wherein a difference between a lateral dimension of the second implantation window and a lateral dimension of the first implantation window is selected depending on a difference between the second implantation energy and the first implantation energy, taking into account the implantation energy-dependent lateral scatter, wherein a maximum lateral dimension of the first section of the doping region (320) differs from a maximum lateral dimension of the second section of the doping region (320) by less than 5% of the maximum lateral dimension of the second section of the doping region (320).

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