PROCESSING METHOD FOR A WAFER

Abstract

A processing method for a wafer (11) in which a front surface (11a) of the wafer, on which a component (15) is formed in each of the chip regions divided by several intersecting division lines (13) formed in an intersecting relationship on the front surface (11a) of the wafer (11), is sealed with a sealing element (23) and several elevations (25) are individually formed in the chip regions of the sealing element (23), wherein the processing method comprises: an alignment step for acquiring an image of a front surface (11a) of the wafer (11) by the sealing element (23) by an infrared imaging means (14) of the front surface (11a) of the wafer (11) to detect alignment marks, and detecting a planned parting line (13) to be laser processed, based on the alignment marks; and a division step for irradiating, after the alignment step has been performed, a laser beam (LB) of a wavelength that is absorbed by the wafer (11) and the sealing element (23), along the planned division line (13) from the front surface (11a) of the wafer (11) to divide the wafer by an ablation process into individual component chips (31) that are sealed with the sealing element (23) on their front surface (11a); wherein the sealing element (23) contains soot of 0.1 to 0.2% by mass percent and has such transparency that infrared rays, which are to be received by the infrared imaging element (14), pass through the sealing element (23).

Description

Technical area

[0001] The present invention relates to a processing method for a WL-CSP wafer. Description of the state of the art

[0002] A WL-CSP (Wafer-Level Chip Size Package) wafer is a technology for sealing a wiring layer and electrodes (metal pins) while the WL-CSP wafer is in a wafer state, covering a front surface of the wafer with plastic, and dividing the wafer into components using a dicing blade or the like. Since the package size obtained by dicing the wafers is equal to the size of the semiconductor device chips, this technology is widely adopted for downsizing and weight reduction.

[0003] In a manufacturing process of the WL-CSP wafer, a wiring layer is formed on a device surface side of a device wafer on which a plurality of devices are formed, and metal pins connected to electrodes in devices are formed through the wiring layer, and then the metal pins and the devices are sealed with plastic.

[0004] Next, a sealing member is thinned so that the metal pins are exposed on the front surface of the sealing member. External terminals, called electrode bumps, are formed on one end surface of the metal pins. Afterward, the WL-CSP wafer is cut by a cutting device or the like to divide the WL-CSP wafer into individual CSPs.

[0005] To protect semiconductor devices from impact, moisture, or the like, it is important to seal the semiconductor devices with a sealing element. Typically, a sealing material is used as a sealing element by mixing a filler formed from SiC into epoxy resin. The thermal expansion coefficient of the sealing element is close to that of the semiconductor device chips, preventing damage to the packages during heating caused by a difference in thermal expansion coefficient.

[0006] A WL-CSP wafer is generally divided into individual CSPs using a slicing device. In this case, since a component used to detect a planned dividing line in the WL-CSP wafer is covered with plastic, a target pattern of the component cannot be detected from the front surface.

[0007] Therefore, alignment of the planned dividing line and the cutting blade must be performed by indexing the planned dividing line, setting the electrode bumps formed on the plastic of the WL-CSP wafer as a target, or by printing a target for alignment on the top surface side of the plastic.

[0008] However, the electrode bumps or the target printed on the plastic are not formed with high accuracy compared to the components, so there is a problem that the target has low accuracy as an alignment target. Similarly, in the case where a planned dividing line is indicated based on the electrode bumps or a printed target, there is a possibility that a cutting location is offset from the planned dividing line, resulting in a component portion being cut. Therefore, for example, Japanese Patent Application Laid-Open No. 2013-74021A has proposed a method according to which alignment is performed based on a pattern of the component wafer exposed at an external periphery of the wafer. JP 2016-15438 A relates to an alignment method. US 6 271 102 B1 relates to a method and system for dividing wafers. US 5 843 831 A relates to a wafer processing method. JP 2017-64 746 A relates to a laser processing apparatus and a laser processing method.

[0009] JP 2015- 28 980 A relates to a wafer processing method. PRESENTATION OF THE INVENTION

[0010] However, in general, a component accuracy at an outer periphery of the wafer is somewhat inaccurate, and if alignment is performed based on a pattern exposed at the outer periphery of the wafer, there is a possibility that the wafer is divided at a position offset from a planned dividing line, and moreover, depending on the wafer, a pattern of the component is not exposed at the outer periphery.

[0011] It is therefore an object of the present invention to provide a wafer processing method by which an alignment step can be performed by a sealing member covering the front surface of the wafer and containing soot.

[0012] In accordance with one aspect of the present invention, there is provided a wafer processing method, in which a front surface of the wafer, on which a component is formed in each chip region divided by a plurality of planned dividing lines formed in an intersecting relationship on the front surface of the wafer, is sealed with a sealing member, and a plurality of protrusions are individually formed in the chip regions of the sealing member, the processing method comprising an alignment step of capturing an image of a front surface side of the wafer through the sealing material with an infrared image pickup means from the front surface side of the wafer to detect alignment marks, and detecting a planned dividing line to be laser-processed based on the alignment marks, and a dividing step of irradiating,After the alignment step has been performed, a laser beam of a wavelength absorbed by the sealing member and the wafer is directed along the planned dividing line from the front surface of the wafer to divide the wafer into individual component chips, each sealed with the sealing member on its front surface, by ablation processing. The sealing member contains 0.1 to 0.2% by mass of carbon black and has a transparency such that infrared rays to be received by the infrared image pickup means pass through the sealing member.

[0013] Preferably, the infrared image pickup means used in the alignment step is an InGaAs image pickup element.

[0014] According to the wafer processing method of the present embodiment, the front surface of the wafer is sealed with the sealing member through which infrared rays to be received by the infrared image pickup means pass. The alignment marks formed on the wafer are detected by the sealing member with an infrared image pickup means, so that alignment can be performed based on the alignment marks. Therefore, the alignment step can be easily performed without removing the sealing member on the outer peripheral portion of the front surface of the wafer, as in the prior art.

[0015] Therefore, it is possible to irradiate the laser beam of a wavelength absorbed by the wafer and the sealing member along a planned dividing line from the front surface side of the wafer to divide the wafer into individual device chips by ablation processing.

[0016] The above and other objects, features and advantages of the present invention and the mode of carrying them out will become clearer and the invention itself best understood by studying the following description and the appended claims with reference to the attached figures which show a preferred embodiment of the invention. SHORT DESCRIPTION OF THE CHARACTERS Fig. 1A is an exploded perspective view of a WL-CSP wafer; Fig. 1B is a perspective view of the WL-CSP wafer; Fig. 2 is an enlarged sectional view of the WL-CSP wafer; Fig. 3 is a perspective view illustrating a manner in which the WL-CSP wafer is adhered to a dividing band whose outer peripheral portion is fixed to an annular frame; Fig. 4 is a sectional view illustrating an alignment step; Fig. 5A is a sectional view illustrating a formation step for a modified layer; Fig. 5B is an enlarged sectional view showing the division step. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0017] In the following, an embodiment of the present invention will be described in detail with reference to the figures. With reference to Fig. 1A shows an exploded perspective view of a WL-CSP wafer 27. In Fig. 1B is a perspective view of the WL-CSP wafer 27. As in Fig. 1A, devices 15 such as LSIs (large scale integrations) are formed in regions divided by a plurality of planned dividing lines (streets) 13 formed in a lattice pattern on a front surface side 11A of the device wafer 11.

[0018] The component wafer (hereinafter sometimes referred to simply as wafer) 11 is previously ground on a rear surface side 11b so that it is thinned to a predetermined thickness (approximately 100 to 200 µm). Thereafter, as shown in Fig. 2, a plurality of metal pins 21 electrically coupled to electrodes 17 in the devices 15 are formed, and then the front surface 11a of the wafer 11 is sealed with a sealing member 23 so that the metal pins 21 are embedded therein.

[0019] The sealing member 23 has a composition containing 10.3% epoxy resin or phenolic resin epoxy resin, 8.53% silica filler, 0.1 to 0.2% carbon black, and 4.2 to 4.3% other components by mass. Other components include, for example, metal hydroxide, antimony trioxide, silicon dioxide, or the like.

[0020] If the front surface 11a of the wafer 11 is covered and sealed with the sealing member 23 having such a composition as described above, the sealing member 23 has a black color resulting from the carbon black contained in a very small amount in the sealing material 23, and it is usually difficult to see the front surface 11a of the wafer 11 through the sealing member 23. Here, the reason why carbon black is mixed into the sealing member 23 is that it is mainly intended to prevent electrostatic destruction of a device 15, and a sealing material that does not contain carbon black is currently unavailable on the market.

[0021] As another embodiment, after a wiring layer is formed on the front surface 11a of the device wafer 11, metal pins 21 electrically coupled to the electrodes 17 in the devices 15 may be formed on the wiring layer.

[0022] Next, the sealing member 23 is thinned using a surface cutter (a surface planer) having a cutting tool formed from single-crystal diamond or a grinding device called a grinder. After the sealing member 23 is thinned, an end surface of the metal pin 21 is exposed, for example, by plasma etching.

[0023] Then, metal bumps 25 made of solder or the like are formed on the exposed end surfaces of the metal pins 21 by a well-known method to complete the WL-CSP wafer 27. In this WL-CSP wafer 27 of the present embodiment, the thickness of the sealing member 23 is approximately 100 μm.

[0024] When the WL-CSP wafer 27 is laser processed by a laser processing apparatus, the WL-CSP wafer 27 is preferably adhered to a dividing tape T as an adhesive tape, the outer peripheral portion of which is fixed to an annular frame F as shown in Fig. 3. Consequently, the WL-CSP wafer 27 is placed in a state supported on the annular frame F by the dividing tape T. However, when the WL-CSP wafer 27 is to be laser processed by the laser processing apparatus, a configuration may be employed in which an adhesion-promoting tape is attached to the rear surface of the WL-CSP wafer 27 without using the annular frame F.

[0025] In the wafer processing method of the present invention, an alignment step of capturing an image of the front surface 11a of the device wafer 11 through the sealing member 23 from a front surface side of the WL-CSP wafer 27 by an infrared image pickup means, detecting at least two alignment marks such as target patterns formed on a front surface of the device wafer 11, and then detecting a planned dividing line 13 to be processed based on the alignment marks is performed.

[0026] This alignment step is described in detail with reference to Fig. 4. In the alignment step, the WL-CSP wafer 27 is sucked and held by a chuck table 10 of the laser processing apparatus with the dividing tape T interposed therebetween, so that the sealing member 23 sealing the front surface 11a of the device wafer 11 is exposed upward, as shown in Fig. 4. Then, the ring-shaped frame 11 is clamped and fixed by a clamp 12.

[0027] Then, an image of the front surface 11a of the device wafer 11 is captured through the sealing member 23 of the WL-CSP wafer 27 by an infrared image pickup element of an image pickup unit 14 of the laser processing apparatus, not shown. Since the sealing member 23 is formed of a sealing material through which infrared rays to be captured by the infrared pickup element of the image pickup unit 14 can pass, at least two alignment marks such as target patterns formed on the front surface 1a of the device wafer 11 can be detected by the infrared image pickup element. Preferably, an InGaAs image pickup element having high sensitivity is adopted as the infrared image pickup element. Preferably, the image pickup unit 14 includes an exposure unit capable of adjusting the exposure time or the like.

[0028] Then, the chuck table 10 is rotated by θ degrees so that a straight line connecting the alignment marks is positioned parallel to a machining feed direction, and the chuck table 10 is further moved in a direction orthogonal to the machining feed direction by a distance equal to a distance between the alignment marks and the center of the planned parting lines 13 to detect the planned parting line 13 to be laser machined.

[0029] After the alignment step is performed, a laser beam LB of a wavelength (for example, 355 nm) absorbed by the device wafer 11 and the sealing member 23 is irradiated from a laser head (condenser) 16 along the planned dividing line 13 on the front surface side of the WL-CSP wafer to form such a laser-machined groove 29 by ablation processing, as shown in Fig.5B, and the WL-CSP wafer 27 is divided into individual device chips (CSPs) 31 sealed with the sealing member 23.

[0030] After this dividing step has been successively performed along the planned dividing lines 13 extending in a first direction, the chuck table 10 is rotated by 90°, and then the dividing step is successively performed along the planned dividing lines 13 extending in a second direction orthogonal to the first direction. This allows the WL-CSP wafer 27 to be divided into individual component chips (CSPs) 31 sealed with the sealing element 23.

[0031] Each component chip (CSP) 31 manufactured in this manner is flipped from top to bottom and can be attached to a motherboard by flip-chip bonding to connect the bumps 25 to conductive pads on the motherboard.

Claims

[1] A processing method for a wafer (11), in which a front surface (11a) of the wafer, on which a component (15) is formed in each of the chip regions divided by a plurality of intersecting dividing lines (13) formed in an intersecting relationship on the front surface (11a) of the wafer (11), is sealed with a sealing member (23), and a plurality of protrusions (25) are individually formed in the chip regions of the sealing member (23), the processing method comprising: an alignment step of capturing an image of a front surface side (11a) of the wafer (11) through the sealing member (23) by an infrared image pickup means (14) from the front surface side (11a) of the wafer (11) to detect alignment marks, and detecting a planned dividing line (13) to be laser-machined based on the alignment marks; and a dividing step of irradiating, after the alignment step has been performed, a laser beam (LB) of a wavelength absorbed by the wafer (11) and the sealing member (23) along the planned dividing line (13) from the front surface side (11a) of the wafer (11) to divide the wafer by ablation processing into individual component chips (31) sealed with the sealing member (23) on their front surface (11a); wherein the sealing element (23) contains carbon black of 0.1 to 0.2% by mass and has a transparency such that infrared rays to be received by the infrared image recording element (14) pass through the sealing element (23). [2] A processing method for a wafer (11) according to claim 1, wherein the infrared image pickup means (14) used in the alignment step includes an InGaAs image pickup element.

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