METHOD FOR PRODUCEING SOURCE AND DRAIN AREAS BY METHOD OF ANNEALING AND ASSOCIATED SEMICONDUCTOR DEVICE

Abstract

A method comprising: forming a gate stack (30) on a first section of a semiconductor substrate (20), removing a second section of the semiconductor substrate (20) on one side of the gate stack (30) to form a depression (40), growing a semiconductor region (42) out of the depression (40), implanting a foreign material into the semiconductor region (42), and performing a melting annealing process (64) on the semiconductor region (42), wherein at least one section of the semiconductor region (42) is melted during the melting annealing process (64), wherein after performing the melting annealing process (64) solidification of the molten section of the semiconductor region (42) begins from a bottom side of the molten section of the semiconductor region (42) and proceeds towards a top side of the molten section of the semiconductor region (42).

Description

BACKGROUNDIn integrated circuits, source / drain contact terminals are used for electrically coupling to the source and drain regions, which may be formed by epitaxy. The source / drain contact terminals are typically connected to source / drain silicide regions. The formation of the source / drain silicide regions includes forming contact openings by etching dielectric layers covering the source / drain regions, wherein the etched dielectric layers may include a silicon nitride layer and an oxide layer over the silicon nitride layer. The source / drain regions are thus exposed to the contact openings. An additional silicon nitride layer is conformally formed to cover the sidewalls and bottoms of the contact openings. A second etching step is then performed to ablate the bottom portions of the silicon nitride layer to expose the source / drain epitaxial regions. A metal layer is then formed to extend into the contact openings, and an anneal process is performed to react the metal layer with the source / drain regions, thereby forming source / drain silicide regions. The remaining portions of the contact openings are then filled with one or more metals to form the source / drain contact terminals.The prior art relating to the subject matter of the invention can be found, for example, in U.S. Pat. No. 2018, / 0 190 653 A1, U.S. Pat. No. 2015 / 0 270 342 A1 and U.S. Pat. No. 2017) / 0 256 613 A1.The invention provides a method according to claim 1, a method according to claim 10 and an apparatus according to claim 16. Embodiments are set forth in the dependent claims.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure will be best understood from a review of the following detailed description and the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not to scale. The dimensions of the various features may be arbitrarily increased or decreased for clarity. FIGS. 1-4, 5A, 5B, 6A, 6B, 7, 8, 9A, 9B, 9C, 10-13, 14A, 14B, 14C, and 15 are perspective and cross-sectional views of intermediate stages in forming a fin field effect transistor (FinFET), in accordance with some embodiments. FIGS. 16A, 16B, 16C, and 16D illustrate a sequence of solidifying a molten silicon-germanium region, in accordance with some embodiments. FIG. 17 illustrates germanium percentages as a function of depths in a silicon-germanium region deposited according to some embodiments. FIG. 18 illustrates comparison of germanium percentages, in accordance with some embodiments. FIG. 19 illustrates comparison of boron concentrations, in accordance with some embodiments. FIG. 20 illustrates a cross-sectional view of a FinFET formed on a crown-shaped semiconductor region, in accordance with some embodiments. FIG. 21 illustrates a process flow for forming a FinFET, in accordance with some embodiments.DETAILED DESCRIPTIONThe following disclosure provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and arrangements will be described below to simplify the present disclosure. These are of course merely examples which are to be understood as non-limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed that are between the first and second features such that the first and second features may not be in direct contact. In addition, in the present disclosure, reference numerals and / or letters may be repeated in the various examples. This repetition is for purposes of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.Furthermore, terms of spatial relationships such as "underlying", "under(half)", "lower / r / s", "overlying", "upper / r / s" are used herein, where appropriate for purposes of simplified description, to describe a relationship of an element or feature to one or more other elements or features as illustrated in the figures. The terms of spatial relationships are intended to also include other orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in other orientations) and the spatial relationship descriptions used herein interpreted accordingly in an analogous manner.According to various embodiments, transistors and the methods of forming the same are provided. The intermediate stages of the formation of the transistors are illustrated in accordance with some embodiments. Some variations of some embodiments are also addressed. In the various views and illustrative embodiments, like reference numerals designate like elements. In the illustrated embodiments, the concept of the present disclosure is explained using the example of forming fin field effect transistors (FinFETs). However, the concept of the present disclosure may also be adopted for planar-shaped transistors. In accordance with some embodiments of the present disclosure, a melt anneal is used to anneal the source and drain regions of the FinFETs, melting at least some portions of the source / drain regions. Due to the melt-annealing process, the interface between the source / drain regions and the silicide regions overlying them is curved, so that the contact resistance to the source and drain regions is reduced.FIGS. 1 to 4, 5A, 5B, 6A, 6B, 7, 8, 9A, 9B, 9C, 10 to 13, 14A, 14B, 14C, and 15 illustrate the cross-sectional views and perspective views of intermediate stages in forming a fin field effect transistor (FinFET) according to some embodiments of the present embodiment. The processes shown in these figures are also schematically depicted in process flow 200 shown in FIG. 21.FIG. 1 illustrates a perspective view of a starting structure formed on a wafer 10. The wafer 10 includes a substrate 20. the substrate 20 may be a semiconductor substrate, which may be a silicon substrate, a silicon-germanium substrate, or a substrate formed of other semiconductor materials. The substrate 20 may be doped with a p- or n-type impurity. Isolation regions 22, such as shallow trench isolation (STI) regions, may be formed to extend into the substrate 20 from a top surface of the substrate 20. The portions of substrate 20 between adjacent STI regions 22 are referred to as semiconductor strips 24. The top surfaces of the semiconductor strips 24 and the top surfaces of the STI regions 22 may be substantially level with each other, in accordance with some embodiments. According to some embodiments of the present disclosure, the semiconductor strips 24 are portions of the original substrate 20, such that the material of the semiconductor strips 24 is the same as that of the substrate 20. According to alternative embodiments of the present disclosure, semiconductor strips 24 are replacement strips formed by etching the portions of substrate 20 between STI regions 22 to form recesses and performing epitaxy to grow another semiconductor material in the recesses. Accordingly, the semiconductor strips 24 are formed of a semiconductor material different from that of the substrate 20. In some embodiments, the semiconductor strips 24 are formed of silicon germanium, silicon carbon, or a III-V compound semiconductor material.The STI regions 22 may include a liner oxide (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of the substrate 20. The liner oxide may also be a deposited silicon oxide layer, which may be formed, for example, by atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). The STI regions 22 may further include a dielectric material over the liner oxide, wherein the dielectric material may be formed by flowable chemical vapor deposition (FCVD), spin-on coating, or the like.Referring to FIG. 2, the STI regions 22 are recessed such that the top portions of the semiconductor strips 24 protrude higher than the top surfaces 22A of the remaining portions of the STI regions 22 to form protruding fins 24'. The corresponding process is illustrated as process 202 in process flow 200 shown in FIG. 21. The etching may be performed by a dry etching process using HF 3 and NH 3 as etching gases. Plasma may be generated during the etching process. Argon may also be included. In accordance with alternative embodiments of the present disclosure, the recessing of the STI regions 22 is performed by a wet etching process. The etching chemical may include, for example, HF.In the embodiments illustrated above, the fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby enabling the creation of patterns having, for example, smaller pitch widths than otherwise achievable using a simple direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed and the remaining spacers, or mandrels, may then be used to pattern the fins.Referring to FIG. 3, a dummy gate stack 30 is formed to extend on the top and sidewalls of the (protruding) fins 24'. The corresponding process is illustrated as process 204 in process flow 200 shown in FIG. 21. The dummy gate stacks 30 may include dummy gate dielectrics 32 and dummy gate electrodes 34 over the dummy gate dielectrics 32. Dummy gate electrodes 34 may be formed using polysilicon, for example, although other materials may be used. Each of the dummy gate stacks 30 may also include a hard mask layer 36 (or a plurality thereof) over the dummy gate electrodes 34. The hard mask layers 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride, or multilayers thereof. Dummy gate stacks 30 may cross a single or a plurality of protruding fins 24' and / or STI regions 22. The dummy gate stacks 30 also have longitudinal directions that are perpendicular to the longitudinal directions of the protruding fins 24'.Next, gate spacers 38 are formed on the sidewalls of the dummy gate stacks 30. According to some embodiments of the present disclosure, the gate spacers 38 are formed of one or more dielectric materials such as silicon nitride, silicon carbonitride, or the like, and may have a single-layer structure or a multilayer structure including a plurality of dielectric layers.An etching step is then performed to etch the portions of the protruding fins 24' not covered by the dummy gate stack 30 and the gate spacers 38, resulting in the structure shown in FIG. 4. The recessing may be anisotropic such that the portions of the fins 24' immediately below the dummy gate stacks 30 and the gate spacers 38 are protected and not etched. In accordance with some embodiments, the tops of the recessed semiconductor strips 24 may be lower than the tops 22A of the STI regions 22. The recesses 40 are located on the opposite sides of the dummy gate stacks 30.Next, a first epitaxial process is performed to form epitaxial portions 42A that are selectively grown out of the recesses 40, resulting in the structure in FIG. 5A. The epitaxial portions 42A may be the lower portions of the epitaxial regions 42. The corresponding process is illustrated as process 206 in process flow 200 shown in FIG. 21. According to some embodiments, epitaxial portions 42A may include silicon germanium or silicon. According to some embodiments of the present disclosure, a p-type impurity such as boron or indium or gallium is doped in situ into the epitaxial portions 42A in the course of epitaxy. After the epitaxial portions 42A completely fill the recesses 40, the epitaxial portions 42A begin to expand horizontally and facets may be formed. The adjacent epitaxial portions 42A start to be joined to each other. As a result, an integral epitaxial region 42A is formed, and the top surface of the integral epitaxial region 42A is corrugated. The epitaxial portions 42A are sometimes referred to as layer 1 (L 1) portions of the epitaxial regions 42.In accordance with some embodiments of the present disclosure, epitaxial portions 42A include silicon germanium having a first germanium atomic percent that may range between about 0 percent and about 40 percent. The germanium percentage may be constant or have a gradually increasing gradient from the bottom to the top of the epitaxy regions 42A. For example, FIG. 17 illustrates an example of the germanium percentages in the epitaxy regions 42 depending on the depth of the epitaxy regions 42. In FIG. 17, the x-axis represents the depth in the epitaxy regions 42, where the x-axis value zero corresponds to the tops of the epitaxy regions 42 (FIG. 6B ). In accordance with some embodiments of the present disclosure, the germanium percentage in epitaxial region 42 (as deposited and without post-anneal) is represented by line 150, which shows that the germanium has a constant atomic percentage in L 1 (and also in L 2 as discussed in the following paragraphs). According to alternative embodiments of the present disclosure, the germanium percentage in the epitaxial region 42 (as deposited and without post-anneal) is represented by line 152 which shows that upper portions of the L1 portions of the epitaxial regions 42 have gradually increased germanium percentages relative to the respective lower portions.FIG. 5B illustrates a cross-sectional view of the structure shown in FIG. 5A, the cross-sectional view being obtained from the vertical plane containing line 5B- 5B in FIG. 5A. In FIG. 5B, the position of the protruding fins 24' that is not in the plane shown is shown by dashed lines to illustrate the relative positions of the protruding fins 24' and epitaxial portions 42A, in accordance with some embodiments.As epitaxy proceeds, the epitaxial regions 42A grown out of adjacent recesses join each other to form an integral epitaxial region 42A. In this case, cavities (air gaps) 43 can be produced. According to some embodiments of the present disclosure, the formation of the epitaxial region 42A is completed when the top surface of the epitaxial region 42A is still corrugated. According to other embodiments of the present disclosure, the formation of the epitaxial region 42A is completed when the top surface of the epitaxial region 42A has become planar.FIG. 6A illustrates continued growth of epitaxy regions 42. The epitaxial regions 42 include upper portions 42B in addition to the lower portions 42A. The epitaxy regions 42B may include silicon germanium and may be optionally doped with a p-type impurity such as boron, indium, gallium, or the like during epitaxy. The upper portions 42B are referred to as the layer 2 (L2) portions of the epitaxial regions 42. According to some embodiments of the present disclosure, the upper portions 42B have a second germanium percentage that is higher than the first germanium percentage of the lower portions 42A. For example, the second germanium percentage may be in the range between about 40 percent and about 100 percent. The difference between the atomic percentages of the upper portions 42B and lower portions 42A may be greater than, for example, about 20 percent. The second germanium percentage may be constant or have a gradually increasing slope from the bottom to the top of the epitaxy regions 42B. For example, FIG. 17 illustrates an example of the percentages of epitaxial regions 42B, which shows that L2 portions 42B have gradually increased germanium percentages or a constant germanium percentage, in accordance with some embodiments of the present disclosure. The top surfaces of the upper portions 42B may be planar as shown in FIG. 6A. In this specification, the epitaxial regions 42 are alternatively referred to as source / drain regions 42.FIG. 6B illustrates a cross-sectional view of the structure shown in FIG. 6A, the cross-sectional view being obtained from the vertical plane containing line 6B- 6B in FIG. 6A. In FIG. 6B, the positions of the protruding fins 24' that are not in the plane shown are shown to illustrate the relative positions of the protruding fins 24' and epitaxial portions 42A and 42B, in accordance with some embodiments.FIG. 7 illustrates a perspective view of the structure after formation of a contact etch stop layer (CESL) 46 and an inter-layer dielectric (ILD) 48. The CESL 46 may be formed of silicon oxide, silicon nitride, silicon carbonitride, or the like, and may be formed by CVD, ALD, or the like. The ILD 48 may include a dielectric material that may be formed, for example, by FCVD, spin-on, CVD, or other deposition process. The ILD 48 may be formed of an oxygen-containing dielectric material that may be based on silicon oxide, such as tetraethylorthosilicate (TEOS) oxide, plasma CVD (PECVD) oxide (SiO 2), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like. A planarization process, such as a chemical mechanical polishing (CMP) process or a mechanical grinding process, may be performed to align the tops of the ILD 48, dummy gate stacks 30, and gate spacers 38 with each other.Next, the dummy gate stacks 30 including the hard mask layers 36, the dummy gate electrodes 34, and the dummy gate dielectrics 32 are replaced with replacement gate stacks 56 including metal gates 54 and gate dielectrics 52 as shown in FIG. 8. In forming the replacement gate stacks 56, the hard mask layers 36, the dummy gate electrodes 34, and the dummy gate dielectrics 32 as shown in FIG. 7 are first removed in one or a plurality of etching steps, resulting in the formation of trenches / openings between the gate spacers 38. The top and side walls of the protruding semiconductor fins 24' are exposed to the resulting trenches.Next, (replacement) gate dielectric layers 52 are formed that extend into the trenches between the gate spacers 38. According to some embodiments of the present disclosure, each of the gate dielectric layers 52 includes, as its lower portion, an interfacial layer (IL) that contacts the exposed surfaces of the corresponding protruding fins 24'. The IL may include an oxide layer, such as a silicon oxide layer, formed by thermal oxidation of the protruding fins 24', a chemical oxidation process, or a deposition process. The gate dielectric layer 52 may also include a high-k dielectric layer formed over the IL. The high-k dielectric layer may include a high-k dielectric such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, silicon nitride, or the like. The dielectric constant (k-value) of the high-k dielectric is higher than 3.9 and may be higher than 7.0. The high-k dielectric layer is formed as a conformal layer and extends on the sidewalls of the protruding fins 24' and the sidewalls of the gate spacers 38.Further, as shown in FIG. 8, the gate electrodes 54 are formed over the gate dielectrics 52, and the gate electrodes 54 include conductive sub-layers. The sub-layers are not shown separately, but the sub-layers are distinguishable from each other. The deposition of the sub-layers can be carried out by means of one or more conformal deposition methods such as ALD or CVD, for example.The stacked conductive layers may include a diffusion barrier layer and one (or more) work function layer over the diffusion barrier layer. The diffusion barrier layer may be formed of titanium nitride (TiN), which may (optionally) be doped with silicon. The work function layer determines the work function of the gate and includes at least one layer or a plurality of layers formed from different materials. The material of the work function layer is selected according to whether the respective FinFET is an n-type FinFET or a p-type FinFET. For example, if the FinFET is an n-type FinFET, then the work function layer may include a TaN layer and a titanium aluminum (TiAl) layer over the TaN layer. If the FinFET is a p-type FinFET, then the work function layer may include a TaN layer, a Tin layer over the TaN layer, and a TiAl layer over the TiN layer. After the deposition of the work function layer(s), a barrier layer is formed, which may be another TiN layer.The deposited gate dielectric layers and conductive layers are formed as conformal layers extending into the trenches and include some portions over the ILD 48. Next, a metallic material is deposited to fill the remaining trenches between the gate spacers 38. The metallic material may be formed of tungsten or cobalt, for example. In a subsequent step, a planarization step, such as a CMP process or a mechanical grinding process, is performed such that the portions of the gate dielectric layers, the conductive sub-layers, and the metallic material over the ILD 48 are ablated. This forms the metal gate electrodes 54 and the gate dielectrics 52. The gate electrodes 54 and the gate dielectrics 52 are referred to in combination as replacement gate stacks 56. The tops of replacement gate stacks 56, gate spacers 38, CESL 46, and ILD 48 may be substantially coplanar at this time.FIG. 8 also illustrates the formation of the hard masks 58, in accordance with some embodiments. The formation of the hard mask 58 may include performing an etch step to recess the gate stacks 56 to form recesses between the gate spacers 38, filling the recesses with a dielectric material, and then performing a planarization process such as a CMP process or a mechanical grinding process to ablate excess portions of the dielectric material. The hard masks 58 may be formed of silicon nitride, silicon oxynitride, silicon oxycarbonitride, or the like.FIG. 9A illustrates the formation of contact openings 60. The formation of the contact openings 60 includes etching the ILD 48 to expose the underlying portions of the CESL 46, and then etching the exposed portions of the CESL 46 to expose the epitaxy regions 42. According to some embodiments of the present disclosure, as shown in FIG. 9A, the length of the contact openings 60 is substantially equal to the length of the planar top surface of the epitaxy regions 42. According to further embodiments of the present disclosure, the contact openings 60 are larger than illustrated and may extend to the positions marked by dashed lines 46'. This may expose the upper and lower facets of the epitaxy regions 42 after the respective portions of the CESL 46 have been etched. Additionally, as illustrated in FIG. 9A, in accordance with some embodiments of the present disclosure, the gate spacers 38 are spaced apart from the closest contact openings 60 by some remaining portions of the ILD 48. According to some embodiments, the sidewalls of the contact openings 60 are exposed towards the contact openings 60.FIG. 9B illustrates a cross-sectional view of the contact hole 60 obtained from the vertical plane including the line 9B- 9B in FIG. 9A. FIG. 9C illustrates a cross-sectional view of the contact opening 60 obtained from the vertical plane containing the line 9C- 9C in FIG. 9A. In FIG. 9C, the levels of the tops 22A and the bottoms 22B of the STI regions 22 are illustrated, and the semiconductor fins 24' overlie the tops 22A.Referring to FIG. 10, a pre-amorphization implantation (PAI, sometimes referred to as pre-amorph implantation) is performed to form PAI regions 62 in the epitaxial regions 42. The corresponding process is illustrated as process 214 in process flow 200 shown in FIG. 21. According to some embodiments, silicon or germanium is implanted. In further embodiments, an inert species such as neon, argon, xenon, and radon is implanted. The PAI regions 62 may be located in the epitaxial portions 42B and do not extend into the epitaxial portions 42A. Alternatively, the PAI regions 62 may extend slightly into the epitaxial portions 42A. The epitaxial portions 42B may optionally include portions that are at the same level as the PAI regions 62 and are not implanted. The lattice structure of the epitaxial portions 42B is destroyed by the PAI, and the PAI regions 62 are converted into amorphous regions.Next, an implantation of a p-type impurity (dopant) is performed. The corresponding process is also illustrated as process 214 in process flow 200 shown in FIG. 21. For example, boron, gallium and / or indium may be implanted.FIG. 11 illustrates the structure after a subsequent annealing process as illustrated by arrows 64. The corresponding process is illustrated as process 216 in process flow 200 shown in FIG. 21. According to some embodiments, the annealing process includes a melt annealing process. In the melt-annealing process, at least a portion of the epitaxy regions 42 is melted. In addition to the melting process, the annealing process may optionally include other non-melting annealing processes such as, but not limited to, a millisecond annealing process that may be performed using laser, UV light, flash lamp, etc. In the non-melting annealing processes, no portion of the epitaxy regions 42 is melted. The effect of the non-melting anneal processes is to activate the dopants in unmelted portions of the source / drain regions in addition to the melted portions of the source / drain regions. The PAI regions 62 are recrystallized by the melt annealing process.According to some embodiments of the present disclosure, the melt-annealing process is performed by laser annealing, wherein a laser beam is projected onto the portions of the wafer 10 to be annealed. According to alternative embodiments of the present disclosure, a UV beam is used for the melt annealing process. When a laser beam is used, the laser beam may be of the size of one die or a plurality of dies or may be of the size of an entire wafer, and a laser pulse is generated to anneal the entire die, the plurality of dies or the entire wafer simultaneously. The size of the laser beam may also be a fraction (e.g., a quarter, a third, half, etc.) of a device die. In this case, a device die is annealed by multiple laser pulses covering the entire die in combination. The duration of the laser beam may range between about 10 nanoseconds and about 1 microsecond. The laser beam can also be small and the laser annealing process can be carried out by scanning the wafer by means of the laser beam. According to some embodiments of the present disclosure, the laser source has a polarization function to generate a polarized light source (wherein the corresponding electric field is either parallel or perpendicular to the plane of incidence of the laser beam). The laser source may also have a pre-heating function to raise the temperature of the annealed source / drain regions from room temperature to a temperature below the melting point (e.g., about 1,000 ° C.). The preheating is performed before melting the source / drain regions. Preheating may also be accomplished by annealing the wafers using the laser beam projected through a plurality of projections, each having an angle of incidence different from other angles of incidence of the plurality of projections, such that the energy and resulting melt depths and ranges may be controlled.According to some embodiments of the present disclosure, the power and duration of the melt annealing process are adjusted such that the upper portions 42B of the epitaxy regions 42 are melted while the lower portions 42A are not melted. Since voids 43 may be present (FIG. 9B ), epitaxial regions 42 may undesirably break into the voids 43 when lower portions 42A are melted, so that it is desirable that at least a part of the lower portions 42A is not melted.The melting point of silicon germanium is related to the atomic percentage of germanium in the epitaxy regions 42, and the higher the germanium percentage, the lower the melting point. For example, the melting point of silicon is 1,415° C. and the melting point of germanium is 937° C. Depending on the atomic percentage of germanium, the melting point of silicon germanium may be in the range between 937° C. and 1,415° C. Since the lower portions 42A have a lower germanium percentage, their melting point is higher than the melting point of the upper portions 42B. Therefore, by adjusting the power and the laser time, the temperature of the annealed portions can be selected to be higher than the melting point of the lower portions 42A and lower than the melting point of the upper portions 42B to cause the upper portions 42B to be melted while the lower portions 42A are not melted.In addition, the amorphized regions 62 have a lower melting point than that of the nonamorphized portions of the upper portions 42B. Thus, the melt-annealing process can be controlled such that the temperature is higher than the melting point of the PAI regions 62 and lower than the melting point of the non-amorphized portions of the upper portions 42B, such that the PAI regions 62 are melted while the non-amorphized portions of the upper portions 42B and the lower portions 42A are not melted.According to some embodiments of the present disclosure in which no voids are formed in the epitaxial regions 42, power and annealing time are set such that the temperature of the annealing portions is lower than the melting point of silicon and higher than the melting point of the entire epitaxial regions 42. Furthermore, the epitaxial (source / drain) regions of p-type FinFETs and n-type FinFETs may be simultaneously annealed. However, during the melt anneal process, the epitaxy (source / drain) regions of p-type FinFETs are melted, while the epitaxy (source / drain) regions of n-type FinFETs may be controlled not to melt because the epitaxy (source / drain) regions of n-type FinFETs have a higher melting point.As a result of the melt-annealing process, the germanium in the melted portions and nearby portions of the epitaxial regions 42 is redistributed and, after the subsequent solidification, is concentrated toward the upper surfaces of the melted portions. Additionally, wafer 10 shown in FIG. 11 may undergo a variety of processes including, but not limited to, cleaning processes after formation of contact openings 60. FIG. 12 illustrates the top profile of the epitaxy regions 42 after the melt anneal and cleaning processes. Due to the concentration of germanium toward the surface of the epitaxy regions 42, the surface portions of the epitaxy regions 42 are more susceptible to oxidation caused by oxygen in the air and the oxidant in the chemicals of the cleaning processes. As a result, the upper surface 42S of the epitaxial region 42 is recessed and continuously curved and continuously rounded.FIG. 12 also illustrates a top surface of the epitaxial region 42 using the dashed line 66, where the dashed line 66 illustrates the top surface profile of the epitaxial region 42 when the anneal does not include a melt anneal. The dashed surface 66 has a planar portion connected to opposing oblique and straight portions. In comparison, the surface 42S is continuously curved. Accordingly, as a result of the melt anneal, the surface of epitaxial region 42 is more curved than in non-melt anneals and the surface area is increased compared to the use of non-melt anneals. In the illustrated cross-sectional view, a deepest point of the curved surface 42S may be the center of the curved surface 42S.Referring to FIG. 13, a metal layer 68 and a metal nitride layer 70 are deposited by means of conformal deposition processes, for example. The corresponding process is illustrated as process 220 in process flow 200 shown in FIG. 21. In some embodiments, the metal layer 68 is a titanium layer. The metal nitride layer 70 may be a titanium nitride layer that may be formed by ALD, CVD, or the like. The metal nitride layer 70 may also be formed by nitriding the upper portion of the metal layer 68 and leaving the lower portion of the metal layer 68 in the non-nitrided state.Next, an annealing process (which may be thermal flash annealing) is performed to react the metal layer 68 with the upper portion of the source / drain regions 42 to form the silicide region 72 as shown in FIG. 14A. The silicide region 72 forms the curved top surface 42S' with the underlying source / drain region 42. The portions of the metal layer 68 on the sidewalls of the ILD 48 are not reacted. Next, either the previously formed metal nitride layer 70 remains, or the previously formed metal nitride layer 70 is removed, followed by the deposition of a new metal nitride layer (such as a titanium nitride layer) that is thinner than the removed metal nitride layer. Subsequently, a metallic material 71 such as tungsten, cobalt or the like is filled in the contact holes 60, followed by planarization to remove excessive materials, resulting in the source / drain contact terminal 74. Accordingly, the source / drain contact terminal 74 includes the remaining portions of the metal layer 68, the metal nitride layer 70, and the metal material 71. due to the curved top surface of the source / drain region 42, the interface between the silicide region 72 and the source / drain region 42 is curved, resulting in an increased interface region. The source / drain contact resistance is thus reduced. The FinFET 76 is thus formed.FIGS. 14B and 14C show a cross-sectional view and a perspective view of the FinFET 76. The cross-sectional view shown in FIG. 14A is obtained from the vertical plane including the line 14A- 14A in FIG. 14C. The cross-sectional view shown in FIG. 14B is obtained from the vertical plane including the line 14B-14B in FIG. 14C.Referring to FIG. 15, an etch stop layer 80 is formed in accordance with some embodiments of the present disclosure. The etch stop layer 80 may be formed of SiN, SiCN, SiC, SiOCN, or other dielectric material. The method of formation may include PECVD, ALD, CVD, or the like. Next, an ILD 82 is formed over the etch stop layer 80. The material of the ILD 82 may be selected from the same materials (and methods) that are also suitable for forming the ILD 48. In some embodiments, the ILD 82 is formed using PECVD, FCVD, spin-on, or the like.The ILD 82 and the etch stop layer 80 are etched to form openings. The etching can be carried out, for example, by means of reactive ion etching (RIE). In a subsequent step, the source / drain contact terminals 86 and the gate contact terminals 88 are formed. In accordance with some embodiments of the present disclosure, contact terminals 86 and 88 include barrier layers and a metal-containing material over the respective barrier layers.As treated in previous paragraphs, the germanium is concentrated towards the top of the source / drain regions. FIGS. 16A, 16B, 16C and 16D are schematically shown to explain the mechanism of germanium concentration. In each of FIGS. 16A, 16B, 16C, and 16D, the x-axis represents the vertical positions in the epitaxy regions 42, while the y-axis represents the normalized germanium atomic percentage values. Figures 16A, 16B, 16C and 16D show the germanium percentages as a function of the depths in a molten portion. The positions TS and BS represent the top and bottom of the melted portion of the epitaxial region, respectively. For example, as shown in FIG. 11, assuming non-melted portions 42A and melted portions 42B, the positions TS and BS are as marked in FIG. 11.FIGS. 16A, 16B, 16C, and 16D illustrate the change in germanium percentage during the solidification process occurring after the melt anneal. As shown in Fig. 16A, the entire molten portion is in a liquid phase which has not yet solidified. It is assumed that the melted portion has a uniform germanium concentration as indicated by the line 102A. After the melt-annealing process, solidification starts from the bottom side BS and continues toward the top side TS. Lines 104 (FIGS. 16B, 16C, and 16D ) represent the interface between the fused portion and the solid portion. Lines 102B, 102C, and 102D in FIGS. 16A, 16B, and 16C, respectively, represent the corresponding germanium percentages as a function of depth. Germanium tends to be drawn from the surface portion of the solidified silicon germanium into the liquid portions. Accordingly, a maximum of the germanium percentage is present in the surface portions of the silicon-germanium region which has just solidified. The germanium in the portion having the maximum diffuses into the closest portion in the liquid phase, whereby the maximum migrates toward the top as solidification progresses. As solidification proceeds, the interface 104 between the melted portion and the unmelted portion gradually moves from the position BS to the position TS as indicated in FIGS. 16B, 16C and 16D. Accordingly, the germanium gradually diffuses from BS to TS, resulting in the germanium maximum at a position close to TS when the entire portion is solidified, as shown in FIG. 16D.FIG. 18 illustrates experimental results of germanium distribution of germanium according to some embodiments, wherein germanium percentages are shown as a function of depth in the silicon-germanium epitaxial region. The zero x-axis value corresponds to the top of the silicon-germanium epitaxial region and the increasing x-axis value corresponds to the increasing depth in the silicon-germanium region. Line 110 represents the germanium percentage prior to the PAI and annealing processes. Line 112 represents the germanium percentage when the non-melting anneal is performed. The line 112 substantially overlaps with the line 110, indicating that the non-melting anneal does not cause the redistribution of the germanium. Line 114 represents the germanium percentage after lower power (and lower temperature) melt annealing. Line 116 represents the germanium percentage after higher power (and higher temperature) melt annealing. In the case of line 114, position 120 and the second portion represent the bottom of the melted portions as shown in Figure 18. In a part of the second subregion, a mixture of liquid and solid is present. Accordingly, line 114 shows that germanium is pulled from the nearby regions of (x-axis) position 120, thereby creating a minimum at position 120 that is between two maxima of the germanium percentages. In the case of line 116, all illustrated portions of the silicon germanium are melted. Accordingly, the germanium is redistributed throughout the epitaxial region so as to gradually decrease from the top to the bottom of the silicon-germanium region.FIG. 19 illustrates the boron distribution of germanium according to some embodiments, wherein boron distributions are shown as a function of depths in the silicon-germanium epitaxial region. The zero x-axis value corresponds to the top of the silicon-germanium epitaxial region and the increasing x-axis value corresponds to the increasing depths in the silicon-germanium region. Line 130 represents the boron concentration prior to the PAI and annealing processes. Line 132 represents the boron concentration when the non-melting annealing is performed. As shown by lines 130 and 132, the non-melting anneal also causes redistribution of the boron to the surface of the silicon-germanium region. Line 134 represents the boron concentration after lower power (and lower temperature) melt annealing. Line 136 represents the boron concentration after higher power (and higher temperature) melt annealing. Lines 134 and 136 disclose an important phenomenon, namely that due to the melting of the silicon germanium, the boron concentration tends to be low at those locations where the germanium percentage is high, and vice versa. Accordingly, due to the maximum of the germanium percentage near the top, the boron concentration at the (x-axis) positions 140 and 142 has minima. In other words, in the case of lines 134 and 136, as the depths increase, the corresponding boron concentrations first decrease and then increase again. This occurs in the depth region in which the germanium concentration (FIG. 17 ) continuously decreases. In addition, as compared to line 114 in FIG. 17 and line 134 in FIG. 18, low point 120 (FIG. 17 ) and high point 140 (FIG. 18 ) occur at the same depth marked by lines 144. The depth range marked TR in FIGS. 18 and 19 has a first sub-range to the left of the line 144 and a second sub-range to the right of the line 144. Germanium concentrations continuously decrease in the first subregion and boron concentrations continuously increase, while germanium concentrations continuously increase and boron concentrations continuously decrease in the second subregion. Accordingly, the melt annealing process results in a clear change in germanium percentage and boron concentration.In the FinFET shown in FIG. 14A, the fins 24' have a non-crown structure in which a plurality of fins and the underlying semiconductor strips are directly connected to the main portion of the substrate 20. FIG. 20 illustrates the FinFET 76' in accordance with some embodiments of the present disclosure, where fins are present in a crown structure that includes a semiconductor base 146 and over the semiconductor base the protruding fins 24' and the underlying semiconductor strips.The embodiments of the present disclosure have some advantageous features. A superactivation can be achieved by the melt annealing process, since boron can achieve a much higher concentration in molten silicon germanium than the maximum concentration achievable with doping in the solid phase. Since the melt anneal is achieved in a very short time, diffusion of the impurity (such as boron) is minimized in the portions of silicon germanium that are not melted, resulting in improved short channel effect and drain induced barrier lowering (DIBL) performance. In addition, the defects in the source / drain portion can be removed by the liquefaction and the recrystallization.According to some embodiments of the present disclosure, a method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region out of the recess, implanting an impurity into the semiconductor region, and performing a melt anneal on the semiconductor region, wherein at least a portion of the semiconductor region is melted during the melt anneal. In an embodiment, growing the semiconductor region includes growing a silicon-germanium region. In an embodiment, the silicon germanium region is included in a p-type fin field effect transistor (FinFET), and simultaneously anneals a source / drain region of an n-type FinFET while not melting the source / drain region of the n-type FinFET. In an embodiment, the semiconductor region includes a lower portion and an upper portion above the lower portion, and during the melt annealing process, the lower portion is not melted while the upper portion is melted. In an embodiment, the lower portion has a first germanium percentage that is less than a second germanium percentage of the upper portion. In an embodiment, a first portion of the semiconductor region is implanted and a second portion of the semiconductor region is masked from the implanting, and during the melt-annealing process, the implanted first portion of the semiconductor region is melted and the non-implanted second portion of the semiconductor region is not melted. In an embodiment, the non-implanted second portion of the semiconductor region that is not melted is level with the implanted first portion and has a side edge contacting it. In one embodiment, a cavity is located below the semiconductor region and portions of the semiconductor region exposed toward the cavity are not melted. In an embodiment, the method further includes depositing a contact etch stop layer over the semiconductor region, forming an interlayer dielectric layer over the contact etch stop layer, and etching the interlayer dielectric layer and the contact etch stop layer to form a contact opening, wherein the implanting and the melt-annealing are performed through the contact opening.According to some embodiments of the present disclosure, a method includes etching a portion of a semiconductor fin on a side of a gate stack to form a recess, epitaxially growing a first silicon-germanium layer, the first silicon-germanium layer being grown out of the recess and the first silicon-germanium layer having a first germanium percentage, epitaxially growing a second silicon-germanium layer over the first silicon-germanium layer, the second silicon-germanium layer having a second germanium percentage that is higher than the first germanium percentage, performing an anneal operation, wherein the second silicon-germanium layer is melted during the anneal operation, forming a silicide layer over and in contact with the second silicon-germanium layer. In one embodiment, the annealing process includes a laser annealing process. In one embodiment, the anneal has a duration in the range between about 10 nanoseconds and about 1 microsecond. In one embodiment, the first silicon-germanium layer remains as a solid during the annealing process. In an embodiment, the method further comprises depositing a contact etch stop layer over the second silicon germanium layer, forming an interlayer dielectric layer over the contact etch stop layer, and etching the interlayer dielectric layer and the contact etch stop layer to form a contact opening, wherein the anneal is performed through the contact opening and the anneal is performed by projecting a laser beam into the contact opening. In an embodiment, the method further comprises amorphizing a first portion of the second silicon-germanium layer, wherein a second portion of the second silicon-germanium layer is free of amorphization, and during the annealing process, the first portion of the second silicon-germanium layer is melted and the second portion of the second silicon-germanium layer remains as a solid.According to some embodiments of the present disclosure, an apparatus includes a first semiconductor fin and a second semiconductor fin that protrude higher than a top surface of isolation regions, the isolation regions including portions on opposite sides of each of the first semiconductor fin and the second semiconductor fin, a gate stack on a top surface and a sidewall of each of the first semiconductor fin and the second semiconductor fin, a source / drain region on a side of the gate stack, the source / drain region including silicon germanium and the source / drain region having sidewalls contacting the first semiconductor fin and the second semiconductor fin, and a silicide layer that is over and interfaces with the source / drain region, wherein, in a cross-sectional view of the interface, the interface is continuously curved, wherein a lowest point of the interface is a center of the interface. In one embodiment, a highest germanium percentage in the source / drain region is at a level near the interface. In an embodiment, in a direction from a top side of the source / drain region into the source / drain region, germanium percentages of the source / drain region have two maxima and a minimum between the two maxima. In one embodiment, the source / drain region comprises boron and germanium concentrations have a course opposite to boron concentrations in a depth region of the source / drain region. In one embodiment, the depth range has a first subregion and a second subregion adjoining the first subregion, wherein germanium concentrations continuously decrease and boron concentrations continuously increase in the first subregion, while germanium concentrations continuously increase and boron concentrations continuously decrease in the second subregion.

Claims

A method comprising: forming a gate stack (30) on a first portion of a semiconductor substrate (20); removing a second portion of the semiconductor substrate (20) on a side of the gate stack (30) to form a recess (40); growing a semiconductor region (42) out of the recess (40); implanting an impurity into the semiconductor region (42); and performing a melt anneal (64) on the semiconductor region (42), wherein at least a portion of the semiconductor region (42) is melted during the melt anneal (64), wherein after performing the melt anneal (64), solidification of the melted portion of the semiconductor region (42) begins from a bottom of the melted portion of the semiconductor region (42) and continues toward a top of the melted portion of the semiconductor region (42).The method of claim 1, wherein growing the semiconductor region (42) comprises growing a silicon-germanium region.The method of claim 2, wherein the silicon-germanium region is included in a p-type Fin Field Effect Transistor, hereinafter referred to as FinFET, and simultaneously anneals a source / drain region of an n-type FinFET while performing the melt anneal process (64), wherein the source / drain region of the n-type FinFET is not melted.The method of any preceding claim, wherein the semiconductor region (42) comprises a lower portion and an upper portion above the lower portion, and during the melt annealing process (64), the lower portion is not melted while the upper portion is melted.The method of claim 4, wherein the lower portion has a first germanium percentage less than a second germanium percentage of the upper portion.The method of any preceding claim, wherein a first portion of the semiconductor region (42) is implanted and a second portion of the semiconductor region (42) is masked from the implanting, and during the melt anneal process (64), the implanted first portion of the semiconductor region (42) is melted and the non-implanted second portion of the semiconductor region (42) is not melted.The method of claim 6, wherein the non-implanted second portion of the semiconductor region (42) that is not melted is level with and has a side edge contacting the implanted first portion.Method according to one of the preceding claims, wherein a cavity (43) lies below the semiconductor region (42) and portions of the semiconductor region (42) exposed towards the cavity (43) are not melted.The method of any preceding claim, further comprising: depositing a contact etch stop layer over the semiconductor region (42); forming an interlayer dielectric layer over the contact etch stop layer; and etching the interlayer dielectric layer and the contact etch stop layer to form a contact opening, wherein the implanting and the melt-annealing process (64) are performed through the contact opening.A method comprising: etching a portion of a semiconductor fin (24) on a side of a gate stack (30) to form a recess (40); epitaxially growing a first silicon-germanium layer (42A), the first silicon-germanium layer (42A) being grown out of the recess (40) and the first silicon-germanium layer (42A) having a first germanium percentage; epitaxially growing a second silicon-germanium layer (42B) over the first silicon-germanium layer (42A), the second silicon-germanium layer (42B) having a second germanium percentage that is higher than the first germanium percentage; and performing an anneal (64), wherein during the annealing process (64), the second silicon-germanium layer (42B) is melted and forming a silicide layer (72) over and in contact with the second silicon-germanium layer (42B), wherein after performing the annealing process (64), solidification of the second silicon-germanium layer (42B) begins from a bottom surface of the second silicon-germanium layer (42B) and continues toward a top surface of the second silicon-germanium layer (42B).The method of claim 10, wherein the annealing process (64) comprises a laser annealing process.The method of claim 11, wherein the annealing process (64) has a duration in the range between about 10 nanoseconds and about 1 microsecond.The method of any of the preceding claims 10 to 12, wherein during the anneal (64), the first silicon-germanium layer (42A) remains as a solid.The method of any of the preceding claims 10 to 13, further comprising: depositing a contact etch stop layer over the second silicon germanium layer (42B); forming an intermediate dielectric layer over the contact etch stop layer; and etching the intermediate dielectric layer and the contact etch stop layer to form a contact opening, wherein the anneal (64) is performed through the contact opening and the anneal (64) is performed by projecting a laser beam into the contact opening.The method of claim 14, further comprising: amorphizing a first portion of the second silicon-germanium layer (42B), wherein a second portion of the second silicon-germanium layer (42B) is free of amorphization, and during the anneal (64), the first portion of the second silicon-germanium layer (42B) is melted and the second portion of the second silicon-germanium layer (42B) remains as a solid.An apparatus comprising: a first semiconductor fin (24) and a second semiconductor fin (24) protruding higher than a top surface of isolation regions (22), wherein the isolation regions (22) comprise portions on opposite sides of each of the first semiconductor fin (24) and the second semiconductor fin (24); a gate stack (30) on a top surface and a sidewall of each of the first semiconductor fin (24) and the second semiconductor fin (24); a source / drain region (42) on a side of the gate stack (30), wherein the source / drain region (42) comprises silicon germanium and wherein the source / drain region (42) has sidewalls contacting the first semiconductor fin (24) and the second semiconductor fin (24); and a silicide layer (72), which is located above the source / drain region (42) and forms an interface therewith, wherein in a cross-sectional view of the interface the interface is continuously curved, wherein a lowest point of the interface is a centre of the interface, wherein a highest germanium percentage in the source / drain region (42) is at a level close to the interface.The device of claim 16, wherein in a direction from a top of the source / drain region (42) into the source / drain region (42) germanium percentages of the source / drain region (42) have two maxima and a minimum between the two maxima.Device according to one of the preceding claims 16 or 17, wherein the source / drain region (42) comprises boron and germanium concentrations have a course opposite to boron concentrations in a depth region of the source / drain region (42).The device of claim 18, wherein the depth region comprises a first sub-region and a second sub-region adjoining the first sub-region, wherein germanium concentrations continuously decrease and boron concentrations continuously increase in the first sub-region, while germanium concentrations continuously increase and boron concentrations continuously decrease in the second sub-region.

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