Histogram-based qualification of data used in background or blind calibration of interleaving errors of time-interleaved ADWS

Abstract

A method for preventing performance degradation of a blind calibration of an interleaving error of a plurality of time-interleaved analog-to-digital converters, the method comprising: Acquiring a block of data comprising output values generated by one of the plurality of time-interleaved analog-to-digital converters; Qualifying the data block by evaluating a variability measurement of a qualification histogram generated from the data block; in response to determining that the data block fails qualification, skipping an update of the interleaving error blind calibration; and in response to determining that the data block qualifies, using the data block to update the blind calibration of the interleaving error.

Description

AREA OF REVELATION

[0001] The present invention relates to the field of integrated circuits, in particular to techniques used in background or blind calibrations of interleaving errors of time-interleaved analog-to-digital converters. GENERAL STATE OF THE ART

[0002] In many electronics applications, an analog-to-digital converter (ADC) converts an analog input signal into a digital output signal, for example, for further digital signal processing or storage by digital electronics. Generally speaking, ADCs can translate analog electrical signals that represent real-world phenomena such as light, sound, temperature, electromagnetic waves, or pressure for data processing purposes. For example, in measurement systems, a sensor takes measurements and generates an analog signal. The analog signal would then be provided as input to an ADC to generate a digital output signal for further processing. In another case, a transmitter generates an analog signal using electromagnetic waves to carry information in the air, or a transmitter transmits an analog signal to carry information over a cable.The analog signal is then provided as input to an ADC at a receiver to generate a digital output signal, e.g. for further processing by digital electronics.

[0003] Due to their wide applicability to many applications, ADCs can be found in places such as broadband communication systems, audio systems, receiver systems, and so on. Designing an ADC is a non-trivial task because each application may have different requirements regarding performance, power, cost, and size. ADCs are used in a wide range of applications, including communications, energy, healthcare, instrumentation and measurement, motor and power control, industrial automation, and aerospace / defense. As the number of applications requiring ADCs grows, so does the need for fast yet accurate conversion. Designing an ADC can be a complex and challenging task.

[0004] US 2017 / 0 117 914 A1 relates to a method and apparatus for providing a digital background calibration for mismatches in M-channel time-interleaved ADCs (TI-ADCs), in particular for providing a purely digital blind calibration technique for offset mismatches, gain mismatches, and timing mismatches that arise primarily from the use of a time-interleaved analog-to-digital converter in systems that must process data at high speed. The offset mismatch and gain mismatch are corrected based on statistical properties of the digital signals sampled and output channel by channel, and the timing mismatch is corrected based on a differential filter and a delay filter. This is intended to make it possible to reduce hardware complexity and increase the efficiency of hardware resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] To provide a more complete understanding of the present disclosure and its features and advantages, reference is made to the following description in conjunction with the accompanying figures, wherein like reference numerals represent like parts. In the drawings: Fig. 1 illustrates an exemplary ADC having M time-interleaved ADCs and digital processing for processing outputs of the M time-interleaved ADCs, in accordance with some embodiments of the disclosure; Fig. 2-6 illustrate two time-interleaved ADCs sampling input signals at certain coherent input frequencies, according to some embodiments of the disclosure; Fig. 7A-B, Fig. 8A-B, Fig. 9A-B, Fig. 10A-B and Fig. 11A-G illustrate histograms of digital output signals generated from input signals having different frequencies, according to some embodiments of the disclosure; Fig. 12 and Fig. 13 shows input frequency versus histogram variance plots for two input signals with different signal ranges, according to some embodiments of the disclosure; Fig. 14 is a flowchart illustrating an example method for qualifying data used for background / blank calibration of interleaving errors, according to some embodiments of the disclosure; Fig. 15 is a flowchart illustrating another example method for qualifying data used for background / blank calibration of interleaving errors, according to some embodiments of the disclosure; Fig. 16 is a flowchart illustrating an example method for qualifying a block of data, according to some embodiments of the disclosure; and Fig. 17 exemplary components within a qualifier 122 used to implement one or more parts of Fig. 15 and Fig. 16 may be used, according to some embodiments of the disclosure. DETAILED DESCRIPTIONOverview

[0006] An ADC may comprise multiple time-interleaved ADCs to increase the overall sampling rate of the ADC. Such an ADC may exhibit interleaving errors because the time-interleaved ADCs within the ADC are not always perfectly matched. For example, the time-interleaved ADCs may often exhibit offset mismatches, gain mismatches, and timing skew. One way to calibrate for these mismatches is by observing the digital output signals of the time-interleaved ADCs in the background, or more generally, without knowledge of the input signal to the ADC (often referred to as "blind calibration"). Due to the nature of these calibrations, the performance of the calibration would degrade significantly if the input signal has certain problematic input conditions, such as a certain coherent input frequency. These problematic input conditions can cause the calibrations to diverge.To address this issue, the data used for interleaving error calibration can undergo a qualification process to evaluate whether error estimates need to be updated based on the data. The qualification process can detect whether the input signal has a problematic input condition or meets certain calibration requirements, such as diversity in amplitude levels in the data. Basics of ADCs

[0007] ADCs are electronic devices that convert a continuous physical quantity carried by an analog signal into a digital output, or a number representing the amplitude of the quantity (or into a digital signal carrying that digital number). An ADC can be defined by the following application requirements: its bandwidth (the range of analog signal frequencies it can properly convert to a digital signal) and its resolution (the number of discrete levels into which the largest analog signal can be divided and represented in the digital signal). An ADC also has various specifications for quantizing an ADC's dynamic performance, including SINAD (signal-to-noise-and-distortion ratio), ENOB (effective number of bits), signal-to-noise ratio (SNR), clarification factor (THD - total harmonic distortion), THD+N (total harmonic distortion plus noise), and SFDR (spurious free dynamic range).ADCs have many different designs that can be chosen based on application requirements and specifications. Understanding time-nested ADCs

[0008] Time interleaving is a technique used to increase the sampling rate of an ADC. Many (slow) ADCs can be used in parallel, sampling an analog input one after the other (in a time-interleaved manner). With the appropriate clock to control the time-interleaved ADCs, the effective combined ADC sampling rate can be greatly increased. Fig. 1 shows an exemplary ADC with M time-interleaved ADCs and digital processing for processing outputs of the M time-interleaved ADCs according to some embodiments of the disclosure. The M time-interleaved ADCs are referred to as ADC0 through ADC M-1shown (sometimes referred to here as sub-ADCs). The example shown has subADC[0] 112, subADC[1] 114, ... and subADC[M-1] 116. The M sub-ADCs, together with a corresponding clock, can provide an effective sampling rate that is higher than a sampling rate of a single sub-ADC. The corresponding clock can be provided by a clock block 102 to provide clock signals or select signals q0, q1, ... q M-1 with different phases to generate one of the M sub-ADCs to sample the analog input signal v in for a given cycle and the analog input signal v in into a digital output signal. In other words, the clock block 102 can generate select signals that trigger the M sub-ADCs in the ADC to convert the analog input signal v in M can be greater than or equal to two. The M sub-ADCs sample the input signal v inone after the other and generate corresponding digital output signals D out0 , D out1 , ... D outM-1 , which are then combined by the digital block 104 to produce the (final) digital output signal D out to generate.

[0009] In one example, the M sub-ADCs can operate in a circular fashion or in a sequential fashion, where the M sub-ADCs sample the input sequentially based on a fixed sequence. When the analog input signal v in is sampled in a sequential manner, the M sub-ADCs sample the analog input signal v in according to a rotation sequence. The sampling order is fixed, and the rotation sampling sequence repeats the sampling order. Each sub-ADC can be programmed with F S / M work, where F S is the effective sampling rate of the ADC.

[0010] Although time interleaving is often used to increase the sampling rate of ADCs, time interleaving can introduce interleaving errors if the interleaved sub-ADCs exhibit mismatches. For example, the interleaving errors can be caused by offset mismatch, gain mismatch, and timing skew. In particular, the type of sequential interleaving described above suffers from the property that any mismatches between the M sub-ADCs manifest themselves in the ADC output frequency spectrum (e.g., a spectrum generated by a fast Fourier transform) as noise in discrete frequency bins (frequency classes, frequency ranges) with a large concentrated energy content. This noise can be undesirable for many applications and can significantly degrade the dynamic performance of the time-interleaved ADC.

[0011] To address this problem, time-interleaved ADCs can operate in a pseudorandomized manner so that the noise can be "spread over the noise floor." The noise moves from peaks at specific frequencies to shaped "bumps" in the noise floor. To implement pseudorandomized time-interleaved sampling, one of the inactive or ready-to-sample sub-ADCs (generally, one or more other ADCs would be busy sampling and / or performing conversion of the analog input) would be randomly selected by clock block 102 as the ADC used to sample the analog input signal for a given cycle and convert the analog input signal to a digital output signal. Such a selection implements pseudorandomization. Randomized time-interleaved ADCs can have three or more ADCs (i.e., M is greater than or equal to three).Randomization requires an increase in the number of sub-ADCs (and additional digital logic to implement randomization) to achieve the same effective sampling rate of an ADC operating with a rotation sequence.

[0012] If randomization or increasing the number of sub-ADCs is impractical, sub-ADCs sampling the analog input signal according to a rotation sequence would introduce noise in the output spectrum. Calibration can be used to extract the interleaving errors that cause this noise and correct the interleaving errors to reduce the noise. Some calibration schemes operate in the background, where the interleaving errors are extracted while the ADC is in normal operation (and does not need to be taken offline). Some calibrations operate blindly without any information about the input signal. In particular, these calibration schemes can out0 , D out1 , ... D outM-1in the background and extract interleaving errors from the digital output signals. Since no fixed test signal is injected or the input signal is unknown, the background calibration schemes can only observe the digital output signals from the sub-ADCs to extract the interleaving errors. For example, the background calibration schemes can compare the digital output signals to derive the interleaving errors of the sub-ADCs. Based on the derived interleaving errors, the background calibration scheme can steer the interleaving errors smaller while the scheme converges on an optimal interleaving error correction coefficient. Unfortunately, these types of background calibration schemes, or blind calibration schemes, are susceptible to certain unwanted input frequencies that cause the background calibration to fail or diverge. Problematic input conditions such as coherent input frequencies

[0013] In particular, calibrations for interleaving errors caused by offset mismatches, gain mismatches, and timing skew are particularly prone to diverging under certain coherent input frequencies (or, more generally, certain input conditions). Certain coherent input frequencies can cause background or blind interleaving error calibrations to diverge because respective digital output signals from the sub-ADCs would cause calibrations to see an interleaving error that does not actually exist. For example, the calibrations may see an interleaving error that is much larger than the actual interleaving error.

[0014] As an example, for an ADC with M = 2 sub-ADCs, e.g., subADC[0] and subADC[1], an interleaving offset mismatch error calibration drives a mean output of each sub-ADC to zero (i.e., DC to zero). When operating according to a rotation sequence, each sub-ADC samples every other sample. This means that the digital output signal y m [n] for a given sub-ADW[m] can be represented as follows: ym[n]=x[Mn+m] x[n] represents a sampled version of the analog input signal v in The data from subADC[0] for the interleaving offset mismatch error calibration in the example is thus y0[n] = x[2n], and the data from subADC[1] for the interleaving offset mismatch error calibration is thus y1[n] = x[2n + 1].

[0015] A perfectly coherent signal such as FSK has only K discrete data points after sampling. These data points do not change over time, and repeatedly sampling these discrete data points and constructing error estimates with them can cause background / blank calibrations to degrade or even diverge. For example, if K=M, i.e. FSM, then the sampled input signal has only M discrete data points. For an ADC with M sub-ADCs, each sub-ADC will repeatedly sample only a single data value from the “grid” of x[n]. Even if there is no actual offset mismatch between sub-ADCs, this causes the background / blank calibration to introduce a large offset mismatch between sub-ADCs. From another perspective, the input signal with a frequency FSM to DC for each of the M sub-ADCs, causing an obvious mismatch to the background / blank calibration.

[0016] As an example, for an ADC with M = 2 sub-ADCs, e.g., subADC[0] and subADC[1], a background / blind interleaving gain mismatch error calibration can control the mean power of the second sub-ADC (subADC[1]) to be equal to or equal to the mean power of the first sub-ADC (subADC[0]) by scaling the amplitude of the second sub-ADC. In other words, the background / blind interleaving gain mismatch error calibration controls the mean absolute output (or mean absolute power) of each sub-ADC to correspond to a reference sub-ADC to normalize the mean power of each sub-ADC. An analog input signal that is a sinusoid with an input frequency of F S / 4 can produce a pattern of values: A, B, -A, -B, A, B... etc. (where A and B are phase-dependent amplitudes). In other words, an input signal with a frequency of F S / 4 4 discrete data points after sampling (e.g., A, B, -A, -B). If the calibration only looks at the amplitude (i.e., the absolute value of the data points), then the input signal has two discrete amplitude points (e.g., A and B). Each sub-ADC samples every other sample. Accordingly, a first sub-ADC, subADC[0] can sample: A, -A, A, -A..., while the second sub-ADC, subADC[1] can sample: B, -B, B, -B... After applying the "power measurement" (e.g., absolute value), the data used to calibrate subADC[0] is: A, A, A, A..., and the data used to calibrate subADC[1] is: B, B, B, B... In an extreme case, depending on the phase of the input signal, A could be large and B could be close to zero.When the interleaving gain mismatch error calibration sees the data from subADC[0] and subADC[1], the calibration might interpret that the "power" of subADC[1] is much smaller than the "power" of subADC[0] and subADC[1], and drive it strongly to correct / compensate for the difference. In reality, the "power" of subADC[0] and subADC[1] may be completely equal. Thus, the correction is not justified and may cause an unintended interleaving gain mismatch error when a different analog input signal is supplied to the ADC. This same phenomenon can occur with other coherent input frequencies, such as F. S / 4 and F S / 8, where the number of discrete data points in the signal after sampling is small, and the difference in the value or magnitude of these discrete data points (or the value of the discrete amplitude points) between the sub-ADCs can cause a gain mismatch (or other mismatches) to appear when none actually exist. In the presence of coherent input frequencies, the calibrations can erroneously extract an interleaving gain mismatch error that is much larger than the actual interleaving gain mismatch error.

[0017] Generally speaking, input signals with a coherent input frequency at FSK, where K is an integer (where e.g. K is less than or equal to 32), or input signals with a coherent input frequency at some integer multiples of FSK, such as L∗FSK, where L is an integer, pose problems for background / blank calibrations for interleaving errors caused, for example, by offset mismatch, gain mismatch, and timing skew. Some coherent input frequencies with the above relationship with the total sampling rate of the ADC, i.e., F S , can cause background / blank calibrations to fail.

[0018] For M sub-ADCs, signals at the following coherent input frequencies can cause interleaving error calibrations to diverge or fail: Ω=L∗FSK

[0019] L and K are integers. Generally, K is a small integer, preferably less than or equal to 32.

[0020] The Fig. 2-6 show two sub-ADCs, subADC[0] and subADC[1], that sample input signals at certain coherent input frequencies, according to some embodiments of the disclosure. "dout" represents a sampled version of the analog input signal v in “abs(dout)” represents absolute values of “dout” (or the magnitude of “dout”). The data from subADC[0] used for calibration is marked with an “×”, and the data from subADC[1] used for calibration is marked with a “•”.

[0021] In Fig. 2 the input frequency is FS4. It can be seen that "abs(dout)" generated four discrete data points and thus two amplitude points (e.g., 1.0 and 0.0). The data from subADC[0] only contains values from one of the two amplitude points (1.0), and the data from subADC[0] only contains values from the other of the two amplitude points (0.0). The interleaved gain mismatch calibration would diverge.

[0022] In Fig. 3, the input frequency is . It can be seen that "abs(dout)" generates eight discrete data points and four amplitude points (e.g., it provides three unique amplitude points because two amplitude points are zero, i.e., 1.0, 0.7, and 0.0). The data from subADC[0] only has values of one of the three amplitude points (0.7), and the data from subADC[0] only has values of the other two of the three amplitude points (1.0, 0.0). The interleaved gain mismatch calibration would diverge.

[0023] In Fig. 4 the input frequency is 3Fs8. It can be seen that "abs(dout)" generates eight discrete data points and four amplitude points (e.g., it provides three unique amplitude points because two amplitude points are zero, i.e., 1.0, 0.7, and 0.0). The data from subADC[0] only has values for one of the three amplitude points (0.7), and the data from subADC[0] only has values for the other two of the three amplitude points (1.0, 0.0). The interleaved gain mismatch calibration would diverge.

[0024] With a small K, such as FS4(K=4), as in Fig. 2, the difference in amplitude points (i.e., the data) between sub-ADCs can be very large, causing the background / blind interleaving mismatch error calibration to diverge significantly and rapidly. For a larger K such as FS64(K=64), the difference in amplitude points (i.e., the data) between sub-ADCs is reduced due to an averaging effect, which minimizes the interleaving gain mismatch calibration divergence. Furthermore, the problem decreases rapidly with increasing n. Fig. 5 and Fig. 6, where the input frequency is FS32 or FS48 The data from subADC[0] have a variety of amplitude points, and the data from subADC[1] also have a variety of amplitude points. The interleaving gain mismatch error calibration can be performed in the Fig. 5 and Fig. 6 examples, but would diverge far less than those shown in Fig. Examples shown in Figures 2-4. Generally speaking, the smaller the number of available unique amplitude points, the more likely and faster the calibrations would diverge.

[0025] Generally speaking, the same coherent input conditions that can cause a background / blind interleaving offset mismatch error calibration or an interleaving gain mismatch error calibration to diverge can also cause other background / blind calibrations, e.g., interleaving timing offset calibration, to diverge.

[0026] While these sections describe coherent input frequencies (such as those represented by Equation 2) as one of the problematic input conditions that would cause background / blank calibrations to diverge or fail, it is noted that there are other problematic input conditions that can also cause calibrations to diverge or fail. For example, an input signal that is a coherent square wave or other collections of coherent tones can also be problematic and cause calibrations to diverge or fail. Such an input signal can cause the data points (or amplitude points) to cluster at only a few points, repeatedly over time. Designing a qualifier to detect problematic input conditions based on histograms

[0027] To address this problem, it is possible to implement a qualifier that can detect problematic input conditions, such as coherent input frequencies. The qualifier can prevent calibration updates if valid signal conditions are not met, such as the presence of a coherent input frequency or the input signal has coherent signal energy at L∗FsK. As a result, the background / blank calibration scheme is more robust, and ADC users can avoid frequency planning. The qualifier is preferably inexpensive, simple, and effective in detecting a coherent input frequency in terms of hardware. It is not practical to extract the input frequency directly. It is more practical to implement a qualifier that can detect the problematic input conditions that are likely to cause interleaving error calibrations to fail or diverge. The qualifier can generate a qualification result to pause or freeze the interleaving error calibrations, preventing the calibrations from diverging.

[0028] Background / blank calibrations for interleaving errors may implement "block processing," where a data block of N data points (N can be from 4,000 to 64,000, or any suitable number of data points) is used to estimate an (averaged) error, an update to the interleaving error correction coefficient is calculated and applied, and the process repeats. A technical task for the qualifier is: for each data block, qualify a calibration data block, with a pass / fail as the qualification result. If the data block fails a qualification, the update is neither calculated nor applied. This means that the interleaving error correction coefficient retains its previous value. If the data block qualifies, the update is calculated and applied.Maintaining the previous value for interleaving error correction is not ideal, but it is cheaper than performing a "bad" update, which would cause the calibration to diverge. Block processing can be performed in real time or on a block of data stored in a buffer.

[0029] As through Fig. As illustrated in Figures 2-6 and the accompanying description, each sub-ADC samples a repeating "grid" of discrete data points when a coherent input frequency is present. When the input does not have a coherent input frequency, each sub-ADC will sample (over time) a diverse or wide range of data points on the input signal or sinusoid. One possible way to effectively and efficiently differentiate coherent input frequencies from non-coherent input frequencies is to use histograms.

[0030] In some embodiments, the qualifier uses a coarse histogram generated from a block of data comprising output values, e.g., output data points, output values, or amplitude points, from one of the plurality of time-interleaved ADCs (one of the M sub-ADCs, such as the sub-ADC used as the reference sub-ADC for background / blank calibration).

[0031] Note that the qualifier can output a qualification result based on the output values of any one of the M sub-ADCs. The qualifier can output a qualification result based on the output values of a sub-ADC used as the reference sub-ADC in the blank calibrations. The sub-ADC whose output values are used in the qualification process can be randomly selected. The qualifier can also apply the qualification process to more than one of the sub-ADCs if desired. The qualifier can generate multiple qualification results based on separate histograms generated from the sub-ADCs and logically combine the multiple qualification results to generate a final qualification result.

[0032] In some cases, the output data points in a 12-bit ADC may have 12 bits of data, and the amplitude points may have 11 bits of data. The coarse histogram may operate on a subset of these bits. In one example, the coarse plot is a 5-bit histogram (i.e., a histogram with 32 bins).

[0033] For non-coherent input frequencies, i.e., analog input signals that are not "bad" sinusoidal inputs (i.e., K in Equation 2 is not an integer such as 3.978), the histogram of amplitude points would appear relatively "smooth," with adjacent bins (classes, ranges) having similar numerical values. In contrast, the histogram resulting from an analog input signal with a coherent input frequency (e.g., "bad" inputs, such as K = 4 or K = 8 in Equation 2) is likely to have many empty histogram bins and a few bins with a large number of counts. This histogram is a result of a sub-ADC sampling a repeating "grid" of amplitude points.

[0034] The Fig. 7A-B, Fig. 8A-B, Fig. 9A-B, Fig. 10A-B and Fig. 11A-G are histograms of digital output signals generated from input signals with different frequencies, according to some embodiments of the disclosure. In Fig. 7A, K = 4 (where the analog input signal has a coherent input frequency), one bin of the histogram has a large count, and the rest of the bins have a count of zero (empty). In Fig. 7B, K = 4.001 (where the analog input signal has a non-coherent input frequency), the histogram is “smooth,” with many neighboring bins sharing similar bin counts. In Fig. 8A is K = 8 (where the analog input signal has a coherent input frequency), two bins have large counts, and the rest of the bins have a count of zero (empty). In Fig. 8B, K = 8.001 (where the analog input signal has a non-coherent input frequency), the histogram is “smooth,” with many neighboring bins sharing similar bin counts. In Fig. 9A, K = 12 (where the analog input signal has a coherent input frequency), three bins have large counts, and the rest of the bins have a count of zero (empty). In Fig. 9B, K = 12,001 (where the analog input signal has a non-coherent input frequency), the histogram is “smooth,” with many neighboring bins sharing similar bin counts. In Fig. 10A is K = 16 (where the analog input signal has a coherent input frequency), four bins have large counts, and the rest of the bins have a count of zero (empty). In Fig. 10B, K = 16,001 (where the analog input signal has a non-coherent input frequency), the histogram is “smooth,” with many neighboring bins sharing similar bin counts.

[0035] As at least by the Fig. 7A, Fig. 8A, Fig. 9A and Fig. 10A, as a result of having an analog input signal with a coherent input frequency, generated histograms are “clustered” in one to a few bins due to each sub-ADC repeatedly sampling the same amplitude points on a fixed “grid.” As at least Fig. 7B, Fig. 8B, Fig. 9B and Fig. As shown in Figure 10B, histograms generated as a result of having an analog input signal with a non-coherent or "nearly coherent" frequency are a relatively smooth histogram. In some cases, analog input signals with non-coherent inputs do not necessarily generate a smooth histogram. Again, referring to Fig. 10A, K = 16 (where the analog input signal has a coherent input frequency), four bins have large counts and the rest of the bins have a count of zero (empty). Fig. 11A-G show histograms generated from the output values of a sub-ADC, where the analog input signal has a non-coherent input frequency. In Fig. 11A is K = 16.2. In Fig. 11B, K = 16.4. In Fig. 11C is K = 16.6. In Fig. 11D is K = 16.8. In Fig. 11E isK = 17.0. In Fig. 11 F is K = 17.2. In Fig. 11G is K = 17.4. The histograms are only slightly smooth (compared to the Fig. 7B, Fig. 8B, Fig. 9B and Fig. 10B) and some histograms may have multiple empty bins.

[0036] A technical task of the qualifier is to distinguish histograms with one or more clusters from histograms that are smooth or somewhat smooth. Implementing such a qualifier is nontrivial. Some non-coherent input frequencies, such as K = 17.2, in Fig. 11F, may have a number of empty bins. Instead of solely evaluating the histograms based on the number of empty bins, the qualifier may detect whether the analog input signal has a coherent input frequency by evaluating a statistic of the histogram. In particular, the qualifier may evaluate a variability measure that may reflect the degree of clustering in the histograms. The present disclosure describes a variability measure that may be used to evaluate a mean deviation from the mean as a measure of smoothness. The absolute value of the deviation / difference from the mean may be used instead of squaring (commonly found in a typical variance calculation) for low-cost implementation.The variability measurement can be compared to a programmable threshold, and the comparison can be used to decide whether or not to update the calibration. A histogram can be considered a tool for roughly estimating the probability distribution function or probability mass function of the input signal.

[0037] The variability measurement V, which reflects the degree of clustering, can be formulated as follows: V=∑k=0B−1|bin[k]−μ|

[0038] B is the number of bins in the histogram. µ is the expected value for the histogram counts. The variability measurement V can be a useful statistic to evaluate, e.g., with a programmable threshold, to detect whether the analog input signal has a coherent input frequency. If the variability measurement V is above the programmable threshold, the qualifier can then determine that the data block fails qualification. If the variability measurement V is below the programmable threshold, the qualifier can then determine that the data block qualifies.

[0039] In other words, the variability measure V is a sum of distances of counts bin[k] in the bins of the qualifying histogram from a mean count µ of the qualifying histogram (e.g., |bin[k] - µ|). An absolute value of the difference of the count from the mean count, bin[k] - µ, is used as the distance / deviation for a lower-cost implementation. Alternatively, the difference of the count from the mean count, bin[k] - µ, can be squared, i.e., (bin[k] - µ) 2 .

[0040] The mean count µ of the qualifying histogram can be an expected value for counts of the qualifying histogram. In other words, the qualifier determines the degree of clustering by summing differences in counts between the qualifying histogram and a uniform histogram. A uniform histogram is a flat histogram where each bin has an equal count, i.e., the expected value for counts of the qualifying histogram. The expected value for counts can be a total count of a histogram divided by a number of bins. For example, if a total count is 2048 and the histogram has 32 bins, then µ = 64.

[0041] The intuition behind the variability measurement V is that the calculation would measure how far the qualifying histogram would be from a perfectly smooth and flat histogram (i.e., a uniform histogram). In other words, the calculation can measure the degree of smoothness. If the analog input signal has a coherent input frequency, a sub-ADC would repeatedly sample an equal number of amplitude points, resulting in a histogram with one or more clusters. As a result, the histogram would yield a high variability measurement V. If the analog input signal has a non-coherent input frequency, a sub-ADC would sample a large range of amplitude points over time, resulting in a smooth or somewhat smooth histogram. As a result, the histogram would yield a low variability measurement V.

[0042] The variability measurement V could be modified in a number of ways to achieve the same goal. After a crude histogram is constructed to estimate the probability distribution function or probability mass function of the unknown input signal, the qualifier can evaluate a statistic of the histogram to obtain a qualification result (e.g., pass or fail). For example, instead of comparing the histogram to a uniform histogram, the qualifier can compare the histogram to some other expected histogram with a different and possibly more realistic or expected shape, such as a Gaussian histogram or an exponential histogram, etc. The shape of the histogram can be chosen to optimize the accuracy of the qualifier.The uniform histogram comparison is an example histogram that can be used to calculate the variability measurement V. The uniform histogram comparison can be advantageous because it is easy and inexpensive to implement in hardware.

[0043] The qualifier does not need to specifically determine or identify that an input signal has a coherent input frequency or other underlying causes of calibration divergence problems. However, the qualifier is implemented to determine whether a sub-ADC's output values meet one or more qualifying conditions. If the qualifier determines that one or more qualifying conditions are met, the qualifier can infer that the problematic input conditions exist and pause the calibrations. For example, the qualifier can assess the degree of diversity, variability, or "richness" in a sub-ADC's output values and use that degree to dictate whether the calibrations should be paused. The qualifier can compare the qualification histogram to an expected histogram.The qualifier can compare the variability measurement to a threshold. Such evaluations detect whether the qualification histogram meets one or more qualifying conditions, but do not specifically determine the input frequency.

[0044] Details of the qualifier architecture and processes are described in the following paragraphs. Considerations for the qualifier: different signal ranges and threshold sensitivity

[0045] One consideration to keep in mind when using a histogram is that the signal range or amplitude of the analog input signal can vary significantly. Ideally, the qualifier and any interleaving error calibration would work properly for relatively small input signals (e.g., down to at least about -30 dB) and relatively large signals. Fig. 12 and Fig. 13 show plots of input frequency versus histogram variability measurement for two input signals with different signal ranges according to some embodiments of the disclosure. In Fig. 12, the signal is at -0.1 dB, and the full range of the histogram is expected to be applied. In Fig. 13, the signal is at -5.9 dB, which would only occupy half the range of the histogram. Note that the variability measurement changes depending on the signal range of the analog input signal. For example, the "floor" of the variability measurement decreases from Fig. 12 to Fig. 13 from ∼]700 to ∼1900.

[0046] Another consideration to take into account is the sensitivity of the threshold. A suitable threshold preferentially allows false positives while aggressively ensuring that there are no or very few false negatives. Allowing false positives means that a qualification would fail, i.e., the threshold check would not pass for some histograms, even if the data block is not a result of an analog input signal with a coherent input frequency. This plays it safe and pauses the calibration update even when it is not needed. Aggressively blocking false negatives prevents a calibration update when it should not update due to the coherent input frequency. For these reasons, Fig. 12-13, a suitable threshold value could be set to -2300 to evaluate the variability measurement.

[0047] Another consideration to take into account is complexity. The histograms mentioned herein can operate exclusively on the most significant bits (e.g., a small number of most significant bits) of a sub-ADC's output values. The histogram does not require the use of all bits of the output values (the least significant bits are not needed for the qualifier). Using only the most significant bits to construct the histogram can significantly reduce complexity and make the qualifier more efficient. Furthermore, the bin counts can be truncated to a certain number of bits as well for additional complexity reduction. The number of bins in a histogram can also contribute to complexity if too many bins are used. Furthermore, too many bins or too few bins can result in a poor histogram that is not informative or useful for the qualifier.A 5-bit histogram with 32 bins may be adequate for some applications. Preferably, a coarse histogram of the sub-ADC's output values is used, and the qualifier is implemented to process a coarse histogram while still achieving the desired sensitivity and performance for the target application. Data block processing and qualification

[0048] Fig. 14 is a flowchart illustrating an exemplary method for qualifying data used for a background / blank calibration of interleaving errors, according to some embodiments of the disclosure. In 1402, a data block is acquired. The data block includes (digital) output values generated by one of the multiple time-interleaved analog-to-digital converters (one of the sub-ADCs). An optional buffer, e.g., buffer 120 of Fig. 1, may be included to store a data block comprising values generated by one of the plurality of time-interleaved analog-to-digital converters. In some embodiments, a qualification histogram may be generated by a histogram function, e.g., 170 of Fig. 1 in qualifier 122, based on the values generated by one of the multiple time-interleaved analog-to-digital converters. Depending on the implementation, the histogram function can run in real time (eliminating the need to store the values in a buffer). In 1404, the data block is qualified by evaluating a variability measurement of a qualification histogram generated from the data block. A qualifier, e.g., qualifier 122 of Fig. 1, can measure a degree of clustering in a qualification histogram generated from the data block and output a qualification result based on the degree of clustering. In response to determining that the data block fails qualification (“N” path of 1404), an update to the background / blank calibration of the interleaving error is skipped (1406). In response to determining that the data block qualifies (“Y” path of 1404), the data block is used to update the background / blank calibration of the interleaving error (1408). An interleaving error calibration engine (interleaving error calibration automaton), e.g., interleaving error calibration engine 150 of Fig. 1, can be controlled by a qualification result from the qualifier. The qualification result dictates whether the interleaving error calibration engine should maintain a previous value of an interleaving error correction coefficient or update an interleaving error correction coefficient.

[0049] In some embodiments, the data block comprises uncorrected (digital) output values generated by one of the plurality of time-interleaved analog-to-digital converters (one of the sub-ADCs) (e.g., D out0 , D out1 , ... D outM-1 ). In some embodiments, the data block has corrected (digital) output values generated by one of the plurality of time-interleaved analog-to-digital converters (one of the sub-ADCs) (e.g., D out0_cal , D out1_cal , ... D outM-1_cal ).

[0050] Again with reference to Fig. 11, the interleaving error calibration engine 150 of Fig. 1 an interleaving error extractor 124 to derive the interleaving error and to generate an interleaving error correction coefficient (e.g. e0, e1, ... e M ) based on the interleaving error. For example, the interleaving error extractor 124 can derive the interleaving error from corrected output values (e.g., D out0_cal , D out1_cal , ... D outM-1_cal ). The Interleaving Error Calibration Engine 150 of Fig. 1 may further comprise an interleaving error correction block 126 for determining an interleaving error correction coefficient (e.g., e0, e1,... e M-1 ) to reduce the interleaving error. The interleaving error correction coefficient can be digitally applied to the uncorrected output values generated by the multiple time-interleaved analog-to-digital converters (e.g., D out0 , D out1 , ... D outM-1 ) can be applied to generate corrected output values (e.g. D out0_cal, D out1_cal , ... D outM-1_cal ). A data combiner 130 can process the corrected output values (e.g., D out0_cal , D out1_cal , ... D outM-1_cal ) to produce a final output D out to generate. Adapting to a signal range

[0051] As discussed previously, signal range can dramatically change the variability measurement. A small signal may appear clustered in a few bins of the histogram because not the full range of the histogram is applied, which could cause the data block to unnecessarily fail qualification. To address this problem, the qualifier can perform a signal range check or perform a signal range estimation and adjust the qualifier according to the signal range. In some cases, a qualifier can use a subset of the output values from a sub-ADC for this purpose (e.g., during the first half of a calibration cycle) and use the rest of the output values (or all of the output values) to construct a qualification histogram (e.g., during the second half of a calibration cycle).In some embodiments, a range histogram may be generated based on a first portion of the data block (e.g., the subset of output values). A signal range may be estimated based on the range histogram. A qualifying histogram may be generated according to the signal range based on the second portion of the data block (e.g., the remainder of the output values). If the signal does not change frequently, this signal range estimation may be skipped in some cycles.

[0052] Fig. 15 is a flowchart illustrating another example method for qualifying data used in background / blank calibration of interleaving errors, according to some embodiments of the disclosure. At 1502, a signal range of the data block is determined. In some embodiments, the signal range may be determined based on a range histogram generated from the subset of output values. One or more upper empty bins of the range histogram are an indicator of the signal range. For a smaller signal, the upper bins would remain empty, as a small signal cannot utilize the full range of the range histogram.

[0053] In 1504, a range for the qualification histogram can be set based on the signal range. For example, the upper limit of the range for the qualification histogram can be shifted to the point where the one or more upper empty bins begin.

[0054] At 1506, one or more programmable thresholds may be set for evaluating the qualification histogram variability measurement based on the signal range. This feature may allow the signal range threshold to be adjusted such that an optimal threshold with the appropriate sensitivity can be used for different signal ranges.

[0055] In 1508, a qualification histogram is generated, e.g., based on the range set in 1504 using the remainder of the output values. The qualification histogram can be generated using only the most significant bits (e.g., [MSB-1:MSB-5]) or some bits below the most significant bits (e.g., [MSB-3:MSB-8]). The latter operates by classifying any output values above the range into the top bin and classifying any output value below the range into the bottom / zero bin. For a given range of the qualification histogram, values above the upper limit of the range are collected in the highest (or "top") histogram bin. Based on the qualification histogram, one or more checks can be performed in 1508 to generate the qualification result.

[0056] Fig. 16 is a flowchart illustrating an example method for qualifying a block of data according to some embodiments of the disclosure. Fig. Figure 17 shows exemplary components within a qualifier 122 that are used to implement one or more parts of Fig. 15 and Fig. 16 may be used, according to some embodiments of the disclosure.

[0057] The range estimator 1702 may determine a signal range estimate of the data block and configure a range of the qualification histogram based on the signal range estimate (e.g., 1502 of Fig. 15). For example, if the signal spans +0 to +2047 codes and a 5-bit histogram is used, then each histogram bin is normally expected to contain 2048 / (2 5) = 64 codes. Thus, bin 0 (the lowest) would be any codes from 0 to 63, bin 1 from 64 to 127, ... and bin 31 (the highest) would be codes 2016 to 2047. These expectations assume a full-scale input signal. If the signal were -18 dB below, then only 1 / 8 of the bins would ever be applied. This would cause those 12% of bins to be very large and the other 88% of bins to be empty, likely causing a variability measurement test to fail. Thus, a signal range estimation is first performed using a range histogram, then a range of the qualification histogram is set to the maximum non-zero bin value of the range histogram. Digital hardware (e.g., histogram function 170 of Fig. 1) is already implemented to generate a qualification histogram, so the same hardware used to generate the qualification histogram can be reused to generate the range histogram. In other words, the upper limit of the qualification histogram's range slides / scales to correspond to where consecutive empty bins stop from the top of the range histogram. In this specific example, if the signal were -18 dB lower, the range histogram would show that the highest non-zero bin value of the range histogram was bin 4. The upper limit of the qualification histogram can be adjusted so that the maximum value is +256 (instead of +2048), and the bin width is now 256 / 32 = 8. Shifting the range of a histogram can adjust the range by powers of 2, e.g., to ½ full scale, ¼ full scale, etc.Assuming that the signal range does not change, the qualification histogram should have more than half of zero different bins.

[0058] Again with reference to Fig. 16 illustrates the flow chart in Fig. 16 the one or more tests taken in 1508 on the qualification histogram of Fig. 15 can be performed. The qualifier can be implemented in such a way as to play it safe, allowing data blocks to fail a qualification even if it is not a result of a coherent input frequency.

[0059] In 1602, the qualifier may determine that the data block fails qualification in response to determining that a number of empty bins in the qualifying histogram exceeds a threshold. For example, if a number of empty bins exceeds half the total number of bins, the data block would fail qualification. This check may verify that the range calculation was correct and the input signal has not shifted within the signal range (since the qualifying histogram is generated based on the remainder of the output values not used in the range histogram). This check may also quickly verify whether the qualifying histogram is indeed one that has a lot of clustering with many empty bins (an indicator of a coherent input frequency). In some embodiments, a fast clustering check 1704 may be performed by Fig. 17 determine whether a number of empty bins of the qualifying histogram exceeds a threshold.

[0060] At 1604, the qualifier may determine that the data block fails qualification in response to determining that a count in a highest bin or a count in a lowest bin in the qualifying histogram exceeds a threshold. This check is to ensure that the range set for the qualifying histogram is reasonable. Intuition dictates that these edge cases, where the highest bin or the lower bin has an unexpectedly high bin count, could indicate that the signal is smaller or larger than the range estimated from the range histogram. Referring again to the example given for the range estimator 1702, note that the top bin of the qualifying histogram would be hit whenever the signal is "greater than 248" (all values above 256 go into the top bin).If the signal level changes or an error was made in the range estimation, then our top bin of the qualifying histogram may be hit many times, perhaps about 50%+. On the other side of the qualifying histogram, if the signal is actually smaller than the estimated range, the bottom bin could receive many hits. While these edge cases may cause the variability measurement test itself to fail, the additional check 1604 may verify that the counts for the top or bottom bin are on the safe side. In some embodiments, if a predetermined percentage of the total count is in the top or bottom bin of the qualifying histogram, the data block would fail qualification (because a bad range was used). In some embodiments, a bad range check 1706 may be performed. Fig. 16 determine whether a count of a highest bin of the qualifying histogram or a count of a lowest bin of the qualifying histogram exceeds a threshold. The threshold may be programmable.

[0061] At 1506, the qualifier may determine that the data block fails qualification in response to determining that the variability measurement of the qualifying histogram exceeds a programmable threshold. For example, the qualifier may determine the variability measurement based on Equation 3. In some cases, the bin counts are truncated to reduce complexity, and the variability measurement is calculated based on an expected value of the truncated bin counts. For example, if the bin counts of a 5-bit histogram (32 bins) are truncated to 11 bits, then the expected value is μ=21132=204832=64. In some embodiments, a cluster measurement test 1708 of Fig. 17 determine the qualification result by comparing the degree of accumulation (e.g., the variability measure of equation 3) with a programmable threshold. Examples

[0062] Example 1 is a method for preventing performance degradation of a blind interleaving error calibration of a plurality of time-interleaved analog-to-digital converters, the method comprising: acquiring a data block having output values generated by one of the plurality of time-interleaved analog-to-digital converters; qualifying the data block by evaluating a variability measurement of a qualification histogram generated from the data block; in response to determining that the data block fails qualification, skipping an update of the blind interleaving error calibration; and in response to determining that the data block qualifies, using the data block to update the blind interleaving error calibration.

[0063] In Example 2, the method of Example 1 can optionally comprise qualifying the data block, comprising: determining a signal range based on the data block.

[0064] In Example 3, the method of Example 2 can optionally comprise qualifying the data block, comprising: setting a range for the qualification histogram based on the signal range.

[0065] In example 4, the method of example 2 or 3 can optionally comprise qualifying the data block, comprising: setting one or more programmable thresholds to evaluate the variability measurement of the qualification histogram based on the signal range.

[0066] In Example 5, the method of any of Examples 1-4 can optionally comprise qualifying the data block, comprising: generating a range histogram based on a first portion of the data block; estimating a signal range based on the range histogram; and generating a qualifying histogram according to the signal range based on a second portion of the data block.

[0067] In Example 6, the method of any of Examples 1-5 can optionally comprise qualifying the data block, comprising: determining that the data block fails qualification in response to determining that a number of empty bins in the qualifying histogram exceeds a threshold.

[0068] In Example 7, the method of any of Examples 1-6 can optionally comprise qualifying the data block, comprising: determining that the data block fails qualification in response to determining that a count in a highest bin or a count in a lowest bin in the qualifying histogram exceeds a threshold.

[0069] In Example 8, the method of any of Examples 1-7 can optionally comprise qualifying the data block, comprising: determining that the data block fails qualification in response to determining that the variability measurement of the qualifying histogram exceeds a programmable threshold.

[0070] In Example 9, the method of any of Examples 1-8 can optionally comprise qualifying the data block, comprising: calculating a sum of distances of counts in bins of the qualifying histogram from a mean count of the qualifying histogram. In some cases, the mean count of the qualifying histogram is an expected value for counts of the qualifying histogram.

[0071] In Example 10, the method of any of Examples 1-9 can optionally comprise qualifying the data block, comprising: comparing the qualifying histogram to an expected histogram; and evaluating the variability measure based on the comparison.

[0072] Example 11 is a blind calibration system for calibrating an interleaving error of a plurality of time-interleaved analog-to-digital converters, the blind calibration system comprising: a histogram function for generating a qualification histogram based on values generated by one of the plurality of time-interleaved analog-to-digital converters; a qualifier for measuring an amount of clustering in the qualification histogram and outputting a qualification result based on the amount of clustering; and an interleaving error calibration engine controllable by a qualification result from the qualifier.

[0073] In Example 12, the blind calibration system of Example 11 can optionally include the qualifier comprising: a range estimator to determine a signal range estimate of the values generated by the one of the plurality of time-interleaved analog-to-digital converters and configuring a range of the qualification histogram based on the signal range estimate.

[0074] In Example 13, the blind calibration system of Example 11 or 12 can optionally include the qualifier determining the qualification result by comparing the amount of accumulation to a programmable threshold.

[0075] In Example 14, the blind calibration system of any of Examples 11-13 can optionally include the qualifier determining the amount of clustering by summing differences in counts between the qualifying histogram and an expected histogram.

[0076] In Example 15, the blind calibration system of any of Examples 11-14 can optionally include the qualifier comprising: a fast accumulation check to determine whether a number of empty bins of the qualifying histogram exceeds a threshold.

[0077] In Example 16, the blind calibration system of any of Examples 11-15 can optionally include the qualifier comprising: a bad range check to determine whether a count of a highest bin of the qualifying histogram or a count of a lowest bin of the qualifying histogram exceeds a threshold.

[0078] In Example 17, the blind calibration system of any of Examples 11-16 can optionally include the qualification result dictating whether the interleaving error calibration engine should maintain a previous value of an interleaving error correction coefficient or update an interleaving error correction coefficient.

[0079] In Example 18, the blind calibration system of any of Examples 11-17 can optionally include the interleaving error calibration engine comprising: an interleaving error extractor for deriving the interleaving error and updating an interleaving error correction coefficient based on the interleaving error; and an interleaving error correction block for applying an interleaving error correction coefficient to reduce the interleaving error.

[0080] Example 19 is an analog-to-digital converter comprising: a plurality of time-interleaved means for sampling an analog input signal according to a rotation sequence; means for extracting an interleaving error by observing values generated by one of the plurality of time-interleaved means; and digital processing means for detecting whether the analog input signal satisfies one or more qualifying conditions and outputting a qualifying result for controlling a state of the means for extracting the interleaving error.

[0081] In Example 20, the analog-to-digital converter of Example 19 can optionally comprise the digital processing means comprising: means for evaluating statistics of a qualifying histogram generated based on the values generated by the one of the plurality of time-interleaved means.

[0082] Example 21 is an apparatus for performing any of the methods described herein. Modifications and implementations

[0083] Please note that FsK is a general problem case (as seen in Equation 2) where there are only K discrete data points to be sampled. Within this general problem case, there are two scenarios. The first scenario is that K=k*M, where k and M are integers and M is the number of sub-ADCs. The second scenario involves other values of K.

[0084] In the first scenario, the input signal is not only synchronous or coherent with the ADC, but also with the sub-ADCs. This means that each Sub-ADW1M of the discrete K data points in the signal. For example, with two sub-ADCs (M=2) and Fs2 than the input frequency K=2 discrete data points (and one amplitude point). Since K=2=1*M, each sub-ADC samples one of the two discrete data points. With Fs8 than the input frequency, each sub-ADC samples 4 of the 8 discrete data points (or 2 of the 4 amplitude points).

[0085] In the second scenario, the input signal is not synchronous or coherent with the sub-ADC. This means that, on average, even though there are only K discrete data points in the s-signal, each sub-ADC samples all K data points evenly over time, so calibration may not be affected. A qualifier may still fail in such a scenario if K is very small (e.g., K = 3), because the qualifier considers the "richness" or diversity of amplitude values in the qualification histogram of a single sub-ADC. If desired, the qualifier can be implemented to qualify multiple sub-ADCs separately and compare the qualification results to detect such a case.However, for efficiency and simplicity, a qualifier can be designed to fail in such a case to be more cautious (assuming that the ADC does not see such input frequencies for a longer period of time).

[0086] In some embodiments, an ADC (e.g., a Fig. 1) comprises a plurality of time-interleaved means (e.g., subADC[0] 112, subADC[1] 114, ... and subADC[M-1] 116) for sampling an analog input signal according to a rotation sequence. The ADC further comprises means for extracting an interleaving error (e.g., interleaving error calibration engine 150 of Fig. 1) by considering values generated by one of the plurality of time-interleaved means. The ADC may further comprise digital processing means for detecting whether the analog input signal satisfies one or more qualifying conditions (e.g., the absence of a coherent input frequency) and outputting a qualification result to indicate a state of the means for extracting the interleaving error (e.g., qualifier 122 of Fig. 1 and Fig.17). The qualifying conditions are chosen to reduce the risk of the background / blank calibrations diverging or failing, e.g., to prevent a "bad" calibration update based on "bad" data. The digital processing means may include means for evaluating a statistic of the qualified histogram generated based on the values generated by the one of the plurality of time-interleaved means. The digital processing means may comprise one or more of the following: dedicated digital hardware, digital logic, and one or more processors configured to execute instructions to perform the methods described herein.

[0087] In some embodiments, the variability measure could be calculated only over the non-zero bins of the qualifying histogram with a corresponding average of the bin counts for the non-zero bins.

[0088] In some embodiments, increasing the number of histogram bins increases complexity but may increase the accuracy of detecting coherent input frequencies.

[0089] In some embodiments, adjusting the scaling of output values going into the qualifying histogram to values other than exponents of 2 (e.g., the equivalent of fetching most significant bits) increases complexity but may increase the accuracy of detecting coherent frequencies.

[0090] In some cases, instead of using a histogram, it is possible to perform autocorrelation to detect coherent input frequencies. The qualifier can then compare peaks of the autocorrelation with a programmable threshold. However, this autocorrelation scheme can be much more expensive in terms of power and area than using a coarse histogram.

[0091] In some cases, it is possible to implement a notch filter before the interleaving error calibration engine averagers to filter out the coherent input frequencies to address the divergence issue. However, a notch filter that covers all coherent input frequencies can easily require hundreds of filter cuts and can also generate nulls and gain variations between the nulls, which can exacerbate other problems.

[0092] In some cases, time-interleaved ADCs have a reference ADC to help the background calibration scheme converge to the optimal interleaving error correction coefficient. The reference ADC, if selected to sample the analog input, can sample the analog input signal at essentially the same time as another selected sub-ADC. While this can help address the background calibration problem discussed herein, it requires an additional ADC and additional timing circuitry to select the reference ADC accordingly. Therefore, having a reference ADC is not always practical. If a reference ADC is not practical, then schemes for addressing problematic input conditions are advantageous in preventing calibration failure.

[0093] ADCs are found in many places, such as broadband communication systems, audio systems, receiver systems, etc. ADCs can translate analog electrical signals representing real-world phenomena, such as light, sound, temperature, or pressure, for data processing purposes. Designing an ADC is a nontrivial task because each application may have different requirements regarding performance, power, cost, and size. ADCs are used in a wide range of applications, including communications, energy, healthcare, instrumentation and measurement, motor and power control, industrial automation, and aerospace / defense.

[0094] The features discussed herein can be applicable to transducers used in a wide variety of applications. The features described herein are particularly applicable to systems where linearity is important. Various example applications include medical systems, scientific instrumentation, transportation systems, aerospace systems, wireless and wired communications, radar, industrial process control, audio and video equipment, consumer appliances, and other transducer-based systems.

[0095] Portions of various devices for qualifying a data block may include electronic circuitry to perform the functions described herein. In some cases, one or more portions of the device may be provided by an on-chip processor or controller specifically configured to perform the functions described herein. For example, the on-chip processor or controller may include one or more application-specific components or may include programmable logic gates configured to perform the functions described herein. The circuitry may operate in the analog domain, the digital domain, or a mixed-signal domain (but preferably, the digital domain).In some cases, the processor or controller may be configured to perform the functions described herein by executing one or more instructions stored in a non-transitory computer medium accessible by the on-chip processor or controller.

[0096] In one embodiment, the chip (or integrated circuit) providing the converter and the on-chip processor may be provided on a circuit board of an associated electronic device. The circuit board may be a general-purpose circuit board that may hold various components of the internal electronic system of the electronic device and further provide connectors for other peripherals. For example, the chip with the converter and the on-chip processor may communicate with the components of the associated electronic device (e.g., signal generators, processors, memory, transmitters, receivers, etc.). In particular, the circuit board may provide the electrical connections through which the other components of the system can communicate electrically. Any suitable processors (including digital signal processors, microprocessors, supporting chipsets, etc.), computer-readable non-volatile memory elements, etc., can be appropriately coupled to the board based on specific training needs, processing requirements, computer designs, etc. Other components, such as external storage, additional sensors, audio / video display controllers, and peripherals, can be attached to the board as plug-in cards, via cables, or integrated into the board itself.

[0097] It is important to note that all of the specifications, dimensions, and relationships outlined herein (e.g., the number of processors, logic operations, etc.) have been offered for purposes of example and teaching only. Such information may vary considerably without departing from the spirit of the present disclosure or the scope of the examples and appended claims. The specifications are for a non-limiting example only and should be construed as such. In the above description, embodiments have been described with reference to a particular processor and / or component arrangements. Various modifications and changes may be made to such embodiments without departing from the scope of the examples and appended claims.The description and drawings are therefore to be regarded in an illustrative rather than a restrictive sense.

[0098] Note that throughout this specification, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in "one embodiment," "an embodiment," "another embodiment," "some embodiments," "various embodiments," "other embodiments," an "alternative embodiment," and the like are intended to mean that such features are included in one or more embodiments of the present disclosure, but may or may not necessarily be combined in the same embodiments.

[0099] It is also important to note that the functions described herein illustrate only some of the possible functions that may be performed by or within systems depicted in the FIGURES. Some of these operations may be deleted or removed where appropriate, or these operations may be significantly modified or altered without departing from the scope of the present disclosure. Furthermore, the timing of these operations may be significantly altered. The foregoing operational flows have been presented for purposes of example and discussion. Considerable flexibility is provided by embodiments described herein in that any suitable arrangements, chronologies, configurations, and timing mechanisms may be provided without departing from the teachings of the present disclosure.

[0100] Numerous other changes, substitutions, variations, alterations, and modifications may be discovered by those skilled in the art, and this disclosure is intended to include all such changes, substitutions, variations, alterations, and modifications as falling within the scope of the examples and appended claims. It should be noted that any optional features of the apparatus described above may also be implemented with respect to the method or process described herein, and features in the examples may be used anywhere in one or more embodiments.

[0101] In one aspect, an ADC may include multiple time-interleaved ADCs to increase the overall sampling rate of the ADC. Such an ADC may have interleaving errors because the time-interleaved ADCs within the ADC are not always perfectly matched. One way to calibrate for these mismatches is to observe the digital output signals of the time-interleaved ADCs in the background, or more generally, without knowledge of the input signal to the ADC (often referred to as "blind calibration"). Due to the nature of these calibrations, the performance of the calibration would degrade significantly if the input signal has certain problematic input conditions, such as a certain coherent input frequency. To address this issue, the data used for interleaving error calibration may undergo a qualification process to assess whether error estimates should be updated based on the data.

Claims

[1] A method for preventing performance degradation of a blind calibration of an interleaving error of a plurality of time-interleaved analog-to-digital converters, the method comprising: Acquiring a block of data comprising output values generated by one of the plurality of time-interleaved analog-to-digital converters; Qualifying the data block by evaluating a variability measurement of a qualification histogram generated from the data block; in response to determining that the data block fails qualification, skipping an update of the interleaving error blind calibration; and in response to determining that the data block qualifies, using the data block to update the blind calibration of the interleaving error. [2] The method of claim 1, wherein qualifying the data block comprises: Determine a signal range based on the data block. [3] The method of claim 2, wherein qualifying the data block comprises: Set a range for the qualification histogram based on the signal range. [4] The method of claim 2 or 3, wherein qualifying the data block comprises: Setting one or more programmable thresholds to evaluate the qualification histogram variability measurement based on the signal range. [5] A method according to any preceding claim, wherein qualifying the data block comprises: Generating a range histogram based on a first part of the data block; Estimating a signal range based on the range histogram; and Generating a qualifying histogram according to the signal range based on a second part of the data block. [6] A method according to any preceding claim, wherein qualifying the data block comprises: Determining that the data block fails a qualification in response to determining that a number of empty bins in the qualifying histogram exceeds a threshold. [7] A method according to any preceding claim, wherein qualifying the data block comprises: Determining that the data block fails a qualification in response to determining that a count in a highest bin or a count in a lowest bin in the qualifying histogram exceeds a threshold. [8] A method according to any preceding claim, wherein qualifying the data block comprises: Determining that the data block fails a qualification in response to determining that the variability measurement of the qualifying histogram exceeds a programmable threshold. [9] A method according to any preceding claim, wherein qualifying the data block comprises: Calculating a sum of distances of counts in bins of the qualifying histogram from a mean count of the qualifying histogram. [10] A method according to any preceding claim, wherein qualifying the data block comprises: Comparing the qualifying histogram with an expected histogram; and Evaluate the variability measurement based on the comparison. [11] Blind calibration system for calibrating an interleaving error of a plurality of time-interleaved analog-to-digital converters, the blind calibration system comprising: a histogram function (170) for generating a qualification histogram based on values generated by one of the plurality of time-interleaved analog-to-digital converters; a qualifier (122) for measuring a degree of clustering in the qualification histogram and outputting a qualification result based on the degree of clustering; and an interleaving error calibration engine (150) that can be controlled by a qualification result from the qualifier (122). [12] The blind calibration system of claim 11, wherein the qualifier (122) comprises: a range estimator (1702) for determining a signal range estimate of the values generated by the one of the plurality of time-interleaved analog-to-digital converters and configuring a range of the qualification histogram based on the signal range estimate. [13] The blind calibration system of claim 11 or 12, wherein the qualifier (122) determines the qualification result by comparing the amount of accumulation to a programmable threshold. [14] A blind calibration system according to any one of claims 11 to 13, wherein the qualifier (122) determines the extent of accumulation by summing differences in counts between the qualifying histogram and an expected histogram. [15] A blind calibration system according to any one of claims 11 to 14, wherein the qualifier (122) comprises: a fast clustering check (1704) to determine whether a number of empty bins of the qualifying histogram exceeds a threshold. [16] A blind calibration system according to any one of claims 11 to 15, wherein the qualifier (122) comprises: a bad range test (1706) to determine whether a count of a highest bin of the qualifying histogram or a count of a lowest bin of the qualifying histogram exceeds a threshold. [17] A blind calibration system according to any one of claims 11 to 16, wherein the qualification result dictates whether the interleaving error calibration engine (150) should hold a previous value of an interleaving error correction coefficient or update an interleaving error correction coefficient. [18] A blind calibration system according to any one of claims 11 to 17, wherein the interleaving error calibration engine (150) comprises: an interleaving error extractor (124) for deriving the interleaving error and updating an interleaving error correction coefficient based on the interleaving error; and an interleaving error correction block (126) for applying an interleaving error correction coefficient to reduce the interleaving error. [19] Analog-to-digital converter, comprising: a plurality of time-interleaved means for sampling an analog input signal (v in ) according to a rotation sequence; Means for extracting an interleaving error by observing values generated by one of the plurality of time-interleaved means; and digital processing means for determining a degree of variability in the values generated by one of the plurality of time-interleaved means and outputting a qualification result based on the degree of variability for controlling a state of the means for extracting the interleaving error. [20] An analog-to-digital converter according to claim 19, wherein the digital processing means comprises: Means for evaluating a statistic of a qualifying histogram generated based on the values generated by the one of the plurality of time-nested means.

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