Converter technologies for receiving and supplying electricity

Abstract

Power stage circuit (102) for a switching converter (100, 101), wherein the power stage (102) comprises: a first detector circuit (223) for receiving a signal indicating the conduction of an inverse diode of a first power transistor, the first power transistor being used to couple a first supply node to an intermediate node; a second detector circuit (224) for receiving a signal indicating the conduction of an inverse diode of a second power transistor, the second power transistor being used to couple a second supply node to the intermediate node; an output node for supplying a load from an inductor (104), the inductor (104) being coupled between the output node and the intermediate node;and a control and / or regulating unit (220) configured to operate the first and second power transistors in such a way as to prevent conduction of the inverse diode through the first and second power transistors, wherein the control and / or regulating unit (220) comprises: a first switching logic for a first operating mode; and a second switching logic for a second operating mode; wherein the control and / or regulating unit (220) is communicatively coupled to the first and second detector circuits; and wherein the control and / or regulating unit (220) is configured to isolate control nodes of the first and second power transistors from the first switching logic using a first multiplexer (335) in response to a first inverse diode conduction event indication.

Description

Technical Field of DisclosureThe present subject matter discusses voltage converters, and more specifically, techniques for switching between operating modes of a voltage converter.BackgroundBuck converters are known to efficiently step down a voltage from an input supply for use by a load connected to an output of the buck converter. Synchronous buck converters may receive current from or output current to the output. However, various situations, such as when a current limit is violated, result in the buck converter operating with a forward biased inverse diode of one of the switches. Such operation may limit the efficiency of the buck converter.SummaryTechniques are provided for a power stage serving as a current sink and as a current source. In one example, a power stage circuit may include a first power transistor configured to couple to a first input current rail, a second power transistor configured to couple to a second input current rail, an output node configured to couple to a load and couple the first power transistor in series with the second power transistor between the first and second input current rails, and a controller configured to operate the first and second power transistors in a first mode to provide current to the load and to operate the first and second power transistors in a second mode to receive current from the load.This summary is intended to provide an overview of the subject matter of the present patent application. It is not intended to provide an exclusive or exhaustive explanation of the invention. The detailed description is included to provide further information about the present patent application.US 2011 / 0 163 731 A1 shows a method for providing threshold voltage monitoring and control in synchronous converters. The method includes establishing a threshold voltage level for a gate drive voltage for upper and lower power switches in a synchronous power converter, each threshold voltage level controlling a switching delay time for one of the upper and lower power switches. The method further includes sensing body diode conduction levels for at least one of the upper and lower power switches and adjusting the threshold voltage level for at least one of the upper and lower power switches based on the sensed body diode conduction levels to fine tune a body diode conduction time around a balance for the at least one of the upper and lower power switches.US 2013 / 0 334 878 A1 describes a method for balancing current in a vehicle electrical system having a system bus, a first battery, a first bi-directional battery voltage converter that selectively transfers a first current between the first battery and the system bus, a second battery, a second bi-directional battery voltage converter that selectively transfers a second current between the second battery and the system bus, and a controller that controls the first bi-directional battery voltage converter and the second bi-directional battery voltage converter.US 2010 / 0 164 446 A1 describes a bidirectional DC-DC converter having a simplified circuit configuration. Each output of the high voltage detection circuit and the low voltage detection circuit is input to the high voltage side error amplifier circuit and the low voltage side error amplifier circuit, which are independently arranged and have an inverse polarity. The output of the high-voltage-side error amplifier circuit or the output of the low-voltage-side error amplifier circuit is selected by the conversion direction switching circuit. The output is input to the control circuit from the PWM comparison circuit, thereby driving the first switching element and the second switching element.An object of the present invention could be to at least partially overcome the disadvantages known in the prior art. This object is achieved by the independent patent claims. Advantageous embodiments are evident from the dependent claims.Brief Description of the DrawingsIn the drawings, which are not necessarily to scale, like reference numerals may designate similar components in different views. Like reference numerals with different letter additions may designate different instances of like components. The drawings generally illustrate, without limitation, various embodiments described in the present document. FIGS. 1A and 1B generally show buck converters that include an example power stage according to the present subject matter. FIG. 2 generally shows a more detailed view of the example power stage. FIG. 3 generally illustrates an example controller in accordance with the present subject matter. FIGS. 4A and 4B generally show example circuitry for the first and second modes of operation. FIG. 5 illustrates an example system including a load that is differentially driven using two example power converters, in accordance with the present subject matter. FIG. 6 generally illustrates a flowchart of an example method of operating a power stage in accordance with the present subject matter.Detailed DescriptionThe present inventor has recognized important techniques for operating a synchronous buck converter. In certain examples, the techniques may include switching an operating mode of the buck converter when a current limit threshold is detected. The mode change may help to operate the buck converter more efficiently. In some examples, the techniques include detecting a forward bias of an inverse diode of a switch of the buck converter and directing that switch to a low impedance mode to conduct current more efficiently. In certain examples, the techniques discussed herein may enable more efficient and reliable performance of a monolithic buck converter. A monolithic buck converter may provide a power stage that may receive a pulse width modulated (PWM) signal, alternately switch first and second power switches of the buck converter according to the PWM signal to provide a desired output voltage or current. Additionally, the monolithic buck converter may be a single semiconductor chip, which may include the power switches, sensors, and a controller to provide the techniques outlined above. In certain examples, a monolithic buck converter according to the present subject matter may be used to differentially feed a load, such as, but not limited to, a motor, such as a stepper motor, or a thermoelectric device.FIGS. 1A and 1B generally show buck converters 100, 101 including an example power stage 102 in accordance with the present subject matter. The voltage converters 100, 101 may include an oscillator 103, the power stage 102, an inductor 104, a feedback circuit 105, 107, an output capacitor 106. The voltage converter 100 of FIG. 1A includes a single loop in the feedback circuit 105. The single loop provides a representation of the output voltage (V OUT) of the converter to an error amplifier 108. The error amplifier 108 may compare the representation of the output voltage (V OUT) with an input reference (V REF) indicative of a desired output voltage (V OUT) and may provide voltage error information. A second amplifier 109 may compare the voltage error information with a ramp signal of the oscillator 103 to provide a PWM signal (PWM) to the example power stage 102.The voltage converter 101 of FIG. 1B includes a second loop in the feedback circuit 107. The first loop provides a representation of the output voltage (V OUT) of the converter 101 to an error amplifier 108. The error amplifier 108 may compare the representation of the output voltage (V OUT) with an input reference (V REF) indicative of a desired output voltage (V OUT) and may provide voltage error information. The second loop may provide a representation of the coil current of the voltage converter 101 and a second amplifier 110 may compare the voltage error with the representation of the coil current to provide a reset output to a flip-flop 111 or latch, such as a set-reset (SR) latch. The flip-flop 111 may generate a PWM signal for the power stage 102, and the oscillator 103 may provide the set signal to the flip-flop 111.As discussed above, the example power stage 102 may provide the power switches and logic to respond to the PWM signal, and may also efficiently handle the detection and improvement of the inverse diode line as well as overcurrent limits of the power switches. In certain examples, a first operating mode of the power stage 102 may include triggering a first switch of the power stage upon a change of the PWM signal and using the second switch as a rectifier. A second mode of the power stage may trigger the second switch of the power stage 102 upon a change of the PWM signal and may use the first switch as a rectifier. The control unit of the power stage can control changes between the operating modes. In certain examples, a transition between the operating modes may be based on the current flow to or from the output of the voltage converter, as discussed below.FIG. 2 generally shows a more detailed view of the example power stage 102. In certain examples, the power stage 102 may include a controller 220, a first power switch 221, a second power switch 222, first and second inverse diode line sensors 223, 224, and a current comparator 225. The first switch 221 may be coupled between a first power supply rail (V IN) and an output node (SW). The second power switch 222 may be coupled between the output node (SW) and a second power supply rail (GND). The output node (SW) may be coupled to the coil 104 of a converter. The first inverse diode conduction sensor 223 may be mounted across the conduction nodes of the first power switch 221 and may provide an indication when the voltage at the output node (SW) is higher than the voltage at the first power supply rail (V IN) by a first offset, such as just less than the forward bias voltage of the inverse diode of the first power switch 221. The second inverse diode conduction sensor 224 may be mounted across the conduction nodes of the second power switch 222 and may provide an indication when the voltage at the output node (SW) is lower than the voltage at the second power supply rail (GND) by a second offset, such as just less than the forward bias voltage of the inverse diode of the second power switch 222. In certain examples, the detection circuitry of the first and second inverse diode line sensors 223, 224 may include a differential amplifier, a comparator, or a combination thereof.In certain applications, if the non-overlapping time is very small, the delays of the first inverse diode line sensor 223 or the second inverse diode line sensor 224 may not trigger the output signals (I_POS, I_NEG). For example, if the first inverse diode line sensor 223 does not trigger the first output signal (I_NEG), the power stage 102 may continue to operate in buck converter mode, for example, while the load current is in negative polarity from the output voltage (V OUT) to the output node (SW). In such a situation, when the bottom side or second power switch 222 turns on and a counter-current event occurs, the bottom side power transistor 222 may turn off and the voltage at the output node (SW) node may increase above the voltage at the first power supply rail (V IN). The first inverse diode line sensor 223 may detect the increase in voltage of the output node (SW) and may trigger the output (I_NEG) to change the operation mode from buck converter to boost converter. Similarly, the second inverse diode line sensor 224 may change the mode of the power stage 102 from up-to-down conversion if the second output signal (I_POS) is erroneously not triggered when the non-overlapping time is very small.FIG. 3 generally shows an example controller 220 that uses the inverse diode line sensors (FIGS. 2 ; 223, 224) and the overcurrent signals (OC, ROC) of the current comparator (FIGS. 2 ; 225) to transition between the modes discussed above and to operate the voltage converter more efficiently, which in turn may result in improved reliability, particularly for monolithic power stages. The control unit 220 may include first mode switching logic 331, second mode switching logic 332, and switching logic 333 for switching between the first and second modes. In certain examples, the logic 333 for transitioning between the first and second modes of operation may include a flip-flop 334 and first and second multiplexers 335, 336. The flip-flop 334 may receive the output (I_NEG, I_POS) of each of the first and second inverse diode line sensors. The output of the flip-flop 334 may be received at the control input of each multiplexer 335, 336 to enable the output of the respective switching logic 331, 332 to control the first and second power switches via a respective signal (hg, Ig) of the control unit.In one example, assume that the output of the flip-flop is logic low (e.g., Q=0) and that the first and second power switches are controlled by the first mode switching logic 331. In such a state, an output signal (I_POS) from the second inverse diode line sensor may be generally ignored, since a positive current is generally desired in the first operation mode. The first inverse diode line sensor may provide an active output signal (I_NEG) when the output voltage of the converter is above the voltage of the first supply rail. In certain examples, the output signal (I_NEG) does not become active until the output voltage of the converter is a first threshold above the voltage of the first supply rail. Such a condition may be an indication that the current flow at the output of the converter is negative or flows from the load to the converter, for example because the load generates a higher voltage than the voltage of the first supply rail. Such a condition may also be an indication that the inverse diode of the first circuit breaker is forward biased or is short of it. In response to the active output signal (I_NEG) of the first inverse diode line sensor, the flip-flop 334 may transition state or be set (e.g., Q=1). The logic high of the flip-flop output (Q) may allow the multiplexers 335, 336 to isolate the control nodes (hg, Ig) of the power switches from the first mode switching logic 331 and couple the control nodes (hg, Ig) of the power switches to the second mode switching logic 332.When the power switches are coupled to and operate in accordance with the second mode of operation circuitry 332, an output signal (I_NEG) from the first inverse diode line sensor may be generally ignored because a negative current is generally accepted during the second mode of operation. The second inverse diode line sensor may provide an active output signal (I_POS) when the output voltage of the converter is below the voltage of the second supply rail. In certain examples, the output signal (I_POS) does not become active until the output voltage of the converter is a second threshold below the voltage of the supply rail. Such a condition may be an indication that the current flow at the output of the converter is positive or flows from the converter to the load, for example because the load consumes current at a voltage that is less than the voltage of the first supply rail. Such a condition may also be an indication that the inverse diode of the second circuit breaker is forward biased or is short of it. In response to the active output signal (I_POS) of the second inverse diode line sensor, the flip-flop 334 may transition state or be reset (e.g., Q=0) by the active output signal (I_POS) of the second inverse diode line sensor. The logic low of the flip-flop output (Q) may allow the multiplexers 335, 336 to isolate the control nodes (hg, Ig) of the power switches from the second mode switching logic 332 and to couple the control nodes (hg, Ig) of the power switches to the first mode switching logic 331.In certain examples, the first operating mode may be analogous to operating the converter as a buck converter such that the first switch is triggered by the PWM signal, the duty cycle of the first switch is limited by the PWM signal, and the second switch responds to the first switch and is used as a rectifier. In the second mode of operation, the converter is operated analogously to a boost converter, such that the second switch is triggered by the PWM signal, the duty cycle of the second switch is limited by the PWM signal, and the first switch responds to the second switch and is used as a rectifier.FIGS. 4A and 4B generally show switching logics 331, 332 for the first and second operating modes, respectively. Each switching logic circuit 331, 332 may receive the PWM signal and the overcurrent signals (OC, ROC) from the current comparator (FIGS. 2 ; 225). Each switching logic circuit 331, 332 may include first and second flip-flops 440, 441, 442, 443, optional delay circuits 444, 445 and various other logic gates 446, 447 for conditioning the logic signal to properly set the respective power switch output (hg, Ig). The switching logic 331, 332 assumes that the first and second power switches assume a low impedance state when their respective control node, or output of the switching logic, is at a logic "high" and a high impedance state when their respective control node is at a logic "low". It should be understood that the impedance state of the first and second power switches may be different without departing from the scope of the present subject matter. Assuming that the positive overcurrent signal (OC) and the negative overcurrent signal (ROC) are at logic "low" and were for a long period of time, the first mode switching circuit 331 sets the output (hg) for the first power switch to assume a low impedance state directly in response to the PWM signal changing from a logic "low" level to a logic "high" level via a first inverter 446 and first NOR gate 447. Conversely, the second mode of operation switching circuit 332 sets the output (lg) for the second power switch to assume a low impedance state directly in response to the PWM signal changing from a logic "high" level to a logic "low" level via a second NOR gate 449.Each switching circuit 331, 332 may optionally include a delay circuit 444, 445 to establish a delay between the PWM triggered switch leaving the low impedance state and the other switch entering the low impedance state. As the respective switch exits from the low impedance state, a delay network including a resistor (R) and a capacitor (C) may begin charging the capacitor via a p-type transistor 450 coupling the delay network to a voltage source (V IN). When the voltage across capacitor (C) reaches a logic "high", the output that controls the other switch may change to a logic "high", placing the other switch in the low impedance state. An n-type transistor 451 may be used to discharge the capacitor (C) when the output for the PWM triggered switch is set to a logic "high" level.FIG. 4A includes a first flip-flop 440 configured to receive the PWM signal and the positive overcurrent limit signal (OC), and provide an output to a NOR gate 447 that controls the output (hg) to the first power switch. The positive overcurrent signal (OC) is provided by the current comparator and indicates the direction of the coil current and that the coil current is greater than a predefined current limit. In combination with the first flip-flop 447, the positive overcurrent limiting signal (OC) may interrupt the low impedance state of the first power switch when the controller is operating in the first mode of operation and the first power switch is in a low impedance state. Such a function may protect the first power switch from a load associated with conducting more current than the switch is designed to conduct.FIG. 4A includes a second flip-flop 441 configured to receive the PWM signal and the negative overcurrent signal (ROC), and provide an output to a first NOR gate 452 that controls the output (lg) to the second power switch. The negative overcurrent limiting signal (ROC) is provided by the current comparator and indicates the direction of the coil current as well as the coil current is greater than a predefined current limit. In combination with the second flip-flop 441, the negative overcurrent limiting signal (ROC) may interrupt the low impedance state of the second power switch when the controller is operating in the first mode of operation and the second power switch is in a low impedance state. Such a function may protect the second power switch from loads associated with conducting more current than the switch is designed to conduct.FIG. 4B includes a first flip-flop 442 configured to receive the PWM signal and the negative overcurrent limiting signal (ROC), and provide an output to a first NOR gate 449 that controls the output (lg) to the second power switch. In combination with the first flip-flop 442, the negative overcurrent limiting signal (ROC) may interrupt the low impedance state of the second power switch when the controller is operating in the second mode of operation and the second power switch is in a low impedance state. Such a function may protect the second power switch from loads associated with conducting more current than the switch is designed to conduct.FIG. 4B includes a second flip-flop 443 configured to receive the PWM signal and the positive overcurrent limiting signal (OC), and an output to a second NOR gate 453 controls an output (hg) for the first power switch. In combination with the second flip-flop 443, the positive overcurrent limiting signal (OC) may interrupt the low impedance state of the first power switch when the controller is operating in the second mode of operation and the first power switch is in a low impedance state. Such a function may protect the first power switch from loads associated with conducting more current than the switch is designed to conduct.FIG. 5 shows an example system 560 including a load 563 differentially driven using two power converters 561, 562, in accordance with the present subject matter. The system 560 may include a system controller 564, a first voltage converter 561, a second voltage converter 562, and the load 563. In certain examples, the load 563 may include, but is not limited to, a motor, a stepper motor, a thermoelectric device, or combinations thereof. Power converters 561, 562 are particularly suitable for differentially driving load 563 because the control scheme discussed above may allow each power converter 561, 562 to efficiently deliver or receive current as controller 564 requests or as the application requires. In addition to delivering and receiving current, the control scheme places each converter 561, 562 in a switching mode of operation that can protect the power switches of each converter 561, 562 from over-current loads and that can efficiently conduct current over a power switch channel rather than over an inverse diode when such a situation is detected. Such situations may occur when a set point of the system controller 564 changes rapidly, or when disturbances to the load environment are encountered.FIG. 6 generally illustrates a flowchart of an example method of operating a power stage in accordance with the present subject matter. At 601, a first switch of a power stage may be triggered "on" in response to a first change of a PWM signal. The power stage may include the first switch coupled in series with a second switch between rails of an input voltage supply. At 603, the first switch may be triggered "off" in response to a second change in the PWM signal. At 605, a first non-overlapping interval may be initiated in response to the "off" state of the first switch. In certain examples, the "on" duration of the switch that directly responds to the change of the PWM signal is the basis of the duty cycle of the power stage, and this switch is the actively controlled switch. The actively controlled switch turns "on" only once during each switching period and turns "on" no longer than the prescribed duty cycle. When a maximum current limit is detected, the actively controlled switch may be switched "off" before the interval defined by the duty cycle ends. The switch that is not actively controlled may be turned "on" in response to the actively controlled switch turning "off" or a non-overlapping interval ending. As used herein, a "maximum current limit" may include a maximum positive current limit or a maximum negative current limit, and may refer to the performance of the actively controlled switch.At 607, an inverse diode conduction sensor may monitor the first switch, or the actively controlled switch, and in certain situations, detect an inverse diode conduction event of the first switch during the first non-overlapping interval. In certain examples, detecting the inverse diode conduction event may include comparing a voltage across the actively controlled switch to a reference voltage. Depending on which switch is actively controlled by the first and second switches, the reference voltage may be near one of the input voltage supply rails, or a small offset from the potential at one of the input voltage supply rails. At 609, in response to the inverse diode conduction event, the second switch may be placed in an "on" state, or a low impedance state. The low impedance state of the second switch may more efficiently redirect system current and pull the voltage of the common node between the first and second switches to a desired level than allowing the current to be redirected across the inverse diode of the first switch. Additionally, the second switch may become the actively controlled switch and may be triggered to an "on" state at 611 in response to a third change in the PWM signal. The power stage may therefore transition an operating mode of a power stage to more efficiently control and / or regulate the current.In certain examples, with the ability of the power stage to transition operating mode, for example by switching the actively controlled switch, the power stage is better able to redirect excessive or unexpected current over a channel of one of the switches, rather than an inverse diode of one of the switches. The use of the channel of one of the switches can develop much less heat than the use of the inverse diode of one of the switches. Less heat can be equalized with less stress and more reliable power level, particularly monolithic power level integrated circuit (IC) or monolithic buck converter ICs.Various Remarks & ExamplesThe above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings illustrate specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as "examples.". Such examples may include additional elements to those shown or described. However, the present inventors also consider examples in which only the elements shown or described are provided. Furthermore, the present inventors also contemplate examples using a combination or permutation of those elements shown or described (or one or more aspects thereof), whether with reference to a particular example (or one or more aspects thereof), or with reference to other examples (or one or more aspects thereof) shown or described herein.In the case of conflicting use between this document and other documents so incorporated by reference, use is in this document.In this document, the terms "a" or "an" are used, as is common in patent documents, to include one or more, regardless of all other cases or uses of "at least one" or "one or more". In this document, the term "or" is used to mean a nonexclusive or such that "A or B" includes "A but not B", "B but not A", and "A and B", unless otherwise specified. In this document, the terms "including" and "wherein" are used as the plain language equivalents of the respective terms "including" and "wherein". Also, the terms "including" and "comprising" are open-ended, that is, a system, device, article, composition, formulation, or method including elements in addition to those listed after such term are further considered to fall within the scope of the treated article. Furthermore, the terms "first", "second" and "third", etc., as may appear in the claims, are used merely as identifiers and are not intended to place numerical requirements on their objects.The method examples described herein may be at least partially machine- or computer-implemented. Some examples may include a computer readable medium or a machine readable medium encoded with instructions by which an electronic device may be configured to perform the methods described in the above examples. An implementation of such methods may include code, such as microcode, assembly language code, higher-level language code, or the like. Such code may include computer readable instructions for performing various methods. The code can form part of computer program products. Further, the code may be, for example, tangibly stored on one or more transitory, non-transitory, or non-transitory computer readable media, such as during execution or at other times. Examples of these tangible computer readable media may include hard disks, removable magnetic disks, removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or sticks, RAMs (random access memories), ROMs (read only memories), and the like.The above description is intended to be illustrative and not limiting. For example, the examples described above (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used, for example, by one skilled in the art after studying the above description. The abstract is provided to enable the reader to quickly ascertain the nature of the technical disclosure. It is provided so that it is not used to interpret or limit the scope or meaning of a claim. In the above detailed description, various features may also be grouped together to further emphasize the disclosure. This should not be understood as meaning that an unclaimed disclosed feature is essential to a claim. Rather, the inventive subject matter may lie in less than all features of a particular disclosed embodiment. The following aspects are hereby incorporated into the detailed description as examples or embodiments, with each aspect representing a distinct embodiment, and it is contemplated that such embodiments may be combined with one another in various combinations and permutations.

Claims

A power stage circuit (102) for a switching converter (100, 101), the power stage (102) comprising: a first detector circuit (223) for receiving a signal indicative of conduction of an inverse diode of a first power transistor, the first power transistor for coupling a first supply node to an intermediate node; a second detector circuit (224) for receiving a signal indicative of conduction of an inverse diode of a second power transistor, the second power transistor for coupling a second supply node to the intermediate node; an output node for feeding a load from a coil (104), the coil (104) coupled between the output node and the intermediate node; A control and / or regulating unit (220) configured to operate the first and second power transistors so as to avoid conduction of the inverse diode through the first and second power transistors, wherein the control and / or regulating unit (220) comprises: first circuitry for a first operating mode; and second circuitry for a second operating mode; wherein the control and / or regulating unit (220) is communicatively coupled to the first and second detector circuits; and wherein the control and / or regulating unit (220) is configured to isolate control nodes of the first and second power transistors from the first circuitry using a first multiplexer (335) in response to a first inverse diode conduction event indication.The power stage circuit (102) of claim 1, wherein the control and / or regulation unit (220) includes: first circuitry for a first operating mode; and second circuitry for a second operating mode.The power stage circuit (102) of claim 2, including a current comparator configured to obtain a representation of an output current of the output node, compare the representation of the output current with one or more maximum current limits to provide one or more maximum current limit comparisons, and provide an indication of each maximum current limit comparison to the control and / or regulation unit (220).The power stage circuit (102) of claim 3, wherein the control and / or regulation unit (220) is configured to: trigger a first low impedance state of the first power transistor upon a first transition of a PWM signal from a first logic level to a second logic level using first circuitry using the first circuitry; trigger a first high impedance state of the first power transistor upon a second transition of the PWM signal from the second logic level to the first logic level using first circuitry using the first circuitry; initiate a first non-overlapping interval in response to the second transition using the first circuitry; receive the first inverse diode conduction event indication of the first power transistor during the first non-overlapping interval from the first detector circuit; coupling the control nodes of the first and second power transistors to the second circuitry using a second multiplexer (336) in response to the inverse diode conduction event; and triggering the second power transistor to a first high impedance state based on a subsequent third change in the PWM signal from the first logic level to the second logic level using the second circuitry.The power stage circuit (102) of claim 4, wherein the control and / or regulation unit (220) is configured to trigger a second low impedance state of the second switch (222) upon a subsequent fourth change of the PWM signal from the second logic level to the first logic level using the second switching logic; wherein, in response to the second switch (222) in the second low impedance state after the fourth change, the control and / or regulation unit (220) is configured to: receive a negative maximum current limit indication from the current comparator in response to the current of the output violated a negative maximum current limit; instruct a second high impedance state of the second switch (221) in response to the negative maximum current limit indication using the second switching logic; instructing a second low impedance state of the first switch (221) in response to the negative current limit indication using the second switching logic.The power stage circuit (102) of claim 5, wherein the control and / or regulation unit (220) is configured to: trigger a second high impedance state of the second switch (222) upon a fourth change of the PWM signal from the first logic level to the second logic level using the second switching logic; initiate a second non-overlapping interval in response to the fourth change using the second switching logic; receive a second inverse diode line indication of the second switch (222) during the second non-overlapping interval from a second inverse diode line sensor coupled via the second power transistor; isolating control nodes of the first and second power transistors from the second circuitry using the second multiplexer (336) in response to the inverse diode conduction event of the second power transistor; coupling the control nodes of the first and second power transistors to the first circuitry using the first multiplexer (335) in response to the inverse diode conduction event of the first power transistor; and triggering the first switch (221) to a second high impedance state based on a subsequent fifth change of the PWM signal from the first logic level to the second logic level using the first circuitry.The power stage circuit (102) of claim 6, wherein the control and / or regulation unit (220) is configured to trigger a second low impedance state of the first switch (221) upon a subsequent sixth change of the PWM signal from the first logic level to the second logic level using the first switching logic; and wherein, in response to the first switch (221) in the second low impedance state after the sixth change, the control and / or regulation unit (220) is configured to: receive a positive maximum current limit indication from the current comparator in response to the current of the output node violateing a positive maximum current limit; instruct a third high impedance state of the first switch (221) in response to the positive current limit indication using the first switching logic; instructing a second low impedance state of the second switch (222) in response to the positive current limit indication using the first switching logic.The power stage circuit (102) of claim 1, wherein a monolithic integrated circuit includes the first power transistor, the second power transistor, the output node, and the control and / or regulation unit (220).A system comprising: a power stage circuit (102) for a switching converter (100, 101) according to any one of claims 1 to 8, a load; a first voltage converter (561) coupled to the load (563), the voltage converter (561) including a switching circuit having a first switch (221) configured to couple to a first supply rail (V IN) a second switch (222) configured to couple to a second supply rail (GND), and a switch node (SW) coupling the first switch (221) in series with the second switch (222), and a coil (104) coupled between the switch node (SW) and the load; and wherein a control and / or regulating unit (220) of the first voltage converter (561) includes: means for triggering a low impedance state of the first switch (221) upon a first change of a first PWM signal from a first logic level to a second logic level; means for triggering a high impedance state of the first switch (221) upon a second change of the first PWM signal from the second logic level to the first logic level; means for initiating a first non-overlapping interval in response to the second change; means for detecting an inverse diode conduction event of the first switch (221) during the first non-overlapping interval; means for instructing a low impedance state of the second switch (222) in response to the inverse diode conduction event of the first switch (221); and means for triggering the second switch (222) to a high impedance state based on a subsequent third change of the first PWM signal from the first logic level to the second logic level.The system of claim 9, wherein the control and / or regulation unit (220) further includes means for triggering a second low impedance state of the second switch (222) upon a subsequent fourth change in the PWM signal from the second logic level to the first logic level; and optionally including, in response to the second switch (222) in the second low impedance state after the fourth change, means for detecting a negative maximum current limit event in response to the current of the coil (104) injuring a negative maximum current limit; means for instructing a second high impedance state of the second switch (222) in response to the means for detecting the negative maximum current limit event; and means for instructing a second low impedance state of the first switch (221) in response to the means for detecting the negative current limit event.The system of claim 9, including a second voltage converter coupled to the load; and optionally wherein the load is a motor; or wherein the load is a thermoelectric device.A method of operating a power stage circuit (102) for a switching converter (100, 101) according to any of claims 1 to 11, comprising: receiving, by a first detector circuit (223), a signal indicative of conduction of an inverse diode of a first power transistor, the first power transistor for coupling a first supply node to an intermediate node; receiving, by a second detector circuit (224), a signal indicative of conduction of an inverse diode of a second power transistor, the second power transistor for coupling a second supply node to the intermediate node; feeding a load from a coil (104) via an output node, the coil (104) being coupled between the output node and the intermediate node; and operating the first and second power transistors by a control and / or regulating unit (220) such that conduction of the inverse diode through the first and second power transistors is avoided, wherein the control and / or regulating unit (220) comprises: a first switching logic for a first operating mode; and a second switching logic for a second operating mode; wherein the control and / or regulating unit (220) is communicatively coupled to the first and second detector circuits; and wherein the control and / or regulating unit (220) is configured to isolate control nodes of the first and second power transistors from the first switching logic using a first multiplexer (335) in response to a first inverse diode conduction event indication.The method of operating a power stage circuit (102) of claim 12, further comprising a first switch (221) configured to couple to a first supply rail (V IN) a second switch (222) configured to couple to a second supply rail (GND), and a switch node (SW) coupling the first switch (221) in series with the second switch (222), and a coil (104) coupled between the switch node (221, 222) and a load, the method comprising: triggering a first low impedance state of the first switch (221) upon a first transition of a pulse width modulated (PWM) signal from a first logic level to a second logic level; triggering a first high impedance state of the first switch (221) upon a second transition of the PWM signal from the second logic level to the first logic level; initiating a first non-overlapping interval in response to the second transition; detecting an inverse diode conduction event of the first switch (221) during the first non-overlapping interval; instructing a first low impedance state of the second switch (222) in response to the inverse diode conduction event of the first switch (221); and triggering the second switch (222) to a first high impedance state based on a subsequent third transition of the PWM signal from the first logic level to the second logic level.The method of claim 13, including triggering a second low impedance state of the second switch (222) upon a subsequent fourth transition of the PWM signal from the second logic level to the first logic level; and optionally including, in response to the second switch (222) in the second low impedance state after the fourth transition, detecting a negative maximum current limit event in response to the current of the coil (104) injuring a negative maximum current limit; instructing a second high impedance state of the second switch (222) in response to the negative maximum current limit event; and instructing a second low impedance state of the first switch (221) in response to the negative current limit event.The method of claim 13, including: triggering a second high impedance state of the second switch (222) upon a fourth transition of the PWM signal from the first logic level to the second logic level; initiating a second non-overlapping interval in response to the fourth transition; detecting an inverse diode conduction event of the second switch (221) during the second non-overlapping interval; and triggering the first switch (221) to a second high impedance state based on a subsequent fifth transition of the PWM signal from the first logic level to the second logic level, wherein in particular triggering a second low impedance state of the first switch (221) upon a subsequent sixth transition of the PWM signal from the first logic level to the second logic level; and optionally including, in response to the first switch (221) in the second low impedance state after the sixth transition, detecting a positive maximum current limit event in response to the current of the coil (104) injuring a positive maximum current limit; instructing a third high impedance state of the first switch (221) in response to the positive current limit event; and instructing a second low impedance state of the second switch (222) in response to the positive current limit event.

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