Monolithically integrated microwave circuit with integrated electrical overload protection, method for electrical overload protection in such a circuit and semiconductor component

Abstract

A monolithic integrated microwave circuit (MMIC) with integrated electrical overload protection, the MMIC comprising: a signal contact point (101) configured to receive a radio frequency (RF) signal; a first ground contact point (102); a balun (125) comprising a primary section (135) configured to receive the RF signal and a secondary section (136) configured to output a differential RF signal; an amplifier (21) configured to amplify the differential RF signal; and a first protective inductor (151) electrically connected between a center tap of the primary section (135) and the first ground contact point (102) and operating to protect the amplifier (21) against electrical overload.

Description

FIELD OF DISCLOSUREEmbodiments of the present invention relate to microwave and millimeter wave integrated circuit electronic systems and, more particularly, to low noise amplifier interfaces with electrical overload protection.BACKGROUNDSpecific electronic systems may be subject to electrical overload events or short duration electrical signals having rapidly alternating voltage and high power. Electrical overload events include, for example, electrical overload (EOS) and electrostatic discharge (ESD) resulting from the sudden release of charge from an object or person to an electronic system.Electrical overload events can damage or destroy integrated circuits (ICs) by creating overvoltage conditions and high levels of power output in relatively small areas of the IC. High power output can increase the IC temperature and can lead to numerous problems such as gate oxide punch-through, transition damage, metal damage, and surface charge accumulation.US 2018 / 0 076 770 A1 relates to devices and methods for differential ground potential power amplifier systems. In certain examples, a semiconductor chip for a radio frequency communication system includes a differential ground potential network configured to distribute a ground voltage. The differential ground potential network is substantially symmetric with respect to a line of symmetry. The semiconductor chip further comprises a first differential power amplifier having a first half-circuit and a second half-circuit that operate differentially to provide gain. The first half circuit and the second half circuit are symmetrically connected to the differential ground potential network. The semiconductor chip may further include a second differential power amplifier, and the differential ground potential network is for isolation between the first differential power amplifier and the second differential power amplifier.US 2013 / 0 009 704 A1 relates to an integrated circuit comprising a balun, a transistor pair and a degeneration inductance coil. The balun has an outer boundary and has a primary winding and a secondary winding. The primary winding is configured to receive an input signal. The secondary winding is magnetically coupled to the primary winding and is configured to convert the input signal to a differential form. The transistor pair is connected to the secondary winding and is configured to amplify the input signal. The degeneration inductor is connected to the transistor pair and is disposed within the outer boundary of the balun.SUMMARY OF THE DISCLOSUREIt is an object of the present invention to provide a microwave amplifier and a corresponding method which enable a resilience with respect to electrical overload events. The object is achieved by the subject matters of the independent claims. Advantageous embodiments are set out in the dependent claims.Microwave amplifiers tolerant to electrical overloading are disclosed. In particular embodiments, a monolithic microwave integrated circuit (MMIC) includes a signal pad receiving a radio frequency (RF) signal, a ground pad, a balun having a primary portion receiving the RF signal and a secondary portion outputting a differential RF signal, an amplifier amplifying the differential RF signal, and a protection inductor connected between the primary portion and the ground pad and operating to protect the amplifier from electrical overload. Such electrical overload events include not only electrostatic discharge (ESD) events, but other types of overload, such as field-induced charged device (FICDM) model events. For example, the protective inductor operates as a shunt inductor for the primary portion of the balun and serves to reduce overload load during short duration overload events.In one aspect, a monolithic microwave integrated circuit (MMIC) with integrated electrical overload protection is disclosed. The MMIC includes a signal pad configured to receive a radio frequency (RF) signal, a first ground pad, a balun including a primary region configured to receive the RF signal and a secondary region configured to output a differential RF signal, an amplifier configured to amplify the differential RF signal, and a first protection inductor connected between the primary region and the first ground pad and operating to protect the amplifier from electrical overload.In a further aspect, a method for electrical overload protection in an MMIC is disclosed. The method includes receiving an RF signal at a signal pad, receiving the RF signal in a primary region of a balun, and outputting a differential RF signal from a secondary region of the balun, amplifying the differential RF signal using an amplifier, and protecting the amplifier from electrical overload using a first protection inductor connected between the primary region of the balun and a ground pad.In a further aspect, a semiconductor die (semiconductor die) is provided. The semiconductor die includes a plurality of pads including a signal pad configured to receive an RF signal and a ground pad. The semiconductor die further includes a balun having a primary region configured to receive the RF signal and a secondary region configured to output a differential RF signal, a pair of field effect transistors (FETs) configured to receive the differential RF signal, the pair of FETs including a first FET and a second FET, and a plurality of input inductors including a first input inductor electrically connected between a first end of the secondary region of the balun and a gate of the first FET and a second input inductor electrically connected between a second end of the secondary region of the balun and a gate of the second FET.In a further aspect, an MMIC with integrated electrical overload protection is disclosed. The MMIC includes an RF signal pad configured to receive the RF signal, and an RF circuit coupled to the RF signal pad and including a transistor layout including an input FET, and an embedded protection device connected between a gate and a source of the input FET.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1 is a schematic diagram of a vehicular radar system according to an embodiment. FIG. 2 is a schematic diagram of a chip interface according to an embodiment. FIG. 3 is a schematic diagram of a millimeter wave amplifier according to an embodiment. FIG. 4 is a schematic diagram of a millimeter wave amplifier according to an embodiment of the present invention. FIG. 5 is a schematic diagram of an embodiment of a bias supply block for a millimeter wave amplifier. FIG. 6 is a schematic diagram of a millimeter wave amplifier according to another embodiment of the present invention. FIG. 7 is a schematic diagram of a millimeter wave amplifier according to another embodiment of the present invention. FIG. 8 is a schematic diagram of a millimeter wave amplifier according to another embodiment. FIG. 9A is a schematic diagram of a millimeter wave amplifier according to another embodiment. FIG. 9B is a schematic diagram of a millimeter wave amplifier according to another embodiment of the present invention. FIG. 9C is a schematic diagram of a millimeter wave amplifier according to another embodiment. FIG. 9D is a schematic diagram of a millimeter wave amplifier according to another embodiment of the present invention. FIG. 10 is a schematic diagram of an inductor and balun layout according to an embodiment. FIG. 11 is a graph of an example of simulation results showing a comparison of a millimeter wave amplifier implemented with and without gate-to-source clamps. FIG. 12 is a graph of an example of simulation results showing a comparison of a millimeter wave amplifier with and without a protection inductor coupled to a primary portion of a balun. FIG. 13 is a graph of an example of simulation results showing a comparison of a millimeter wave amplifier implemented with and without protection inductors coupled to primary and secondary regions of a balun. FIG. 14 is a graph of an example of simulation results showing a comparison of a millimeter wave amplifier implemented with and without gate-to-source terminals and protection inductors coupled to primary and secondary regions of a balun. FIG. 15 is a graph of another example of simulation results showing a comparison of a millimeter wave amplifier implemented with and without a protection inductor coupled to a primary portion of a balun. FIG. 16 is a graph of another example of simulation results showing a comparison of a millimeter wave amplifier implemented with and without protection inductors coupled to primary and secondary regions of a balun. FIG. 17 is a graph of another example of simulation results showing a comparison of a millimeter wave amplifier implemented with and without gate-to-source terminals and protection inductors coupled to primary and secondary regions of a balun. FIG. 18A is a schematic diagram of a compound semiconductor high electron mobility transistor (compound semiconductor HEMT) coupled to an interface network and protected by a protection element. FIG. 18B is a graph of an example of voltage vs. current characteristics for a Schottky gate diode structure of a HEMT. FIG. 19 is a cross-section of an embodiment of a HEMT. FIG. 20 is a cross-section of another embodiment of a HEMT.DETAILED DESCRIPTIONThe following detailed description of embodiments presents various descriptions of specific embodiments of the invention. However, the invention may be practiced in a variety of different ways. In this specification, reference is made to the drawings, wherein like reference numerals may indicate like or functionally similar elements. It should be understood that elements illustrated in the figures are not necessarily drawn to scale. It is also to be understood that specific embodiments may include more elements than shown in a drawing and / or a subset of the elements shown in a drawing. Further, some embodiments may incorporate any suitable combination of features from two or more drawings.Specific electronic systems include overload protection circuits to protect circuits or components from electrical overload events. To help guarantee that an electronic system is reliable, manufacturers may review the electronic system under defined loading conditions, which may be described by standards established by various organizations such as the Joint Electronic Device Engineering Council (JEDEC), the International Electrotechnical Commission (IEC), and the Automotive Engineering Council (AEC). The standards may cover a wide variety of electrical overload events, including electrical overload (EOS) and / or electrostatic discharge (ESD).FIG. 1 is a schematic diagram of a vehicular radar system according to an embodiment. The vehicular radar system of FIG. 1 illustrates an example of an application for the amplifier interfaces that are subject to electrical overload conditions and protected by the electrical overload protection schemes herein.For example, the vehicular radar system may include low noise amplifiers (LNAs) implemented in accordance with the teachings herein and used to amplify high frequency (RF) signals received from antennas of the / the vehicular radar / system or to amplify signals representing light received by the one and / or the plurality of lidar systems of the vehicle. Example vehicle applications for LNAs include, but are not limited to, parking assist, collision warning, cross traffic warning, blind spot detection, adaptive cruise control, autonomous driving, and / or emergency braking / collision avoidance.Although FIG. 1 illustrates an example application for millimeter wave amplifiers, the teachings herein are applicable to a wide range of applications. In another example, a millimeter wave amplifier is incorporated into a phased array antenna system such as those used for mobile communication and / or military and defense systems.Although specific embodiments are suitable herein for providing gain for millimeter waves, other frequency ranges are possible. For example, the teachings herein are applicable to RF communication systems operating over a wide range of frequencies including not only RF signals between 100 MHz and 7 GHz, but also higher frequencies such as those in the X band (about 7 GHz to 12 GHz), the K u- band (about 12 GHz to 18 GHz), the K band (about 18 GHz to 27 GHz), the K a- band (about 27 GHz to 40 GHz), the V band (about 40 GHz to 75 GHz) and / or the W band (about 75 GHz to 110 GHz). Accordingly, the teachings herein are applicable to a wide variety of RF communication systems that include microwave communication systems.The RF signals amplified by the amplifiers may be associated with a variety of communication standards including, but not limited to, the global system for mobile communication (GSM), extended data rates for GSM evolution (EDGE), code division multiple access (CDMA), wideband CDMA (W-CDMA), 3G, long term evolution (LTE), 4G, and / or 5G, and also other proprietary and non-proprietary communication standards.Electrical Overload Protection for Microwave AmplifiersFIG. 2 is a schematic diagram of a chip interface 60 according to an embodiment. The chip interface 60 comprises both a plurality of contact points (also referred to here as pins) and also various circuits of a semiconductor die or chip. The chip interface 60 of FIG. 2 illustrates an embodiment of a chip interface that may be implemented in accordance with one or more features of the present disclosure. The chip interface 60 corresponds to an input / output (I / O) interface of a semiconductor die such as a monolithic microwave or millimeter wave integrated circuit (MMIC).In the illustrated embodiment, the chip interface 60 includes a plurality of pins or pads including an input signal pad 1, an output signal pad 2, an RF signal pad 3, a first high power pad 5 (VDD 1) for a first power domain, a second high power pad 6 (VDD 2) for a second power domain, a first low power pad 7 or ground pad (VSS 1) for the first power domain, a second low power pad 8 (VSS 2) for the second power domain, and an ESD low power pad 9 (ESDVSS). Although an example of pads is shown, a chip interface may have a wide range of types of pads including, but not limited to, input and / or output (IO) pads, power supply pads, and / or ground pads. Although a particular number of pads are shown, more or fewer pads may be included and / or another array of pads may be used.In the illustrated embodiment, the chip interface 60 further comprises a first core circuit 31 (which may be digital, analog or mixed signal) and a second core circuit 32 connected in cascade between the input signal pad 1 and the output signal pad 2.The chip interface 60 further comprises a primary forward overload protection circuit 11 for the input signal pad 1, a primary reverse overload protection circuit 12 for the input signal pad 1, a secondary forward overload protection circuit 13 for the input signal pad 1, a secondary reverse overload protection circuit 14 for the input signal pad 1, a first supply terminal 15 between VDD1 and VSS1, a second supply terminal 16 between VDD1 and ESDVSS, a third supply terminal 17 between VDD2 and ESDVSS, a fourth supply terminal 18 between VDD2 and VSS2, a primary forward protection circuit 19 for the output signal pad 2, a primary reverse protection circuit 20 for the output signal pad 2, a microwave amplifier 21, a protection inductor 22, a / n bias supply block or circuit 23, a first pair of anti-parallel diodes between VSS1to ESDVSS, a second pair of anti-parallel diodes 36 between VSS2and ESDVSS, a gate grounded FET 37 connected between the input of the second core circuit 32 and VSS2, and a balun 50.Also shown are various resistors including an input resistor Rin1 to the first core circuit 131, an input resistor Rin2 to the second core circuit 32, and various resistors associated with the resistance values of the metallization used to carry the power supplies through the chip interface 60.The chip interface 60 of FIG. 2 illustrates an embodiment of a chip interface that may be implemented in accordance with one or more features of the present disclosure. Although an example of circuits for a chip interface is shown, a chip interface may include a wide range of types and / or numbers of circuits. Accordingly, other implementations are possible.A portion of the chip interface 60 includes pads and circuitry for amplifying RF signals. For example, the chip interface 60 includes the RF signal pad 3, the ground pad 8 (VSS 2 in this example), the power supply pad 6 (VDD 2 in this example), the balun 50, the microwave amplifier 21, the protection inductor 22, and the bias supply block 23.The balun 50 has a primary region 51 that receives an RF signal from the RF signal pad 3 and a secondary region 52 that provides a differential RF signal to the microwave amplifier 21 for amplification. The primary region 51 and the secondary region 52 of the balun 50 are magnetically coupled.As shown in FIG. 2, the bias supply block 23 receives a supply voltage from the power supply pad 6 and supplies a regulated supply voltage and / or one or more controlled bias currents to the microwave amplifier 21. The microwave amplifier 21 also receives a ground voltage from the ground pad 8.The protective inductor 22 is electrically connected between the primary region 51 of the balun 50 and the ground pad 8 and operates to protect the microwave amplifier 21 from electrical overload. Additionally or alternatively, the microwave amplifier 21 may be implemented with any of the protection structures disclosed herein. In particular implementations, the microwave amplifier 21 is a millimeter wave amplifier.FIG. 3 is a schematic diagram of a millimeter wave amplifier 150 according to an embodiment. The millimeter wave amplifier 150 includes a balun 125, a pair of input inductors 126, amplification circuitry 127, a pair of source inductors 128, a first cross-coupled capacitor 131, and a second cross-coupled capacitor 132.Although millimeter wave amplifier 150 is an embodiment of an amplifier implemented with electrical overload protection, the teachings herein are applicable to amplifiers implemented in a wide variety of ways. Moreover, the teachings herein are also applicable to other types of RF circuits that process a differential RF signal from a balun.As shown in FIG. 3, the balun 125 has a primary region 135 that receives an RF signal from the RF signal pad 101. The primary region 135 is electrically connected between the RF signal pad 101 and a ground voltage provided by a ground pad (not shown in FIG. 3 ). The balun 125 further includes a secondary portion 136 that outputs a differential RF signal provided to the gain circuitry 127 by way of the pair of input inductors 126.In the illustrated embodiment, the amplification circuitry 127 includes a first amplification field effect transistor (amplification FET) 141 and a second amplification FET 142. In addition, the input inductors 126 include a first input inductor 137 and a second input inductor 138. As shown in FIG. 3, a gate of the first amplification FET 141 is electrically connected to a first end of the secondary region 136 of the balun 125 by way of the first input inductor 137, while a gate of the second amplification FET 142 is electrically connected to a second end of the secondary region 136 of the balun 125 by way of the second input inductor 138.The incorporation of the first input inductor 137 and the second input inductor 138 contributes to protecting the first boost FET 141 and the second boost FET 142 from damage. For example, the first input inductor 137 and the second input inductor 138 may serve to block or inhibit high frequency currents, reach the gates of the FETs, and cause voltage buildup.The first gain FET 141 and the second gain FET 142 may be implemented in a wide variety of ways, such as using metal oxide semiconductor (MOS) transistors, FinFET transistors, and / or compound semiconductor transistors, such as high electron mobility transistors (HEMTs). Thus, the teachings herein are applicable to a wide range of processing technologies including, but not limited to, silicon processes (e.g., silicon-on-insulator or SOI) and compound semiconductor processes (e.g., gallium nitride or GaN). Although an example with n-type transistors is shown, the teachings herein are also applicable to amplifiers with p-type transistors or a combination of p-type and n-type transistors. Moreover, although an example with FETs is shown, the teachings herein are also applicable to amplifiers implemented with bipolar transistors or a combination of FETs and bipolar transistors. In addition, the teachings herein are also applicable to other types of RF circuits that process a differential RF signal from a balun.The first gain FET 141 and the second gain FET 142 may have any suitable geometry, such as a smallest channel length for technology (to provide improved power at microwave frequencies) and a width selected based on constraints on the noise factor (NF). The FET layouts may include multi-contact pin devices electrically connected to each other using metallization. In one example, each gain FET 64 has 320 nm wide contact pins to achieve an overall device width of 18 μm. However, other implementations are possible.As shown in FIG. 3, the pair of source inductors 128 includes a first source inductor 143 electrically connected between a source of the first boost FET 141 and a ground voltage, and a second source inductor 144 electrically connected between a source of the second boost FET 142 and the ground voltage.The ground voltage for the sources of the first boost FET 141 and the second boost FET 142 may be equal to or different from the ground voltage of the primary region 135 of the balun 125.In one example, a common ground pad provides a ground voltage for the primary region 135 of the balun 125 and for the sources of the first boost FET 141 and the second boost FET 142.In a second example, the first ground pad provides a first ground voltage to the primary region 135 of the balun 125, while a second ground pad provides a second ground voltage to the sources of the first boost FET 141 and the second boost FET 142. In particular implementations, the first ground pad and the second ground pad are connected within the chip using a decoupling circuit such as a decoupling inductor and / or anti-parallel diodes. Thus, the teachings herein are applicable to chip interfaces having multiple ground domains coupled inside the chip or outside the chip to achieve a desired amount of isolation.The first cross-coupled capacitor 131 is electrically connected between a gate of the first amplification FET 141 and a drain of the second amplification FET 142. In addition, the second cross-coupled capacitor 132 is electrically connected between a gate of the second amplification FET 142 and a drain of the first amplification FET 141. In particular implementations, the cross-coupled capacitors are implemented as metal-oxide-metal (MOM) capacitors. The cross-coupled capacitors may have any suitable capacitance, such as a capacitance in the range of 5 fF to 25 fF.Millimeter wave amplifier 150 provides a differential RF signal between the drains of first gain FET 141 and second gain FET 142 in this example. In particular implementations, power is also provided to the millimeter wave amplifier 150 using the drains of the first amplification FET 141 and the second amplification FET 142. For example, the millimeter wave amplifier 150 may further include a first choke inductor electrically connected between the drain of the first amplification FET 141 and a regulated supply voltage from a bias supply block, and a second choke inductor electrically connected between the drain of the second amplification FET 142 and the regulated supply voltage.FIG. 4 is a schematic diagram of a millimeter wave amplifier 160 according to an embodiment of the present invention. The millimeter wave amplifier 160 includes a balun 125, a first cross-coupled capacitor 131, a second cross-coupled capacitor 132, a first input inductor 137, a second input inductor 138, a first amplification FET 141, a second amplification FET 142, a first source inductor 143, a second source inductor 144, and a protection inductor 151 (also referred to herein as a first protection inductor or inductor L 1).The millimeter wave amplifier 160 of FIG. 4 is similar to the millimeter wave amplifier 150 of FIG. 3, except that the millimeter wave amplifier 160 further includes the protection inductor 151.Incorporating the protection inductor 151 helps protect against electrical overload events at the RF signal pad 101. Such electrical congestion events include not only ESD events, but other types of congestion, such as field-induced charged device (FICDM) model events. For example, the protective inductor 151 operates as a shunt inductor for the primary region 135 of the balun 125 and serves to reduce overload load during short duration overload events.In particular implementations, the protective inductor 151 is electrically connected to a center tap of the primary region 135 of the balun 125.The protective inductor 151 may have any suitable inductance, for example an inductance of at least 150 pH. In particular implementations, the protection inductor 151 has a maximum inductance selected based on the ESD event power at 10 GHz.FIG. 5 is a schematic diagram of an embodiment of a bias supply block 200 for a millimeter wave amplifier. For example, bias supply block 200 illustrates one embodiment of bias supply block 23 of FIG. 2. Although FIG. 5 illustrates an embodiment of a bias supply block, the teachings herein are applicable to bias supply blocks implemented in other ways.In the illustrated embodiment, the bias supply block 200 includes a first p-type field effect transistor (PFET) 181, a second PFET 182, a third PFET 183, a fourth PFET 184, a fifth PFET 185, a first amplifier 187, a second amplifier 188, a third amplifier 189, a first bias resistor 191, a second bias resistor 192, and a voltage divider 194 including a first voltage divider resistor 195 and a second voltage divider resistor 196.In FIG. 5, the millimeter wave amplifier is illustrated as a transconductance gain element schematically depicted as an n-type field effect transistor (NFET) 171. However, the millimeter wave amplifier may be implemented in any suitable manner. Although one embodiment of a bias supply block is depicted, a millimeter wave amplifier may draw power in a wide variety of ways.In the illustrated embodiment, the bias supply block 200 receives a supply voltage V DD( e.g., 0.9 V) from a power supply pad (not shown in FIG. 5 ). The bias supply block 200 also receives a reference voltage V REF( for example 0.7 V), which may be a bandgap voltage. Moreover, the bias supply block 200 also receives a reference current I ref as well. The reference voltage V REF and the reference current I ref may be generated within the chip, outside the chip, or in a combination thereof.As shown in FIG. 5, the bias supply block 200 includes a first control loop that sets a regulated supply voltage (corresponding to V drain in this example) substantially equal to the reference voltage V REF. In addition, the bias supply block 200 includes a second control loop that operates to control a current through the transconductance gain element 171 substantially equal to the reference current (I ref). When used to bias voltage / current a millimeter wave amplifier, the bias supply block 200 strictly controls the supply voltage and current of the millimeter wave amplifier (schematically represented as NFET 171).In some embodiments, the NFET 171 corresponds to one of the first amplification FET 141 or the second amplification FET 142 of FIGS. 3, 4, and 6-9D. In particular embodiments, the depicted circuitry of the bias supply block 200 is replicated to provide regulated voltages and controlled bias currents for each transistor of an input transistor pair of a millimeter wave differential amplifier. For example, a first instantiation of the depicted circuitry may be used to bias / current the first gain FET 141 of FIGS. 3, 4, and 6-9D (where the first instantiation of the NFET 171 corresponds to the first gain FET 141), while a second instantiation of the depicted circuitry may be used to bias / current the second gain FET 142 of FIGS. 3, 4, and 6-9D (where the second instantiation of the NFET 171 corresponds to the second gain FET 142).In the illustrated embodiment, the bias supply block 200 also generates a test current I test, which may be processed to verify the accuracy of the depicted bias current control loop.FIG. 6 is a schematic diagram of a millimeter wave amplifier 250 according to another embodiment of the present invention. The millimeter wave amplifier 250 includes a balun 125, a first cross-coupled capacitor 131, a second cross-coupled capacitor 132, a first input inductor 137, a second input inductor 138, a first amplification FET 141, a second amplification FET 142, a first source inductor 143, a second source inductor 144, a first protection inductor 151 (also referred to herein as an inductor L 1), a second protection inductor 152 (also referred to herein as an inductor L 2), a capacitor 241, a resistor 242, and a voltage source 243.The millimeter wave amplifier 250 of FIG. 6 is similar to the millimeter wave amplifier 160 of FIG. 4 except that the millimeter wave amplifier 250 further includes the second protection inductor 152, the capacitor 241, the resistor 242, and the voltage source 243.As shown in FIG. 6, the second protective inductor 152 is electrically connected to the secondary region 136 of the balun 125. In particular implementations, the second protection inductor 152 is connected to a center tap of the secondary region 136. The second protective inductor 152 may have any suitable inductance value, for example, an inductance of at least 150 pH.The second protective inductor 152 is electrically connected in series to the capacitor 241 between the secondary region 136 of the balun 125 and a ground voltage from a ground pad.In particular implementations, the first protection inductor 151 and / or the second protection inductor 152 may be connected to the balun 125 using a metallization option. Thus, the first protective inductor 151 and / or the second protective inductor 152 may be metal programmable to provide additional clamping as needed.As shown in FIG. 6, the voltage source 242 is electrically connected in parallel to the capacitor 241 and operates to control a DC input voltage to the first amplification FET 141 and the second amplification FET 142. In particular implementations, the voltage level of voltage source 242 is controlled by a control loop of a supply control block, and thereby control is provided for a bias current through amplifier 250.FIG. 7 is a schematic diagram of a millimeter wave amplifier 270 according to another embodiment of the present invention. The millimeter wave amplifier 270 includes a balun 125, a first cross-coupled capacitor 131, a second cross-coupled capacitor 132, a first input inductor 137, a second input inductor 138, a first amplification FET 141, a second amplification FET 142, a first source inductor 143, a second source inductor 144, a protection inductor 151, a first clamping FET 261, a second clamping FET 262, a common gate resistor 263, and a decoupling inductor 265.The millimeter wave amplifier 270 of FIG. 7 is similar to the millimeter wave amplifier 160 of FIG. 4 except that the millimeter wave amplifier 270 further includes the first clamp FET 261, the second clamp FET 262, the common gate resistor 263, and the decoupling inductor 265. In addition, the illustrated embodiment operates using multiple ground domains (associated with a first ground pad 102 and a second ground pad 103 in this example) that are decoupled from each other using a decoupling circuit (corresponding to the decoupling inductor 265 in this example).The first clamp FET 261 is electrically connected via the gate and source of the first amplification FET 141, while the second clamp FET 262 is electrically connected via the gate and source of the second amplification FET 142. In addition, the common resistor 263 has a first end electrically connected to the first ground pad 102 and a second end electrically connected to a gate of the first clamp FET 261 and a gate of the second clamp FET 262. However, other implementations are possible. For example, low noise amplifier configurations may include different numbers of FETs directly connected to the interface, in which case the same concept may be applied.The first clamp FET 261 and the second clamp FET 262 serve as protection embedded outside the FET (e.g., outside the NMOS) for the amplification FETs of the millimeter wave amplifier 270. For example, the clamp FETs may serve to provide FICDM self-protection.In particular implementations, a boost FET and corresponding clamp FET are implemented using a shared multi-contact pin layout. For example, a first portion of the contact pins of the layout may be used to implement the boost FET (e.g., the first boost FET 141), while a second portion of the contact pins of the layout may be used to implement the clamp FET (e.g., the first clamp FET 261).In another embodiment, the active input device for high power, high frequency microwave and millimeter wave applications may be implemented using GaAs or GaN HEMT devices, and these types of technology provide an advantage for high frequency operation and noise performance. In such implementations, the gate terminal functions as a forward Schottky diode in one direction or polarity of the applied voltage, while being sensitive to damage induced by negative overload in the opposite direction. To address this limitation, the implementation described above (which may correspond to, for example, implementation in a silicon process such as a CMOS process) is implemented in the case of high electron mobility GaAs and / or GaN transistor (HEMT) devices, for example the cross-sections of FIG. 19 or 20.FIG. 8 is a schematic diagram of a millimeter wave amplifier 290 according to another embodiment. The millimeter wave amplifier 290 includes a balun 125, a first cross-coupled capacitor 131, a second cross-coupled capacitor 132, a first input inductor 137, a second input inductor 138, a first amplification FET 141, a second amplification FET 142, a first source inductor 143, a second source inductor 144, a first clamp FET 261, a second clamp FET 262, a first common gate resistor 263, a decoupling inductor 265, a third clamp FET 281, a fourth clamp FET 282, a second common gate resistor 283, and a voltage source 284.Millimeter wave amplifier 290 of FIG. 8 is similar to millimeter wave amplifier 270 of FIG. 7, except that millimeter wave amplifier 290 omits protection inductor 151 and further includes third clamp FET 281, fourth clamp FET 282, second common gate resistor 283, and voltage source 284.In the illustrated embodiment, the third clamp FET 281 is electrically connected between the gate of the first amplification FET 141 and a clamping node, and the fourth clamp FET 282 is electrically connected between the gate of the second amplification FET 142 and the clamping node. The clamping node is connected to the voltage source 284 in this example. In addition, the second common resistor 283 has a first end electrically connected to the clamping node and a second end electrically connected to a gate of the third clamping FET 281 and the gate of the fourth clamping FET 282.As shown in FIG. 8, the first and second clamp FETs 261, 262 have a first device polarity (n-type in this example), while the third and fourth clamp FETs 281, 282 have a second device polarity (p-type in this example). For example, the clamp FETs may be implemented as a first pair of NMOS off-clamps and a second pair of PMOS off-clamps.FIG. 9A is a schematic diagram of a millimeter wave amplifier 410 according to another embodiment. The millimeter wave amplifier 410 includes a balun 125, a first input inductor 137, a second input inductor 138, a first amplification FET 141, a second amplification FET 142, a first source inductor 143, a second source inductor 144, a first cascode FET 401, a second cascode FET 402, and a cascode bias voltage source 403.The teachings herein are applicable to a wide variety of amplifier types including, but not limited to, common source amplifiers, common emitter amplifiers, FET cascode amplifiers, and / or bipolar cascade amplifiers. Although depicted as having a pair of cascode transistors, additional pairs of cascode transistors may be included.FIG. 9B is a schematic diagram of a millimeter wave amplifier 420 according to another embodiment of the present invention. The millimeter wave amplifier 420 includes a balun 125, a first input inductor 137, a second input inductor 138, a first amplification FET 141, a second amplification FET 142, a first source inductor 143, a second source inductor 144, a first cascode FET 401, a second cascode FET 402, a cascode bias voltage source 403, a protection inductor 151, and a decoupling inductor 265.Millimeter wave amplifier 420 of FIG. 9B is similar to millimeter wave amplifier 410 of FIG. 9A, except that millimeter wave amplifier 420 further includes protection inductor 151 and decoupling inductor 265.FIG. 9C is a schematic diagram of a millimeter wave amplifier 430 according to another embodiment. The millimeter wave amplifier 430 includes a balun 125, a first input inductor 137, a second input inductor 138, a first amplification FET 141, a second amplification FET 142, a first source inductor 143, a second source inductor 144, a first cascode FET 401, a second cascode FET 402, a cascode bias voltage source 403, a decoupling inductor 265, a first clamping FET 261, a second clamping FET 262, and a common gate resistor 263.The millimeter wave amplifier 430 of FIG. 9C is similar to the millimeter wave amplifier 420 of FIG. 9B, except that the millimeter wave amplifier 430 omits the protection inductor 151 and further includes the first clamp FET 261, the second clamp FET 262, and the common gate resistor 263.FIG. 9D is a schematic diagram of a millimeter wave amplifier 440 according to another embodiment of the present invention. The millimeter wave amplifier 440 includes a balun 125, a first input inductor 137, a second input inductor 138, a first amplification FET 141, a second amplification FET 142, a first source inductor 143, a second source inductor 144, a first cascode FET 401, a second cascode FET 402, a cascode bias voltage source 403, a decoupling inductor 265, a first clamping FET 261, a second clamping FET 262, a common gate resistor 263, and a protection inductor 151.Millimeter wave amplifier 440 of FIG. 9D is similar to millimeter wave amplifier 430 of FIG. 9C, except that millimeter wave amplifier 440 further includes protection inductor 151.FIG. 10 is a schematic diagram of an inductor and balun layout according to an embodiment. The inductor and balun layout includes a balun 531, a pair of input transistor source inductors 532 located at position 534, and a pair of input inductors 533 for protecting the gates of the pair of input transistors at position 534. Although an embodiment of a metallization layout is depicted, the teachings herein are applicable to baluns and inductors implemented in a wide variety of ways.FIG. 11 is a graph of an example of simulation results showing a comparison of a millimeter wave amplifier implemented with and without gate-to-source clamps. The graphs plot the input transistor gate voltage versus time for the two scenarios.FIG. 12 is a graph of an example of simulation results showing a comparison of a millimeter wave amplifier implemented with and without a protection inductor coupled to a primary portion of a balun. As shown in FIG. 12, the simulated stress event is 5 amps.FIG. 13 is a graph of an example of simulation results showing a comparison of a millimeter wave amplifier implemented with and without protection inductors coupled to primary and secondary regions of a balun. As shown in FIG. 13, the simulated stress event is 5 amps.FIG. 14 is a graph of an example of simulation results showing a comparison of a millimeter wave amplifier implemented with and without gate-to-source terminals and protection inductors coupled to primary and secondary regions of a balun. As shown in FIG. 14, the simulated stress event is 5 amps.FIG. 15 is a graph of another example of simulation results showing a comparison of a millimeter wave amplifier implemented with and without a protection inductor coupled to a primary portion of a balun.FIG. 16 is a graph of another example of simulation results showing a comparison of a millimeter wave amplifier implemented with and without protection inductors coupled to primary and secondary regions of a balun.FIG. 17 is a graph of another example of simulation results showing a comparison of a millimeter wave amplifier implemented with and without gate-to-source terminals and protection inductors coupled to primary and secondary regions of a balun.Although FIGS. 11-17 illustrate various examples of simulation results, other simulation results are possible that include results that depend on implementation, application, and / or processing technology.FIG. 18A is a schematic diagram of a compound semiconductor HEMT coupled to an interface network and protected by a protection element. In particular implementations, an enhancement mode HEMT (E HEMT) is present that may fail when negative polarity overload occurs on the RF terminal with respect to ground. For example, the interface between the metal gate of the HEMT and the channel may operate as a Schottky diode that is reverse biased and fails.In such applications, RFIN terminals may require protection only in one direction or polarity, for example, against negative polarity overload on the RF terminal with respect to ground (GND). Additionally, positive polarity overload can be handled by the core HEMT gate-to-source diode.FIG. 18B is a graph of an example of voltage vs. current characteristics for a Schottky gate diode structure of a HEMT such as the HEMT of FIG. 18 Often, there is a greater design tolerance compared to advanced CMOS because the core Schottky junction being protected may have a relatively large breakdown voltage (BV), for example 15 V or higher. Although FIG. 18B illustrates an example of diode blocking characteristics, other results are possible.FIG. 19 is a cross-section of an embodiment of a HEMT 600 with integrated protection. The HEMT is fabricated in a III-V compound semiconductor technology (GaAs in this example). Although an example is shown with GaAs, the teachings herein are applicable to other processing technologies, such as silicon and GaN.To provide low capacitance overload protection, an ESD protection component may be explicitly added between gate and source (see, for example, the E-HEMT of FIG. 18A with gate-source protection).Additionally or alternatively, an additional gate / drain stripe may be used within multi-stripe layouts to protect the Schottky gate.For example, in the illustrated embodiment, the HEMT 600 is fabricated over an undoped GaAs substrate 601. In addition, an InGaAs channel layer 602 (comprising a two-dimensional electron gas or 2 DEG region) is formed over the undoped GaAs substrate 601. Moreover, an AlGaAs spacer layer 603 is formed over the InGaAs channel layer 602, and an N AlGaAs layer is formed over the AlGaAs spacer layer 603.The HEMT 600 includes a first gate region 611 a, a second gate region 611 b, a drain region 613 positioned between the first gate region 611 aand the second gate region 611 b. The gate regions are formed from metal and are associated with metal-semiconductor interfaces and corresponding Schottky diodes. The HEMT 600 further includes a first source region 612 aand a second source region 612 b, wherein the first gate region 611 ais positioned between the first source region 612 aand the drain region 613, and wherein the second gate region 611 bis positioned between the drain region 613 and the second source region 612 b.To protect the HEMT 600, an additional transistor pin has been included to provide a protection HEMT associated with a protection gate region 615, a protection drain region 617 and the source region 612 bcommonly used by the HEMT 600 and the protection HEMT. As shown in FIG. 19, the gate of the metal protection HEMT (back end metallization) is connected to the source of the HEMT 600, while the drain of the protection HEMT is connected to the source of the HEMT 600.Implementing the HEMT 600 in this manner provides an integrated Schottky diode between the gate and the source of the HEMT 600.FIG. 20 is a cross-section of another embodiment of a HEMT 700. As shown in FIG. 20, an embedded protection region and / or element 701 may be included between the gate and the source of the HEMT 700.Although specific layers and materials are depicted, other implementations are possible. In one example, an Si substrate is omitted in favor of using a silicon carbide (SiC) substrate.Applications Using ApplicationsDevices applying the schemes described above may be implemented in various electronic devices. Examples of the electronic devices may include, but are not limited to, consumer electronics products, portions of the consumer electronics products, electronic test equipment, communication infrastructure applications, etc. Further, the electronic device may include unfinished products including those for communication, industrial, medical, automotive, radar, and aeronautical applications.Conclusion NoteThe foregoing description may refer to elements or features that are "connected" or "coupled" together. As used herein, unless expressly stated otherwise, "connected" means that one element / feature is directly or indirectly connected to another element / feature, and not necessarily mechanically. Similarly, unless expressly stated otherwise, "coupled" means that one element / feature is directly or indirectly coupled to another element / feature, and not necessarily mechanically. Thus, although the various circuit diagrams shown in the figures depict example arrangements of elements and components, additional intervening elements, devices, features, or components may be present in an actual embodiment (assuming that the functionality of the depicted circuits is not adversely affected).Although specific embodiments have been described, these embodiments have been presented by way of example only and are not intended to limit the scope of the disclosure. Rather, the novel apparatuses, methods, and systems described herein may be embodied in a variety of other forms; moreover, various omissions, substitutions, and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. For example, although the disclosed embodiments are presented in a given arrangement, alternative embodiments may perform similar functionalities with other components and / or circuit topologies, and some elements may be deleted, displaced, added, divided, combined, and / or modified. Each of these elements may be implemented in a variety of different ways. Any suitable combination of the elements and acts of the various embodiments described above may be combined to provide further embodiments. Accordingly, the scope of the present invention is defined only by reference to the appended claims.In one aspect, electrical overload tolerant microwave amplifiers are provided. In particular embodiments, a monolithic microwave integrated circuit (MMIC) includes a signal pad receiving a radio frequency (RF) signal, a ground pad, a balun having a primary portion receiving the RF signal and a secondary portion outputting a differential RF signal, an amplifier amplifying the differential RF signal, and a plurality of decoupling elements, some of which are connected between the primary portion and the ground pad, others of which are connected to a plurality of nodes of the amplifier in the secondary portion, and operates to protect the amplifier from electrical overload. Such electrical overload events may include both electrostatic discharge (ESD) events, such as field-induced charged device (FICDM) model events, as well as other types of overload conditions.

Claims

A monolithically integrated microwave circuit (MMIC) with integrated electrical overload protection, the MMIC comprising: a signal pad (101) configured to receive a radio frequency (RF) signal; a first ground pad (102); a balun (125) comprising a primary portion (135) configured to receive the RF signal and a secondary portion (136) configured to output a differential RF signal; an amplifier (21) configured to amplify the differential RF signal; and a first protection inductor (151) electrically connected between a center tap of the primary portion (135) and the first ground pad (102) and operating to protect the amplifier (21) from electrical overload.The MMIC of claim 1, further comprising a second protective inductor (152) electrically connected to the secondary region (136) of the balun (125).The MMIC of claim 2, further comprising a capacitor (241) and a voltage source (243) electrically connected in parallel with the capacitor (241) and operative to control a DC input voltage to the amplifier (21), wherein the second protection inductor (152) and the capacitor are electrically connected in series between the secondary region (136) of the balun (125) and the first ground pad (102).The MMIC of claim 2 or 3, wherein the second protective inductor (152) is electrically connected to a tap of the secondary region (136).The MMIC of any preceding claim, wherein the primary region (135) of the balun (125) is electrically connected between the signal pad (101) and the first ground pad (102).The MMIC of any preceding claim, further comprising a second ground pad (103), wherein the primary region (135) of the balun (125) is electrically connected between the signal pad (101) and the second ground pad (103).The MMIC of claim 6, further comprising a decoupling inductor (265) electrically connected between the first ground pad (102) and the second ground pad (103).The MMIC of any preceding claim, wherein the amplifier (21) comprises a first gain field effect transistor (FET) (141) having a gate electrically connected to a first end of the secondary region (136), and a second gain FET (142) having a gate electrically connected to a second end of the secondary region (136).The MMIC of claim 8, further comprising a first input inductor (137) between the gate of the first boost FET (141) and the first end of the secondary region (136), and a second input inductor (138) between the gate of the second boost FET (142) and the second end of the secondary region (136).The MMIC of claim 8 or 9, further comprising a first decoupling inductor (143) between a source of the first boost FET (141) and the first ground pad (102), and a second decoupling inductor (144) between a source of the second boost FET (142) and the first ground pad (102).The MMIC according to any one of claims 8 to 10, further comprising a first clamp FET (261) electrically connected via the gate and the source of the first amplification FET (141), and a second clamp FET (262) electrically connected via the gate and the source of the second amplification FET (142).The MMIC of claim 11, further comprising a common gate resistor (263) having an end electrically connected to the first ground pad (102) and a second end electrically connected to a gate of the first clamp FET (261) and to a gate of the second clamp FET (262).The MMIC of claim 11 or 12, further comprising a third clamp FET (281) electrically connected between the gate of the first gain FET (141) and a clamping node, and a fourth clamp FET (282) electrically connected between the gate of the second gain FET (142) and the clamping node, wherein the third and fourth clamp FETs (281, 282) have a device polarity opposite to the first and second clamp FETs (261, 262).The MMIC of any of claims 11 to 13, further comprising a multi-pin transistor layout, wherein the first boost FET (141) is implemented using a first portion of the contact pins of the multi-pin transistor layout and the first clamp FET (261) is implemented using a second portion of the contact pins of the multi-pin transistor layout.The MMIC of any preceding claim, further comprising a bias supply block (200) configured to generate a regulated supply voltage for supplying the amplifier (21), wherein the bias supply block (200) comprises a first control loop configured to adjust the regulated supply voltage based on a reference voltage and a second control loop operative to control a current through the amplifier (21) based on a reference current.A method for electrical overload protection in a monolithically integrated microwave (MMIC) circuit, the method comprising: receiving a radio frequency (RF) signal at a signal pad (101); receiving the RF signal at a primary portion (135) of a balun (125), and outputting a differential RF signal from a secondary portion (136) of the balun (125); amplifying the differential RF signal using an amplifier (21); and protecting the amplifier (21) against electrical overload using a first protection inductor (151) connected between a center tap of the primary portion (135) and a ground pad (102).The method of claim 16, further comprising protecting the amplifier (21) from electrical overload using a second protection inductor (152) connected to the secondary region (136) of the balun (125).A semiconductor device comprising: a plurality of pads including a signal pad (101) configured to receive a radio frequency (RF) signal and a ground pad (102); a balun (125) including a primary region (135) configured to receive the RF signal and a secondary region (136) configured to output a differential RF signal; a pair of field effect transistors (FETs) configured to receive the differential RF signal, the pair of FETs including a first FET (141) and a second FET (142); a plurality of input inductors comprising a first input inductor (137) electrically connected between a first end of the secondary region (136) of the balun (125) and a gate of the first FET (141), and a second input inductor (138) electrically connected between a second end of the secondary region (136) of the balun (125) and a gate of the second FET (142); and a first protection inductor (151) electrically connected between a center tap of the primary region (135) and the ground pad (102) and operating to protect the pair of FETs from electrical overload.

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