Analog-to-digital converter with resistance-based digital-to-analog converters for reference voltage tuning

Abstract

Circuit for an analog-to-digital converter, wherein the circuit comprises: a first power source (56); a second power source (60); a first buffer (68), and a first resistance digital-to-analog converter, RDAU (54), comprising a first reference node (58) coupled to the first current source (56), a second reference node (62) coupled to the second current source (60), an input port (52) configured to receive a first voltage, and an output port (76) coupled to the first buffer (68), wherein the first RDAU (54) is configured to generate a second voltage comprising a first voltage offset from the first voltage, and to provide the second voltage from the output port (76) of the first RDAU (54) to the first buffer (68), where the first voltage offset is independent of the value of the first voltage.

Description

background

[0001] The present invention relates generally to electrical circuits and in particular to circuits for an analog-to-digital converter and methods for operating an analog-to-digital converter.

[0002] An analog-to-digital converter (ADC) with a successive approximation register (SAR) typically uses a capacitive digital-to-analog converter (CDAC), in which individual capacitors are connected between a reference voltage and ground to adjust a suitable output voltage. Although an ideal CDAC outputs a precisely linear reference voltage, real-world CDACs are subject to the influence of external factors, such as temperature, and are therefore prone to errors. For example, the reference voltage output by the CDAC can drift with temperature fluctuations, which can introduce a gain error.

[0003] A time-nested ADC can contain a time-multiplexed parallel array of n identical successive approximation register (SAR) slices, increasing the net sampling rate, although each individual slice in the array actually samples at a lower rate. Each SAR slice contains a buffer, e.g., a source follower, which has one or more transistors that generate a voltage drop relative to a stable reference voltage at its input. However, the output voltage can exhibit significant temperature variation between the different SAR slices, e.g., due to process variations between the transistors in the different SAR slices. The result is a temperature dependency that can cause different SAR slices to output different voltages despite using the same reference voltage.

[0004] Currently, the stresses of the different slices cannot be set and calibrated separately. Such separate settings are desirable to provide a mechanism for compensating for differences in gain due to manufacturing-related mismatches. Furthermore, these separate settings should be enabled without increasing temperature fluctuations.

[0005] Document US 8,847,811 B2 relates to a circuit for an analog-to-digital converter (ADC) that converts an analog input signal into a digital output signal. The circuit comprises a plurality of conversion stages coupled in series, each of which is configured to generate one bit for the digital output signal. A data storage circuit is also provided, which stores the bits supplied by the conversion stages and uses them to generate the digital output signal. Each conversion stage contains a comparator circuit that compares a sampled input signal with a reference signal and generates one bit for the output signal depending on the result, as well as a multiplexer circuit that passes the respective reference signal to the comparator circuit of the subsequent conversion stage.Overall, the ADC circuit is designed as an asynchronous serial ripple ADC that receives an external clock signal to trigger the comparator of the first conversion stage and generates a plurality of clock pulses with which the comparators of the subsequent conversion stages are controlled.

[0006] Accordingly, improved circuits for an analog-to-digital converter and methods for operating an analog-to-digital converter are required. Summary

[0007] In one embodiment, a circuit for an analog-to-digital converter is provided. The circuit comprises a resistor digital-to-analog converter (RDAU) with a first reference node coupled to a first current source, a second reference node coupled to a second current source, an input port configured to receive a first voltage, and an output port coupled to a buffer. The RDAU is configured to generate a second voltage, which includes a first voltage offset from the first voltage, and to supply the second voltage from the output port of the RDAU to the buffer, the first voltage offset being independent of the value of the first voltage.

[0008] In another embodiment, a method for operating an analog-to-digital converter is provided. The method comprises supplying a first voltage to an input port of a resistance-to-digital converter (RDAC) calibrated to provide a voltage offset. The method further comprises generating a second voltage through the RDAC, comprising the voltage offset from the first voltage, and supplying the second voltage from an output port of the RDAC to a buffer, wherein the first voltage offset is independent of the value of the first voltage. Brief description of the drawings

[0009] The accompanying drawings, which form part of this description, illustrate various embodiments of the invention and, together with the general description of the invention above and the detailed description of the embodiments below, serve to explain these embodiments. In the drawings, the same reference numerals denote the same features in the different views. Fig. Figure 1 is a circuit view of an exemplary receiver circuit comprising an analog-to-digital converter according to embodiments of the invention. Fig. Figure 2 is a circuit view of a voltage reference circuit of an analog-to-digital converter according to embodiments of the invention. Fig. Figure 3 is a circuit diagram of an embodiment of a SAR slice. Fig. Figure 3A is a circuit diagram of an alternative embodiment of the SAR slice. Fig. Figure 4 is a circuit diagram of an embodiment of the ohmic digital-to-analog converter. Fig. 3. Fig. Figure 5 is a circuit diagram of an embodiment of the capacitive digital-to-analog converter. Fig. 3. Detailed description

[0010] With reference to Fig. 1. A receiver circuit 10 can include an analog-to-digital converter (ADC) 15 configured to sample analog input signals and convert them into digital outputs. The ADC 15 can be configured with sufficient resolution to provide digital outputs that accurately represent the analog input signals. For example, the ADC 15 can be configured to convert a continuous analog waveform into a discrete digital representation by performing a binary search through several possible quantization levels before converging to a digital output at each conversion. By the process of temporally interleaving identical successive approximation register (SAR) slices, the ADC 15 can be configured to process sampled data at a higher rate than the operating sampling rate of each individual SAR slice.To achieve a higher net sampling rate, the ADU 15 can comprise a time-multiplexed parallel array of n identical SAR slices of a successive approximation register (SAR) 18, even if each individual SAR slice in the array is actually sampled at a lower rate. The number of SAR slices in the array can be thirty-two (32), sixty-four (64), one hundred and twenty-eight (128), and so on.

[0011] According to the representation in Fig. Analog input signals can be provided as an input 11 from a signal source to a variable gain amplifier (VGA) 12. The VGA 12 can provide signal conditioning with an electronically adjustable voltage gain. To avoid problems arising from variations in the gain temperature of the SAR 18, the receiver circuit 10 can compensate for gain temperature variations by varying the electronically adjustable voltage gain of the VGA 12 as a function of temperature. The receiver circuit 10 can provide the output of the VGA 12 to an equalizer circuit in the form of a continuous-time linear equalizer (CTLE) 14. The CTLE 14 provides signal conditioning in the form of equalization, which can restore the balance between the different frequency components of the signal received by the VGA 12.An interleaver 16 can sample an output of the CTLE 14 and provide lower-frequency samples at each of the n SAR slices of the SAR 18. The interleaver 16 implements temporal interleaving, which allows the ADU 15 to process signals received as input 11 at the faster rate in temporal sequence by utilizing the multiple slices of the SAR 18. The signals are effectively quantized by the parts of the SAR 18 and processed separately. A digital circuit (not shown) then interleaves the B-bit samples from each of the n slices of the SAR 18 into a B-bit stream, representing a B-bit digital code at the sampling rate of the ADU 15.

[0012] With reference to Fig. 2-4 and according to embodiments of the invention, the ADU 15 ( Fig. 1) comprise a global reference circuit 20 comprising a transistor 26, an operational amplifier 34, and a voltage divider 45. The transistor 26 can be a p-type field-effect transistor with a source 28 coupled to a current source 22, a drain 32, and a gate 30. The gate 30 of the transistor 26 can be coupled to the drain 32 of the transistor 26, so that the transistor 26 is configured as a diode. In one embodiment, the current source 22 can be a constant current source, e.g., a 1 / R bandgap current reference. The operational amplifier 34 can have a non-inverting input 36 coupled to a constant reference voltage source 24, which provides a constant reference voltage (VREFGLOBAL). The operational amplifier 34 can have an inverting input 38 connected to the source 28 of the transistor 26.The feedback loop of the operational amplifier 34 regulates the gate voltage of the transistor 26. The voltage divider 45 includes a resistor 44 connected between the drain 32 of the transistor 26 and ground 46. The voltage divider 45 also includes a resistor 48 connected to the output 41 of the operational amplifier 34 and to the drain 32 of the transistor 26. The global reference circuit 20 is configured to generate a reference voltage (VMID) that is output at the output 40 of the global reference circuit 20.

[0013] The output 40 of the global reference circuit 20 can be assigned to any of a number of successive approximation register (SAR) slices 42 (e.g. the n slices of SAR 18 ( Fig. 1)) are coupled in parallel. The reference voltage (VMID) generated by the global reference circuit 20 of the ADU 15 is therefore provided in parallel to each of the SAR slices 42 of the ADU 15. However, no voltage is provided as feedback from any of the SAR slices 42 to any of the inputs 36, 38 of the operational amplifier 34.

[0014] Each SAR slice 42 can have a resistive digital-to-analog converter (RDAU) 54 and a buffer 68 coupled to the RDAU 54. The RDAU 54 has multiple resistors 82, each with a fixed resistance value and arranged in a network, as well as multiple switches 86 that are controlled to change the resistance value of the RDAU 54. In one embodiment, the resistors 82 can have nominally identical resistance values. The RDAU 54 of each SAR slice 42 has a center tap or input port 52, which provides an input to the SAR slice 42. The input port 52 is coupled to the output 40 of the global reference circuit 20, and each SAR slice 42 receives the reference voltage (VMID) from the output 40 of the global reference circuit 20 at the input port 52.The RDAU 54 can be accessed at its input port 52 in the middle, so that the number of resistors 82 arranged between the input port 52 and the reference node 58 in the upper half of the resistor string is nominally equal to the number of resistors 82 arranged between the input port 52 and the reference node 62 in the lower half of the resistor string. A current source 56 can be coupled to a reference node 58 of the RDAU 54 from each SAR slice 42, and another current source 60 can be coupled to a reference node 62 of the RDAU 54 from each SAR slice 42. The resistors 82 generate resistive (IR) voltage drops, so that the current source 56 drives the upper half of the resistor string to a voltage (VTOP) and the current source 60 drives the lower half of the resistor string to a voltage (VBOT).In one embodiment, the current source 60 can be equivalent to the current source 56, such that a negligible current, ideally zero, flows from the SAR slice 42 into the input port 52. In another embodiment, the current sources 56 and 60 can be constant current sources, such as 1 / R bandgap current reference sources, so that the voltage drop across each resistor 82 is stable and constant. In yet another embodiment, the current sources 56 and 60 can be shared by all SAR slices 42, in which case the connections to the current sources 56 and 60 are common nodes between all SAR slices 42, similar to the connection between the SAR slices 42 and the global reference circuit 20.

[0015] The reference voltage (VMID) provided by the global reference circuit 20 for each SAR slice 42 can be adjusted by the RDAU 54 before it is provided as the reference voltage (VREF) for the buffer 68. Specifically, adjusting the resistance of the RDAU 54 can change the voltage transmitted to the buffer 68. Furthermore, the bias voltage of each RDAU 54 can be supplied by the current sources 56 and 60 to maintain a constant voltage drop across each RDAU 54, which can produce a precisely defined level shift of the reference voltage (VMID) received at the input port 52, corresponding to the resistance value of the RDAU 54. In one embodiment, the switches 86 of the RDAU 54 of each SAR slice 42 are configured to be independently controlled, allowing the output voltage of each RDAU 54 to be individually set to a specific value.The voltage offset for the RDAU 54 of each SAR disk 42 is independent of any value or magnitude of the reference voltage (VMID).

[0016] The buffer 68 of each SAR slice 42 can have an input and an output with low output resistance, resulting in a level shift of the input voltage at the output port. The buffer 68 of each of the parallel SAR slices 42 of the SAR 18 can generate an analog voltage at its output port based on the voltage received at its input port 52. In one embodiment, the buffer 68 can be a source-follower buffer comprising a current source 66 and a transistor 64. The transistor 64 can be a p-type field-effect transistor, and the current source 66 can be coupled to a source 70 of the transistor 64, a drain 72 of the transistor 64 can be coupled to ground 46, and a gate 74 of the transistor 64 can be coupled to the output port 76 of the RDAU 54 to receive the reference voltage (VREF) from the output of the RDAU 54.

[0017] A reference voltage (VREF) can be applied from the output port 76 of the RDAU 54 to the input of the buffer 68. The voltage (VREFBUF) at the output 80 of the buffer 68 can represent a gate-to-source voltage drop across the reference voltage (VREF). Since the gate 74-source 70 voltage of transistor 64 can be temperature-dependent due to temperature-dependent factors such as threshold voltage and mobility, VREFBUF from each SAR slice 42 can exhibit a temperature variation (e.g., typically 70 mV from -10°C to 125°C) at the output 80. The threshold voltage of transistor 26 in the global reference circuit 20 can partially compensate for the temperature dependence of transistor 64 in each buffer 68. In particular, transistor 26 and each transistor 64 can be similarly biased such that their temperature coefficients of the output voltage are essentially the same.However, the operation of the RDAU 54 can enable temperature-independent voltage settings, so that a reference voltage can be used for each SAR slice 42 that differs from the global reference voltage but exhibits the same temperature dependence. Thus, the compensation of the temperature-dependent deviation of the threshold voltage of transistor 64 can be combined with predictable delta voltage steps of the RDAU 54 that are not process-corner dependent. The result is that the voltage values ​​(VREFBUF) at the output 80 of buffer 68 of the different slices 42 can be constant as a function of temperature and individually tuned to specific voltages per slice.

[0018] Each of the SAR slices 42 of the SAR 18 can further include a capacitive digital-to-analog converter (CDAU) 88 and a SAR control circuit 89 coupled to the CDAU 88. The CDAU 88, which in conjunction with Fig. As further described in section 5, the reference voltage (VREFBUF) is received from output 80 of buffer 68.

[0019] In an alternative embodiment and as in Fig. As shown in Figure 3A, buffer 68 can be a super-source follower comprising another transistor 69 and another current source 67. Transistor 69 can be an n-type field-effect transistor whose gate is coupled to the drain of transistor 64, whose source is coupled to ground 46, and whose drain is coupled to output 80. The drain of transistor 64 is coupled to current source 67.

[0020] According to the representation in Fig. 4. The RDAU 54 can use a resistor string architecture (e.g., a string DAU) with multiple resistors 82 connected in series and a node 84 between each of the resistors 82. For example, multiple switches 86 can be connected to one or more resistors 82 to provide a selectable resistance and associated voltage at the output port 76. The RDAU 54 has digital input codes (e.g., d0, d1, d2) with complementary digital codes (e.g., đ0, đ1, đ2) that provide an RDAU code which activates and controls the switches 86 to connect selected resistors 82 to the output port 76. The digital input codes supplied to the RDAU 54 set the switches 86 to produce a fixed and temperature-independent voltage drop above or below the reference voltage (VMID). For example, if a full-scale code is created, the top switches can close and the output (e.g.,VREF) can go full-scale (e.g., the full-scale code of the RDAU 54 can produce an output VTOP minus 1 least significant bit). When a zero-scale code is applied, the lowest switches 86 can be closed, and the output (e.g., VREF) can go to zero (e.g., the zero-scale code of the RDAU 54 can produce an output of VBOT). For example, each resistor 82 in the string can produce a voltage drop of 1 least significant bit. Furthermore, a resistor-switch pair can be applied to the RDAU 54 for each code. For this reason, as the resolution increases, the number of resistors 82 and switches 86 in the design of the RDAU 54 can increase exponentially. Each resistor 82 can have a fixed resistance value, and therefore each resistor 82 can produce a constant delta voltage. Accordingly, each RDAU stage can be a constant voltage away from the voltage at input port 52.

[0021] Each SAR slice 42 of the SAR 18 can be calibrated using a calibration algorithm. For example, the local RDAU 54 of each SAR slice 42 can be set to a nominal value by providing a given RDAU code. The reference voltage (VREFGLOBAL) can then be set by individually sampling the output port 76 of each local RDAU 54 (e.g., VREF) (e.g., for 1 to n parallel SAR slices 42 of the SAR 18). The reference voltage (VREFGLOBAL) can then be set to an average value of the output port 76 of each local RDAU 54. Alternatively, the reference voltage (VREFGLOBAL) can be set to a nominal value, and individual RDAUs can be used for calibration. Then the global reference voltage (VREFGLOBAL) can be adjusted so that the local RDAUs 54 are centered or to avoid them being railed.For example, the reference voltage (VREFBUF) can be lowered by a preset number of least significant bits when railing occurs (VREF equals VTOP), or the maximum and minimum of output port 76 of each local RDAU 54 can be set to output a minimal deviation from the voltage (VMID) at the center tap.

[0022] With reference to Fig.Each slice 42 of the SAR 18 can have a capacitive digital-to-analog converter (CDAU) 88 operating on the basis of charge redistribution. The CDAU 88 includes capacitors C1, ..., CN-3, CN-2, CN-1, and CN, which are switched between the voltage (VREFBUF) and ground via switches S1, ..., SN-3, SN-2, SN-1, and SN. Capacitors C1, ..., CN-3, CN-2, CN-1, and CN are switched to set the corresponding output voltage VOUT. The step size of the CDAU output voltage is set by the capacitor ratios and the reference voltage (VREFBUF). The CDAU gain is defined as the slope of the curve from the CDAU analog output to the digital input. The charge redistribution across capacitors C1, ..., CN-3, CN-2, CN-1, and CN causes the current to be drawn from or diluted by the positive reference voltage (VREFBUF). The capacitance of capacitors C1, ...CN-3, CN-2, CN-1, and CN are affected by the ambient temperature, although the effect on the CDAU step size is minimal, as it is a function of the capacitor ratios. The voltage (VREFBUF) can be affected by temperature drift. Since VREFBUF 80 in CDAU 88 can fluctuate with temperature, the gain of CDAU 88 can move linearly with VREFBUF. The gain of CDAU 88 directly affects the gain of ADU 15. Therefore, gain fluctuations in ADU 15 can occur in an environment where the voltage represented by VREFBUF exhibits temperature drift.

[0023] References herein to terms modified by imprecise language, such as "approximately," "about," and "essentially," are not limited to the precisely stated value. The imprecision may correspond to the accuracy of an instrument used to measure the value and, unless otherwise dependent on the accuracy of the instrument, may indicate + / - 10% of the stated value(s).

[0024] A feature that is "connected" or "coupled" to another feature can be directly connected or coupled to the other feature, or one or more intervening features can be present. A feature can be "directly connected" or "directly coupled" to another feature if no intervening features are present, or one or more intervening features can be present. A feature can be "indirectly connected" or "indirectly coupled" to another feature if at least one intervening feature is present. A feature that is attached to or "contacts" another feature can be directly attached to or in direct contact with another feature, or one or more intervening features can be present.A feature can be "directly adjacent" or in "direct contact" with another feature if no intervening features exist. A feature can be "indirectly adjacent" or in "indirect contact" with another feature if at least one intervening feature exists.

[0025] The description of the various embodiments of the present invention serves for illustration purposes but is neither intended to be exhaustive nor limited to the embodiments described. Many modifications and variations are apparent to those skilled in the art without deviating from the scope and essence of the described embodiments. The terminology used here has been chosen to best explain the principles of the embodiments, their practical application, or the technical improvement over technologies available on the market, or to enable those other than those skilled in the art to understand the embodiments described herein.

Claims

[1] Circuit for an analog-to-digital converter, wherein the circuit comprises: a first power source (56); a second power source (60); a first buffer (68), and a first resistance digital-to-analog converter, RDAU (54), comprising a first reference node (58) coupled to the first current source (56), a second reference node (62) coupled to the second current source (60), an input port (52) configured to receive a first voltage, and an output port (76) coupled to the first buffer (68), wherein the first RDAU (54) is configured to generate a second voltage comprising a first voltage offset from the first voltage, and to provide the second voltage from the output port (76) of the first RDAU (54) to the first buffer (68), where the first voltage offset is independent of the value of the first voltage. [2] Circuit according to claim 1, wherein the first RDAU (54) comprises a first plurality of resistors and a second plurality of resistors and the input port (52) of the first RDAU (54) is tapped centrally between the first plurality of resistors and the second plurality of resistors. [3] Circuit according to claim 2, wherein the first plurality of resistors is arranged in a first string between the first reference node (58) and the input port (52) and the second plurality of resistors is arranged in a second string between the second reference node (62) and the input port (52). [4] Circuit according to claim 1, wherein the first buffer (68) has a transistor (64) with a gate (74) and the output port (76) of the first RDAU (54) is coupled to the gate (74) of the transistor (64). [5] Circuit according to claim 1, wherein the first RDAU (54) comprises a plurality of resistors (82) and a plurality of switches (86) and the switches (86) are configured to selectively connect one or more of the resistors (82) to the output port (76) to generate the first voltage offset. [6] Circuit according to claim 5, wherein the first RDAU (54) is configured to respond to a digital n-bit input signal for controlling the switches (86) of the first RDAU (54). [7] Circuit according to claim 1, further comprising: a global reference circuit (20) with an output (40) coupled to the input port (52) of the first RDAU (54), wherein the global reference circuit (20) is configured to generate the first voltage. [8] Circuit according to claim 7, wherein the global reference circuit (20) comprises a transistor (26) and an operational amplifier (34), the transistor (26) having a drain (32) and a gate (30) coupled to the drain (32), and the operational amplifier (34) having an inverting input (38) coupled to a source (24) of the transistor (26), and further comprising: a third power source (22); and a constant reference voltage source (24), wherein the source (22) of the transistor (26) is coupled to the third current source (22) and the operational amplifier (34) has a non-inverting input (36) coupled to the constant reference voltage source (24). [9] Circuit according to claim 8, wherein the operational amplifier (34) has an output (41), and further comprising: a voltage divider (45) with a first resistor (48) and a second resistor (44), wherein the first resistor (48) is connected between the output (41) of the operational amplifier (34) and the input port (52) of the first RDAU (54) and the second resistor (44) is connected between the drain (32) of the transistor (26) and ground (46). [10] Circuit according to claim 1, wherein the first buffer (68) and the first RDAU (54) are provided in a first successive approximation register slice (42). [11] Circuit according to claim 10, further comprising: a second successive approximation register slice, which includes a second buffer and a second resistor-to-digital-to-analog converter, RDAU, wherein the second RDAU comprises an input port (52)9 configured to receive the first voltage and an output port (76) coupled to the second buffer, and the second RDAU is configured to generate a third voltage having a second voltage offset relative to the first voltage, and to provide the third voltage from the output port (76) of the second RDAU to the second buffer. [12] Circuit according to claim 11, wherein the second RDAU has a first reference node (58) coupled to the first power source (56) and a second reference node (62) coupled to the second power source (60). [13] Circuit according to claim 11, further comprising: a global reference circuit (20) with an output (40) that is coupled in parallel to the input port (52) of the first RDAU (54) and the input port (52) of the second RDAU, wherein the global reference circuit (20) is configured to generate the first voltage. [14] Circuit according to claim 1, wherein the first current source (56) and the second current source (60) are constant current sources. [15] Method for operating an analog-to-digital converter, the method comprising: a provision of an initial voltage at an input port (52) of a first resistance digital-to-analog converter, RDAU (54), which has been calibrated to provide an initial voltage offset; a generation of a second voltage comprising the first voltage offset from the first voltage by the first RDAU (54); and a provision of the second voltage from an output port (76) of the first RDAU (54) for a first buffer (68), where the first voltage offset is independent of the value of the first voltage. [16] Method according to claim 15, wherein the first buffer (68) comprises a first transistor (64), and further comprising: a provision of the second voltage from the output port (76) of the first RDAU (54) to a gate (74) of the first transistor (64). [17] The method of claim 16, further comprising: comparing a source voltage of a second transistor (26) in a reference circuit (20) with a constant reference voltage using an operational amplifier (34) to generate the first voltage. [18] The method of claim 17, further comprising: a biasing of the second transistor (26) to compensate for a temperature dependence of the first transistor (64). [19] Method according to claim 15, wherein the first voltage is provided in parallel to an input port (52) of a second resistance digital-to-analog converter, RDAU, which has been calibrated to provide a second voltage offset, and further comprising: a generation of a third voltage, comprising the second voltage offset from the first voltage, by the second RDAU; and a provision of the third voltage from an output port (76) of the second RDAU to a second buffer.

Images