Method for producing fins in an nFET zone and a pFET zone

Abstract

Method comprising: providing a substrate (102) comprising a first semiconductor material; generating a mask (103) covering an nFET region of the substrate (102); etching a pFET region of the substrate (102) to form a trench (102'); epiaxially growing a second semiconductor material in the trench (102'), wherein the second semiconductor material differs from the first semiconductor material;and structuring the nFET zone and the pFET zone to produce a first fin (108n) in the nFET zone and a second fin (108p) in the pFET zone, wherein the first fin (108n) has the first semiconductor material and the second fin (108p) has an upper section (104) over a lower section (106), wherein the upper section (104) has the second semiconductor material and the lower section (106) has the first semiconductor material, wherein structuring the nFET zone and the pFET zone includes: forming fin hard masks (105) over the nFET zone and the pFET zone; and etching of the nFET zone and the pFET zone through the fin hard masks (105) by the same process to produce the first (108n) and the second fin (108p), wherein the etching of the nFET zone and the pFET zone comprises: anisotropic etching of the nFET zone and the pFET zone through the fin hard masks (105);Isotropic etching of the nFET zone and the pFET zone through the fin hard masks (105) after anisotropic etching; treatment of a structure resulting from the anisotropic etching and the isotropic etching with a treatment gas mixture; and repetition of the anisotropic etching, the isotropic etching and the treatment to produce the first fin (108n) in the nFET zone and the second fin (108p) in the pFET zone, using different gases for the anisotropic etching, the isotropic etching and the treatment.

Description

BACKGROUNDThe electronics industry is faced with an ever-increasing demand for smaller and faster electronic devices that are simultaneously capable of supporting a higher number of increasingly complex and sophisticated functions. To meet this demand, there is a continuing trend in the integrated circuit (IC) industry to produce low cost, high power, low power ICs. Heretofore, these objectives have been largely achieved by reducing the IC dimensions (e.g., minimum IC feature size), thereby improving production efficiency and reducing the associated costs. However, this downsizing has also made the complexity of the IC manufacturing method higher. Thus, realization of continuing advances in IC devices and their performance requires similar advances in IC fabrication methods and technology.FinFET devices have been introduced to increase gate-channel coupling, decrease OFF-state current, and decrease short channel effects (SCEs) as compared to planar transistors. As downsizing progresses, e.g., toward 5 nm and 3 nm process nodes, conventional silicon-based FinFETs also approach their performance limits. For example, aggressively narrow gate dimensions and small device volume make doping and stress management very difficult for better performance for FinFET devices. Improvements in FinFET fabrication are highly desirable.Document US 2015 / 0 028 454 A1 describes silicon and silicon germanium fins formed on a semiconductor wafer. A patterned mandrel layer is used to form one or more recesses in the wafer prior to epitaxial growth of a silicon germanium layer filling the recess. Spacers are formed on the sidewalls of the patterned mandrel layer and then the mandrel layer is removed. The exposed regions of the wafer and the silicon-germanium layer between the spacers are etched to form fins used for nFET devices from the wafer and fins for pFET devices from the silicon-germanium layer.Document US 2018 / 0 247 938 A1 describes a method for simultaneously forming vertical fins on a substrate, the method comprising: forming a mask segment on a first region of the substrate while exposing the surface of a second region of the substrate, removing a portion of the substrate in the second region to form a recess, forming a fin layer in the recess, the fin layer having a different material composition than the substrate, and forming at least one vertical fin on the first region of the substrate and at least one vertical fin on the second region of the substrate, the vertical fin being formed on the second region of the substrate from the fin layer and the substrate.Document US 2017 / 0 047 331 A1 describes a method of forming a CMOS device, comprising aligning a semiconductor layer of a semiconductor-on-insulator (SOI) substrate with a base substrate of the SOI, exposing the base substrate in an N-well region by etching through a mask layer, a dielectric layer, the semiconductor layer and a buried dielectric to form a trench, and forming spacers on sidewalls of the trench. The base substrate is epitaxially grown from a bottom of the trench to form an extended region. A fin material is epitaxially grown from the extended region within the trench. pFET fins are etched onto the base substrate, and nFET fins are etched into the semiconductor layer.The invention is defined by the main claim. Further embodiments of the invention are set forth in the dependent claims.BRIEF DESCRIPTION OF THE DRAWINGSThe present disclosure will be best understood from the following detailed description taken in conjunction with the accompanying drawings. It should be appreciated that, in accordance with practice in the industry, various features are not drawn to scale and are used for illustrative purposes only. Indeed, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased. FIGS. 1A and 1B are flowcharts of a method of forming a semiconductor device according to various aspects of the present disclosure. FIGS. 2A, 3, 4, 5A, 5B, 5C, 6, 7, 9B, 10 and 11 show cross-sectional views of a portion of a semiconductor device according to some embodiments in intermediate steps in manufacturing according to embodiments of the method of FIGS. 1A to 1B. FIG. 2B shows a top view of a portion of a semiconductor device, in accordance with some embodiments. FIGS. 8 and 9A show perspective views of a portion of a semiconductor device, in accordance with some embodiments.DETAILED DESCRIPTIONThe following disclosure provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and arrangements will be described below to simplify the present disclosure. For example, forming a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which further features may be formed between the first and second features such that the first and second features need not be in direct contact. In addition, in the present disclosure, reference numerals and / or letters may be repeated in the various examples. This repetition is for convenience and clarity of illustration and does not alone dictate a relationship between the various embodiments and / or configurations described.Further, for convenience of description herein, terms of spatial relationship such as "below", "below", "lower", "above", "upper", and the like may be used to describe the relationship of one element or feature to (one) other element(s) or feature(s) as illustrated in the figures. The terms spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices may be otherwise oriented (rotated 90 degrees or having different orientations) and the spatial relationship descriptors used herein may likewise be interpreted accordingly. Moreover, when a number or range of numbers is described as "about", "about", and the like, the term includes numbers that, according to the knowledge of one of ordinary skill in the art of the particular technology disclosed herein, are within certain variations (e.g., ±10% or other variations) of the number described, unless otherwise indicated. For example, the term "about 5 nm" may include the dimensional range of 4.5 nm to 5.5 nm, 4.0 nm to 5.0 nm, etc.The present application relates generally to semiconductor structures and fabrication methods, and more particularly to complementary metal-oxide semiconductor (CMOS) devices having p-channel FinFET transistors and n-channel FinFET transistors. An object of the present disclosure is to provide methods for forming p-channel fins and n-channel fins on the same substrate, wherein the n-channel fins include a first semiconductor material and the p-channel fins include a second semiconductor material having a higher charge carrier mobility (e.g., hole mobility) than the first semiconductor material. In an embodiment of the present disclosure, the first semiconductor material is monocrystalline silicon and the second semiconductor material is a silicon germanium alloy. In one embodiment, the p-channel fins are used to form a p-FinFET and the n-channel fins are used to form an n-FinFET. Using the p-channel fins further improves the performance of the p-type FinFET over approaches where both the n-type FinFET and the p-type FinFET use the same material in their channels. In embodiments of the present disclosure, etching of the p-channel fins and the n-channel fins is also optimized by the same etching methods, thereby forming the p-channel fins and the n-channel fins to have closely matched critical dimensions and closely matched fin heights. This further enhances the flatness of an isolation structure between the p-channel fins and the n-channel fins. The flatness of the isolation structure in turn improves subsequent manufacturing processes, e.g., gate formation. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other methods and structures to achieve the same purposes and / or obtaining the same advantages as the embodiments presented herein.FIG. 1A is a flow diagram of a method 10 of forming a semiconductor device according to various aspects of the present disclosure. In the present disclosure, further processing is provided. Additional operations may be provided before, during, and after method 10, and some of the operations described may be shifted, replaced, or omitted for further embodiments of method 10.The method 10 will be described below in connection with FIGS. 2A-11 which show different views of a semiconductor device (or structure) 100 in different manufacturing steps according to the method 10 in accordance with some embodiments. In some embodiments, device 100 is a portion of an IC chip, a system-on-chip (SoC), or a portion thereof, that includes various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs or pFETs), n-type field effect transistors (NFETs or nFETs), FinFETs, nanosheet FETs, nanowire FETs, other types of multi-gate FETs, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor transistors (CMOS transistors), Bipolar Junction Transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, memory devices, other suitable components, or combinations thereof. FIGS. 2A-11 have been simplified for clarity of illustration in order to better understand the inventive concepts of the present disclosure. Additional features may be added in the device 100, and some of the features described below may be replaced, modified, or omitted in other embodiments of the device 100.At operation 12, a substrate 102 is provided in the method 10 (FIG. 1A ), as shown in FIG. 2A, for example. In the illustrated embodiment, the substrate 102 is a silicon substrate, e.g., a silicon wafer, comprising crystalline silicon. Alternatively, the substrate 102 may include another elemental semiconductor, e.g., germanium; a compound semiconductor, e.g., silicon carbide, gallium nitride, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor, e.g., silicon germanium, gallium arsenide phosphide, aluminum indium phosphide, Aluminiumgalliumarsenid gallium indium arsenide, gallium indium phosphide, and Galliumindiumarsenidphosphid; or combinations thereof.At operation 14, in the method 10 (FIG. 1A ), a patterned mask 103 is formed over the substrate 102, as shown in FIGS. 2A and 2B, for example. FIG. 2A shows the patterned mask 103 and the substrate 102 in a cross-sectional view in the "X-Z plane" according to an embodiment, while FIG. 2B shows the patterned mask 103 and the substrate 102 in a plan view in the "X-Y plane" according to an embodiment. The patterned mask 103 covers the substrate 102 in nFET regions and exposes the substrate 102 in pFET regions. In the present disclosure, n-type transistors, e.g., n-type FinFETs, are formed in the n-type FET regions, and p-type transistors, e.g., p-type FinFETs, are formed in the p-type FET regions. The n-type transistors and the p-type transistors may be coupled to form CMOS devices. The patterned mask 103 is shown as having parallel rectangular stripes in the present embodiment. In alternative embodiments, the patterned mask 103 may have other shapes and configurations. The patterned mask 103 may be formed by one or more photolithography methods including dual or multiple patterning methods. The patterned mask 103 may include silicon oxide, silicon nitride, photoresist, or other suitable materials in various embodiments.At operation 16, in the method 10 (FIG. 1A ), the substrate 102 is etched through the patterned mask 103, thereby forming trenches 102' in the substrate 102, such as illustrated in FIG. 3, according to an embodiment. The trenches 102' (one is shown in FIG. 3) are formed in the pFET regions, while the substrate 102 remains intact or substantially intact in the nFET regions under the patterned mask 103. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable methods. For example, in a dry etching process, an oxygen-containing gas, a fluorine-containing gas (e.g., CF 4, SF 6, CH 2 F 2, CHF 3 and / or C 2 F 6), a chlorine-containing gas (e.g., Cl 2, CHCl 3, CCl 4 and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBr3), an iodine-containing gas, other suitable gases and / or plasmas, and / or combinations thereof may be used. For example, a wet etching process may include etching in dilute hydrofluoric acid (HF); potassium hydroxide solution (KOH); ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO 3) and / or acetic acid (CH 3 COOH); or another suitable wet etchant. In one embodiment, the etch process is anisotropic such that the boundary between the nFET regions and the pFET regions can be well matched during operation 16. In some embodiments, the depth of the trenches 102' is controlled to be in a range from about 40 nm to about 70 nm from the top surface of the substrate 102 along the "Z direction.". This region is chosen to provide an appropriate semiconductor thickness for forming fins, as will be described below. In the present embodiment, the depth of the trench 102' may be controlled using a timer and depending on the etching speed of the material in the substrate 102 in the etching process.At operation 18, in the method 10 (FIG. 1A ), a semiconductor material is epitaxially deposited in the trenches 102', thereby forming a semiconductor layer 104 over the substrate 102 in the pFET regions, such as illustrated in FIG. 4 according to an embodiment. In the present embodiment, the semiconductor material of the semiconductor layer 104 has a higher charge carrier mobility (or simply mobility) than the material in the substrate 102. In the present embodiment, the substrate 102 includes crystalline silicon, and the semiconductor layer 104 includes silicon germanium (SiGe) having a higher hole mobility than crystalline silicon. This is suitable for producing high-power pFETs in the pFET regions and high-power nFETs in the nFET regions. In another embodiment, the silicon germanium in the semiconductor layer 104 has a constant or nearly constant atomic percentage (atomic %) of germanium. In another embodiment, the silicon germanium in the semiconductor layer 104 has a constant or nearly constant atomic percentage of germanium in a range from about 15 at % to about 30 at %. In other words, the semiconductor layer 104 includes Si 1-x Ge x where x is in the range of 15 at % to 30 at %. This range of Ge at % is chosen to provide good performance improvement when portions of the semiconductor layer 104 are used as FinFET transistor channels. In another embodiment, the semiconductor layer 104 includes silicon germanium (SiGe) having a Ge-At % gradient. For example, the Ge at % in the semiconductor layer 104 may gradually increase as the semiconductor layer 104 grows to adjust the crystal quality. In this example, when the growth of the semiconductor layer 104 is completed, the lower portion of the semiconductor layer 104 (near the substrate 102) has a lower Ge at % than the upper portion of the semiconductor layer 104. In various embodiments, depending on the material in the substrate 102, the material in the semiconductor layer 104 may include silicon, germanium, silicon carbide, gallium nitride, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide, silicon germanium, gallium arsenide phosphide, aluminum indium phosphide, Aluminiumgalliumarsenid gallium indium arsenide, gallium indium phosphide, gallium indium arsenide phosphide, or combinations thereof. In embodiments, the epitaxial growth of the semiconductor layer 104 is performed by a molecular beam epitaxy (MBE) method, a chemical vapor deposition (CVD) method, a metal organic CVD (MOCVD) method, or another suitable epitaxial growth method, or combinations thereof.After completion of the growth of the semiconductor layer 104, the patterned hard mask 103 is removed in operation 18 and the top surface of the device 100 is planarized, for example, by chemical mechanical planarization (CMP). As shown in FIG. 4, the top surface of the semiconductor layer 104 (in the pFET regions) and the top surface of the substrate 102 are coplanar or substantially coplanar in the nFET regions. The height (or thickness) h 1 of the semiconductor layer 104 along the Z direction is in a range from about 40 nm to about 70 nm in one embodiment. This height range is chosen to provide sufficient sidewall surfaces for pFET fin channels, which is approximately twice the product of the height h1and the length of the fin channel (or the gate length Lg). It is also chosen to provide a good aspect ratio for the pFET fins (which is the ratio of height h1 to width of the pFET fins) to achieve robust mikroability. If the height h1is too low (e.g., less than 40 nm), the pFET fins resulting from the semiconductor layer 104 may not have sufficient surfaces to conduct current, which would result in poorer pFET performance. If the height h1is too large (e.g., greater than 70 nm), the aspect ratio of the pFET fins resulting from the semiconductor layer 104 may be undesirably high and the pFET fins may be prone to breakage during fabrication.In operation 20, hard masks 105 are formed in the method 10 (FIG. 1A ) that are used in etching the substrate 102 and the semiconductor layer 104 to form the fins. The hard masks 105 are also referred to as fin hard masks 105. Operation 20 includes various steps illustrated in FIGS. 5A, 5B, and 5C. Referring to FIG. 5A, in operation 20, hard mask layers 105A, 105B, and 105C are formed over the top surface of the substrate 102 and the semiconductor layer 104. In an embodiment, the hard mask layer 105A includes an oxide that may be formed by oxidizing the top surface of the substrate 102 and the semiconductor layer 104 or by deposition (e.g., chemical vapor deposition (CVD)); the hard mask layer 105B includes a nitride, e.g., silicon nitride (Si 3 N 4), which may be formed by CVD; and the hard mask layer 105C includes an oxide, e.g., silicon dioxide (SiO 2) which may be formed by CVD. Referring further to FIG. 5A, patterned masks 105D are further formed over the hard mask layer 105C by the operation 20. The patterned mask 105D may be formed by one or more photolithography methods including dual or multi-patterning methods. Generally, double or multiple patterning processes combine photolithography and self-alignment processes that allow structures to be created that have, for example, spacings less than those otherwise achievable with a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over the hard mask layer 105C and patterned by a photolithography method. Spacers are formed along the patterned sacrificial layer by a self-alignment process. The sacrificial layer is then removed and the remaining spacers or mandrels become the patterned mask 105D. The patterned mask 105D may include silicon oxide, silicon nitride, or other suitable materials in various embodiments.Referring to FIG. 5B, a capping layer 105E is formed over the patterned mask 105D and the hard mask layer 105C by the operation 20 in some embodiments. In an embodiment, the capping layer 105E includes silicon nitride or other suitable materials and is deposited by atomic layer deposition (ALD). The thickness of the capping layer 105E is controlled so that the dimensions of the combined hard mask 105 (e.g., the combined dimensions of the hard masks 105D and 105E along the "X direction") are adjusted to match a target fin width. In some embodiments, the capping layer 105E is omitted at operation 20. Referring to FIG. 5C, the hard mask layers 105C, 105B, and 105A are etched using the combined hard masks 105D and 105E as an etching mask, and the combined hard masks 105D and 105E are consumed in the etching processes or removed after completion of the processes. At this stage, the fin hard masks 105 include the patterned hard masks 105A, 105B, and 105C.At operation 22, in the method 10 (FIG. 1A ), the substrate 102 and the semiconductor layer 104 are etched to form nFET fins 108 nin the nFET regions and pFET fins 108 pin the pFET regions. The resulting structure according to an embodiment is illustrated in FIG. 6. In etching the substrate 102 and the semiconductor layer 104, the fin hard masks 105 are used as etch masks. An etching process that provides the same etch rate for the semiconductor layer 104 and the substrate 102 is ideal for the operation 22 to fabricate the fins 108 nand 108 pto have the same dimensions. However, since the semiconductor layer 104 and the substrate 102 comprise different materials, in practice they are typically etched at different speeds in the same etching process. For example, if the semiconductor layer 104 comprises SiGe and the substrate 102 comprises crystalline Si, the semiconductor layer 104 may be etched faster than the substrate 102 in typical dry etching processes. Thus, if a usual etching process is used to etch the nFET and pFET regions, the pFET fins 108 pmay be narrower and higher than the nFET fins 108 n. If the difference between the dimensions (e.g., height and width) of the pFET fins 108 pand the nFET fins 108 nis large (e.g., greater than 30%), problems arise for the subsequent manufacturing processes and production yield may be reduced. In the present embodiment, at operation 22, a repeated etch process is implemented that includes multiple steps of dry etching and chemical treatment such that the nFET fins 108 nand the pFET fins 108 pmay be formed simultaneously and with closely matched dimensions (e.g., closely matched fin widths w 1 and w 2 along the "X direction" and closely matched fin heights h 3 and h 4 along the "Z direction"). This generally improves production yield while manufacturing fins 108 nand 108 pwith acceptable matched dimensions (for example, the mismatch is less than 25%). Further, the present embodiment saves manufacturing costs and manufactures the fin hard masks 105 with a better pattern uniformity by forming the fin hard masks 105 by a photolithography method compared to approaches, wherein the pFET fins 108 pand the nFET fins 108 nare etched in separate etch processes (e.g., forming a mask covering the pFET regions while the nFET regions are etched, and vice versa, which requires forming the fin hard masks 105 separately for the nFET regions and the pFET regions).FIG. 1B shows a flow chart of operation 22 using a repeated etch process, according to an embodiment. Referring to FIG. 1B, operation 22 includes a step 30 of simultaneous anisotropic etching to the pFET regions and the nFET regions. In an embodiment, in the anisotropic etching, a dry etching method is realized using HBr gas, Cl 2- gas, Ar gas, other suitable gases, or a mixture thereof. The gas flow rate, etch time, and other etch parameters (e.g., temperature and pressure) of the anisotropic etch are controlled to create an initial pattern of the pFET fins 108 pand the nFET fins 108 n. For example, in step 30, the pFET regions and the nFET regions may be etched a few nanometers deep. Then, the operation 22 proceeds to a step 32 in which isotropic etching is performed simultaneously to the pFET regions and the nFET regions. In one embodiment, in the isotropic etching, a dry etching process is implemented using NF 3- gas, CHF 3- gas, CF 4- gas, other suitable gases, or a mixture thereof. The gas flow rate, etch time, and other etch parameters (e.g., temperature and pressure) of the isotropic etch are controlled to maintain good profiles in the fins 108 nand 108 p, and to some extent balance the different etch depths between the nFET regions and the pFET regions during anisotropic etch (step 30). Next, operation 22 proceeds to a step 34 where the heights of the fins 108 nand 108 pare checked (or monitored). If the fins 108 nand 108 phave not reached a target fin height, operation 22 proceeds to a step 36 where the sidewalls of the fins 108 nand 108 pare treated with certain chemicals. For example, in step 36, a treatment gas comprising O 2, CO 2, SF 6, CH 3 F, other suitable gases, or a mixture thereof may be employed. The treatment generates some polymers on the sidewalls of the fins 108 nand 108 pthat help control the profile of the fins 108 nand 108 pduring subsequent etch processes. After completion of the treatment, operation 22 proceeds to step 30 to begin a further repetition of the anisotropic and isotropic etch processes. In operation 22, steps 30, 32, 34, and 36 may be repeated until fins 108 nand 108 pproceeds a target fin height.In one embodiment, even though the repeated etch processes are implemented in operation 22, the fins 108 nand 108 pmay still have slightly different heights (e.g., the fin heights differ by 25% from each other) at the end. The zones etched slower at operation 22 than the other zones control when to end operation 22. For example, if the substrate 102 comprises crystalline Si and the semiconductor layer 104 comprises SiGe, the nFET regions will etch more slowly than the pFET regions. Thus, in operation 22, in step 34, the height of the nFET fins 108nis used as a controller. In other words, if it is determined in step 34 that the height of the nFET fins 108 nhas reached the target fin height, operation 22 proceeds to step 38 to end the etching. In step 38, a cleaning process may also be performed on fins 108 nand 108 p. Because the pFET regions are etched faster, in the embodiment shown in FIG. 6, the final pFET fins 108 pare slightly higher than the nFET fins.Referring to FIG. 6, each nFET fin 108 nhas a width w 2 along the "X direction" and a height h 4 along the "Z" direction from the top surface of the remaining substrate 102 to the bottom surface of the fin hardmask 105. The nFET fins 108 nresult from the etching of the substrate 102 through the operation 22, thus having the same material as the substrate 102. Each pFET fin 108 phas a width w 1 along the "X direction" and a height h 3 along the "Z" direction from the top surface of the remaining substrate 102 to the bottom surface of the fin hardmask 105. Each pFET fin 108 phas an upper portion resulting from the etching of the semiconductor layer 104 by the operation 22 and a lower portion resulting from the etching of the substrate 102 by the operation 22. To simplify the description, the upper portion of the pFET fin 108 pis referred to as the upper portion 104 and the lower portion of the pFET fin 108 pis referred to as the lower portion 106. The upper portion 104 comprises the same material as the semiconductor layer 104, and the lower portion 106 comprises the same material as the substrate 102. The upper portion has a height h1, the lower portion has a height h2, and the height h3is the sum of the height h1and the height h2. Since the pFET regions are etched faster in this embodiment, the top surface of the remaining portion of the substrate 102 in the pFET region is lower than the top surface of the remaining portion of the substrate 102 in the nFET region by a step height h 5. Although FIG. 6 shows two nFET fins 108 nadjacent to two pFET fins 108 p, the present disclosure is not limited thereto. In various embodiments, there may be one or more nFET fins 108 nin an nFET region and one or more pFET fins 108 pin a pFET region.In the present embodiment, the nFET fins 108 nand the bottom portion 106 of the pFET fins 108 pcomprise crystalline Si, and the top portion 104 of the pFET fins 108 pcomprise SiGe. The width w 2 may be slightly greater than the width w 1, for example, by about 5% to about 10%, as SiGe is etched faster than Si in operation 22. For example, width w 1 may be in a range from about 6.1 nm to about 7.1 nm, and width w 2 may be in a range from about 6.5 nm to about 7.5 nm. These regions of the fin widths are selected for good gate channel control when these fins are used as FinFET channels. Further, the height h 1 is in a range from about 40 nm to about 70 nm, as described with reference to FIG. 4. The height h 4 is in a range from about 100 nm to about 115 nm in one embodiment. As will be described, the height h 4 of the nFET fins 108 nmay differ from fin to fin depending on the distance (or center-to-center distance) between the adjacent nFET fins 108 n. This range is selected to provide sufficient fin sidewall surfaces for conducting current and provide a robust aspect ratio (h4:w2) for mFET fins 108n machiety. The height h 3 is greater than the height h 4 because SiGe is etched faster than Si in operation 22. In the present embodiment, the height h 3 is slightly greater than the height h 4 due to the repeated etch and treatment processes implemented in operation 22. For example, the height h3is 25% or less, e.g., 20% or less, greater than the height h4. For example, in one embodiment, the height h 3 may be in a range from about 115 nm to about 125 nm. Further, in various embodiments, the step height h 5 may be in a range from about 10 nm to about 30 nm. Operation 22 may be adjusted to minimize step height h 5.At operation 24, in the method 10 (FIG. 1A ), an isolation structure 110 is formed over the remaining portions of the substrate 102, and the various fins 108 nand 108 pare laterally isolated. The resulting structure is illustrated in FIG. 7, in accordance with some embodiments. For example, isolation structure 110 surrounds a bottom portion of fins 108 nand 108 pto separate and isolate fins 108 nand 108 pfrom each other. The isolation structure 110 may include silicon oxide, silicon nitride, silicon oxynitride, another suitable isolation material (e.g., including silicon, oxygen, nitrogen, carbon, or other suitable isolation components), or combinations thereof. The isolation structure 110 may have various structures, e.g., shallow trench isolation (STI) structures and / or deep trench isolation (DTI) structures. In some embodiments, the isolation structure 110 has a multilayer structure. For example, the isolation structure 110 may include a thermally formed oxide liner layer on surfaces of the substrate 102 and the fins 108 nand 108 p, and a silicon nitride layer disposed over the oxide liner layer. In an embodiment, the isolation structure 110 is formed by filling the trenches between the fins 108 nand 108 pwith one or more insulator materials (e.g., by a CVD method or a spin-on-glass method); performing a chemical mechanical polishing (CMP) method to remove excess insulator materials, remove the fin hard masks 105, and / or planarize a top surface of the insulator materials; and etching back the insulator materials to form the isolation structure 110. In the present embodiment, the etch back of the isolation structure 110 is controlled such that the top surface of the isolation structure 110 in the pFET region is level with or slightly above the bottom surface of the top portion 104 of the pFET fins 108 p. Due to the step profile in the substrate 102, the upper surface of the isolation structure 110 may also include a step. In other words, the upper surface of the isolation structure 110 in the nFET regions may be slightly higher than the upper surface of the isolation structure 110 in the pFET regions by a step height h 6. In some embodiments, wherein height h5is in a range from about 10 nm to about 30 nm, height h6is in a range from about 1 nm to about 6 nm. Such a range of height h6is generally within the desired range, which results in good production yield. Operation 22 may be adjusted to minimize step height h 5, resulting in minimizing step height h 6.At operation 26, the method 10 (FIG. 1A ) proceeds to further fabrication steps to form FinFET devices over the nFET fins 108 nand the pFET fins 108 p. For example, in operation 26, dummy gates may be formed over fins 108 nand 108 p, source / drain regions may be formed by etching fins 108 nand 108 pin the source / drain regions and epitaxially growing source / drain features over remaining portions of fins 108 nand 108 pin the source / drain regions, replacing dummy gates with high-k metal gates, forming an interlayer dielectric layer, forming contacts to the source / drain features and the high-k metal gates, forming multilevel interconnect structures, and performing other fabrication steps. In this regard, FIG. 8 shows a perspective view of the device 100 after completion of operation 24, showing two nFET fins 108 nand two pFET fins 108 pthat extend from the substrate 102 and through the isolation structure 110. Each of the pFET fins 108 phas an upper portion 104 and a lower portion 106. FIG. 9A shows a perspective view of the device 100 according to an embodiment after a further production step has been carried out on the device 100 in the operation 26. FIG. 9B shows a cross-sectional view of the device 100 along the line "B-B" in FIG. 9A. As illustrated in FIGS. 9A and 9B, at operation 26, an n-type FinFET is formed over the nFET fins 108 nand a p-type FinFET over the pFET fins 108 p, with portions of the fins 108 nand 108 pfunction as the channels for the corresponding FinFET. In the embodiment illustrated in FIGS. 9A and 9B, a common high-k metal gate 112 accesses the fins 108 nand 108 pto form a CMOS device. In alternative embodiments, the n-type FinFET and the p-type FinFET may include separate high-k metal gates.Referring to FIGS. 9A and 9B, in this embodiment, device 100 includes a high-k metal gate 112, gate spacers 114 on sidewalls of high-k metal gate 112, fin sidewall spacers 116, n-source / drain features 118 nover a remaining portion of fin 108 n(after a source / drain trench etch process), and p-source / drain features 118 pover a remaining portion of fin 108 p(after a source / drain trench etch process). The apparatus 100 may include various other elements not shown in FIGS. 9A and 9B. Referring to FIG. 9B, in the p-type FinFET, the high-k metal gate 112 is disposed over the top portion 104 of the pFET fin 108 p, which provides high charge carrier mobility. The top portion 104 of the pFET fin 108 pconnects the two p-source / drain features 118 pand functions as the transistor channel. Since a semiconductor material having high mobility is used for the upper portion 104, the performance of the p-type FinFET is improved. In the present embodiment, the top portion 104 of the pFET fins 108 pin the source / drain regions is partially etched and the source / drain features 118 pare directly disposed on remaining portions of the top portion 104 in the source / drain region. In an alternative embodiment, the top portion 104 of the pFET fins 108 pin the source / drain regions is fully etched and the source / drain features 118 pare disposed directly on the bottom portion 106 in the source / drain region.The source / drain features 118 nand 118 pmay be formed by any suitable epitaxy method, e.g., vapor phase epitaxy, molecular beam epitaxy, other suitable methods of epitaxial growth, or combinations thereof. In some embodiments, the source / drain features 118 ncomprise silicon and may be doped with carbon, phosphorus, arsenic, other n-dopants, or a combination thereof (e.g., forming Si:C epitaxial source / drain features, Si:P epitaxial source / drain features, or Si:C:P epitaxial source / drain features). In some embodiments, the epitaxial source / drain features 118 nand 118 pare doped during deposition by adding foreign materials (i.e., in situdoped) to a starting material of the epitaxy method. In some embodiments, the epitaxial source / drain features 118 nand 118 pare doped by an ion implantation process after a deposition process. In some embodiments, anneal processes (e.g., rapid thermal anneal (RTA) and / or laser anneal) are performed to activate dopants in the epitaxial source / drain features 118 nand 118 p. In some embodiments, the epitaxial source / drain features 118 nand 118 pare formed in separate processing sequences including, for example, masking pFET regions when forming the epitaxial source / drain features 118 ninto nFET regions and masking nFET regions when forming the epitaxial source / drain features 118 pinto pFET regions.In an embodiment, high-k metal gate 112 includes high-k gate dielectric layer 112A and gate electrode layer 112B. The gate electrode layer 112B may include a work function layer and a bulk metal layer. The high-k metal gate 112 may include further layers, e.g., an interfacial dielectric layer between the top portion 104 and the high-k gate dielectric layer 112A. In various embodiments, the interfacial dielectric layer may include a dielectric material such as silicon oxide, silicon oxynitride, or silicon germanium oxide, and may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The interfacial dielectric layer may include different dielectric materials for n-type FinFETs and for p-type FinFETs. For example, the interfacial dielectric layer may include silicon oxide for n-type FinFETs and silicon germanium oxide for p-type FinFETs. The high-k gate dielectric layer 112A may include hafnium oxide (HfO 2), zirconium oxide (ZrO 2), lanthanum oxide (La 2 O 3), titanium oxide (TiO 2), yttrium oxide (Y 2 O 3), strontium titanate (SrTiO 3), other suitable metal oxides, or combinations thereof, and may be formed by ALD and / or other suitable methods. The work function layer (portion of the gate electrode layer 112B) may include a metal selected from, but not limited to, the group consisting of titanium aluminum nitride (TiAlN), titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten (W), platinum (Pt), aluminum (Al), or combinations thereof; and may be deposited by CVD, PVD, and / or another suitable method. The bulk metal layer (portion of the gate electrode layer 112B) may include a metal such as aluminum (Al), tungsten (W), cobalt (Co), copper (Cu), and / or other suitable materials, and may be deposited by plating, CVD, PVD, or other suitable methods.Each of the fin sidewall spacers 116 and the gate spacers 114 may be a single layer or a multilayer structure. In some embodiments, each of the spacers 116 and 114 includes a dielectric material, such as silicon oxide (SiO 2), silicon nitride (Si 3 N 4), silicon oxynitride (SiON), another dielectric material, or combinations thereof. In one example, spacers 116 and 114 are formed by depositing a first dielectric layer (e.g., a SiO 2- layer having a substantially uniform thickness) as a liner layer over device 100 and a second dielectric layer (e.g., a Si 3 N 4- layer) as a main D-shaped spacer over the first dielectric layer, and then performing anisotropic etching to remove portions of the dielectric layers to form spacers 116 and 114. Additionally, the fin sidewall spacers 116 may be partially removed during the etching process, which forms recesses in the fins 108 nand 108 pbefore the source / drain features 118 nand 118 pare formed. In some embodiments, the fin sidewall spacers 116 may be completely removed by such an etching process.FIG. 10 shows a cross-sectional view of a portion of the apparatus 100 according to an embodiment. For example, the portion of the device 100 in FIG. 10 may be a portion of a ring oscillator circuit, wherein a high-power p-type FinFET may be used to boost the performance of the circuit. Referring to FIG. 10, the device 100 includes dual nFET fins 108 nand dual pFET fins 108 pin a repeating structure. In particular, the device 100 includes a repeating structure of a pair of nFET fins 108 n, another pair of nFET fins 108 n, a pair of pFET fins 108 p, and another pair of pFET fins 108 p. In some embodiments, the two nFET fins 108 nin the same pair are used to form a single n-type FinFET and the two pFET fins 108 pin the same pair are used to form a single p-type FinFET. The distance (center-to-center distance) between two nFET fins 108 nin the same pair is S 2 and the distance between two pFET fins 108 pin the same pair is S 4. In one embodiment, S4is substantially equal to S2. The center-to-center distance between one nFET fin 108 nand another nFET fin 108 nof two adjacent pairs is S 1. The center-to-center distance between one pFET fin 108 pand another pFET fin 108 pfrom two adjacent pairs is S 5. The center-to-center distance between an nFET fin 108 nand another pFET fin 108 pof two adjacent pairs is S 3. In one embodiment, the distances S 1, S 3, and S 5 are substantially equal. FIG. 10 also shows various depths D 1, D 2, D 3, D 4, D 5, D 6, and D 7 measured from the top surface of the fins 108 n / 108 pto the top surface of the substrate 102, respectively, after operation 22 is completed. The depth D 1 is measured between two nFET fins 108 nof the same pair. The depth D 2 is measured between two adjacent pairs of nFET fins 108 n. The depths D 3, D 4, and D 5 are measured at different points between a pair of nFET fins 108 nand a pair of pFET fins 108 p. The depth D 6 is measured between two adjacent pairs of pFET fins 108 p. The depth D 7 is measured between two pFET fins 108 pof the same pair.FIG. 10 shows the influence of the distances S 1 to S 5 on the depths D 1 to D 7. Specifically, when two fins in the same device region (both in nFET regions or both in pFET regions) are closer together, an etch depth between the two fins is less. For example, each of the distances S 1 and S 5 is greater than the distances S 2 and S 4, and each of the depths D 2 and D 6 is greater than the depths D 1 and D 7. Further, although S2 and S4 are substantially equal, the depth D7 is greater than the depth D1 because the semiconductor layer 104 is etched at a faster rate than the substrate 102 as described above. In some embodiments, the depth D 7 is greater than the depth D 1, e.g., by about 5% to about 20%, by about 25% or less. For the same reason, the depth D 6 is greater than the depth D 2, although S 1 and S 5 are substantially the same. In some embodiments, the depth D 6 is greater than the depth D 2 by about 25% or less, e.g., by about 5% to about 20%. The difference between D 6 and D 2 represents the step height h 5 (FIG. 6 ) for this embodiment. The depths D 3, D 4, and D 5 increase stepwise as the measurement point moves from the nFET fin 108 ntoward the pFET fin 108 p. In other words, D4 is greater than D3 and D5 is greater than D4. Further, in this embodiment, the depth D 2 is less than or equal to the depth D 3 and the depth D 5 is less than or equal to the depth D 6. The gradual change in the depths from D 3 to D 5 represents the step between an nFET region and a pFET region as illustrated in FIG. 6.In an embodiment, the width of the pFET fins 108 pis in a range from about 6.1 nm to about 7.1 nm and the width of the nFET fins 108 nis greater than the width of the pFET fins 108 pand may be in a range from about 6.5 nm to about 7.5 nm. These fin width ranges are chosen to achieve desirable FinFET performance, e.g., drain induced barrier lowering (DIBL), as well as increasing fin density. Further, S2 and S4 are in a range from about 23 nm to about 28 nm, and S1, S3 and S5 are in a range from about 68 nm to about 73 nm. These spacer regions are chosen to increase fin density (or device density) while avoiding fin-to-fin bridging problems. Further, depth D 1 is in a range from about 100 nm to about 105 nm; depth D 2 is in a range from about 101 nm to about 106 nm; depth D 3 is in a range from about 105 nm to about 110 nm; depth D 4 is in a range from about 113 nm to about 118 nm; depths D 5 and D 6 are each in a range from about 120 nm to about 125 nm; and depth D 7 is in a range from about 115 nm to about 120 nm. These depth regions achieve good uniformity of the depths, which provides good topography when performing a CMP on the isolation structure 110.FIG. 11 shows a cross-sectional view of a portion of the apparatus 100 according to another embodiment. For example, the portion of device 100 in FIG. 11 may be a portion of an SRAM circuit, and a high-power p-type FinFET may be used to boost the performance of the circuit. Referring to FIG. 11, the device 100 includes dual nFET fins 108 nand dual pFET fins 108 pin a repeating structure. In particular, the device 100 includes a repeating structure of a single pFET fin 108 p, another single pFET fin 108 p, a pair of nFET fins 108 n, another pair of nFET fins 108 n, a single pFET fin 108 p, and another single pFET fin 108 p. In some embodiments, the two nFET fins 108 nin the same pair are used to form a single n-type FinFET and each pFET fin 108 pis used to form a single p-type FinFET. The distance (center-to-center distance) between two nFET fins 108 nin the same pair is S 8, the distance between two adjacent pFET fins 108 pis S 6, the distance between one pFET fin 108 pand one adjacent nFET fin 108 nis S 7, and the distance between two nFET fins 108 nfrom two adjacent pairs is S 9. In one embodiment, S7 is substantially equal to S9 and S8 is less than S6 which is less than S7. FIG. 11 also shows various depths D 8, D 9, D 10, and D 11 measured from the top surface of the fins 108 n / 108 pto the top surface of the substrate 102, respectively, after completion of the operation 22. The depth D 8 is measured between two adjacent pFET fins 108 p. The depth D 9 is measured between a pFET fin 108 pand an adjacent nFET fin 108 n. The depth D 10 is measured between two nFET fins 108 nof the same pair. The depth D 11 is measured between two adjacent pairs of nFET fins 108 n.FIG. 11 shows the influence of the distances S 6 to S 9 on the depths D 8 to D 11. Specifically, when two fins in the same device region (both in nFET regions or both in pFET regions) are closer together, an etch depth between the two fins is less. For example, the distance S 9 is greater than the distance S 8 and the depth D 11 is greater than the depth D 10 (both are measured between the nFET fins 108 n). Further, although S 7 and S 9 are substantially the same, since the depth D 9 is between a pFET fin 108 pand an nFET fin 108 n, and the semiconductor layer 104 is etched at a faster rate than the substrate 102, the depth D 9 is greater than the depth D 11 as described above. Further, depending on the distances S 6 and S 7, in various embodiments, the depth D 8 may be greater than, equal to, or less than the depth D 9. If the distance S 6 is about equal to the distance S 7 (e.g., within 10% of each other), the depth D 8 may be greater than or equal to the depth D 9, as the depth D 8 between two pFET fins 108 pis measured and the depth D 9 between one pFET fin 108 pand one nFET fin 108 nis measured. In some embodiments, the depth D 11 is greater than the depth D 10 by about 10% or less. In some embodiments, the depth D 8 is greater than the depth D 11 by about 20% or less, e.g., by about 5% to about 12%. The difference between D 8 and D 11 represents the step height h 5 (FIG. 6 ) for this embodiment.In an embodiment, the width of the pFET fins 108 pis in a range from about 6.1 nm to about 7.1 nm and the width of the nFET fins 108 nis greater than the width of the pFET fins 108 pand may be in a range from about 6.5 nm to about 7.5 nm. These fin width ranges are chosen to achieve desirable FinFET performance, e.g., DIBL (drain-induced barrier sinking), as the fin density is increased. Further, the distance S 6 is in a range from about 33 nm to about 38 nm; the distance S 7 is in a range from about 40 nm to about 45 nm; the distance S 8 is in a range from about 23 nm to about 28 nm; and the distance S 9 is in a range from about 40 nm to about 45 nm. These spacer regions are chosen to increase fin density (or device density) while avoiding fin-to-fin bridging problems. Further, depth D 8 is in a range from about 120 nm to about 125 nm; depth D 9 is in a range from about 117 nm to about 122 nm; depth D 10 is in a range from about 100 nm to about 105 nm; and depth D 11 is in a range from about 108 nm to about 113 nm. These depth regions achieve good uniformity of the depths, which provides good topography when performing a CMP on the isolation structure 110.Without being limiting, embodiments of the present disclosure provide one or more of the following advantages. For example, in embodiments of the present disclosure, pFET fins and nFET fins are formed over the same substrate, where the pFET fins include a material that has a higher hole mobility than the material of the nFET fins. This improves the performance of p-type FinFETs formed from the pFET fins. Further, in embodiments of the present disclosure, the pFET fins and nFET fins are etched by a common method in which repeated etching and processing is realized. Such a method reduces or minimizes the difference in dimensions of the pFET fins and the nFET fins and results in good planarity of an isolation structure formed below. Embodiments of the present disclosure may be easily incorporated into existing semiconductor manufacturing methods.The invention relates to a method comprising providing a substrate comprising a first semiconductor material; forming a mask covering an nFET region of the substrate; etching a pFET region of the substrate to form a trench; epitaxially growing a second semiconductor material in the trench, the second semiconductor material being different from the first semiconductor material; and patterning the nFET region and the pFET region to form a first fin in the nFET region and a second fin in the pFET region, the first fin including the first semiconductor material and the second fin including an upper portion over a lower portion, the upper portion including the second semiconductor material and the lower portion including the first semiconductor material.In an embodiment of the method, the substrate is a silicon substrate and the second semiconductor material comprises silicon germanium. In an embodiment, the method further includes planarizing a top surface of the nFET region and the pFET region after epitaxially growing the second semiconductor material.Patterning the nFET region and the pFET region includes forming fin hard masks over the nFET region and the pFET region and etching the nFET region and the pFET region through the fin hard masks by the same method to form the first and second fins. The etching of the nFET region and the pFET region includes anisotropically etching the nFET region and the pFET region through the fin hard masks; after the anisotropic etching, isotropically etching the nFET region and the pFET region through the fin hard masks; treating a pattern resulting from the anisotropic etching and the isotropic etching with a treatment gas mixture, and repeating the anisotropic etching, the isotropic etching, and the treating to form the first fin in the nFET region and the second fin in the pFET region, wherein different gases are applied in the anisotropic etching, the isotropic etching, and the treating. In some embodiments, the anisotropic etching includes applying HBr, Cl 2, Ar, or a mixture thereof. In some embodiments, the isotropic etching includes applying NF 3, CHF 3, CF 4 or a mixture thereof. In some embodiments, the treating comprises applying O 2, CO 2, SF 6, CH 3 F, or a mixture thereof.In an embodiment, the method further comprises forming an isolation structure between the first fin and the second fin, wherein a first bottom surface of the isolation structure adjacent to the first fin is about 10 nm to about 30 nm higher than a second bottom surface of the isolation structure adjacent to the second fin.In another exemplary aspect, the present disclosure relates to a structure including a substrate; a first fin extending from the substrate; and a second fin extending from the substrate. The second fin has an upper portion over a lower portion. The first fin and the bottom portion of the second fin include crystalline silicon. The upper portion of the second fin includes a semiconductor material having a higher charge carrier mobility than silicon. A top surface of the second fin and a top surface of the first fin are substantially coplanar. The lower portion of the second fin extends deeper than the first fin toward the substrate.In an embodiment of the structure, the first fin extends from a first portion of the substrate, the second fin extends from a second portion of the substrate, the first portion being higher than the second portion. In another embodiment, the first portion is about 10 nm to about 30 nm higher than the second portion. In another embodiment of the structure, the upper portion of the second fin includes silicon germanium.In an embodiment, the structure further includes an isolation structure adjacent to the first fin and the second fin, wherein a top surface of the isolation structure is approximately level with a bottom surface of the top portion of the second fin. In some embodiments, the structure further includes a first gate structure over the isolation structure that engages the first fin; and a second gate structure over the isolation structure that engages the top portion of the second fin.In yet another exemplary aspect, the present disclosure relates to a structure including a substrate; two first adjacent fins extending from a first region of the substrate; two second adjacent fins extending from a second region of the substrate; and an isolation structure over the substrate and adjacent to the first and second fins. Each of the second fins has an upper portion over a lower portion. The first fins and the bottom portions of the second fin include crystalline silicon. The upper portions of the second fins include silicon germanium. Top surfaces of the second fins and top surfaces of the first fins are substantially coplanar. Each of the second fins is higher than the first fins.In an embodiment of the structure, a first portion of the isolation structure extends laterally between the two first fins, a second portion of the isolation structure extends laterally between the two second fins, a first distance between the two first fins is about equal to a second distance between the two second fins, and a depth of the first portion of the isolation structure is less than a depth of the second portion of the isolation structure. In another embodiment, a third portion of the isolation structure extends laterally between one of the two first fins and one of the two second fins, and a depth of the third portion of the isolation structure is greater than the depth of the second portion of the isolation structure.In an embodiment of the structure, a first portion of the isolation structure extends laterally between the two first fins, a second portion of the isolation structure extends laterally between the two second fins, a first distance between the two first fins is less than a second distance between the two second fins, and a depth of the first portion of the isolation structure is less than a depth of the second portion of the isolation structure. In another embodiment, a third portion of the isolation structure extends laterally between one of the two first fins and one of the two second fins, and a depth of the third portion of the isolation structure is greater than the depth of the first portion of the isolation structure and less than the depth of the second portion of the isolation structure.

Claims

A method comprising: providing a substrate (102) comprising a first semiconductor material; creating a mask (103) covering an nFET region of the substrate (102); etching a pFET region of the substrate (102) to form a trench (102'); epitaxially growing a second semiconductor material in the trench (102'), wherein the second semiconductor material is different from the first semiconductor material; and patterning the nFET region and the pFET region to form a first fin (108n) in the nFET region and a second fin (108p) in the pFET region, the first fin (108n) comprising the first semiconductor material and the second fin (108p) comprising an upper portion (104) over a lower portion (106), the upper portion (104) comprising the second semiconductor material and the lower portion (106) comprising the first semiconductor material, wherein patterning the nFET region and the pFET region comprises: forming fin hard masks (105) over the nFET region and the pFET region; and etching the nFET region and the pFET region through the fin hard masks (105) by the same method to form the first (108n) and second fins (108p), wherein etching the nFET region and the pFET region comprises: anisotropically etching the nFET region and the pFET region through the fin hard masks (105); isotropically etching the nFET region and the pFET region through the fin hard masks (105) after the anisotropic etching; treating a structure resulting from the anisotropic etching and the isotropic etching with a treatment gas mixture; and repeating the anisotropic etching, the isotropic etching, and the treating to form the first fin (108n) in the nFET region and the second fin (108p) in the pFET region, wherein different gases are applied in the anisotropic etching, the isotropic etching, and the treating.The method of claim 1, wherein the substrate (102) is a silicon substrate and the second semiconductor material comprises silicon germanium.The method of claim 1 or 2, further comprising: planarizing a top surface of the nFET region and the pFET region after epitaxially growing the second semiconductor material.The method of any one of claims 1 to 3, wherein the anisotropic etching comprises applying HBr, Cl 2, Ar, or a mixture thereof.The method of any one of claims 1 to 3, wherein the isotropic etching comprises applying NF 3, CHF 3, CF 4 or a mixture thereof.The method of any one of claims 1 to 5, wherein the treating comprises applying O 2, CO 2, SF 6, CH 3 F, or a mixture thereof.The method of any of claims 1 to 6, further comprising: forming an isolation structure (110) between the first fin (108n) and the second fin (108p), wherein a first bottom surface of the isolation structure (110) adjacent to the first fin (108n) is about 10 nm to about 30 nm higher than a second bottom surface of the isolation structure (110) adjacent to the second fin (108p).

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