Multigate component with channel configuration for performance improvement and method for its manufacture

Abstract

Component comprising: a channel arranged over a substrate (202), the channel comprising a first nanosheet (215A, 230-1, 215B), a second nanosheet (215A, 230-1, 215B) and a nanosheet connecting section (230-2) connecting the first nanosheet (215A, 230-1, 215B) and the second nanosheet (215A, 230-1, 215B), wherein: between the first nanosheet (215A, 230-1, 215B) and the second nanosheet (215A, 230-1, 215B) in a first direction which is essentially perpendicular to the substrate (202), a distance (h2) is present. the nanosheet connection section (230-2) has a thickness (s4) in a second direction which is essentially parallel to the substrate (202), and the thickness (s4) is less than the distance (h2); a first source / drain feature (270) and a second source / drain feature (270) arranged above the substrate (202), wherein the first nanosheet (215A, 230-1, 215B) and the second nanosheet (215A, 230-1, 215B) extend in a third direction from the first source / drain feature (270) and the second source / drain feature (270), the third direction being different from the first direction and the second direction; and a metal gate (296, 298) located between the first source / drain feature (270) and the second source / drain feature (270), wherein the metal gate (296, 298) encloses the channel.

Description

BACKGROUND

[0001] The electronics industry has experienced a growing need for smaller and faster electronic components capable of supporting a greater number of increasingly complex and sophisticated functions simultaneously. To meet these demands, the IC industry has seen an ongoing trend toward producing ICs (integrated circuits) that are low-cost, high-performance, and low-power. To date, these goals have largely been achieved by reducing IC dimensions (e.g., the minimum size of IC features) to improve manufacturing efficiency and lower associated costs. However, such downscaling also increases the complexity of IC manufacturing processes. Therefore, achieving continued progress in IC components and their performance requires similar advances in IC manufacturing processes and IC technology.

[0002] Recently, multigate devices have been introduced to improve gate control. Multigate devices have been observed to increase gate-channel coupling, decrease reverse current, and / or reduce short-channel effects (SCEs). Such a multigate device is a gate-all-around (GAA) device that incorporates a gate structure which can partially or completely surround a channel area to provide access to the channel area on at least two sides. GAA devices enable a significant downscaling of IC technology, maintain gate control, and mitigate SCEs, while seamlessly integrating into conventional IC manufacturing processes. However, with the ongoing scaling of IC density, increasing the drive current of GAA devices has become problematic.While GAA components and methods for manufacturing them have generally been sufficient for the intended purposes, they have not yet been completely satisfactory in every respect.

[0003] Prior art relating to the subject matter of the invention can be found, for example, in US 2017 / 0104061A1 and US 2019 / 0057867A1.

[0004] The invention is defined by the main claim and the dependent claim. Further embodiments of the invention are described by the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The present disclosure is best understood by referring to the following detailed description, which is read in conjunction with the accompanying figures. It is emphasized that, in accordance with standard industry practice, various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various features may be enlarged or reduced as desired for the clarity of the discussion. Fig. Figure 1 is a flowchart of a process for manufacturing a multigate device according to various aspects of the present disclosure. Fig. 2A-17A, Fig. 2B-17B, Fig. 2C-17C, Fig. 2D-17D and Fig. 2A-17E are schematic partial views of a section or the entirety of a multigate device at various stages of fabrication (such as those produced using the method in Fig. 1 are connected) according to various aspects of the present revelation. Fig. Figures 18A-18C are three-dimensional perspective views of a section or the entirety of the multigate device in manufacturing stages, which are Fig. 15A-15E ( Fig. 18A) or Fig. 17A-17E ( Fig. 18B and Fig. 18B) are connected, according to various aspects of the present revelation. Fig. 19A and Fig. 19B provide graphs of a percentage change in the effective channel width as a function of the horizontal segment leaf width, leaf spacing, and vertical segment leaf width of a multigate device according to various aspects of the present disclosure. Fig. Figure 20 presents cross-sectional views of two different multigate components, one of which was constructed according to the method from Fig. 1 was produced, and a graph of the driver current as a function of the leaf spacing according to various aspects of the present disclosure is provided. Fig. Figures 21A-21F are partial cross-sectional views of a section or the entirety of another multigate device at various stages of fabrication (such as those produced using the method in Fig. 1 are connected) according to various aspects of the present revelation. Fig. Figures 22A-22F are partial cross-sectional views of a section or the entirety of another multigate device at various stages of fabrication (such as those produced using the method in Fig. 1 are connected) according to various aspects of the present revelation. Fig. Figures 23A-23H are partial cross-sectional views of a section or the entirety of another multigate device at various stages of fabrication (such as those produced using the method in Fig. 1 are connected) according to various aspects of the present revelation. DETAILED DESCRIPTION

[0006] The present disclosure relates generally to integrated circuit components and in particular to multigate components such as gate-all-around (GAA) components.

[0007] Recently, multigate devices have been introduced to improve gate control. Multigate devices have been observed to increase gate-channel coupling, decrease reverse current, and / or reduce short-channel effects (SCEs). Multigate devices incorporate a gate structure that can partially or completely surround a channel region to provide access to the channel region on at least two sides. Such a multigate device is a gate-all-around (GAA) device, which includes channel layers (regions) that are stacked and suspended vertically or horizontally in such a way that a gate structure can enclose (or surround) the channel layers. GAA devices enable a significant downscaling of IC technology, maintain gate control, and mitigate SCEs, while seamlessly integrating into conventional IC manufacturing processes.

[0008] Due to the scaling of GAA devices, channel layers often have dimensions in the nanometer range and feature contours designed to optimize performance, such as cylindrical shapes (e.g., nanowires), rectangular shapes (e.g., nanorods), and / or sheet shapes (e.g., nanosheets). Since nanosheet channel layers have wider channels (i.e., a larger effective channel width (W)), effGAA devices with nanosheet channel layers can provide higher driver currents and thus switch on / off faster. With nanosheet-based GAA devices, the size of conventional standard cells limits the increase in nanosheet channel width and therefore also the corresponding increase in current-conducting area and driver current. For example, increasing the nanosheet channel width increases the footprint of a nanosheet-based GAA device in a standard cell, which is incompatible with the dense packing of IC features (e.g., GAA devices) required for nodes in advanced IC technology within standard cells.While increasing the number of nanosheet channel layers in nanosheet-based GAA devices can further increase the driver current without increasing their footprint, it has been observed that increasing the number of nanosheet channel layers undesirably increases the parasitic capacitance and thus reduces the performance of the nanosheet-based GAA device. Furthermore, increasing the number of nanosheet channel layers introduces challenges in source / drain design and fabrication that can offset any increase in driver current achieved through the additional nanosheet channel layers.

[0009] To overcome such challenges, the present disclosure proposes multigate devices, such as GAA devices, with at least two sheet-like channel layers connected by a channel link section. Such a configuration provides multigate devices with sheet-like channels, T-channels, H-channels, E-channels, F-channels, and / or combinations thereof. Multigate devices with the sheet-like channel layers connected by channel link sections exhibit larger current-conducting areas compared to conventional GAA devices and can therefore provide a higher drive current. The proposed techniques for fabricating the sheet-like channel layers connected by channel link sections are easily and seamlessly integrated into existing multigate device fabrication.The proposed techniques for fabricating sheet-like channel layers connected by channel link sections also allow for tuning the current-conducting area (for example, by adjusting the spacing between sheet-like channel layers (e.g., nanosheets) and / or the thickness of the channel link sections) and thus tuning the driver current based on design considerations of the disclosed multigate devices. In some embodiments, a window for filling metal gates is enlarged by tuning the current-conducting area. Details of the proposed sheet-like channel layers connected by channel link sections for multigate devices and methods for fabricating them are described on the following pages and / or in the drawings.

[0010] Fig. Figure 1 is a flowchart of a method 100 for fabricating a multigate device according to various aspects of the present disclosure. In some embodiments, the method 100 fabricates a transistor of a multigate device comprising sheet-like channel layers, wherein at least two of the sheet-like channel layers are connected by a channel connection section. In block 102, a semiconductor layer stack is formed over a substrate. The semiconductor layer stack comprises first semiconductor layers and second semiconductor layers stacked vertically in an alternating configuration. In block 104, a semiconductor strand is formed in the semiconductor layer stack. The semiconductor strand extends from a first of the first semiconductor layers through one of the second semiconductor layers to a second of the first semiconductor layers. The semiconductor strand has a first width.In Block 106, the semiconductor layer stack is structured to form a fin structure extending from the substrate. The fin structure comprises a portion of the first of the first semiconductor layers, a portion of one of the second semiconductor layers, and a portion of the second of the first semiconductor layers. The fin structure further comprises the semiconductor strand. In some embodiments, the semiconductor strand is formed before the semiconductor layer stack is structured to form the fin structure. In other embodiments, the semiconductor strand is formed after the semiconductor layer stack has been structured to form the fin structure. In Block 108, the portion of one of the second semiconductor layers is selectively removed from the semiconductor layer stack such that the first of the first semiconductor layers is separated from the second of the first semiconductor layers by a distance in a first direction.The semiconductor strand extends in the first direction between the first and second semiconductor layers, connecting them. In block 110, the semiconductor strand is trimmed to reduce the first width to a second width. The first and second widths run in a second direction, different from the first. In some embodiments, the first width is greater than the spacing, and the second width is less than the spacing. Additional steps may be provided before, during, and after Method 100, and some of the described steps may be shifted, substituted, or omitted in additional embodiments of Method 100. The following discussion illustrates various embodiments for multigate devices with improved performance characteristics that can be fabricated using Method 100.

[0011] Fig. 2A-17A, Fig. 2B-17B, Fig. 2C-17C, Fig. 2D-17D and Fig. 2E-17E are schematic partial views of a section or the entirety of a Multigate component 200 in various stages of manufacture (such as those produced using method 100 in Fig. 1 are connected) according to various aspects of the present revelation. In particular, are Fig. 2A-17A Top views of the Multigate component 200 in an XY plane; Fig. Figures 2B-17B are schematic cross-sectional views of the Multigate component 200 in a YZ plane, each along line BB' in Fig. 2A-17A; Fig. 2C-17C are schematic cross-sectional views of the Multigate component 200 in a YZ plane, each along the corresponding line CC' in Fig. 2A-17A; Fig. 2D-17D are schematic cross-sectional views of the Multigate component 200 in the XZ plane, each along the line DD' in Fig. 2A-17A; and Fig. 2E-17E are schematic cross-sectional views of the Multigate component 200 in the XZ plane, each along the line EE' in Fig. 2A-17A. Fig. Figures 18A-18C are three-dimensional perspective views of a section or the entirety of the Multigate 200 component in manufacturing stages, which are equipped with Fig. 15A-15E ( Fig. 18A) or Fig. 17A-17E ( Fig. 18B and Fig. 18B). The multigate component 200 can be contained within a microprocessor, a memory, and / or another IC component. In some embodiments, the multigate component 200 is a section of an IC chip, a system-on-a-chip (SoC), or a section thereof, comprising various passive and active microelectronic components, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS transistors (LDMOS transistors), high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. Fig. 2A-17A, Fig. 2B-17B, Fig. 2C-17C, Fig. 2D-17D and Fig. References 2E-17E have been simplified for clarity to make the concepts of the invention as presented in this disclosure more understandable. Additional features may be added to the multigate device 200, and some of the features described below may be replaced, modified, or omitted in other embodiments of the multigate device 200.

[0012] Referring to Fig. In Figures 2A-2E, the multigate device 200 comprises a substrate (wafer) 202. In the illustrated embodiment, the substrate 202 contains silicon. Alternatively or additionally, the semiconductor substrate 202 contains another elemental semiconductor such as germanium; a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Alternatively, the substrate 202 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. Semiconductor-on-insulator substrates can be fabricated using SIMOX (Separation by Implantation of Oxygen), wafer bonding and / or other suitable methods.Depending on the design requirements for the multigate device 200, the substrate 202 can comprise various doped regions. In the illustrated embodiment, the substrate 202 comprises a doped region 204 (hereinafter referred to as the doped well) containing n-type dopants, p-type dopants, or a combination thereof. For example, the doped well 204 is a p-type doped region, such as a p-type well configured for an n-GAA transistor. In another example, the doped well 204 is an n-type doped region, such as an n-type well configured for a p-GAA transistor. N-type doped regions are doped with n-type dopants, such as phosphorus, arsenic, other n-type dopants, or combinations thereof. P-type doped regions are doped with p-type dopants, such as boron, indium, other p-type dopants, or combinations thereof.In some embodiments, the substrate 202 comprises doped regions formed with a combination of p-type and n-type dopants. The various doped regions, such as the doped well 204, can be formed directly on and / or within the substrate 202, for example, to provide a p-well structure, an n-well structure, a double-well structure, a raised structure, or combinations thereof. An ion implantation process, a diffusion process, and / or another suitable doping process can be carried out to form the various doped regions, such as the doped well 204.

[0013] A semiconductor layer stack 205 is formed on the substrate 202, the semiconductor layer stack 205 comprising semiconductor layers 210 and semiconductor layers 215 stacked vertically (e.g., in the z-direction) on a surface of the substrate 202 in an alternating configuration. In some embodiments, the semiconductor layers 210 and the semiconductor layers 215 are grown epitaxially in the alternating configuration shown. For example, a first semiconductor layer 210 is grown epitaxially on the substrate 202, a first semiconductor layer 215 is grown epitaxially on the first semiconductor layer 215, a second semiconductor layer 210 is grown epitaxially on the first semiconductor layer 215, and so on, until the semiconductor layer stack 205 comprises a desired number of semiconductor layers 210 and semiconductor layers 215.In such embodiments, the semiconductor layers 210 and the semiconductor layers 215 can be referred to as epitaxial layers. In some embodiments, the epitaxial growth of the semiconductor layers 210 and the semiconductor layers 215 is achieved by a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) process, a metal-organic chemical vapor deposition (MOCVD) process, another suitable epitaxial growth process, or combinations thereof. The composition of the semiconductor layers 210 differs from the composition of the semiconductor layers 215 to achieve etch selectivity and / or different oxidation rates during subsequent processing.In some embodiments, the semiconductor layers 210 have a first etch rate with respect to an etchant, and the semiconductor layers 215 have a second etch rate with respect to the etchant, the second etch rate being different from the first etch rate. In some embodiments, the semiconductor layers 210 have a first oxidation rate, and the semiconductor layers 215 have a second oxidation rate, the second oxidation rate being different from the first oxidation rate. In the illustrated embodiment, the semiconductor layers 210 and the semiconductor layers 215 have different materials, atomic percentages of the composition, weight percentages of the composition, thicknesses, and / or properties to achieve the desired etch selectivity during an etching process, for example, an etching process performed to form suspended channel layers in channel regions of the multigate device 200.For example, if semiconductor layers 210 contain silicon germanium and semiconductor layers 215 contain silicon, the silicon etch rate of semiconductor layers 215 will differ from the silicon germanium etch rate of semiconductor layers 210. In some embodiments, semiconductor layers 210 and semiconductor layers 215 can contain the same material, but with different atomic percentages of the composition to achieve different etch selectivity and / or oxidation rates. For example, semiconductor layers 210 and semiconductor layers 215 can contain silicon germanium, wherein semiconductor layers 210 have a first silicon atomic percentage and / or a first germanium atomic percentage, and semiconductor layers 215 have a different second silicon atomic percentage and / or a different second germanium atomic percentage.The present disclosure considers that the semiconductor layers 210 and the semiconductor layers 215 may contain semiconductor materials in any combination which may provide a desired etch selectivity, desired differences in oxidation rate and / or desired performance characteristics (e.g. materials which maximize current flow), including any of the semiconductor materials disclosed herein.

[0014] As described below, the semiconductor layers 215, or sections thereof, form channel regions (channels) of the multigate device 200. In the illustrated embodiment, the semiconductor layer stack 205 comprises three semiconductor layers 210 and three semiconductor layers 215 configured to form three semiconductor layer pairs arranged over the substrate 202, each semiconductor layer pair comprising a corresponding first semiconductor layer 210 and a corresponding second semiconductor layer 215. Such a configuration results in the multigate device 200 having three channels after subsequent processing. However, the present disclosure also considers embodiments in which the semiconductor layer stack 205 comprises more or fewer semiconductor layers, for example, depending on a requirement for the multigate device 200 (e.g.,a GAA transistor) desired number of channels and / or design requirements for the multigate device 200. For example, the semiconductor layer stack 205 can comprise two to ten semiconductor layers 210 and two to ten semiconductor layers 215. According to another aspect of the illustrated embodiment, the semiconductor layers 210 have a thickness t1 and the semiconductor layers 215 have a thickness t2, wherein the thickness t1 and the thickness t2 are chosen based on considerations regarding the fabrication and / or device performance of the multigate device 200. For example, the thickness t1 can be configured to provide a desired spacing (or gap) between adjacent channels of the multigate device 200 (e.g.,between the semiconductor layers 215), the thickness t2 can be configured to achieve a desired thickness of channels of the multigate device 200, and both the thickness t1 and the thickness t2 can be configured to achieve the desired performance of the multigate device 200. In some embodiments, the thickness t1 is approximately 6 nm to approximately 15 nm. In some embodiments, the thickness t2 is approximately 6 nm to approximately 15 nm.

[0015] Referring to Fig. In steps 3A-3E, an extreme ultraviolet (EUV) lithography process is performed to form a structured EUV mask layer, such as an EUV mask 220, over the multigate device 200. The EUV mask 220 has an opening 222 that partially exposes a channel region C of the multigate device 200, which can correspond to a channel region of a transistor of the multigate device 200. Fig. 3A-3E exposes a central section of channel area C with the EUV mask 220 and covers peripheral sections of channel area C. "EUV lithography process" generally refers to a lithography process in which EUV light (radiation) is used during exposure. For example, the EUV mask 220 is formed by depositing an EUV photoresist layer over the semiconductor stack 205 (in some embodiments by rotational coating), performing an exposure process using a mask, and performing a development process. During the exposure process, the EUV photoresist layer is exposed to EUV light, with the mask, depending on a mask structure, reflecting the EUV light onto the EUV photoresist layer such that an image corresponding to the mask structure is projected onto the EUV photoresist layer. In some embodiments, the wavelength of the EUV light is approximately 11 nm to approximately 15 nm (e.g., approximately 13.5 nm).Since the EUV photoresist layer is sensitive to EUV light, exposed sections of the EUV photoresist layer are chemically modified and become either resistant (insoluble) or insoluble (soluble) to a developing solution. During the development process, depending on the properties of the EUV photoresist layer and the properties of the developing solution, exposed (or unexposed) sections of the EUV photoresist layer dissolve in the developing solution. After development, the structured EUV photoresist layer (i.e., the EUV mask 220) comprises a photoresist structure corresponding to the mask. In some embodiments, the EUV lithography process includes performing a bake-out process before exposure and / or performing a bake-out process after exposure. The EUV photoresist layer contains a photoresist material that is sensitive to EUV light (i.e., properties of the photoresist material change in response to exposure to EUV light).The photoresist material can comprise a polymer resistant to an IC process (e.g., an etching process and / or an implantation process), an acid-labile group (ALG), an acid-generating component (e.g., a photoacid generator (PAG)), a thermal acid generator component (TAG), a (basic) neutralizer component (quencher), a chromophoric component, a crosslinking component, a surfactant component, a solvent component, and / or another suitable component. In some embodiments, the EUV photoresist layer is a metal protective layer, for example, a metal oxide protective layer.

[0016] Referring to Fig. In steps 4A-4E, the exposed section of channel region C of the semiconductor stack 205 is subjected to an etching process using the EUV mask 220 as the etching mask. For example, a section of the semiconductor stack 205 exposed through the opening 222 of the EUV mask 220 is removed to form a trench 225 in channel region C of the multigate device 200, thereby creating semiconductor layer sections 210A separated by the trench 225 from semiconductor layer sections 210B, and semiconductor layer sections 215A separated by the trench 225 from semiconductor layer sections 215B. The depth of the trench 225 is selected based on a desired configuration of channel layers of the multigate device 200. In the illustrated embodiment, the semiconductor layer stack 205 exposed by the EUV mask 220 is completely removed by the etching process, so that the trench 225 exposes the substrate 202.In some embodiments, as further described below, the semiconductor layer stack 205 exposed by the EUV mask 220 is partially removed by the etching process, such that the trench 225 extends to one of the semiconductor layers 210 or one of the semiconductor layers 215. A width w1 (for example, in the y-direction) of the trench 225 is selected based on a desired channel configuration and / or a desired performance (e.g., driver current) of the multigate device 200. For example, the width w1 is greater than a spacing between channel layers, such as sheet-channel layers, to be formed for the multigate device 200. In such an example, the width w1 is greater than the thickness t1, which corresponds to the spacing between the channel layers. In some embodiments, the width w1 is approximately 3 nm to approximately 15 nm. In some embodiments, the width w1 is essentially equal to or less than the thickness t1.The etching process may comprise a dry etching process, a wet etching process, another suitable etching process, or combinations thereof. In some embodiments, the etching process is a multi-stage etching process. For example, the etching process may alternate between etchants to remove the semiconductor layers 210 and the semiconductor layers 215 individually and alternately. In some embodiments, the etching process uses a single etchant capable of removing both the semiconductor layers 210 and the semiconductor layers 215 without requiring any adjustment of other etching parameters. In some embodiments, the parameters of the etching process are configured such that the semiconductor layer stack 205 is selectively etched with minimal (or no) etching of the EUV mask 220. In some embodiments, the etching process may partially etch the EUV mask 220.In some embodiments, the EUV mask 220 is formed over a hard mask layer arranged above the semiconductor layer stack 205. In such embodiments, a first etching process removes sections of the hard mask layer to form a structured hard mask layer, and a second etching process removes sections of the semiconductor layer stack 205 using the structured hard mask layer as the etch mask.

[0017] Referring to Fig. 5A-5E and Fig. 6A-6E the EUV mask 220 is removed from the multigate component 200 by any suitable process (e.g. a photoresist removal process and / or an etching process) ( Fig. 5A-5E), and a semiconductor layer 230, which fills the trench 225, is formed over the multigate device 200 ( Fig. 6A-6E). In the illustrated embodiment, a deposition process forms a semiconductor material that overfills the trench 225 and covers an upper surface of the semiconductor layer stack 205, such as the upper surfaces of the topmost semiconductor layer sections 215A, 215B. In some embodiments, the semiconductor material has a crystalline structure (i.e., a material with an ordered atomic structure), such as crystalline silicon (e.g., c-Si), crystalline germanium, and / or crystalline silicon germanium (e.g., c-SiGe), and / or another crystalline semiconductor material. In some embodiments, the semiconductor material has a non-crystalline structure (i.e., a material with a disordered atomic structure), such as amorphous silicon (e.g., a-Si), amorphous germanium (e.g., a-Ge), amorphous silicon germanium (e.g., a-SiGe), and / or another amorphous semiconductor material. In some embodiments, the semiconductor material contains n dopants (e.g.Arsenic, phosphorus and / or antimony), p-dopers (boron, gallium and / or indium) or combinations thereof. In the illustrated embodiment, the semiconductor material is crystalline silicon or amorphous silicon, and the semiconductor layer 230 can be referred to as a silicon layer or an amorphous silicon layer, respectively. In some embodiments, the semiconductor layer 230 contains silicon and / or amorphous silicon doped with boron, phosphorus, carbon, fluorine, another suitable dopant, or combinations thereof. In some embodiments, the dopant concentration in the semiconductor layer 230 is less than or equal to approximately 2 x 10⁻⁶. 18 cm -3In some embodiments, the semiconductor layer 230 is doped with carbon. In some embodiments, the concentration of carbon in the semiconductor layer 230 is less than or equal to approximately 2%. The introduction of a dopant, such as carbon, into the semiconductor layer 230 can modify the etch rate of the semiconductor layer 230 relative to the etch rate of the semiconductor layer sections 210A, 215A and / or the semiconductor layer sections 210B, 215B such that, during subsequent processing, etch selectivity between the semiconductor layer 230 and the semiconductor layer sections 210A, 215A and / or the semiconductor layer sections 210B, 215B can be achieved, as described below with reference to Fig. The deposition process is described in Figures 16A-16E. It is a CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma condensing and deposition (HDPCVD), molecular organic carbon deposition (MOCVD), remote plasma condensing and deposition (RPCVD), plasma-assisted CVD (PECVD), low-pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), other suitable methods, or combinations thereof. In some embodiments, the semiconductor layer 230 is epitaxially grown from the semiconductor layer sections 210A, 210B, and / or the semiconductor layer sections 215A, 215B. An epitaxial process may employ CVD deposition techniques (for example, VPE, UHV-CVD, LPCVD, and / or PECVD), molecular beam epitaxy, other suitable selective epitaxial growth processes, or combinations thereof. In such embodiments, the semiconductor layer 230 can be referred to as an epitaxial semiconductor layer, for example as an epitaxial silicon layer.The epitaxy process can use gaseous and / or liquid precursors that interact with the composition of the semiconductor layer sections 210A, 210B and / or the semiconductor layer sections 215A, 215B. In some embodiments, the semiconductor layer 230 is formed by a deposition process that deposits a semiconductor material over the entire surface of the multigate device 200.

[0018] The quality of the semiconductor layer 230 and of interfaces between the semiconductor layer 230 and the semiconductor layer stack 205, for example, an interface I1 formed between the semiconductor layer 230 and the semiconductor layer sections 210A, 215A, and an interface I2 formed between the semiconductor layer 230 and the semiconductor layer sections 210B, 215B, can influence the performance of a transistor of the multigate device 200. In some embodiments, semiconductor material formed by the deposition process can fill or close (pinch off) an upper part of the trench 225 before the trench 225 is completely filled, resulting in the semiconductor layer 230 having one or more cavities (gaps) after deposition, such as a cavity (e.g., an air gap) that runs vertically through the center of a section of the semiconductor layer 230 that fills the trench 225.Cavity formation is particularly likely if the trench 225 has a high aspect ratio, such as when the trench 225 is narrow and its depth d is significantly greater than its width w1 (e.g., when the ratio of depth d to width w1 is greater than approximately 1.05). Cavities may also form at interface I1 and / or interface I2 if the semiconductor layer 230 does not adhere well to semiconductor layer sections 210A, 215A or 210B, 215B, respectively. Since the semiconductor layer 230 later forms a section of channel layers of a transistor, cavities within it can oppose and / or impede the flow of current (e.g., of charge carriers such as electrons or holes) through the channel layers of the transistor, thereby degrading the operation and / or performance of the transistor.In some embodiments, unsaturated silicon bonds at interface I1 and interface I2, which can trap and accumulate charge, can generate leakage current paths and / or undesirably alter the transistor's threshold voltage. To find a compromise between production requirements and electronic performance requirements, it may be desirable in some embodiments to form the semiconductor layer 230 by depositing an amorphous semiconductor material (e.g., a-Si), which is easier and less expensive to deposit than crystalline semiconductor material (amorphous semiconductor material can be formed, for example, by a cost-effective low-temperature process such as PECVD), and then to convert the amorphous semiconductor material into crystalline semiconductor material, in which current can flow more readily (the charge carrier mobility of c-Si, for example, is greater than that of a-Si).

[0019] To solve such problems, a tempering process is carried out on the semiconductor layer 230 after deposition in order to (1) remelt the semiconductor material of the semiconductor layer 230 to reduce (and in some embodiments eliminate) voids that have formed during deposition in the semiconductor layer 230 and / or at the interfaces I1, I2; (2) repair unsaturated bonds, e.g. unsaturated silicon bonds, in the semiconductor layer 230 and / or at the interfaces I1, I2; and / or (3) convert (crystallize) amorphous semiconductor material (i.e., semiconductor material with a non-crystalline structure) into crystalline semiconductor material (i.e., semiconductor material with a crystalline structure).As long as the temperature and other parameters of the tempering process are adjusted (controlled) such that the remelting, repair, and / or conversion described herein is sufficient to improve the quality of the semiconductor layer 230 and / or the quality of the interfaces I1, I2, any suitable tempering process can be carried out. In some embodiments, parameters of the tempering process are selected based on various properties of the semiconductor layer 230 and / or the semiconductor layer stack 205, for example, the remelting temperature and / or the crystallization temperature. In some embodiments, the temperature of the tempering process is approximately 550 °C to approximately 950 °C. If the temperature of the tempering process is below 550 °C, little or no remelting of semiconductor material may occur (e.g.,silicon) to improve the crystallinity of semiconductor layer 230 and / or to reduce unsaturated silicon bonds. If the temperature of the tempering process is higher than 950 °C, damage to semiconductor layer sections 210A, 210B, semiconductor layer sections 215A, 215B, and / or semiconductor layer 230 may occur. In some embodiments, the duration of the tempering process is approximately 1 minute to approximately 30 minutes. In some embodiments, the tempering process is carried out at a pressure of approximately 1 atmosphere (atm) to approximately 10 atm. In some embodiments, the tempering process is carried out in a gas environment containing or comprising hydrogen, nitrogen, helium, argon, neon, another suitable tempering gas environment, or combinations thereof. In some embodiments, the gas environment contains hydrogen, with a hydrogen concentration in the gas environment of approximately 0.5% to approximately 4%.In some embodiments, the annealing process causes the semiconductor layer 230 to flow in a manner that reduces or eliminates voids in the semiconductor layer 230 at interface I1 and / or interface I2. In some embodiments, the annealing process reduces unsaturated silicon bonds at interface I1 and / or interface I2, thereby decreasing the density of unsaturated silicon bonds (and thus the density of trapped interfacial charges) at interface I1 and / or interface I2, which can improve the mobility of charge carriers through channel layers and / or stabilize a threshold voltage of the multigate device 200.In some embodiments, the tempering process reduces lattice defects and / or dislocations at interface I1, at interface I2, and / or within semiconductor layer 230, which can improve the mobility of charge carriers through channel layers of the multigate device 200. In some embodiments, the tempering process recrystallizes an amorphous semiconductor material of semiconductor layer 230 (in other words, it rearranges its atomic structure) so that semiconductor layer 230 contains crystalline semiconductor material. For example, if semiconductor layer 230 contains amorphous silicon, the tempering process recrystallizes the amorphous silicon (i.e., it rearranges its atomic structure) so that semiconductor layer 230 contains crystalline silicon (i.e., silicon with an ordered atomic structure).

[0020] Referring to Fig. In embodiments 7A-7E, a chemical-mechanical planarization (CMP) process and / or another planarization process is performed on the semiconductor layer 230. In the illustrated embodiment, the CMP process removes sections of the semiconductor layer 230 that are located above the semiconductor layer stack 205. A portion of the semiconductor layer 230 remaining after the CMP process forms a semiconductor strand 230' with a width w1 and a height that is substantially equal to the height of the semiconductor layer stack 205. The semiconductor strand 230' is formed in an active region of the multigate device 200, for example, in a region of the multigate device 200 in which a channel region and source / drain regions for a transistor of the multigate device 200 are formed. The semiconductor strand 230' is arranged between the semiconductor layer sections 210A, 215A and the semiconductor layer sections 210B, 215B.The semiconductor strand 230' has an interface I1 with the semiconductor layer sections 210A, 215A and an interface I2 with the semiconductor layer sections 210B, 215B. Accordingly, the semiconductor layer stack 205 has first semiconductor layers formed from corresponding semiconductor layer sections 210A, corresponding semiconductor layer sections 210B and corresponding intermediate sections of the semiconductor strand 230', and second semiconductor layers formed from corresponding semiconductor layer sections 215A, corresponding semiconductor layer sections 215B and corresponding intermediate sections of the semiconductor strand 230'. In some embodiments, the uppermost semiconductor layer sections 215A, 215B serve as a CMP stop layer such that the CMP process is carried out until it reaches and exposes the uppermost semiconductor layer sections 215A, 215B.In some embodiments, the composition of semiconductor layer 230 differs from the composition of semiconductor layer sections 215A, 215B in such a way that the CMP process stops when it reaches semiconductor layer sections 215A, 215B. In some embodiments, the duration of the CMP process is selected to ensure that the CMP process stops when it reaches semiconductor layer sections 215A, 215B. The CMP process can planarize an upper surface of semiconductor strand 230' and the upper surfaces of the topmost semiconductor layer sections 215A, 215B such that these surfaces are substantially planar after the CMP process.

[0021] Referring to Fig. In steps 8A-8E, the semiconductor layer stack 205 is structured to form a fin 235 (also referred to as fin structure, fin element, etc.), and one or more isolation features 240 are formed above and / or within the substrate 202 in isolation regions 236 to separate and isolate active device regions, such as an active region 238, from other active regions of the multigate device 200. The fin 235 comprises a substrate section (i.e., a section of the substrate 202) and a semiconductor layer stack section (i.e., a remaining section of the semiconductor layer stack 205, comprising the semiconductor layer sections 210A, 210B, the semiconductor layer sections 215A, 215B, and the semiconductor strand 230'). The fin 235 extends in an x-direction, having a length defined in the x-direction, a width defined in a y-direction, and a height defined in a z-direction.In some embodiments, a lithography and / or etching process is performed to structure the semiconductor layer stack 205 to form the fin 235. The lithography process may include forming a photoresist layer over the semiconductor layer stack 205 (for example, by rotational coating), performing a bake-out process before exposure, performing an exposure process using a mask, performing a bake-out process after exposure, and performing a development process.During the exposure process, the photoresist layer is exposed to radiant energy (for example, ultraviolet (UV), deep UV (DUV), or EUV light). Depending on the mask structure and / or type (for example, binary, phase-shift, or EUV), the mask blocks, transmits, and / or reflects the radiation to the photoresist layer in such a way that an image corresponding to the mask structure is projected onto the photoresist layer. Because the photoresist layer is sensitive to radiant energy, exposed sections of the photoresist layer undergo chemical changes. Depending on the properties of the photoresist layer and the properties of the developing solution used in the development process, exposed (or unexposed) sections of the photoresist layer dissolve during development.After development, the structured photoresist layer comprises a photoresist structure corresponding to the mask, wherein the photoresist structure covers an active component area of ​​the multigate component 200 and exposes an isolation area of ​​the multigate component 200. For example, the photoresist structure exposes sections of the semiconductor layer segments 210A, 215A and sections of the semiconductor layer segments 210B, 215B, which are located in the isolation areas 236 of the multigate component 200, and covers the semiconductor strand 230', sections of the semiconductor layer segments 210A, 215A and unexposed sections of the semiconductor layer segments 210B, 215B, which are located in an active area 238 of the multigate component 200.The etching process removes the exposed sections of semiconductor layer segments 210A, 215A and the exposed sections of semiconductor layer segments 210B, 215B in the insulation regions 236 using the structured photoresist layer as an etching mask. In some embodiments, the structured photoresist layer is formed over a hard mask layer arranged over the semiconductor layer stack 205. A first etching process removes sections of the hard mask layer to form a structured hard mask layer, and a second etching process removes sections of the semiconductor layer stack 205 using the structured hard mask layer as an etching mask. The etching process may include a dry etching process, a wet etching process, another suitable etching process, or combinations thereof.After the etching process, the structured photoresist layer (and in some embodiments a hard mask layer) is removed, for example by a photoresist removal process or another suitable process. In some embodiments, the fin 235 is formed by a multiple patterning process, for example a double patterning lithography (DPL) process (for example a lithography-etch-lithography-etch (LELE) process, a self-aligned double patterning (SADP) process, a spacer-is-dielectric (SID) SADP process, another double patterning process, or combinations thereof), a triple patterning process (for example a lithography-etch-lithography-etch-lithography-etch (LELELE) process, a self-aligned triple patterning (SID) process, or a combination thereof), a triple patterning process (for example a lithography-etch-lithography-etch-lithography-etch (LELELE) process, a self-aligned triple patterning (SID) process, or a combination thereof).SATP process, another triple patterning process, or combinations thereof), another multi-patterning process (for example, a self-aligned quadruple patterning (SAQP) process), or combinations thereof. In some embodiments, directed self-assembly (DSA) techniques are used to pattern the semiconductor layer stack. Furthermore, in some embodiments, maskless lithography, electron beam writing, and / or ion beam writing can be used to pattern the photoresist layer during the exposure process.

[0022] After the fin 235 has formed, insulation features 240 are formed, for example by depositing an insulator material (e.g., an oxide material) over the substrate 202 after the fin 235 has formed, such that the thickness of the insulator material is greater than the height of the fin 235 (i.e., the insulator material fills gaps (trenches) between the fin 235 and other fins); planarizing (for example, by a CMP process) the insulator material, thereby reducing the thickness of the insulator material, for example, until it has essentially the same height as the fin 235; and back-etching (deepening) the insulator material. The deposition process is a flowable CVD process (FCVD process), a high aspect ratio deposition process (HARP - High Aspect Ratio Deposition), a high density plasma CVD process (HDPCVD), another suitable deposition process, or a combination thereof.In some embodiments, the uppermost semiconductor layer sections 215A, 215B and / or the semiconductor strand 230' serve as a planarization stop layer (e.g., CMP stop layer) such that the planarization process is carried out until it reaches and exposes the uppermost semiconductor layer sections 215A, 215B and / or the semiconductor strand 230'. In some embodiments, the insulator material is recessed by back-etching until a desired height (target height) of an upper active fin region of the fin 235 is reached. In the illustrated embodiment, back-etching continues until the semiconductor layer stack section of the fin 235 (e.g., the semiconductor layer sections 210A, 210B, the semiconductor layer sections 215A, 215B and the semiconductor strand 230') is completely exposed and the substrate section of the fin 235 (e.g.,The substrate 202 / the doped well 204) is reached, such that an upper surface of the substrate section of the fin 235 is substantially flush with the upper surfaces of the insulating features 240 relative to an upper surface of the substrate 202. In some embodiments, the back-etching is continued until the substrate section of the fin 235 is also partially exposed, so that the upper surface of the substrate section of the fin 235 is higher than the upper surfaces of the insulating features 240 relative to the upper surface of the substrate 202. In some embodiments, the semiconductor layer stack section of the fin 235 is not completely, but only partially, exposed by the back-etching, so that the upper surface of the substrate section of the fin 235 is lower than the upper surfaces of the insulating features 240 relative to the upper surface of the substrate 202.

[0023] The isolation features 240 surround a lower section of the fin 235, thereby providing the upper active fin region of the fin 235 (generally defined as a section of the fin 235 extending from and over the upper surfaces of the isolation features 240) and a lower active fin region of the fin 235 (generally defined as a section of the fin 235 surrounded by the isolation features 240 and extending from the upper surface of the substrate 202 to the upper surface of the isolation features 240). The isolation features 240 electrically separate and isolate the fin 235 from other fins, other active regions and / or inactive regions of the multigate device 200 and / or other features of the multigate device 200.The insulating features 240 contain silicon oxide, silicon nitride, silicon oxynitride, another suitable insulating material (containing, for example, silicon, oxygen, nitrogen, carbon, or other suitable insulating components), or combinations thereof. The dimensions and / or properties of the insulating features 240 can be configured during processing to provide shallow trench insulation structures (STI structures), deep trench insulation structures (DTI structures), local silicon oxidation structures (LOCOS structures), other suitable insulating structures, or combinations thereof. In the illustrated embodiment, the insulating features 240 are STIs. In some embodiments, the insulating features 240 have a multilayer structure, such as a solid silicon nitride layer over a lining layer of oxide.In some embodiments, the insulating features 240 comprise a solid dielectric layer over a doped lining layer (which, for example, contains borosilicate glass (BSG) and / or phosphosilicate glass (PSG)). In some embodiments, the insulating features 240 comprise a solid dielectric layer (e.g., a solid silicon oxide layer) arranged over one or more dielectric lining layers (e.g., a silicon nitride lining, a silicon oxide lining, a silicon lining, and / or another suitable lining), wherein the solid dielectric layer and the dielectric lining layer contain materials that depend on the design requirements.

[0024] Referring to Fig. In 9A-9E, a gate structure 250 is formed over the fin 235 and the isolation features 240. The gate structure 250 extends longitudinally in a direction different from the longitudinal direction of the fin 235 (e.g., orthogonal to it). For example, the gate structure 250 extends in the y-direction, having a length defined in the y-direction, a width defined in the x-direction, and a height defined in the z-direction. The gate structure 250 crosses the fin 235 such that the channel region C is located between source / drain regions S / D of the multigate device 200, which can correspond to the source / drain regions of a transistor of the multigate device 200. In the YZ plane, the gate structure 250 encloses an upper surface and sidewall surfaces of the fin 235.In the XZ plane, the gate structure 250 is arranged above an upper surface of the fin 235 in the channel region C and between the source / drain regions S / D. Fig. 9A-9E comprises the gate structure 250, a dummy gate stack 252, and gate spacers 256, which are arranged adjacent to the dummy gate stack 252 (i.e., along its side walls). One width (here in the x-direction) of the dummy gate stack 252 can correspond to one gate length (L). g ) of a transistor, where the gate length corresponds to a distance or distance traveled by an electric current (e.g. charge carriers such as electrons or holes) between the source / drain regions S / D when the transistor is switched on.

[0025] The dummy gate stack 252 comprises a dummy gate electrode and, in some embodiments, a dummy gate dielectric. The dummy gate electrode comprises a suitable dummy gate material, for example, a polysilicon layer. In embodiments in which the dummy gate stack 252 comprises a dummy gate dielectric arranged between the dummy gate electrode and the fin 235, the dummy gate dielectric comprises a dielectric material such as silicon oxide. The dummy gate stack 252 may comprise numerous other layers, such as cover layers, interface layers, diffusion layers, barrier layers, hard mask layers, or combinations thereof. For example, the dummy gate stack 252 may further comprise a hard mask layer arranged over the dummy gate electrode. The dummy gate stack 252 is formed by deposition processes, lithography processes, etching processes, other suitable processes or combinations thereof.For example, a deposition process is performed to form a dummy gate dielectric layer (e.g., an oxide layer) over the fin 235 and the insulating features 240, and a deposition process is performed to form a dummy gate electrode layer (e.g., a polysilicon layer) over the dummy gate dielectric layer. In some embodiments, a hard mask layer is deposited over the dummy gate electrode layer. The deposition process includes CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable methods, or combinations thereof.Then a lithography and etching process is carried out to structure the dummy gate dielectric layer and the dummy gate electrode layer (and in some embodiments the hard mask layer) to form the dummy gate stack 252 such that the dummy gate stack 252 (comprising the dummy gate electrode layer, the dummy gate dielectric layer, the hard mask layer and / or other suitable layers) as shown in . Fig. The configuration is shown in 9A-9D. Lithographic texturing processes include photoresist coating (e.g., rotary coating), gentle bake-out, mask alignment, exposure, post-exposure bake-out, photoresist development, rinsing, drying (e.g., intense bake-out), other suitable lithographic processes, or combinations thereof. Etching processes include dry etching, wet etching, other etching methods, or combinations thereof.

[0026] The gate spacers 256 are formed by any suitable process and contain a dielectric material. The dielectric material can be silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbide, silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN)). For example, a silicon nitride layer can be deposited over the dummy gate stack 252 and subsequently etched (e.g., anisotropically etched) to form the gate spacers 256. In some embodiments, the gate spacers 256 comprise a multilayer structure, such as a first dielectric layer containing silicon nitride and a second dielectric layer containing silicon oxide.In some embodiments, more than one set of spacers, for example, closure spacers, offset spacers, sacrificial spacers, dummy spacers, and / or main spacers, is formed adjacent to the dummy gate stack 252. In such embodiments, the different sets of spacers may contain materials exhibiting different etch rates. For example, a first dielectric layer containing silicon and oxygen (e.g., silicon oxide) may be deposited and etched to form a first set of spacers adjacent to the dummy gate stack 252, and a second dielectric layer containing silicon and nitrogen (e.g., silicon nitride) may be deposited and etched to form a second set of spacers adjacent to the first set of spacers.

[0027] Referring to Fig. In 10A-10E, exposed sections of the fin 235 (i.e., the source / drain regions S / D not covered by the gate structure 250) are at least partially removed to form source / drain depressions (trenches) 260. In the illustrated embodiment, an etching process removes the semiconductor strand 230', the semiconductor layer sections 215A, 215B, and the semiconductor layer sections 210A, 210B in the source / drain regions S / D, thereby exposing the substrate section of the fin 235 in the source / drain regions S / D (e.g., the doped well 204). The source / drain depressions 260 thus have side walls formed by remaining sections of the fin 235 in the channel area C (for example, the semiconductor strand 230', the semiconductor layer sections 215A, 215B and the semiconductor layer sections 210A, 210B under the gate structure 250), and bottoms formed by the substrate 202 in the source / drain areas S / D.In some embodiments, the etching process partially, but not completely, removes the semiconductor strand 230', the semiconductor layer sections 215A, 215B, and / or the semiconductor layer sections 210A, 210B, such that the source / drain depressions 260 have bottoms formed by the semiconductor strand 230', the semiconductor layer sections 215A, 215B, and / or the semiconductor layer sections 210A, 210B in the source / drain regions S / D. In some embodiments, such as the one shown, the etching process partially, but not completely, removes the substrate portion of the fin 235, such that the source / drain depressions 260 extend below a top surface of the substrate 202. The etching process may comprise a dry etching process, a wet etching process, another suitable etching process, or combinations thereof. In some embodiments, the etching process is a multi-stage etching process.For example, the etching process can alternate between etchants to remove the semiconductor strand 230', the semiconductor layer sections 215A, 215B, and / or the semiconductor layer sections 210A, 210B individually and alternately. In some embodiments, parameters of the etching process are configured such that the semiconductor strand 230', the semiconductor layer sections 215A, 215B, and / or the semiconductor layer sections 210A, 210B are selectively etched with minimal (or no) etching of the gate structure 250 (i.e., the dummy gate stack 252 and the gate spacers 256) and / or the isolation features 240. In some embodiments, a lithography process, such as one described herein, is carried out to form a structured mask layer covering the gate structure 250 and / or the isolation features 240, and the etching process uses the structured mask layer as the etching mask.

[0028] Referring to Fig. Internal spacers 265 are formed in the channel regions C along the sidewalls of the semiconductor layer sections 210A and 210B by any suitable process. For example, a first etching process is carried out which selectively etches the semiconductor layer sections 210A and 210B, exposed by the source / drain depressions 260, with minimal (or no) etching of the semiconductor strand 230' and the semiconductor layer sections 215A and 215B, such that gaps are formed between the semiconductor layer sections 215A, between the semiconductor layer sections 215B, between the semiconductor layer sections 215A and the substrate 202, and between the semiconductor layer sections 215B and the substrate 202 under the gate spacers 247. Sections (edges) of the semiconductor layer sections 215A, 215B are thus suspended in the channel area C under the gate spacers 256.In some embodiments, the gaps extend partially below the dummy gate stack 252. The first etching process is configured to etch the semiconductor layer sections 210A, 210B laterally (e.g., in the x-direction) to reduce their length in the x-direction. In some embodiments, the first etching process is configured to modify the length of the semiconductor layer sections 210A, 210B in the x-direction such that the length is substantially equal to a desired gate length. The first etching process is a dry etching process, a wet etching process, another suitable etching process, or a combination thereof. Then a deposition process, for example CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable processes or combinations thereof, forms a spacer layer over the gate structure 250 and over features that form the source / drain depressions 260 (e.g.the semiconductor strand 230', the semiconductor layer sections 215A, 215B, the semiconductor layer sections 210A, 210B and the substrate 202). The spacer layer partially fills (and in some embodiments completely fills) the source / drain depressions 260. The deposition process can be configured to ensure that the spacer layer fills the gap between the semiconductor layer sections 215A, between the semiconductor layer sections 215B, between the semiconductor layer sections 215A and the substrate 202, and between the semiconductor layer sections 215B and the substrate 202 under the gate spacers 256. Then a second etching process is performed, which selectively etches the spacer layer to create internal spacers 265 as shown in [reference]. Fig. Figures 11A-11E are shown to form the spacer layer with minimal (or no) etching of the semiconductor strand 230', the semiconductor layer sections 215A, 215B, and the gate structure 250. In some embodiments, the spacer layer is removed from the side walls of the gate spacers 256, the side walls of the semiconductor strand 230', the side walls of the semiconductor layer sections 215A, 215B, the dummy gate stack 256, and the substrate 202. The spacer layer (and thus the inner spacers 265) contains a material different from that of the semiconductor strand 230', the semiconductor layer sections 215A, 215B, and the gate spacers 256 to achieve the desired etch selectivity during the second etching process.In some embodiments, the spacer layer contains a dielectric material comprising silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or silicon oxycarbonitride). In some embodiments, the spacer layer contains a dielectric material with a low k-value (dielectric constant), such as one of those described herein. In some embodiments, dopants are introduced into the dielectric material such that the spacer layer contains a doped dielectric material.

[0029] Referring to Fig. Epitaxial source / drain features are formed in the source / drain depressions 260. For example, a semiconductor material is epitaxially grown from sections of the substrate 202, the semiconductor strand 230', and the semiconductor layer sections 215A, 215B, which are exposed through the source / drain depressions 260, thereby forming epitaxial source / drain features 270 in the source / drain regions S / D. An epitaxial growth process can employ CVD deposition techniques (e.g., VPE and / or UHV-CVD), molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. The epitaxial process can utilize gaseous and / or liquid precursors that interact with the composition of the substrate 202, the semiconductor strand 230', and / or the semiconductor layer sections 215A, 215B. The epitaxial source / drain features 270 are doped with n-type and / or p-type dopants.In embodiments where the multigate device 200 is configured as an n-GAA transistor, the epitaxial source / drain features 270 may contain silicon. In such embodiments, the epitaxial source / drain features 270 may be doped with carbon, phosphorus, arsenic, another n-type dopant, or combinations thereof. In embodiments where the multigate device 200 is configured as a p-GAA transistor, the epitaxial source / drain features 270 may contain silicon germanium or germanium. In such embodiments, the epitaxial source / drain features 270 may be doped with boron, another p-type dopant, or combinations thereof. In some embodiments, the epitaxial source / drain features 270 comprise more than one epitaxial semiconductor layer, wherein the epitaxial semiconductor layers contain or have the same or different materials and / or dopant concentrations.The epitaxial source / drain features 270 can, for example, comprise a first epitaxial layer arranged over a second epitaxial layer, wherein the dopant concentration of a dopant in the first epitaxial layer is greater than the dopant concentration of the dopant in the second epitaxial layer. In some embodiments, the epitaxial source / drain features 270 contain materials and / or dopants that achieve a desired mechanical tensile and / or compressive stress in the channel region C. In some embodiments, the epitaxial source / drain features 270 are doped during deposition by adding foreign substances to a starting material of the epitaxial process (i.e., in situ). In some embodiments, the epitaxial source / drain features 270 are doped after deposition by an ion implantation process. In some embodiments, tempering processes (e.g.,rapid thermal annealing (RTA - Rapid Thermal Anneal) and / or laser annealing) was performed to activate dopants in the epitaxial source / drain features 270, heavily doped source / drain regions and / or lightly doped source / drain regions (LDD regions) of the multigate device 200.

[0030] Referring to Fig. In 13A-13E, an interlevel dielectric (ILD) layer 280 is formed over the insulating features 240, the epitaxial source / drain features 270, and the gate spacers 256, for example, by a deposition process (such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable processes, or combinations thereof). In some embodiments, the ILD layer 280 is formed by a flowable CVD process (FCVD process), which, for example, includes depositing a flowable material (such as a liquid compound) over the multigate device 200 and converting the flowable material into a solid material by a suitable technique such as thermal annealing and / or UV radiation treatment.The ILD layer 280 contains a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, TEOS-formed oxide, PSG, BPSG, a low-k dielectric material, another suitable dielectric material, or combinations thereof. Examples of low-k dielectric materials include FSG, carbon-doped silicon oxide, Black Diamond® (Applied Materials, Santa Clara, California), xerogels, aerogels, amorphous fluorinated carbon, parylene, BCB, SiLK (Dow Chemical, Midland, Michigan), polyimide, other low-k dielectric materials, or combinations thereof. In the described embodiment, the ILD layer 280 is a dielectric layer containing a low-k dielectric material (generally referred to as a low-k dielectric layer).The ILD layer 280 can comprise a multilayer structure containing several dielectric materials. In some embodiments, a contact etch stop layer (CESL) is arranged between the ILD layer 280 and the insulating features 240, the epitaxial source / drain features 280, and the gate spacers 256. The CESL contains a different material than the ILD layer 280, such as a dielectric material different from that of the ILD layer 280. If the ILD layer 280 contains a dielectric material with a low k-value, the CESL contains silicon and nitrogen, for example, silicon nitride or silicon oxynitride. After deposition of the ILD layer 280 and / or the CESL, a CMP process and / or another planarization process can be carried out until an upper section (or upper surface) of the dummy gate stack 252 is reached (exposed).In some embodiments, the planarization process removes hard mask layers of the dummy gate stack 252 to expose an underlying dummy gate electrode of the dummy gate stack 252, e.g. a polysilicon gate electrode.

[0031] Referring to Fig. In steps 14A-14E, the dummy gate stack 252 is removed from the gate structure 250, forming a gate opening (gate trench) 285 that exposes the fin 235 in the channel region C. For example, the gate trench 275 exposes the semiconductor strand 230, the semiconductor layer sections 215A, the semiconductor layer sections 215B, the semiconductor layer sections 210A, and the semiconductor layer sections 210B. In the illustrated embodiment, an etching process completely removes the dummy gate stack 252. The etching process is a dry etching process, a wet etching process, another suitable etching process, or a combination thereof. In some embodiments, the etching process is a multi-stage etching process. For example, the etching process can alternate between etchants to remove different layers of the dummy gate stack 252, such as the dummy gate electrode layers, the dummy gate dielectric layers and / or the hard mask layers.In some embodiments, the etching process is configured to selectively etch the dummy gate stack 252 with minimal (or no) etching of other features of the multigate device 200, such as the ILD layer 280, the gate spacers 256, the isolation features 240, the semiconductor strand 230', the semiconductor layer sections 215A, the semiconductor layer sections 215B, the semiconductor layer sections 210A, and the semiconductor layer sections 210B. In some embodiments, a lithography process, such as one described herein, is performed to form a structured mask layer covering the ILD layer 280 and / or the gate spacers 256, with the etching process using the structured mask layer as the etch mask.

[0032] Referring to Fig. 15A-15E and Fig. 18A A channel release process is carried out, for example by selectively removing the semiconductor layer sections 210A and the semiconductor layer sections 210B of the fin 235 (which are exposed through the gate opening 285) from the channel region C, thereby forming suspended semiconductor layer sections 215A', suspended semiconductor layer sections 215B', semiconductor strand sections 230'-1 and semiconductor strand sections 230'-2. The channel release process provides sheet-like channel layers, each formed from a corresponding suspended semiconductor layer section 215A', a corresponding suspended semiconductor layer section 215B' and a corresponding semiconductor strand section 230'-1, and channel layer interconnection sections, each formed from a corresponding semiconductor strand section 230'-2. The sheet-like channel layers extend substantially parallel to the substrate 202, e.g.parallel to an upper surface of the substrate 202, and the channel layer connection sections extend substantially perpendicular to the substrate 202. In . Fig. 15A-15E provide the sheet-like channel layers and the channel layer connection sections exposed through the gate opening 285 to the multigate device 200 with at least one T-shaped sheet-like channel layer (also referred to as a T-shaped channel). For example, three T-shaped channels are stacked vertically in the z-direction, such as a T-shaped channel 290A positioned above and connected to the substrate 202, a T-shaped channel 290B positioned above and connected to the T-shaped channel 290A, and a T-shaped channel 290C positioned above and connected to the T-shaped channel 290B, which are described in more detail below. The T-shaped channels 290A-290C provide three channels through which current can flow between the epitaxial source / drain features 270 during operation of the multigate device 200.In some embodiments, an etching process selectively etches the semiconductor layer sections 210A, 210B with minimal (or no) etching of the semiconductor layer sections 215A, the semiconductor layer sections 215B, the semiconductor strand 230', and the substrate 202. For the etching process, an etchant is selected, for example, that etches the material of the semiconductor layer sections 210A, 210B (e.g., silicon germanium) at a higher rate than the material of the semiconductor layer sections 215A, the semiconductor layer sections 215B, and the semiconductor strand 230' (e.g., silicon) (i.e., the etchant exhibits high etch selectivity with respect to the material of the semiconductor layer sections 210A, 210B). The etching process is a dry etching process, a wet etching process, another suitable etching process, or a combination thereof. In some embodiments, a dry etching process (such as a reactive ion etching (RIE) process) utilizes a fluorine-containing gas (e.g.SF6) to selectively etch the semiconductor layer sections 210A, 210B. In some embodiments, the ratio of the fluorine-containing gas to an oxygen-containing gas (e.g., O2), an etching temperature, and / or a power level can be adjusted to selectively etch silicon germanium. In some embodiments, a wet etching process uses an etching solution containing ammonium hydroxide (NH4OH) and water to selectively etch the semiconductor layer sections 210A, 210B. In some embodiments, a chemical vapor etching process uses hydrochloric acid (HCl) to selectively etch the semiconductor layer sections 210A, 210B. In some embodiments, the etching process is further configured to selectively etch the semiconductor layer sections 210A, 210B with minimal (or no) etching of the isolation features 240, the gate spacers 256, the inner spacers 265 and / or the ILD layer 280.

[0033] Each of the T-shaped channels 290A-290C has a first segment extending in a first direction and a second segment extending in a second direction that is different from the first direction (and in some embodiments is essentially orthogonal to it). Fig. In 15A-15E, the first segment extends substantially in the y-direction and can subsequently be referred to as the horizontal segment, while the second segment extends substantially in the z-direction and can subsequently be referred to as the vertical segment. The horizontal segment is formed by a corresponding suspended semiconductor layer section 215A', a corresponding suspended semiconductor layer section 215B', and a corresponding semiconductor strand section 230'-1, extending from the corresponding suspended semiconductor layer section 215A' to the corresponding suspended semiconductor layer section 215B'. The horizontal segment has a width w2 in the YZ plane, a width w3 in the XZ plane, and a thickness h1 in both the YZ and XZ planes.The width w2 is the sum of the width s1 of the corresponding suspended semiconductor layer section 215A', the width s2 of the corresponding suspended semiconductor layer section 215B', and the width s3 of the corresponding semiconductor strand section 230'-1. In the illustrated embodiment, the width s1 is substantially equal to the width s2, and the width s3 is substantially equal to the width w1. In some embodiments, the width s1 is approximately 1 nm to approximately 20 nm, the width s2 is approximately 1 nm to approximately 20 nm, and the width s3 is approximately 3 nm to approximately 20 nm. Depending on the desired channel configuration, the width s3 is greater than, less than, or substantially equal to the width s1 and / or the width s2. In some embodiments, the width s1 is different from the width s2. Depending on the desired channel configuration, the width w3 can be substantially equal to, greater than, or less than the width w2.In some embodiments, the thickness h1 is approximately 2 nm to approximately 10 nm. In some embodiments, such as the one shown, the thickness h1 is essentially equal to the thickness t2 of the semiconductor layers 215. The vertical segment comprises a corresponding semiconductor strand section 230'-2 extending from the corresponding semiconductor strand section 230'-1 to another T-shaped channel (in particular, to a corresponding semiconductor strand section 230'-1 of a horizontal segment of another T-shaped channel) or to the substrate 202. The vertical segment also has a width s3 and a thickness h2 (i.e., the semiconductor strand sections 230'-2 have a width w3 and a thickness h2). In some embodiments, the thickness h2 is approximately 8 nm to approximately 15 nm. In some embodiments, such as the one shown, the thickness h2 is essentially equal to the thickness t1 of the semiconductor layers 210.The width of columns 292A, which separate the suspended semiconductor layer sections 215A', and of columns 292B, which separate the suspended semiconductor layer sections 215B', corresponds to the thickness h2, and thus the spacing between adjacent sheet-like channels (i.e., the spacing between adjacent suspended semiconductor layer sections 215A' of the T-shaped channels 290A-290C and the spacing between adjacent suspended semiconductor layer sections 215B' of T-shaped channels) is essentially equal to the thickness h2. In the illustrated embodiments, the spacing between adjacent suspended semiconductor layer sections 215A' is equal to the spacing between adjacent suspended semiconductor layer sections 215B'.In some embodiments, the spacing between adjacent suspended semiconductor layer sections 215A' differs from the spacing between adjacent suspended semiconductor layer sections 215B'. In some embodiments, the T-shaped channels 290A-290C have dimensions in the nanometer range; the vertical stack of T-shaped channels 290A-290C can be referred to as a nanostructure; the horizontal segments of the T-shaped channels 290A-290C can be referred to as nanostructure elements, e.g., nanosheets; and the vertical segments of the T-shaped channels 290A-290C can be referred to as nanostructure connecting elements (or sections), e.g., nanosheet connecting elements. The present disclosure also considers embodiments in which the T-shaped channels 290A-290C have sub-nanoscale dimensions or dimensions larger than nanoscale, depending on the design requirements of the multigate device 200.

[0034] Referring to Fig. In 16A-16E, a trimming process is performed to reduce the width of channel connection sections of the multigate device 200, e.g., the vertical segments of the T-shaped channel layers 290A-290C. For example, the trimming process etches the semiconductor strand sections 230'-2 laterally (e.g., in the y-direction), thereby providing the semiconductor strand sections 230'-2 with a width s4 that is smaller than the width s3. The width w4 can be selected (tuned) based on a desired drive current and / or a desired current-conducting area of ​​a transistor. In some embodiments, to maximize the drive current of a transistor, the width s4 is smaller than the spacing between sheet-like channels of the multigate device 200, for example, smaller than a spacing between adjacent horizontal segments of the T-shaped channels 290A-290C (e.g.,between adjacent suspended semiconductor layer sections 215A' and / or between adjacent suspended semiconductor layer sections 215B') (i.e., the thickness h2). In some embodiments, the width s4 is approximately 3 nm to approximately 10 nm. In the illustrated embodiment, the semiconductor strand sections 230'-2 have rounded sidewalls after the trimming process such that the semiconductor strand sections 230'-2 have a width that varies along the thickness h2. For example, the semiconductor strand sections 230'-2 have a narrow central section arranged between wider end sections, the wider end sections being connected to horizontal segments corresponding to the T-shaped channel layers 290A-290C. In such embodiments, the width of the semiconductor strand sections 230'-2 decreases from a maximum width (i.e.,The width s3 decreases to a minimum width at a horizontal segment of a first of the T-shaped channel layers 290A-290C and then increases from the minimum width to the maximum width at a horizontal segment of a second of the T-shaped channel layers 290A-290C. In such embodiments, the width s4, which is smaller than the width s3, is an average width of the semiconductor strand sections 230'-2. In some embodiments, after the trimming process, the semiconductor strand sections 230'-2 have substantially straight, parallel sidewalls, such that the semiconductor strand sections 230'-2 have a substantially uniform width along the thickness h2. In such embodiments, the width s4 is substantially the same along the thickness h2.In some embodiments, the semiconductor strand sections 230'-2 have beveled sidewalls after the trimming process such that the semiconductor strand sections 230'-2 have a width that increases or decreases along the thickness. In some embodiments, the trimming process partially exposes lower surfaces and / or upper surfaces of the semiconductor strand sections 230'-1, which in some embodiments can increase the current-conducting area.

[0035] The trimming process comprises any suitable process that can selectively reduce the width of vertical segments of the T-shaped channel layers 290A-290C (i.e., the semiconductor strand sections 230'-2) with minimal or no effect on the contours and / or dimensions of horizontal segments of the T-shaped channel layers 290A-290C (i.e., the suspended semiconductor layer sections 215A', the suspended semiconductor layer sections 215B', and the semiconductor strand sections 230'-1). In some embodiments, the trimming process is an etching process such as a dry etching process, a wet etching process, another suitable etching process, or a combination thereof. In some embodiments, the etching process is an anisotropic etching process, which generally refers to an etching process that has different etch rates in different directions, such that the etching process removes material in certain directions, e.g.,The anisotropic etching process removes material essentially in a single direction. In the illustrated embodiment, the etching process can be configured to have a horizontal etch rate greater than a vertical etch rate (in some embodiments, the vertical etch rate is zero). Thus, the anisotropic etching process removes material essentially in the horizontal direction (here, the y-direction) with minimal (or no) material removal in the vertical direction (here, the z-direction). In such embodiments, the anisotropic etching does not remove, or removes only minimally, portions of the T-shaped channel layers 290A-290C in the z-direction. In some embodiments, the etching process is a directed etching process that directs etchant in the y-direction but not in the x- or z-directions to effect lateral etching of the semiconductor strand portions 230'-2 in the y-direction.In some embodiments, the etching process selectively removes the semiconductor strand sections 230'-2 with minimal (or no) etching of the suspended semiconductor layer sections 215A', 215B'. For example, an etchant is selected for the etching process which etches the material of the semiconductor strand sections 230'-2 (e.g., silicon with a first composition) at a higher rate than the material of the suspended semiconductor layer sections 215A', 215B' (e.g., silicon with a second composition) (i.e., the etchant exhibits high etch selectivity with respect to the material of the semiconductor strand sections 230'-2). In some embodiments, the etching process is further configured to selectively etch the semiconductor strand sections 230'-2 with minimal (or no) etching of the insulation features 240, the gate spacers 256, the inner spacers 265 and / or the ILD layer 280.In some embodiments, the trimming process is further configured to modify the dimensions and / or shape of horizontal segments of the T-shaped channel layers 290A-290C. In some embodiments, the trimming process is used to modify and / or fine-tune the contours and / or dimensions of horizontal segments of the T-shaped channel layers 290A-290C (i.e., the suspended semiconductor layer sections 215A', the semiconductor layer sections 215B', and the semiconductor strand sections 230'-1). For example, the trimming process can reduce the height h1 of the suspended semiconductor layer sections 215A', the semiconductor layer sections 215B', and / or the semiconductor strand sections 230'-1. In another example, the trimming process can reduce the width s2 and / or the width s3 of the suspended semiconductor layer sections 215A' and 215B', respectively.In yet another example, the trimming process can adjust the contours of the suspended semiconductor layer sections 215A', 215B' such that the cross-sectional contours of the suspended semiconductor layer sections 215A', 215B' have a desired shape, such as circular, rectangular, square, hexagonal and / or another suitable shape.

[0036] Referring to Fig. 17A-17E, Fig. 18B and Fig. At 18C, a metal gate stack 295 (also called metal gate and / or high-k / metal gate) is formed in and fills the gate opening 285. The metal gate stack 295 comprises a gate dielectric 296 (for example, a gate dielectric layer) and a gate electrode 298 (for example, an exit work layer and a solid metal layer). The metal gate stack 295 may include numerous other layers.In some embodiments, forming the metal gate stack 295 comprises depositing a gate dielectric layer over the multigate device 200, which partially fills the gate opening 285, depositing a gate electrode layer over the gate dielectric layer, which fills a remaining part of the gate opening 285, and performing a planarization process on the gate electrode layer and the gate dielectric layer (for example, until the ILD layer 280 is reached and exposed), thereby forming the metal gate stack 295, which comprises the gate dielectric 296 and the gate electrode 298.

[0037] The gate dielectric 296 partially fills the gate opening 285 and surrounds the T-shaped channels 290A-290C such that the gate dielectric 296 partially fills the column 292A and the column 292B. Fig. 17A-17E covers the gate dielectric 296 exposed surfaces of the T-shaped channels 290A-290C such that the gate dielectric 296 is arranged along the upper surfaces, lower surfaces, and side faces of the suspended semiconductor layer sections 215A', 215B' of the T-shaped channels 290A-290C, the side walls of the semiconductor strand sections 230'-2 of the T-shaped channels 290A-290C, and the upper surface of the T-shaped channel 290C. The gate dielectric 296 is further arranged over a fin section of the substrate 202 (i.e., the substrate section of the fin 235, also referred to as the substrate extension section), the insulating features 240, and the gate spacers 256 in the channel region C.The gate dielectric 296 comprises a high k-value dielectric layer containing a high k-value dielectric material, which generally refers to a dielectric material having a dielectric constant greater than that of silicon dioxide (k ≈ 3.9). For example, the high k-value dielectric layer contains HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlOx, ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), Si3N4, a hafnium dioxide-aluminum oxide (HfO2-Al2O3-) alloy, other suitable high k-value dielectric materials for metal gate stacks or combinations thereof. The high k-value dielectric layer is formed by any of the processes described herein, such as ALD, CVD, PVD, an oxide-based deposition process, another suitable process, or a combination thereof.For example, an ALD process deposits the high k-value dielectric layer. In some embodiments, the ALD process is a conformal deposition process, such that the thickness of the high k-value dielectric layer is substantially uniform (conformal) across the various surfaces of the multigate device 200. In some embodiments, the gate dielectric 296 comprises an interface layer located between the high k-value dielectric layer and the T-shaped channels 290A-290C. The interface layer may contain a dielectric material such as SiO₂, HfSiO₂, SiON₂, another silicon-containing dielectric material, another suitable dielectric material, or combinations thereof. The interface layer is formed by any of the processes described herein, such as thermal oxidation, chemical oxidation, ALD, CVD, another suitable process, or combinations thereof.

[0038] The gate electrode 298 is formed above the gate dielectric 296, filling a remaining portion of the gate opening 285 and surrounding the T-shaped channels 290A-290C such that the gate electrode 298 fills remaining portions of the gaps 292A and 292B. In the illustrated embodiment, the gate electrode 298 is arranged along the upper surfaces, lower surfaces, and side faces of the suspended semiconductor layer sections 215A', 215B' of the T-shaped channels 290C-290C, the side walls of the semiconductor strand sections 230'-2 of the T-shaped channels 290A-290C, and the upper surface of the T-shaped channel 290C. The gate electrode 298 is further arranged above the fin section of the substrate 202, the insulating features 240, and the gate spacers 256 in the channel region C.The gate electrode 298 contains a conductive material such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, molybdenum, cobalt, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, other conductive materials, or combinations thereof. In some embodiments, the gate electrode 298 comprises a work function layer and a conductive solid layer. The work function layer is a conductive layer tuned to exhibit a desired work function (e.g., an n-type or p-type work function), and the conductive solid layer is a conductive layer formed above the work function layer. In some embodiments, the exit work layer contains n-type exit work materials such as Ti, silver, manganese, zirconium, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, other suitable n-type exit work materials or combinations thereof.In some embodiments, the exit work layer contains a p-type exit work material such as ruthenium, molybdenum, aluminum, titanium nitride (TiN), tantalum (TaN), tungsten nitride (WN), zirconia (ZrSi2), molybdenum nitride (MoSi2), tungsten nitride (TaSi2), tungsten nitride (NiSi2), tungsten nitride (WN), other suitable p-type exit work materials, or combinations thereof. The conductive solid layer (or filler layer) contains a suitable conductive material, such as aluminum nitride (Al), tungsten nitride (W), titanium nitride (Ti), tungsten nitride (Ta), polysilicon, copper (Cu), metal alloys, other suitable materials, or combinations thereof. The gate electrode 298 is formed by any of the processes described herein, such as ALD, CVD, PVD, plating, another suitable process, or a combination thereof.

[0039] Thus, the multigate device 200 comprises a T-channel transistor with a metal gate 295 located between the epitaxial source / drain features 270. The metal gate 295 (i.e., the gate dielectric 296 and the gate electrode 298) is positioned over the T-shaped channels 290A-290C of the T-channel transistor, such that each of the T-shaped channels 290A-290C (e.g., in the YZ plane) is enclosed and / or surrounded by the metal gate 295, and each of the T-shaped channels 290A-290C (e.g., in the XZ plane) extends between the epitaxial source / drain features 270. A blade spacing (here the thickness t2) and a blade width of vertical segments (here the width w4) can be adjusted to achieve the desired driver current and / or the desired current-conducting area, thus providing a transistor with optimal performance for a desired application.It was observed that the effective channel width (Weff), and thus the size of the current conduction area, of the proposed T-channel transistor increases with increasing blade spacing (here increasing thickness h2) and with decreasing blade width of vertical segments (here decreasing width s4), as shown in . Fig. 19A and Fig. 19B is illustrated. Fig. 19A and Fig. 19B provide graphs of a percentage change in the effective channel width (ΔWeff) as a function of the sheet width of horizontal segments in nm (e.g. the width w2), the sheet spacing in nm (e.g. the thickness h2) and the sheet width of vertical segments (e.g. the width s4) according to various aspects of the present disclosure. Fig. Figure 19A shows ΔWeff at a sheet width of vertical segments of approximately 10 nm (e.g. width s4 ≈ 10 nm) and Fig. Figure 19B shows ΔWeff at a vertical segment leaf width of approximately 5 nm (e.g., width s4 ≈ 5 nm), where line A1 and line B1 correspond to the T-channel transistor with a leaf spacing of x nm (i.e., thickness h2 = x nm), line A2 and line B2 correspond to the T-channel transistor with a leaf spacing of x nm + 1 nm (i.e., thickness h2 = x + 1 nm), and line A3 and line B3 correspond to the T-channel transistor with a leaf spacing of x nm + 2 nm (i.e., thickness h2 = x + 2 nm). In some embodiments, x is approximately 8 nm to approximately 15 nm. Lines A1-A3 and B1-B3 show that ΔWeff decreases with increasing blade width of horizontal segments (increasing width w2), but increases with increasing blade spacing (increasing thickness h2) and increases further with decreasing blade width of vertical segments (decreasing width s4). For example, in Fig. 19A and Fig. 19B Each increase in leaf spacing by 1 nm results in an increase in ΔWeff (e.g., the ΔWeff values ​​(increases) of line A1 are smaller than the ΔWeff values ​​of line A2, which in turn are smaller than the ΔWeff values ​​of line A3; the ΔWeff values ​​of line B1 are smaller than the ΔWeff values ​​of line B2, which in turn are smaller than the ΔWeff values ​​of line B3). Furthermore, reducing the segment width of vertical leaves (here by approximately 5 nm) increases ΔWeff (for example, ΔWeff values ​​of line A1 are greater than ΔWeff values ​​of line B1, ΔWeff values ​​of line B1 are greater than ΔWeff values ​​of line B2, and ΔWeff values ​​of line A3 are greater than ΔWeff values ​​of line A (with a leaf width of approximately 15 nm, ΔWeff is, for example, approximately 20% when the segment width of vertical leaves is approximately 10 nm (line A3), but approximately 42% when the segment width of vertical leaves is reduced by 5 nm to approximately 5 nm (line B3)).

[0040] Furthermore, the T-channel transistor, as shown and described above, can be more efficient than a conventional nanosheet channel transistor. Fig. Figure 20, for example, provides cross-sectional views of a T-channel transistor, such as the T-channel transistor of the multigate device 200, and of a nanosheet channel transistor 300. The nanosheet channel transistor 300 can be manufactured according to the process described above; however, in such a manufacturing process, the processing steps with regard to Fig. 3A-3E, Fig. 4A-4E, Fig. 5A-5E, Fig. 6A-6E, Fig. 7A-7E and Fig. 16A-16E are omitted, thus providing the nanosheet channel transistor 300 with three suspended sheet-like channel layers 215' (hereafter referred to as nanosheet channels 310A-310C) surrounded by the metal gate 295. The nanosheet channels 310A-310C have essentially the same dimensions as the T-shaped channels 290A-290C. For example, the nanosheet channels 310A-310C have a width w2 (i.e., the sum of width s1, width s2, and width s3) and a thickness h1, and the nanosheet channels 310A-310C have a spacing that is essentially equal to the thickness h2. Fig. Reference 20 further provides a graph of the driver current as a function of the sheet spacing in nanometers (nm) according to various aspects of the present disclosure, where line T corresponds to the T-shaped transistor and line NS corresponds to the nanosheet channel transistor 300. Lines T and NS indicate that both the T-channel transistor and the nanosheet channel transistor 300 have a driver current that is proportional to the sheet spacing. In other words, the driver current (and thus performance improvements) can be increased by increasing the spacing between sheets (i.e., the thickness h2), for example, the spacing between horizontal segments of the T-channels 290A-290C of the T-channel transistor (which can be referred to as sheet-like channels or nanosheets of the T-channel transistor) and the spacing between the suspended channel layers 215' of the nanosheet channel transistor 300.It should be noted that the leaf spacing between adjacent leaves can vary intentionally or unintentionally in such a way that the leaf spacing of the graph in . Fig. 20 and / or the sheet spacing of the T-channel transistor and / or the nanosheet channel transistor 300 (i.e. the thickness h2) can represent an average sheet spacing.

[0041] The graph also shows that a driver current for the T-channel transistor is larger than a driver current for the nanosheet channel transistor 300, and furthermore shows that the T-channel transistor can provide larger increases in driver current with increasing sheet spacing than the nanosheet channel transistor 300. Such improvements can be achieved because the current-conducting area of ​​the T-channel transistor is larger than that of the nanosheet channel transistor 300, and because the current-conducting area of ​​the T-channel transistor increases more with increasing sheet spacing than that of the nanosheet channel transistor 300. For example, each of the nanosheet channels 310A-310C has an effective sheet width (i.e., perimeter) equal to the sum of the width w2 of an upper surface of its corresponding suspended channel layer 215' (i.e., w2 = s1 + s2 + s3), the width w2 of a lower surface of its corresponding suspended Channel layer 215' (i.e.w2 = s1 + s2 + s3), a length of a first side wall of its corresponding suspended channel layer 215' (i.e. thickness h1) and a length of a second side wall of its corresponding suspended channel layer 215' (i.e. thickness h1) is (i.e., effective sheet width. 310A, 310B oder 310C = (2×s1) + (2×s2) + (2×s3) + (2×h1)). Total Effective Sheet Width (TESW) 310A-310C ) of the nanosheet channel transistor 300 is therefore equal to three times the effective sheet width according to the following equation (1). 310A, 310B oder 310C : TESW310A−310C=3×((2×s1)+(2×s2)++(2×s3)+(2×h1))=6s1+6s2+6s3+6h1

[0042] In the case of s2 = s1, as in the embodiment shown, the effective total sheet width of the nanosheet channel transistor 300 is also given by equation (2): TESW310A−310C=12s1+6h1+6s3.

[0043] Although the driver current of the nanosheet channel transistor 300 increases with increasing sheet spacing, such increases cannot be offset by increasing the sheet spacing to increase TESW in such a configuration. 310A-310C (and thus the power line area) can be achieved, since TESW 310A-310Cdoes not depend on the sheet spacing. On the other hand, in the T-channel transistor, each of the T-shaped channels 290A, 290B has an effective sheet width that is the sum of the width s1 of an upper surface of its corresponding suspended semiconductor layer section 215A', the width s2 of an upper surface of its corresponding suspended semiconductor layer section 215B', the length of a side wall of its corresponding suspended semiconductor layer section 215A' (i.e., thickness h1), the width s1 of a lower surface of its corresponding suspended semiconductor layer section 215A', the width s2 of a lower surface of its corresponding semiconductor layer section 215B', and the length of a first side wall of its corresponding semiconductor strand section 230'-2 (i.e., thickness h1).thickness h2) and a length of a second side wall of its corresponding semiconductor strand section 230'-2 (i.e. thickness h2) is (i.e., effective sheet width. 290A oder 290B = (2×s1) + (2×s2) + (2×h1) + (2×h2)); and the T-shaped channel 290C has an effective width (i.e., circumference) equal to the sum of the width s3 of its corresponding semiconductor strand section 230'1 and an effective width of the T-shaped channels 290A, 290B (i.e., effective sheet width). 290C = s3 + (2×s1) + (2×s2) + (2×h1) + (2×h2)). An effective total blade width (TESW) 290A-290C ) of the T-channel transistor is therefore, according to the following equation (3), equal to a sum of the width s3 and three times the effective sheet width. 290A oder 290B : TESW290A−290C=s3+(3×((2×s1)+(2×s2)+(2×h1)+(2×h2))=s3+6s1+6s2+6h1+6h2

[0044] In the case of s2 = s1, as in the illustrated embodiment, the effective total sheet width of the T-channel transistor is also given by equation (4): TESW290A−290C=s3+12s1+6h1+6h2.

[0045] Since TESW 290A-290CSince the current-conducting area and / or the driving current of the T-channel transistor depend directly and proportionally on the blade spacing (i.e., the thickness h2), in this configuration the current-conducting area and / or the driving current can increase directly and proportionally with the increase in blade spacing. In some embodiments, the current-conducting area and / or the driving current are optimized when the blade spacing is larger than the width s4 (e.g., h2 ≥ s4), for example, when the blade spacing is approximately two to five times larger than the width s4. For example, decreasing the width s4 (the thickness) increases the contact area between the metal gate 295 and the upper and / or lower surfaces of horizontal segments of the T-channels 290A-290C, thereby increasing the current-conducting area and / or the driving current. 290A-290Cfurther increased. In some embodiments, the current-conducting area and / or the driving current are optimized when the sheet spacing is approximately 8 nm to approximately 15 nm and the width s4 is approximately 3 nm to approximately 10 nm. Increasing the sheet spacing to enlarge the current-conducting area and / or increase the driving current also enlarges the window for filling the metal gate, so that the gate electrode 298 and / or the gate dielectric 296 can better fill the gap 292A, 292B between adjacent sheet-like channel layers (i.e., horizontal segments of the T-shaped channels 290A-290C) and void formation within the metal gate 295 is reduced and / or eliminated.Increasing the leaf spacing to fine-tune the current-conducting area, driver current, and / or other performance characteristics of multigate devices, as described herein, can also be seamlessly integrated into existing IC manufacturing processes for multigate device production. Different embodiments may offer different advantages, and no single embodiment necessarily has to offer a particular advantage.

[0046] Manufacturing can continue to produce the multigate device 200. For example, various contacts can be formed to facilitate the operation of the transistor. For instance, one or more ILD layers similar to ILD layer 280 and / or CESL layers can be formed over the substrate 202 (especially over ILD layer 280 and the gate structure 250). Contacts can then be formed in ILD layer 280 and / or in ILD layers arranged over ILD layer 280. The contacts are, for example, each electrically and / or physically coupled to the gate structure 250 and each electrically and / or physically coupled to the epitaxial source / drain features 270. The contacts contain a conductive material, such as a metal. Metals include aluminum, aluminum alloys (e.g.,Aluminum / silicon / copper alloys), copper, copper alloys, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, metal silicide, other suitable metals, or combinations thereof. The metal silicide may include nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, or combinations thereof. In some implementations, ILD layer 280, ILD layers arranged above ILD layer 280, and the contacts (arranged, for example, in ILD layer 280 and / or the other ILD layers) form part of a multilayer interconnect (MLI) feature.The MLI feature electrically couples various devices (e.g., transistors, resistors, capacitors, and / or inductors) and / or components (e.g., gate structures and / or epitaxial source / drain features) such that the various devices and / or components can operate as specified by the design requirements of the Multigate Device 200. The MLI feature comprises a combination of dielectric layers and electrically conductive layers (e.g., metal layers) configured to form various interconnection structures. The conductive layers are configured to form vertical interconnection features, such as device contacts and / or vias, and / or horizontal interconnection features, such as traces. Vertical interconnection features typically connect horizontal interconnection features in different layers (or different levels) of the MLI feature.During operation, the connection features are configured to transmit signals between the components and / or elements of the Multigate 200 and / or to distribute signals (for example, clock signals, voltage signals and / or ground signals) to the components and / or elements of the Multigate 200.

[0047] The present disclosure considers the initiation of the processing operations that are associated with Fig. 3A-3E, Fig. 4A-4E, Fig. 5A-5E, Fig. 6A-6E, Fig. 7A-7E and Fig. References 16A-16E are related to achieving different channel shapes that exhibit larger TESWs than conventional nanosheet channel transistors, thereby increasing the drive current of nanosheet-based transistors. The different channel shapes can be achieved by forming a semiconductor material trench in a semiconductor layer stack, which is then machined to form nanosheets. The semiconductor material trench has a first thickness greater than a sheet spacing (e.g., an average sheet spacing that may correspond to a thickness of several layers of the semiconductor layer stack), and this first thickness is reduced during gate replacement to a second thickness smaller than the sheet spacing. The first thickness, second thickness, and sheet spacing can be tuned to provide different current-conducting areas and / or different drive current performance.

[0048] Instead of as with reference to Fig. As described in 4A-4E, to completely remove the semiconductor layer stack 205 exposed by the EUV mask 220, for example in some embodiments the semiconductor layer stack 205 exposed by the EUV mask 220 is partially removed by the etching process. Fig. Figures 21A-21F are partial cross-sectional views of a section or the entirety of a Multigate device 400 in various stages of manufacture according to such embodiments. Fig. 21A has the Multigate component 400 with reference to Fig. 2A-2E and Fig. The processing described in 3A-3E is carried out and then subjected to processing that corresponds to the processing described in reference to Fig. The embodiments described in 4A-4E are similar, except that the semiconductor layer stack 205, exposed by the EUV mask 220, is partially removed by the etching process such that the trench 225 extends partially through the semiconductor layer stack 205 instead of extending completely through it. For example, the trench 225 extends through the upper semiconductor layer 215, the upper semiconductor layer 210, and the middle semiconductor layer 215, forming semiconductor layer sections 210A, separated by the trench 225 from semiconductor layer sections 210B, and semiconductor layer sections 215A, separated by the trench 225 from semiconductor layer sections 215B, in an upper half of the semiconductor layer stack 205. In such embodiments, the semiconductor layers 210 and 215 remain in a lower half (ordepending on the depth of the trench 225 in a lower section) of the semiconductor layer stack 205 connected. In . Fig. 21B-21D, the Multigate component 400 is then subjected to processing that corresponds to the above with reference to Fig. 5A-5E, Fig. 6A-6E or Fig. The semiconductors described in Figures 7A-7E are similar, wherein a portion of the semiconductor layer 230 remaining after the CMP process forms a semiconductor strand 430' having a width w1 and a height less than the height of the semiconductor layer stack 205. The semiconductor strand 430' is formed in an active region of the multigate device 400, specifically in a region of the multigate device 400 where a channel region and source / drain regions for a transistor of the multigate device 400 are formed. Accordingly, the semiconductor layer stack 205 has an upper section with the semiconductor strand 430', which is located between the semiconductor layer sections 210A, 215A and the semiconductor layer sections 210B, 215B, and a lower section with the semiconductor layers 210, 215. The semiconductor strand 430' has an interface I1 to the semiconductor layer sections 210A, 215A and an interface I2 to the semiconductor layer sections 210B, 215B.In . Fig. 21E the Multigate component 400 is then subjected to processing that corresponds to the above with reference to Fig. The embodiments described in Figures 8A-8E are similar, wherein the fin 235 is formed from the semiconductor layer stack 205. In the illustrated embodiment, the fin 235 comprises a substrate section (i.e., a section of the substrate 202) and a semiconductor layer stack section (i.e., a remaining section of the semiconductor layer stack 205, comprising an upper section (here, an upper half) with the semiconductor layer sections 210A, 210B, the semiconductor layer sections 215A, 215B, and the semiconductor strand 430', and a lower section (here, a lower half) with the semiconductor layers 210 and the semiconductor layers 215).

[0049] In Fig. 21F has the Multigate component 400 which refers to Fig. 9A-9E, Fig. 10A-10E, Fig. 11A-11E, Fig. 12A-12E, Fig. 13A-13E, Fig. 14A-14E, Fig. 15A-15E, Fig. 16A-16E and Fig. The processes described in 17A-17E are carried out. Since the semiconductor strand 430' extends partially through the fin 235, the multigate device 400 has a different channel configuration than the multigate device 200. For example, the multigate device 400 has a nanosheet channel 490A and an H-shaped channel 490B, both of which are surrounded by the metal gate 295. In such embodiments, the channel release process is formed by Fig. 15A-15E and the trimming process from Fig. 16A-16E from the lower semiconductor layer 215 of the fin 235, a suspended channel layer 215'; from the semiconductor layer sections 215A, 215B of the fin 235, suspended semiconductor strand sections 215A', 215B'; and from the semiconductor strand 430' of the fin 235, semiconductor strand sections 430'-1 and one semiconductor strand section 430'-2. The nanosheet channel 490A comprises a suspended channel layer 215'. The H-shaped channel 490B comprises two horizontal segments (which can be referred to as nanosheets) and a vertical segment that extends between and connects the horizontal segments.Each of the horizontal segments is formed by a corresponding suspended semiconductor layer section 215A' (having, for example, a width of s1), a corresponding suspended semiconductor layer section 215B' (having, for example, a width of s2), and a corresponding semiconductor strand section 430'-1 (having, for example, a width of s3) that extends between and connects the corresponding suspended semiconductor layer section 215A' and the corresponding semiconductor layer section 215B'. The vertical segment is formed by the semiconductor strand section 430'-2 (having, for example, a width of s4). In the illustrated embodiment, a spacing between the nanosheet channel 490A and the H-shaped channel 490B is equal to the thickness of the semiconductor strand section 430'-2, for example, the thickness h2 (which also provides a spacing between horizontal segments of the H-shaped channel 490B).In some embodiments, the spacing between the nanosheet channel 490A and the H-shaped channel 490B differs from the thickness of the semiconductor strand section 430'-2. Similar to the Multigate device 200, the sheet spacing (e.g., the thickness h2), the width of vertical segments (e.g., the width s4), the width of horizontal segments (e.g., the width w2), and / or other channel dimensions can be adjusted to achieve a desired current-conducting area and / or a desired driving current of the Multigate device 400, thus optimizing the transistor performance for a particular application. For clarity and simplicity, similar features of the Multigate devices 400 and 200 described above are designated by the same reference numerals. Fig. References 21A-21F have been simplified for clarity to make the concepts of the invention as presented in this disclosure more readily understandable. Additional features may be added to the multigate device 400, and some of the features described below may be replaced, modified, or omitted in other embodiments of the multigate device 400.

[0050] In some embodiments, the orientation of the opening 222 in the EUV mask 220 is offset with respect to the channel area C in order to change the position of a semiconductor strand within the semiconductor stack 205 (and the fin 235) and thus provide a multigate device with a different channel configuration. Fig. Figures 22A-22F are partial cross-sectional views of a section or the entirety of a Multigate device 500 in various stages of manufacture according to such embodiments. Fig. 22A has undergone 500 processing cycles of the multigate component, which, with reference to Fig. 2A-2E, Fig. 3A-3E and Fig. 4A-4E were described, except that, instead of aligning the center of the opening 222 in the EUV mask 220 with the center of the channel region C as in the fabrication of the multigate device 200, an EUV lithography structuring process aligns an edge of the opening 222 in the EUV mask 220 with an edge of the channel region C, for example, a left edge of the channel region C. Accordingly, an edge of the trench 225 is aligned with an edge of the channel region C, the semiconductor layer sections 210A and the semiconductor layer sections 215A are located outside the channel region C, and sections of the semiconductor layer sections 210B and sections of the semiconductor layer sections 215B are located in the channel region C. Fig. 22B-22D, the Multigate component 500 is then subjected to processing that corresponds to the above with reference to Fig. 5A-5E, Fig. 6A-6E or Fig. The semiconductors described in Figures 7A-7E are similar, wherein a remaining portion of the semiconductor layer 230 after the CMP process forms a semiconductor strand 530' having a width w1 and a height substantially equal to the height of the semiconductor layer stack 205. Accordingly, the semiconductor layer stack 205 includes the semiconductor strand 530', which is located between the semiconductor layer sections 210A, 215A and the semiconductor layer sections 210B. The semiconductor strand 530' has an interface I1 with the semiconductor layer sections 210A, 215A and an interface I2 with the semiconductor layer sections 210B, 215B. Fig. 22E the Multigate component 500 is then subjected to processing that corresponds to the above with reference to Fig. The fins 235 described in Figures 8A-8E are similar, with the fin being formed from the semiconductor layer stack 205. Since the semiconductor strand 530' is aligned with an edge of the channel region C, the fin 235 in the illustrated embodiment comprises a substrate section (i.e., a section of the substrate 202) and a semiconductor layer stack section (i.e., a remaining section of the semiconductor layer stack 205). Unlike the fin 235 of the multigate device 200, the fin 235 of the multigate device 500 does not include semiconductor layer sections 210A, 210B. Instead, the fin 235 of the multigate device 500 includes the semiconductor strand 530', the semiconductor layer sections 210B and the semiconductor layer sections 215B, the semiconductor layer sections 210B and the semiconductor layer sections 215B extending from the semiconductor strand 530'.

[0051] In Fig. 22F has the Multigate component 500 which refers to Fig. 9A-9E, Fig. 10A-10E, Fig. 11A-11E, Fig. 12A-12E, Fig. 13A-13E, Fig. 14A-14E, Fig. 15A-15E, Fig. 16A-16E and Fig. The processes described in Sections 17A-17E are performed. Since the fin 235 of the multigate device 500 does not include semiconductor layer sections 210A, 210B, the multigate device 500 has a different channel configuration than the multigate device 200. For example, the multigate device 500 has an E-shaped channel 590 surrounded by the metal gate 295. In such embodiments, the channel release process depends on Fig. 15A-15E and the trimming process from Fig. 16A-16E, the semiconductor layer sections 215B' are connected to the semiconductor layer sections 215B of the fin 235, and the semiconductor strand sections 530'-1 and 530'-2 are connected to the semiconductor strand 530' of the fin 235. The E-shaped channel 590B comprises three horizontal segments (which can be referred to as nanosheets), two vertical segments extending between and connecting the horizontal segments, and one vertical segment extending between and connecting a lower of the horizontal segments and the substrate 202 (specifically, a fin section (substrate extension section) of the substrate 202). Each of the horizontal segments is formed by a corresponding semiconductor strand section 530'-1 and a corresponding suspended semiconductor layer section 215B' extending from it. The vertical segments are formed by the semiconductor strand sections 530'-2.Depending on the desired channel configuration and / or transistor power, the width of the semiconductor strand sections 530'-1 is less than, greater than, or substantially equal to the width of the suspended semiconductor layer sections 215B'. The width of the semiconductor strand sections 530'-2 is configured to be less than the spacing between the horizontal segments (i.e., less than the thickness of the semiconductor strand sections 530'-2) to optimize the performance of the Multigate device 500. Depending on the desired channel configuration and / or transistor power, the width of the semiconductor strand sections 530'-2 can be less than, greater than, or substantially equal to the width of the semiconductor strand sections 530'-1. Similar to the Multigate device 200, the sheet spacing (e.g., the thickness of the semiconductor strand sections 530'-2), the width of vertical segments (e.g., the thickness of the semiconductor strand sections 530'-2), and the thickness of the semiconductor strand sections 530'-2 can be adjusted.The width of the semiconductor strand sections 530'-2), the width of horizontal segments (e.g., the sum of the width of a corresponding semiconductor strand section 530'-1 and the width of a corresponding suspended semiconductor layer section 215B'), and / or other channel dimensions are adjusted to achieve a desired current-conducting area and / or a desired driver current of the Multigate device 500, which optimizes the transistor performance for a specific application. For clarity and simplicity, similar features of the Multigate devices 500 and 200 described above bear the same reference numerals. Fig. References 22A-22F have been simplified for clarity to make the concepts of the invention as presented in this disclosure more readily understandable. Additional features may be added to the multigate device 500, and some of the features described below may be replaced, modified, or omitted in other embodiments of the multigate device 500.

[0052] In some embodiments, a semiconductor strand is formed in the semiconductor layer stack 205 before all semiconductor layers of the semiconductor layer stack 205 are deposited. Fig. Figures 23A-23H are partial cross-sectional views of a section or the entirety of a Multigate component 600 in various manufacturing stages according to such embodiments. Fig. 23A has undergone 600 processing cycles of the multigate component, which were carried out with reference to Fig. As described in 2A-2E, however, two pairs of semiconductor layer pairs are formed above the substrate 202, and not three pairs of semiconductor layer pairs as in the fabrication of the multigate device 200. Each pair of semiconductor layer pair comprises a corresponding semiconductor layer 215 arranged above a corresponding semiconductor layer 210. Fig. 23B has undergone 600 processing cycles of the multigate component, which were carried out with reference to Fig. 3A-3E and Fig. 4A-4E were described, wherein the trench 225 is formed such that it extends completely through the semiconductor layer stack 205 and partially into the substrate 202, thereby forming semiconductor layer sections 210A separated by the trench 225 from the semiconductor layer sections 210B, and semiconductor layer sections 215A separated by the trench 225 from the semiconductor layer sections 215B. Fig. 23C-23E, the Multigate component 600 is then subjected to processing that corresponds to the above with reference to Fig. 5A-5E, Fig. 6A-6E or Fig. The components described in Figures 7A-7E are similar, wherein a portion of the semiconductor layer 230 remaining after the CMP process forms a semiconductor strand 630' having a width w1 and a height substantially equal to the height of the semiconductor layer stack 205 at the time of fabrication. The semiconductor strand 630' is formed in an active region of the multigate device 200, approximately in a region of the multigate device 600 in which a channel region and source / drain regions for a transistor of the multigate device 600 are formed. Accordingly, the semiconductor layer stack 205 has the semiconductor strand 630' located between the semiconductor layer sections 210A, 215A and the semiconductor layer sections 210B, 215B. The semiconductor strand 630' has an interface I1 to the semiconductor layer sections 210A, 215A and an interface I2 to the semiconductor layer sections 210B, 215B.An interface I3 lies between the semiconductor strand 630' and the substrate 202. In . Fig. 23F then the fabrication of the semiconductor layer stack 205 is completed before the formation of the fin 235. For example, a third semiconductor layer pair (e.g., a corresponding semiconductor layer 215 arranged above a corresponding semiconductor layer 210) is formed above the semiconductor layer sections 210A, 215A, the semiconductor strand 630', and the semiconductor layer sections 210B, 215B. In such embodiments, the semiconductor layers 210, 215 remain connected in an upper half (or depending on the number of semiconductor layer pairs of the semiconductor layer stack 205 in an upper section) of the semiconductor layer stack 205. Fig. 23G, the Multigate component 600 is then subjected to processing that corresponds to the above with reference to Fig. The embodiments described in Figures 8A-8E are similar, wherein the fin 235 is formed from the semiconductor layer stack 205. In the illustrated embodiment, the fin 235 comprises a substrate section (i.e., a section of the substrate 202) and a semiconductor layer stack section (i.e., a remaining section of the semiconductor layer stack 205). The semiconductor layer stack section has an upper section comprising the semiconductor layer 210 and the semiconductor layer 215, and a lower section comprising the semiconductor layer sections 210A, 215A, the semiconductor layer sections 210B, 215B, and the semiconductor strand 630' arranged between them.According to another aspect of the illustrated embodiment, the substrate section has an upper section with the semiconductor strand 630' arranged between sections of the substrate 202, and a lower section with a continuous section of the substrate 202 extending along a bottom side of the semiconductor strand 630'.

[0053] In Fig. 22H has the Multigate component 600 which, with reference to Fig. 9A-9E, Fig. 10A-10E, Fig. 11A-11E, Fig. 12A-12E, Fig. 13A-13E, Fig. 14A-14E, Fig. 15A-15E, Fig. 16A-16E and Fig. The processes described in 17A-17E are carried out. Since the semiconductor strand 630' extends partially through the fin 235 and is located on one underside of the fin 235, the multigate device 600 has a different channel configuration than the multigate device 200. For example, the multigate device 600 has an H-shaped channel 690A and a nanosheet channel 690B, both of which are surrounded by the metal gate 295. In such embodiments, the channel release process from Fig. 15A-15E and the trimming process from Fig. 16A-16E from the upper semiconductor layer 215 of the fin 235, a suspended channel layer 215', from the semiconductor layer sections 215A, 215B of the fin 235 suspended semiconductor strand sections 215A', 215B', and from the semiconductor strand 630' of the fin 235 semiconductor strand sections 630'-1 and semiconductor strand sections 630'-2. The nanosheet channel 690B comprises the suspended channel layer 215', which is arranged vertically above the H-shaped channel 690A. The H-shaped channel 690A comprises two horizontal segments (which can be referred to as nanosheets), a vertical segment that extends between and connects the horizontal segments, and a vertical segment that extends between and connects one of the lower horizontal segments and the substrate 202.Each of the horizontal segments is formed by a corresponding suspended semiconductor layer section 215A' (having, for example, a width of s1), a corresponding semiconductor layer section 215B' (having, for example, a width of s2), and a corresponding semiconductor strand section 630'-1 (having, for example, a width of s3), which extends between and connects the corresponding suspended semiconductor layer section 215A' and the corresponding semiconductor layer section 215B'. The vertical segment is formed by the semiconductor strand section 630'-2 (having, for example, a width of s4). In the illustrated embodiment, a spacing between the nanosheet channel 690B and the H-shaped channel 690A is equal to the thickness of the semiconductor strand sections 630'-2, for example, the thickness h2 (which also provides a spacing between horizontal segments of the H-shaped channel 690A).In some embodiments, the spacing between the nanosheet channel 690B and the H-shaped channel 690A differs from the thickness of the semiconductor strand sections 630'-2. In the illustrated embodiment, the thickness of a lower semiconductor strand section 230'-2 is greater than the thickness of the semiconductor strand section 230'-2 that connects horizontal segments of the H-shaped channel 690A, because the semiconductor strand 630' extends into the substrate 202. In some embodiments, the semiconductor strand sections 230'-2 have the same thickness. Similar to the Multigate 200 component, the blade spacing (e.g., the thickness h2), the width of vertical segments (e.g., the width s4), the width of horizontal segments (e.g., the width w2), and / or other channel dimensions can be adjusted to achieve a desired current-conducting area and / or a desired driver current of the Multigate 600 component.which optimizes transistor performance for a specific application. For clarity and simplicity, similar features of the Multigate 600 and 200 devices described above are designated with the same reference symbols. Fig. References 23A-23H have been simplified for clarity to make the concepts of the invention as presented in this disclosure more readily understandable. Additional features may be added to the multigate device 600, and some of the features described below may be replaced, modified, or omitted in other embodiments of the multigate device 600.

[0054] The present disclosure provides many different embodiments. One exemplary device comprises a channel layer arranged over a substrate, a first source / drain feature and a second source / drain feature arranged over the substrate, and a metal gate arranged between the first and second source / drain features. The metal gate encloses the channel layer. The channel layer has a first horizontal segment, a second horizontal segment, and a vertical segment extending between and connecting the first and second horizontal segments. The first and second horizontal segments extend in a first direction, and the vertical segment extends in a second direction different from the first.The vertical segment has a width in the first direction and a thickness in the second direction. The thickness is greater than the width. The channel layer extends in a third direction, different from the first and second directions, between the first source / drain feature and the second source / drain feature.

[0055] In some embodiments, the first horizontal segment and the vertical segment form a first T-channel, and the second horizontal segment forms a section of a second T-channel, with the first T-channel being arranged above the second T-channel. In such embodiments, the vertical segment can be a first vertical segment, and the channel layer can further comprise a second vertical segment extending between and connecting the second horizontal segment and the substrate. According to another aspect of such embodiments, the second vertical segment can extend in the second direction and form a section of the second T-channel. In some embodiments, the first horizontal segment, the second horizontal segment, and the vertical segment form an H-shaped channel suspended above and separated from the substrate.In such embodiments, the channel layer can be a first channel layer, and the component can further comprise a second channel layer arranged vertically between the H-shaped channel and the substrate. According to another aspect of such embodiments, the second channel layer can comprise a third horizontal segment suspended above and separate from the substrate. According to yet another aspect of such embodiments, the third horizontal segment can be different from the first horizontal segment and / or the second horizontal segment.

[0056] In some embodiments, the first horizontal segment, the second horizontal segment, and the vertical segment form an H-shaped channel. In such embodiments, the vertical segment can be a first vertical segment, and the channel layer can further comprise a second vertical segment that extends between the second horizontal segment and the substrate, connecting them. The second vertical segment extends in the second direction. According to another aspect of such embodiments, the channel layer can be a first channel layer, and the device can further comprise a second channel layer. The H-shaped channel can be arranged vertically between the second channel layer and the substrate. The second channel layer can comprise a third horizontal segment that is suspended above and separate from the substrate.According to another aspect of such embodiments, the third horizontal segment can be different from the first and second horizontal segments. In some embodiments, the vertical segment is a first vertical segment, and the channel layer further comprises a third horizontal segment and a second vertical segment. A second vertical segment extends between and connects the second and third horizontal segments. The first horizontal segment, the second horizontal segment, the third horizontal segment, the first vertical segment, and the second vertical segment form an E-shaped channel. In such embodiments, the channel layer can include a third vertical segment that extends between and connects the third horizontal segment and the substrate.

[0057] Another exemplary device comprises a channel positioned above a substrate, a first source / drain feature and a second source / drain feature positioned above the substrate, and a metal gate located between the first and second source / drain features. The metal gate encloses the channel. The channel includes a first nanosheet, a second nanosheet, and a nanosheet connector section that joins the first and second nanosheets. A gap exists between the first and second nanosheets in a first direction, which is essentially perpendicular to the substrate. The nanosheet connector section has a thickness in a second direction, which is essentially parallel to the substrate. This thickness is less than the gap.The first nanosheet and the second nanosheet extend from the first source / drain feature and the second source / drain feature in a third direction. This third direction differs from the first and second directions. In some embodiments, the channel is connected to the substrate. In other embodiments, the channel is not connected to the substrate. In some embodiments, the nanosheet connection section connects a first center of the first nanosheet to a second center of the second nanosheet. In other embodiments, the nanosheet connection section connects a first edge of the first nanosheet to a second edge of the second nanosheet. In other embodiments, the channel further comprises a third nanosheet that is not connected to the first and second nanosheets.In some embodiments, the nanosheet connection section extends in the third direction from the first source / drain feature to the second source / drain feature.

[0058] An exemplary method comprises forming a semiconductor layer stack over a substrate. The semiconductor layer stack comprises first semiconductor layers and second semiconductor layers stacked vertically in an alternating configuration. The method further comprises forming a semiconductor strand extending from one of the first semiconductor layers through one of the second semiconductor layers to another of the first semiconductor layers. The semiconductor strand has a first width. The method further comprises structuring the semiconductor layer stack to form a fin structure extending from the substrate. The fin structure comprises the semiconductor strand, a portion of the first of the first semiconductor layers, a portion of one of the second semiconductor layers, and a portion of the second of the first semiconductor layers.The method further comprises selectively removing a portion of one of the second semiconductor layers, such that the first of the first semiconductor layers is separated from the second of the first semiconductor layers by a distance in a first direction, and the semiconductor strand extends between and connects the first and second of the first semiconductor layers in the first direction. The method further comprises trimming the semiconductor strand to reduce the first width to a second width. The first width and the second width extend in a second direction, which differs from the first direction, with the first width being greater than the distance and the second width being less than the distance.In some embodiments, forming the semiconductor strand extending from the first of the first semiconductor layers through one of the second semiconductor layers to the second of the first semiconductor layers comprises performing an extreme ultraviolet (EUV) lithography process to form an EUV mask over the semiconductor layer stack; etching a trench using the EUV mask as the etching mask, the trench extending through the first of the first semiconductor layers, one of the second semiconductor layers, and the second of the first semiconductor layers; and filling the trench with a semiconductor material.

[0059] Another exemplary device comprises a T-shaped channel layer over a substrate, a first source / drain feature and a second source / drain feature over the substrate, and a metal gate positioned between the first and second source / drain features. The T-shaped channel layer is positioned between the first and second source / drain features. The T-shaped channel layer includes a first channel segment and a second channel segment, each extending in a first direction substantially parallel to an upper surface of the substrate, and a channel extension segment extending in a second direction substantially perpendicular to the upper surface of the substrate. The channel extension segment is positioned between and connects the first and second channel segments.The metal gate encloses the first channel section and the second channel section. The metal gate is arranged along the side walls of the channel extension section. In some embodiments, the first material of the first channel section and the second channel section differs from the second material of the channel extension section. In some embodiments, the first material of the first channel section and the second channel section is the same as the second material of the channel extension section. In some embodiments, the channel extension section has a thickness defined in the first direction, and the first channel section and the second channel section are separated from the substrate by a spacer defined in the second direction, the thickness being smaller than the spacer.In some embodiments, the first channel section and the second channel section each have an upper surface, a lower surface, and a side wall surface extending between the upper surface and the lower surface. In such embodiments, the metal gate covers the upper surface, the lower surface, and the side wall surface.

[0060] In some embodiments, the T-shaped channel layer is a first T-shaped channel layer, and the channel extension section is a first channel extension section. In such embodiments, the device may further comprise a second T-shaped channel layer arranged above and connected to the first T-shaped channel layer. The second T-channel layer comprises a third channel section and a fourth channel section, each extending in the first direction, and a second channel extension section extending in the second direction. The second channel extension section is arranged between and connects the third and fourth channel sections. The second channel extension section is connected to the first channel extension section. The second T-shaped channel layer is arranged between the first source / drain feature and the second source / drain feature.The metal gate encloses the third and fourth channel sections and is arranged along the side walls of the second channel extension section. In such embodiments, the first and second channel extension sections can each have a thickness defined in the first direction. The first channel section can be separated from the third channel section by a first spacing defined in the second direction, and the second channel section can be separated from the fourth channel section by a second spacing defined in the second direction. The first and second spacings are each greater than the thickness.In some embodiments, the first channel expansion section has a first thickness and the second channel section has a second thickness, the first and second thicknesses being defined in the first direction. Depending on the design considerations, the first thickness may be equal to or different from the second thickness. In some embodiments, the metal gate may fill both the first and second spacings. In some embodiments, the first spacing is different from the second spacing. In some embodiments, the first spacing is equal to the second spacing.

[0061] Another exemplary device comprises an F-shaped channel layer above a substrate, a first source / drain feature and a second source / drain feature above the substrate, and a metal gate positioned between the first and second source / drain features. The F-shaped channel layer is located between the first and second source / drain features. The F-shaped channel layer includes a first channel segment and a second channel segment, each extending in a first direction that is substantially parallel to an upper surface of the substrate. The first channel segment is positioned above the second channel segment. The F-shaped channel layer further includes a channel extension segment extending in a second direction that is substantially perpendicular to the upper surface of the substrate.Both the first and second channel sections are connected to and extend from a first side of the channel extension section. The metal gate encloses both the first and second channel sections. The metal gate is arranged along a second side of the channel extension section. The metal gate fills a space between the first and second channel sections. In some embodiments, the channel extension section has a thickness defined in the first direction, the spacing between the first and second channel sections is defined in the second direction, and the thickness is less than the spacing.

[0062] Another exemplary method involves forming a semiconductor layer stack over a substrate. The semiconductor layer stack comprises a first semiconductor layer arranged over the substrate and a second semiconductor layer arranged over the first semiconductor layer. The second semiconductor layer is different from the first semiconductor layer. The method includes forming a third semiconductor layer that extends through the second semiconductor layer and the first semiconductor layer of the semiconductor layer stack. The method includes structuring the semiconductor layer stack to form a fin structure extending from the substrate.The fin structure comprises a first section of the second semiconductor layer arranged above a first section of the first semiconductor layer, a second section of the second semiconductor layer arranged above a second section of the first semiconductor layer, and a third semiconductor layer that separates the first section of the second semiconductor layer from the second section of the second semiconductor layer and separates the first section of the first semiconductor layer from the second section of the first semiconductor layer. The process includes etching the fin structure to form source / drain depressions. A channel region of the fin structure is arranged between the source / drain depressions. The process includes forming source / drain features within the source / drain depressions.The method comprises forming a metal gate enclosing the first and second sections of the second semiconductor layer after selectively removing the first and second sections of the first semiconductor layer from the channel region of the fin structure. The metal gate is further arranged along sidewalls of the third semiconductor layer. In some embodiments, the method further comprises modifying the thickness of the third semiconductor layer before forming the metal gate and after selectively removing the first and second sections of the first semiconductor layer from the channel region of the fin structure.

[0063] In some embodiments, modifying the thickness of the third semiconductor layer includes reducing the thickness of the third semiconductor layer such that the thickness is smaller than a first spacing between the first section of the second semiconductor layer and the substrate and a second spacing between the second section of the second semiconductor layer and the substrate.In some embodiments, forming the third semiconductor layer, which extends through the second and first semiconductor layers of the semiconductor stack, involves performing a lithography process to expose a portion of the semiconductor stack, etching the exposed portion of the semiconductor stack to form a trench, depositing a semiconductor material in the trench and over the semiconductor stack, performing an annealing process on the semiconductor material, and performing a planarization process on the semiconductor material, thereby removing the semiconductor material above the semiconductor stack. In some embodiments, the third semiconductor layer extends through the semiconductor stack into the substrate. In some embodiments, the lithography process is an extreme ultraviolet (EUV) lithography process that forms an EUV mask over the semiconductor stack.The EUV mask has an opening that exposes the section of the semiconductor layer stack. In some embodiments, the semiconductor material contains silicon. In some embodiments, the semiconductor material contains amorphous silicon. In such embodiments, the annealing process recrystallizes the amorphous silicon.

[0064] In some embodiments, the semiconductor layer stack further comprises a fourth semiconductor layer arranged between a fifth semiconductor layer and the first semiconductor layer. The material of the fourth semiconductor layer is the same as that of the second semiconductor layer, the material of the fifth semiconductor layer is the same as that of the first semiconductor layer, and the fifth semiconductor layer is arranged between the substrate and the fourth semiconductor layer.In such embodiments, the fin structure can further comprise a first section of the fourth semiconductor layer arranged above a first section of the fifth semiconductor layer, a second section of the fourth semiconductor layer arranged above a second section of the fifth semiconductor layer, and the third semiconductor layer, which separates the first section of the fourth semiconductor layer from the second section of the fourth semiconductor layer and separates the first section of the fifth semiconductor layer from the second section of the fifth semiconductor layer. In such embodiments, after the selective removal of the first section and the second section of the fifth semiconductor layer from the channel region of the fin structure, the metal gate further encloses the first section and the second section of the fourth semiconductor layer.In some embodiments, the method further comprises reducing the thickness of the fourth semiconductor layer before forming the metal gate and after selectively removing the first portion of the first semiconductor layer, the second portion of the first semiconductor layer, the first portion of the fifth semiconductor layer, and the second portion of the fifth semiconductor layer from the channel region of the fin structure. The thickness is less than a first spacing between the first portion of the second semiconductor layer and the first portion of the fourth semiconductor layer, and a second spacing between the second portion of the second semiconductor layer and the second portion of the fourth semiconductor layer.

Claims

[1] Component comprising: a channel arranged over a substrate (202), the channel comprising a first nanosheet (215A, 230-1, 215B), a second nanosheet (215A, 230-1, 215B) and a nanosheet connecting section (230-2) connecting the first nanosheet (215A, 230-1, 215B) and the second nanosheet (215A, 230-1, 215B), wherein: between the first nanosheet (215A, 230-1, 215B) and the second nanosheet (215A, 230-1, 215B) in a first direction which is essentially perpendicular to the substrate (202), a distance (h2) is present. the nanosheet connection section (230-2) has a thickness (s4) in a second direction which is essentially parallel to the substrate (202), and the thickness (s4) is less than the distance (h2); a first source / drain feature (270) and a second source / drain feature (270) arranged above the substrate (202), wherein the first nanosheet (215A, 230-1, 215B) and the second nanosheet (215A, 230-1, 215B) extend in a third direction from the first source / drain feature (270) and the second source / drain feature (270), the third direction being different from the first direction and the second direction; and a metal gate (296, 298) located between the first source / drain feature (270) and the second source / drain feature (270), wherein the metal gate (296, 298) encloses the channel. [2] Component according to claim 1, wherein the channel is connected to the substrate (202). [3] Component according to claim 1, wherein the channel is not connected to the substrate (202). [4] Component according to any one of the preceding claims 1 to 3, wherein the nanosheet connecting section (230-2) connects a first center of the first nanosheet (215A, 230-1, 215B) to a second center of the second nanosheet (215A, 230-1, 215B). [5] Component according to any one of the preceding claims 1 to 4, wherein the nanosheet connection section (230-2) connects a first edge of the first nanosheet (215A, 230-1, 215B) to a second edge of the second nanosheet (215A, 230-1, 215B). [6] Component according to any one of the preceding claims 1 to 5, wherein the channel further comprises a third nanosheet (215A, 230-1, 215B) which is not connected to the first nanosheet (215A, 230-1, 215B) and the second nanosheet (215A, 230-1, 215B). [7] Component according to any one of the preceding claims 1 to 6, wherein the nanosheet connection section (230-2) extends in the third direction from the first source / drain feature (270) to the second source / drain feature (270). [8] Component according to claim 1, wherein the first nanosheet (215A, 230-1, 215B) is a first horizontal segment, the second nanosheet (215A, 230-1, 215B) is a second horizontal segment, and the nanosheet connection section (230-2) is a vertical segment extending between the first horizontal segment and the second horizontal segment, wherein: the first horizontal segment and the second horizontal segment extend in the second direction, and the vertical segment extends in the first direction, which is different from the second direction, the channel extends in the third direction between the first source / drain feature (270) and the second source / drain feature (270). [9] Component according to claim 8, wherein the first horizontal segment and the vertical segment form a first T-channel and the second horizontal segment forms a section of a second T-channel, wherein the first T-channel is arranged above the second T-channel. [10] Component according to claim 9, wherein the vertical segment is a first vertical segment and the channel further comprises a second vertical segment extending between the second horizontal segment and the substrate (202) and connecting them together, wherein the second vertical segment extends in the second direction and the second vertical segment forms a section of the second T-channel. [11] Component according to any one of the preceding claims 8 to 10, wherein the first horizontal segment, the second horizontal segment and the vertical segment form an H-shaped channel suspended above and separated from the substrate (202). [12] Component according to claim 11, wherein the channel is a first channel layer and the component further comprises a second channel layer arranged vertically between the H-shaped channel and the substrate (202), wherein the second channel layer comprises a third horizontal segment suspended above and separated from the substrate (202). [13] Component according to claim 12, wherein the third horizontal segment is different from the first horizontal segment and the second horizontal segment. [14] Component according to any one of the preceding claims 8 to 13, wherein: the first horizontal segment, the second horizontal segment, and the vertical segment form an H-shaped channel; and the vertical segment is a first vertical segment and the channel further comprises a second vertical segment which extends between the second horizontal segment and the substrate (202) and connects them, and the second vertical segment extends in the second direction. [15] Component according to claim 14, wherein the channel is a first channel layer and the component further comprises a second channel layer, wherein the H-shaped channel is arranged vertically between the second channel layer and the substrate (202) and wherein the second channel layer further comprises a third horizontal segment suspended above and separated from the substrate (202). [16] Component according to claim 15, wherein the third horizontal segment is different from the first horizontal segment and the second horizontal segment. [17] Component according to any one of the preceding claims 8 to 16, wherein: the vertical segment is a first vertical segment; the channel further comprises a third horizontal segment and a second vertical segment, the second vertical segment extending between and connecting the second horizontal segment and the third horizontal segment; and The first horizontal segment, the second horizontal segment, the third horizontal segment, the first vertical segment and the second vertical segment form an E-shaped channel. [18] Component according to claim 17, wherein the channel further comprises a third vertical segment extending between the third horizontal segment and the substrate (202) and connecting them together. [19] Methods, comprising: Forming a semiconductor layer stack (205) over a substrate (202), wherein the semiconductor layer stack (205) comprises first semiconductor layers (215) and second semiconductor layers (210) stacked vertically in an alternating configuration; Forming a semiconductor strand (230') extending from a first of the first semiconductor layers (215) through one of the second semiconductor layers (210) to a second of the first semiconductor layers (215), wherein the semiconductor strand (230') has a first width (w1); Structuring the semiconductor layer stack (205) to form a fin structure (235) extending from the substrate (202), wherein the fin structure (235) comprises the semiconductor strand (230'), a section of the first of the first semiconductor layers (215), a section of one of the second semiconductor layers (210) and a section of the second of the first semiconductor layers (215); selective removal of the section of one of the second semiconductor layers (210) such that the first of the first semiconductor layers (215) is separated in a first direction by a distance (h2) from the second of the first semiconductor layers (15) and the semiconductor strand (230') extends in the first direction between the first of the first semiconductor layers (215) and the second of the first semiconductor layers (215) and connects them together; and Trimming the semiconductor strand (230') to reduce the first width (w1) to a second width (s4), wherein the first width (w1) and the second width (s4) are in a second direction different from the first direction, wherein the first width (w1) is greater than the distance (h2) and the second width (s4) is less than the distance (h2). [20] Method according to claim 19, wherein the formation of the semiconductor strand (230') extending from the first of the first semiconductor layers (215) through one of the second semiconductor layers (210) to the second of the first semiconductor layers (215) comprises: Performing an extreme ultraviolet (EUV) lithography process to form an EUV mask over the semiconductor layer stack (205); Etching a trench using the EUV mask as the etching mask, wherein the trench extends through the first of the first semiconductor layers (215), one of the second semiconductor layers (210), and the second of the first semiconductor layers (215); and Filling the trench with a semiconductor material.

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