Package with overhang inductance and method and device using this

Abstract

Component-On-Top (CoP) package that includes: a system-in-package (SIP) comprising regulator circuitry, the SIP having a top portion and a first side portion; and an inductor on the upper part of the SIP, the inductor having first and second terminals, each located a certain distance within a periphery formed by the ends of the inductor, the first and second terminals extending from a bottom of the inductor, the first and second terminals being physically connected directly to the upper portion of the SIP to form an empty space region between the bottom of the inductor and the upper portion of the SIP, the empty space region having a width corresponding to a distance between the first and second terminals and a height corresponding to a length of the first and second terminals, the SIP being a first separate component and the inductor being a second separate component, wherein: the inductance is coupled to the regulator circuitry via the upper part of the SIP; and the periphery formed by the ends of the inductor extends beyond a periphery of the SIP.

Description

FIELD OF DISCLOSUREThis document relates generally to a component-on-top (component-up)(CoP) package regulator device.BACKGROUNDTypical systems provide regulators, such as DC / DC regulators, using discrete physical components coupled together on a printed circuit board. Variations among these discrete components are typically accounted for using various passive components that introduce noise and inefficiencies and consume board space. As a result, combining all of these discrete components on a circuit board to provide voltage regulators limits system diversity and performance reliability, increases manufacturing complexity and cost, and consumes a large amount of physical board space.US 9 111 954 B2 relates, according to the abstract, to a power conversion module comprising a circuit carrier plate, a semiconductor module and an inductor module. The circuit carrier plate has a plurality of bonding pads. The semiconductor module is located on a first surface of the circuit carrier plate. The inductor module includes a plurality of pins extending along a first direction thereof and connected to respective bonding pads of the circuit carrier plate, such that a space is created between the inductor module and the circuit carrier plate in which the semiconductor module can be housed.US 2014 / 0218155 A1, in summary, relates to an embedded printed circuit board module (PCB) for packaging and mounting a flat power conversion system that can be used in limited-space environments of small computer and electronic systems. The module includes an embedded circuit board, a power semiconductor device embedded within the circuit board, a magnetic component either embedded in or disposed on the circuit board, and input and output terminals on the sides of the embedded circuit board. The components are designed in a flat plate-like shape in order to save vertical space. The module can additionally be integrated into a recess of the system printed circuit board in order to save even more vertical space.SUMMARY OF THE DISCLOSUREThe disclosure describes techniques for providing a regulator circuit using a CoP package (or CoP package). The CoP package includes: a system in package (SIP) including regulator circuitry, the SIP including a top portion and a first side portion; and an inductor on the top portion of the SIP, wherein: the inductor is coupled to the regulator circuitry via the top portion of the SIP; and a first end of the inductor extends beyond the first side portion of the SIP.In some implementations, the inductance and regulator circuitry of the SIP together implement a switching regulator.In some implementations, the regulator circuitry includes switching circuitry for charging and discharging the inductor.In some implementations, the inductor provides a charge to a load coupled to the CoP package.In some implementations, a second end of the inductor extends beyond the second side portion of the SIP. In some implementations, the second end of the inductor is parallel or perpendicular to the first end of the inductor. In some implementations, the second end of the inductor is parallel to the second side portion of the SIP.In some implementations, the SIP has four sides, and wherein the respective ends of the inductance extend beyond each of the four sides of the SIP.In some implementations, the inductor includes first and second terminals, the first and second terminals extending vertically from a lower portion of the inductor through the upper portion of the SIP down to the regulator circuitry. In some implementations, the first terminal is at a first position on the lower portion of the inductor, the first position being a predetermined distance from the first end of the inductor, and the first position overlapping with the upper portion of the SIP.In some implementations, the SIP is coupled to a circuit board, wherein a passive or active component external to the SIP is coupled to the SIP via the circuit board, wherein at least a portion of the passive or active component is physically located within a region between the first end of the inductor and the first side of the SIP. In some implementations, the passive or active component includes another SIP, a resistor, a capacitor, an integrated passive device, a transistor, or an inductor.In some implementations, the SIP is coupled to a circuit board, wherein a plurality of passive or active components external to the SIP is coupled to the SIP via the circuit board, wherein at least a portion of the plurality of passive or active components is physically placed around a periphery of the SIP within a region between ends of the inductance and sides of the periphery of the SIP.In some implementations, a void space region is formed between a bottom of the inductor and the top of the SIP.In some implementations, the disclosure performs operations including: generating, by regulator circuitry implemented on a system in package (SIP), a regulated voltage signal, the SIP having a top portion and a first side portion, the SIP coupled to an inductor via the top portion of the SIP, and a first end of the inductor extending beyond the first side portion of the SIP; and supplying the regulated voltage to a load.This summary is intended to provide an overview of the subject matter of the present patent application. It is not intended to provide an exclusive or exhaustive explanation of the subject matter of the invention. The detailed description is incorporated to provide further information about the present patent application.BRIEF DESCRIPTION OF THE DRAWINGSIn the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals with different letter additions may represent different instances of similar components. The drawings generally illustrate various embodiments discussed herein by way of example and not limitation. FIG. 1 is a block diagram of an example of a CoP package regulator device according to various embodiments. FIG. 2 is a block diagram of an example of a switching regulator implemented by the CoP package according to various embodiments. FIG. 3 is a block diagram of an example of a physical layout of the CoP package regulator device according to various embodiments. FIG. 4 is a block diagram of an example of a side view of the physical layout of the CoP package regulator device according to various embodiments. FIG. 5 is a block diagram of an example of a top view of the physical layout of the CoP package regulator device according to various embodiments. FIG. 6 is a block diagram illustrating an example of a machine on which one or more embodiments may be implemented.DETAILED DESCRIPTIONA system-in-package (SIP) or a system-in-a-package is a physical component manufactured with a number of integrated circuits enclosed in a single module (package). These including integrated circuits may be vertically stacked on a substrate. They are internally connected by fine wires bonded to the package. Alternatively, flip chip technology uses solder bumps to join stacked chips. SIP dies can be vertically stacked or horizontally tiled, unlike less dense multichip modules that stack dies horizontally on a carrier. This means that a complete functional unit can be built in a multi-chip package, so that fewer external components are used to fabricate the functional working unit.A CoP package (or package-on-package PoP (package-on-package)) is an integrated circuit packaging method for combining vertically discrete logic and ball grid array (BGA) packages, such as two or more SIP packages. Two or more packages are installed on top of each other, e.g. stacked, with a standard interface for carrying signals between them. This allows for higher component density in devices such as mobile phones, personal digital assistants (PDAs), and digital cameras, at the expense of somewhat higher height requirements.The size of the footprint of a printed circuit board (PCB) and the power output of a regulator (e.g., a DC / DC switching regulator) are typically taken into account in the manufacture of regulators. A larger size regulator may have a higher power output, but may occupy a larger area on the PCB. Certain systems employ CoP packages to construct some components of the regulator in one package that is stacked on another package. The physical size of the PCB in these systems is dictated by the top package because the bottom package is designed to be the same size or larger than the top package. As an example, in these systems, the amount of PCB space is determined by the magnitude of the inductance (on top or bottom).Some typical systems rely on a higher switching frequency for the DC / DC regulator to reduce the physical footprint of the regulator on the PCB. However, such methods often result in lower operating efficiency, higher power loss, and an increase in transition temperature. Namely, efficiency and thermal performance are sacrificed to achieve a smaller PCB footprint by the controller.The disclosure describes, among other things, techniques for providing a regulator, such as a DC / DC regulator, using a CoP package in which the inductance physically overhangs the regulator package thereunder. In particular, the disclosure provides a CoP package that provides a SIP package with regulator circuitry and inductance. The SIP has an upper portion and a first side portion, and an inductor on the upper portion of the SIP is coupled to the regulator circuitry via the upper portion of the SIP. The inductor has a first end that extends beyond the first side portion of the SIP. In this way, the physical footprint occupied by the regulator circuitry on the bottom side of the CoP package is not limited by the amount of inductance on the top side of the package. This allows a smaller footprint to be occupied by the regulator on the PCB, and increases the efficiency and thermal performance of the regulator relative to systems that increase the switching frequency of the regulator to occupy a footprint of similar size.FIG. 1 is a block diagram of an example of a component on top package regulator device 100, according to various embodiments. The component-on-top package regulator device 100 includes SIP regulator circuitry 110 and an inductor 120. Although the SIP circuitry 110 is shown as implemented in the component on top package regulator device 100, any other type of amplifier, digital-to-analog converter, radio frequency transmitter / receiver, or other device may be used instead of or in addition to the SIP regulator circuitry 110.The component-on-top package regulator device 100 also includes an integrated passive component network (not shown) (e.g., an integrated passive resistor and capacitor network) coupled within the component-on-top package regulator device 100 or external to the component-on-top package regulator device 100. One or more external passive or active components, such as capacitors, inductors, resistors, transistors, and so forth, are coupled to the component on top package regulator device 100 to adjust parameters of the SIP regulator circuitry 110.The component-on-top package regulator device 100 receives an analog signal 112, which may be a differential signal or a single signal. The analog signal 112 may be an AC or DC signal. Although only one differential or single analog signal 112 is shown in FIG. 1, any number of additional differential or single input signals may be received and processed in parallel by the component-on-top package regulator device 100. The component-on-top package regulator device 100 processes the analog signal 112 to generate an output signal 132, such as a regulated DC voltage, that is stepped up or stepped down relative to the analog signal 112.Each component of the SIP regulator circuitry 110 may be implemented and manufactured together on the same system-in-package and bonded to the SIP with one or more wires. The system-in-package may be a land grid array (LGA), a ball grid array (BGA), or a pin grid array (PGA) package. The inductor 120 may be fabricated together with the SIP regulator circuitry 110 or separately from the SIP regulator circuitry 110. The inductor 120 is physically connected to the SIP regulator circuitry 110 from an upper portion of the SIP regulator circuitry 110 to form the component on top package regulator device 100.In some implementations, a first portion of the components implemented on the SIP regulator circuitry 110 and / or the component on top package regulator device 100 may be fabricated using a first fabrication process (e.g., low voltage MOS, high voltage MOS, low voltage DMOS, high voltage DMOS, low voltage bipolar, high voltage bipolar, high speed bipolar, BiCMOS, JFET, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, gallium nitride on silicon carbide, gallium nitride on silicon, or silicon on insulator). A second portion of the components implemented on the SIP regulator circuitry 110 and / or the component on top package regulator device 100 may be fabricated using a second manufacturing process (e.g., low voltage MOS, high voltage MOS, low voltage DMOS, high voltage DMOS, low voltage bipolar, high voltage bipolar, high speed bipolar, BiCMOS, JFET, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, gallium nitride on silicon carbide, gallium nitride on silicon or silicon on insulator) different from the first manufacturing process. For example, SIP regulator circuitry 110 may be implemented with low voltage JFET devices and the inductor 120 may be implemented by a discrete passive or active physical component.The components in the SIP regulator circuitry 110 and / or the component on top package regulator device 100 may be coupled through the series of integrated passive devices (resistors and capacitors) by way of one or more wires bonded to or within the SIP. These integrated passive devices may be fabricated using standard wafer fabrication techniques such as thin film and photolithography processing. The substrates for the integrated passive devices may be thin film substrates such as silicon, aluminum oxide, or glass. For example, the integrated passive resistors may be made of high-accuracy thin-film silicon chromium (SiCr). The integrated passive capacitors may be made of metal-insulator-metal (MIM) capacitors.Using such integrated passive devices (components) (i Devices) provides a technological improvement over conventional systems using discrete passive components. In particular, implementing integrated passive devices in SIP regulator circuitry 110 and / or component on top package regulator device 100 enables superior performance over that obtained with discrete passive components, and the piece-to-piece variations in integrated passive devices are lower than those in discrete passive components typically used on a printed circuit board to implement a conventional regulator.FIG. 2 is a block diagram of an example of a switching regulator implemented by the component-on-top package regulator device 100, according to various embodiments. As an example, the component-on-top package regulator device 100 implements a single-input multiple-output (SIMO) switching regulator.The component-on-top package regulator device 100 may be a current mode (CM) switching DC / DC power supply, also known as a current mode DC / DC converter. Many other transducer configurations may also benefit from the present disclosure. The type of converter shown in FIG. 2 is a peak current mode converter. An overview of the functionality of the switching regulator shown in FIG. 2 is provided below and further details are provided in U.S. Pat. No. 5,617,015 A, filed Jun. 7, 1995, which is hereby incorporated by reference in its entirety.During operation, control circuitry (not shown) included in the component on top package regulator device 100 (e.g., as part of the SIP regulator circuitry 110) switches common loop switches 132A-C (S 1, S 2, and S 3, respectively) of the switching regulator ON and OFF based on common loop signals at a particular frequency to control current flowing to negative channels 133 (Vnegk.. Vneg1) and positive channels 134 (Vposii... Vpos1) flows. The control circuitry also switches differential loop switches (Snk... SN1 and Spi... Sp1) based on differential loop signals ON and OFF to control a current flowing to individual positive and negative channels.In one example, when the control circuitry turns ON the common loop switches 132A and 132C, an input voltage Vin (e.g., analog signal 112) is applied through the common loop switch 132A (S 1) to an inductor 120 and causes a ramp current to flow through the inductor 120 in one phase. This current flows through a current sensor 135 (e.g., current sensing circuitry). In another phase, the current flows from the inductor 120 (which may not be the same ramp current as in the previous phase) through each of the negative channels 133 coupled to one terminal of the inductor 120 and through each of the positive channels 134 coupled to another terminal of the inductor 120. The control circuitry controls which individual ones of the positive and negative channels receive the current flowing through the inductor 120 by having respective ones of the differential loop switches (Snk... Sn1 and Spi... Sp1) can be turned ON and OFF.The inductor 120 may be implemented by an upper component of the component on top package regulator device 100, and the remaining circuit components shown in FIG. 2 may be implemented by a lower component of the component on top package regulator device 100. In some cases, the inductor 120 and a first set of other elements shown in FIG. 2 may be implemented by the upper component of the component on top package regulator device 100, and the remaining second set of elements may be implemented by the lower component of the component on top package regulator device 100. In some cases, the inductor 120 may be implemented by an upper component of the component-on-top package regulator device 100, a first set of the remaining circuit components shown in FIG. 2 may be implemented by a lower component of the component-on-top package regulator device 100, and a second set of the remaining circuit components shown in FIG. 2 may be implemented off-chip and external to the component of the component-on-top package regulator device 100.In some cases, the second set of remaining circuit components may be at least partially or completely covered by one or more sides of the inductor 120. For example, a side of the inductor 120 overhangs on a second or upper level of the component of the component on top package regulator device 100 and extends beyond a side of the lower component on a first or lower level of the component on top package regulator device 100. This physical arrangement creates a physical empty space between the lower component side and the inductance 120 side. One or more passive or active circuit elements (e.g., resistors, capacitors, transistors, integrated passive components, inductors, and so forth) may be placed at least partially within the physical void space at the same level or levels as the lower component of the component of the component on top package regulator device 100.The control circuitry receives the voltage outputs from each of the positive and negative channels. Based on a comparison of the voltages to a reference voltage, the control circuitry determines when the common loop switches 132A-C are turned ON or OFF. In one embodiment, the control circuitry calculates a sum of all positive channel voltages (Vposi... Vpos1) and also calculates a sum of all the negative channel voltages (Vnegk.. Vneg1). The control circuitry calculates a difference between the sums of the positive and negative voltages and applies this difference to the negative input of a transconductance error amplifier (not shown). A reference voltage Vref is applied to the positive input of the transconductance error amplifier. The output current of the transconductance error amplifier corresponds to the difference between the average actual output voltage across all channels and the desired output voltage. A voltage across a capacitor at the output of the transconductance error amplifier is adjusted up or down based on the positive or negative current output of the transconductance error amplifier. Such a voltage is referred to as a control voltage Vcomp.The control voltage Vcomp is applied to a pulse width modulation (PWM) comparator (also referred to as a current comparator) (not shown). The ramp voltage across the current sensing circuitry, when the common loop switch 132A is turned ON, is sensed by a differential amplifier in the current sensor 135 with a certain gain factor, and when the output of the amplifier in the current sensor 135 exceeds the control voltage Vcomp, the PWM comparator is triggered to output a signal in the control circuitry. The control circuitry logically combines this signal with a clock signal received by the control circuitry to turn the common loop switch 132A on or off and to control companion switches 132B and 132C. In one embodiment, the control companion switches 132B and 132C are companion switches for the common loop switch 132A and turn ON and OFF at the same time when the switch 132A is turned ON and OFF. In one embodiment, control companion switches 132B and / or 132C are turned OFF when common loop switch 132A is turned ON. For example, when the common loop switch 132A turns OFF, the control companion switch 132B turns ON to discharge the inductor 120, causing a ramp-down current. In this manner, the peak current through inductor 120 is controlled for each cycle to provide the required average current to provide a controlled output voltage at each positive and negative channel. An example of when certain of the common loop switches 132A-C and differential loop switches are turned ON and OFF based on an output of the PWM comparator associated with each loop is provided in U.S. Pat. No. 9,479,052, filed Mar. 13, 2015, which is hereby incorporated by reference in its entirety.FIG. 3 is a block diagram of an example physical layout 300 of the component on top package regulator device (e.g., the component on top package regulator device 100 (FIG. 1 )) in accordance with various embodiments. As shown in physical layout 300, an inductor 310 (corresponding to inductor 120) is physically placed on another component 320 (corresponding to SIP regulator circuitry 110). The component 320 may be referred to as a lower component or first layer / plane component placed on a PCB, and the inductor 310 may be referred to as the upper component or second layer / plane component placed on the first layer / plane component 320.The inductor 310 has a first side 314 and a bottom portion 316. The component 320 may include an upper portion 322. The first side 314 of the inductor 310 extends beyond an end or side of the component 320. As a result, the inductor 310 has an empty space region between the bottom part 316 and the PCB on which the component 320 is placed. Although two sides of the inductor 310 are shown as extending beyond respective sides of the component 320, any number of sides of the inductor 310 may extend beyond respective sides of the component 320. For example, only one side of the inductor 310 may extend beyond only one side of the component 320, while another side of the inductor 310 may be adjacent to another respective side of the component 320. In some cases, all four sides of the inductor 310 (which may be a rectangle) may extend beyond a perimeter of the component 320.The inductor 310 has a first terminal 330A and a second terminal 330B. The first terminal 330A may extend vertically down from a middle or non-end or non-lateral portion of the inductor 310. In particular, the first terminal 330A may extend from a first position that is a threshold or a predetermined distance from a side of the inductor 310 toward the center of the inductor 310. Likewise, the second terminal 330B may extend vertically downward from an opposing central or non-one-end or non-lateral portion of the inductor 310. In particular, the second terminal 330B may extend from a second position that is a threshold or a predetermined distance away from an opposite side of the inductor 310 toward the center of the inductor 310. The first and second terminals 330A and 330B may be evenly or non-uniformly spaced or positioned relative to the center of the inductor 310. The first terminal 330A extends vertically through the component 320 to couple the inductor 310 to a first portion of the circuitry implemented by the component 320. The second terminal 330B extends vertically through the component 320 to couple the inductor 310 to a second portion of the circuitry implemented by the component 320.FIG. 4 is a block diagram of an example of a side view 400 of the component-on-top package regulator device (e.g., the component-on-top package regulator device 100 (FIG. 1 )) implemented in accordance with various embodiments. As shown in side view 400, the inductor (e.g., inductor 310) has a length 410 (e.g., 4 millimeters to 8 millimeters). The component 320 (below the inductance 310) may have a width 413 of 3 millimeters to 9 millimeters. As an example, the length 410 of the inductor 310 may be 8 millimeters while the width of the component 320 is 3 millimeters. In this example, the inductance 310 may extend beyond the component 320 on either side thereof by an amount 440 (e.g., 2.5 millimeters).A height of the leads or terminals 330A and 330B of the inductor 310 may be selected or adjusted to control the transition gap 411 from the bottom of the inductor 310 to the top of the component 320 (e.g., how much empty space exists between a bottom of the inductor 310 and a top of the component 320). By creating longer leads or terminals 330A and 330B, a greater amount of empty space may be provided between the inductor 310 and the component 320, thereby allowing the component 320 to dissipate a greater amount of heat. In this way, instead of increasing the potting thickness of component 320 as a way to dissipate heat, potting thickness 416 may remain small and heat may be dissipated through inductor 310 in high airflow or liquid immersion applications. Namely, the increased space between the inductor and the molded package allows for greater heat dissipation in such applications. Alternatively, shorter leads or terminals 330A and 330B of inductor 310 may be used to bring inductor 310 closer to component 320 to serve as a heat sink for component 320.In one example, the height 414 represents the overhang gap from the bottom of the inductor 310 to the top of the PCB on which the component 320 is placed, and may be 1.5 millimeters to 2.7 millimeters. The height 412 represents the overall height of the CoP package regulator device and may be 4 millimeters to 10 millimeters.In some implementations, one or more active and / or passive components 419 and 418 may be coupled to the CoP package regulator device and external to the CoP package regulator device. These components 419 and 418 may be coupled to the PCB on the same layer as the component 320. The component 419 may be completely covered or covered by the inductor 310 (e.g., the area within the amount 440 for which the inductor 310 extends beyond sides of the component 320), while the component 418 is partially covered or covered by the inductor 310. Height 420 is the overhang gap from below inductor 310 to the top of components 419 and 418.FIG. 5 is a block diagram of an example of a top view 500 of the component on top package regulator device (e.g., the component on top package regulator device 100 (FIG. 1 )) is implemented in accordance with various embodiments. As shown in plan view 500, inductor 310 has a width 520 (e.g., 4 millimeters to 8 millimeters) that extends beyond a length 530 of component 320 (e.g., 2 millimeters to 6.25 millimeters). The inductor 310 has four sides that extend beyond the periphery of the component 320. A first component 544 (e.g., an active or passive capacitor or resistor) may be placed in an area that is fully covered or below one of the sides of the inductor 310 that extends beyond a side of the component 320. A second component 540 (e.g., an active or passive capacitor or resistor) may be placed in an area that is partially covered or below a second one of the sides of the inductor 310 that extends beyond a second side of the component 320. A third component 542 (e.g., an active or passive capacitor or resistor) may be placed in an area that is outside the area of the inductor 310 that extends beyond a side of the component 320. Each of the first, second, and third components 540, 542, and 544 may be a component external to the CoP package regulator device, which is coupled to the CoP package regulator device through a PCB on which the CoP package regulator device is placed.FIG. 6 illustrates a block diagram of an example machine 600 upon which any one or more of the techniques (e.g., methodologies) discussed herein may be performed. In alternative embodiments, machine 600 may operate as a stand-alone device or may be connected (e.g., networked) to other machines. In a networked environment, the machine 600 may operate as a server machine, a client machine, or both in server-client network environments. In one example, machine 600 may act as a peer machine in a peer-to-peer (P2P) network environment (or other distributed network environment). The machine 600 may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a web appliance, an loT device, an automotive system, an aerospace system, or any machine capable of executing instructions (sequential or otherwise) that specify the actions to be taken by that machine. Further, although only a single machine is illustrated, the term "machine" is also intended to be inclusive of any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any of the methodologies discussed herein, such as cloud computing, software as a service (SaaS), other computer cluster configurations.Examples as described herein may include or operate through logic, components, devices, packages, or mechanisms. Circuitry is a collection (e.g., a set) of circuits implemented in tangible entities that include hardware (e.g., simple circuits, gates, logic, etc.). Circuitry membership may be flexible over time and have underlying hardware variability. Circuit arrangements include elements that, alone or in combination, can perform specific tasks when operating. In one example, hardware of the circuitry may be invariably configured to perform a particular operation (e.g., hardwired). In one example, the hardware of the circuitry may include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.) including a computer readable medium that is physically (e.g., magnetically, electrically, modified by movable placement of invariant mass particles, etc.) to encode instructions of the particular operation. When connecting the physical components, the underlying electrical properties of a hardware component are changed, for example from an insulator to a conductor or vice versa. The instructions enable involved hardware (e.g., execution units or a load mechanism) to create elements of the circuitry in hardware via the variable connections to execute portions of the particular tasks when in operation. Accordingly, the computer readable medium is communicatively coupled to the other components of the circuitry when the device is operating. In one example, any of the physical components may be used in more than one element of more than one circuitry. For example, in operation, execution units in a first circuit of a first circuit arrangement may be used at one time and reused at another time by a second circuit in the first circuit arrangement or by a third circuit in a second circuit arrangement.The machine (e.g., computer system) 600 may include a hardware processor 602 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof), a main memory 604, and a static memory 606, a portion or all of which may communicate with each other via a link (e.g., a bus) 608. The machine 600 may further include a display unit 610, an alphanumeric input device 612 (e.g., a keyboard), and a user interface (UI) navigation device 614 (e.g., a mouse). In an example, the display unit 610, the input device 612, and the UI navigation 614 may be a touch screen display. The machine 600 may additionally include: a storage device (e.g., a drive unit); a signal generation device 618 (e.g., a speaker); a network interface device 620; one or more sensors 616, such as a global positioning system (GPS) sensor, wing sensors, mechanical device sensors, temperature sensors, ICP sensors, bridge sensors, audio sensors, industrial sensors, compass, accelerometer, or other sensors. The machine 600 may include an output controller 628, such as a serial (e.g., Universal Serial Bus (USB)), parallel or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) In some embodiments, the connection may include a connection for communicating with or controlling one or more peripheral devices (e.g., a printer, a card reader, etc.).The storage device may include a machine-readable medium 622 having stored thereon one or more sets of data structures and instructions 624 (e.g., software) that perform or are utilized by any one or more of the techniques or functions described herein. The instructions 624 may also reside, completely or at least partially, within the main memory 604, within the static memory 606, or within the hardware processor 602 during execution thereof by the machine 600. In an example, one or any combination of the hardware processor 602, the main memory 604, the static memory 606, or the storage device 621 may represent the machine readable medium 622.Although machine-readable medium 622 is illustrated as a single medium, the term "machine-readable medium" may include a single medium or multiple media (e.g., a centralized or distributed database or associated caches and servers) configured to store the one or more instructions 624.The term "machine-readable medium" may include any transitory or non-transitory medium capable of storing, encoding, or carrying transitory or non-transitory instructions for execution by the machine 600, and causing the machine 600 to perform any one or more of the techniques of the present disclosure, or capable of storing, encoding, or carrying data structures used by or associated with such instructions. Non-limiting examples of a machine readable medium include solid state memories and optical and magnetic media. In one example, a mass-laden machine-readable medium includes a multi-particle machine-readable medium having an invariant (e.g., quiescent) mass. Accordingly, ground-type machine-readable media are non-transitory propagating signals. Specific examples of mass-ground machine readable media include non-volatile memory such as semiconductor memory devices (e.g., electrically programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), and flash memory devices; magnetic disks such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.The instructions 624 (e.g., software, programs, an operating system (OS), etc.) or other data are stored on the storage device 621 and can be accessed by the main memory 604 for use by the hardware processor 602. Main memory 604 (e.g., DRAM) is typically fast, but volatile, and accordingly some other type of storage than storage device 621 (e.g., an SSD) suitable for long-term storage, including when in an "off" state. The instructions 624 or data used by a user or machine 600 are typically loaded into the main memory 604 for use by the hardware processor 602. When main memory 604 is full, virtual memory may be allocated by storage device 621 to supplement main memory 604; however, because storage device 621 is typically slower than main memory 604 and write speeds are typically at least twice as slow as read speeds, the use of virtual memory may greatly reduce a user experience due to storage device latency (as opposed to main memory 604, e.g., DRAM). Further, the use of the virtual storage device 621 can greatly reduce the useful life of the storage device 621.The instructions 624 may further be transmitted or received over a communication network 626 using a transmission medium via the network interface device 620 utilizing any of a number of transfer protocols (e.g., frame relay, internet protocol (IP), transmission control protocol (TCP), user datagram protocol (UPD), hypertext transfer protocol (HTTP), etc.). Exemplary communication networks may include, but are not limited to, a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), cellular telephone networks (e.g., cellular networks, plain old telephone service (POTS) networks, wireless data networks (e.g., 802.11 family of Institute of Electrical and Electronics Engineers (IEEE) standards known as Wi-Fi® 802.16 family of IEEE standards known as WiMax® ), Networks of the 802.15.4 family of IEEE standards and peer-to-peer (P2P) networks include. In an example, network interface device 620 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas for connecting to communication network 626. In an example, the network interface device 620 may include multiple antennas for wirelessly communicating using a single-input multiple-output (SIMO), a multiple-input multiple-output (MIMO), or a multiple-input single-output (MISO) technique. The term "transmission medium" is intended to include any tangible or non-tangible medium that is capable of storing, encoding, or carrying instructions for execution by the machine 600, and includes digital or analog communication signals or other tangible or non-tangible media to enable communication of such software.Various AnnotationsEach / each of the non-limiting aspects or examples described herein may stand alone or may be combined with one or more of the other examples in various permutations or combinations.The above detailed description has references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the subject matter of the invention may be practiced. These embodiments are also referred to herein as "examples.". Such examples may include elements in addition to those shown or described. However, the inventors of the present invention also intend examples in which only those elements shown or described are provided. In addition, the inventors of the present invention also intend examples that use any combination or permutation of those elements shown or described (or one or more aspects thereof), either with respect to a particular example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein.In the case of inconsistent uses between this document and any other documents incorporated by reference, the use applies in this document.In this document, the terms "a", "an" or "an" are used as common in patent documents to include one / one / one / more than one / one, irrespective of any other instances or uses of "at least one / one" or "one / more". In this document, the term "or" is used to refer to a non-exclusive "or" such that "A or B", "A but not B", "B but not A", and "A and B" include, unless otherwise indicated. In this document, the terms "including" and "in which" are used as the equivalents of the respective terms "comprising" and "wherein" are used in a simple language. Moreover, the terms "including" and "comprising" in the following claims are open ended terms; that is, a system, apparatus, article, composition, formulation, or process comprising elements / s in addition to those listed after such term in a claim is still considered to fall within the scope of this claim. Moreover, in the following claims, the terms "first", "second", "third", etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.Method examples described herein may be at least partially machine- or computer-implemented. Some examples may include a computer readable medium or a machine readable medium encoded with transitory or non-transitory instructions operable to configure an electronic device to perform methods as described in the above examples. An implementation of such methods may include code such as microcode, assembly language code, high-level language code, or the like. Such code may include transitory or non-transitory computer readable instructions for performing various methods. The code may form parts of computer program products. Further, in one example, the code may be tangibly stored on one or more transitory, non-transitory, or non-transitory tangible computer readable media, such as during execution or at other times. Examples of these tangible computer readable media can include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or sticks, random access memories (RAMs), read only memories (ROMs), and the like.In one aspect, this disclosure describes techniques for providing a regulator circuit using a component-on-top (CoP) package. The CoP package includes: a system in package (SIP) including regulator circuitry, the SIP including a top portion and a first side portion; and an inductor on the top portion of the SIP, wherein: the inductor is coupled to the regulator circuitry via the top portion of the SIP; and a first end of the inductor extends beyond the first side portion of the SIP.

Claims

A component on top (CoP) package, comprising: a system in package (SIP) comprising regulator circuitry, the SIP comprising a top portion and a first side portion; and an inductor on the top portion of the SIP, the inductor comprising first and second terminals each located a certain distance within a periphery formed by the ends of the inductor, the first and second terminals extending from a bottom surface of the inductor, the first and second terminals being physically connected directly to the top portion of the SIP to form an empty space region between the bottom surface of the inductor and the top portion of the SIP, wherein the void space region has a width corresponding to a distance between the first and second terminals and a height corresponding to a length of the first and second terminals, wherein the SIP is a first separate component and the inductance is a second separate component, wherein: the inductance is coupled to the regulator circuitry via the top portion of the SIP; and the periphery formed by the ends of the inductance extends beyond a periphery of the SIP.The CoP package of claim 1, wherein the inductor and the regulator circuitry of the SIP together implement a switching regulator, wherein the first and second terminals extend vertically from the bottom of the inductor.The CoP package of claim 1 or 2, wherein the regulator circuitry comprises switching circuitry for charging and discharging the inductor, wherein the SIP comprises a ball grid array package.The CoP package of any preceding claim, wherein a first portion of the SIP is manufactured using a first manufacturing process, and wherein a second portion of the SIP is manufactured using a second manufacturing process different from the first manufacturing process.The CoP package of any preceding claim, wherein the components on the SIP are bonded together by a series of integrated passive devices manufactured using thin film or photolithography techniques.The CoP package of any preceding claim, wherein the heat is dissipated by the inductor across the void space region in a liquid dipping application.The CoP package of any preceding claim, wherein the heat dissipation is controlled based on the size of the void space area determined by the length of the first and second terminals.The CoP package of any preceding claim, wherein the first and second terminals are unequally spaced relative to a center of the inductance.The CoP package of any preceding claim, wherein the first terminal is at a first distance from the center of the inductor and the second terminal is at a second distance from the center, wherein the first distance is greater than the second distance.The CoP package of claim 9, wherein the first terminal is at a first position on the lower portion of the inductor, the first position being a predetermined distance from a first end of the inductor, and the first position overlapping with the upper portion of the SIP.The CoP package of any preceding claim, wherein the SIP is coupled to a printed circuit board.The CoP package of claim 11, wherein a passive or active component on the circuit board comprises another SIP, a resistor, a capacitor, an integrated passive device, a transistor, or an inductor.The CoP package of any preceding claim, wherein at least a portion of a plurality of passive or active components is physically placed around a periphery of the SIP within a region between ends of the inductance and sides of the periphery of the SIP.A method, comprising: generating, by regulator circuitry implemented on a system in package (SIP), a regulated voltage signal, the SIP having a top portion and a first side portion, the SIP coupled to an inductor via the top portion of the SIP, the inductor having first and second terminals each located within a certain distance within a periphery formed by the ends of the inductor, the first and second terminals extending from a bottom surface of the inductor, the first and second terminals being physically directly connected to the top portion of the SIP to form an empty space region between the bottom surface of the inductor and the top portion of the SIP, wherein the void space region has a width corresponding to a distance between the first and second terminals and a height corresponding to a length of the first and second terminals, wherein the SIP is a first discrete component and the inductance is a second discrete component and the periphery formed by the ends of the inductance extends beyond a periphery of the SIP; and supplying the regulated voltage to a load.The method of claim 14, wherein the heat dissipation is controlled based on the size of the void space area determined by the length of the first and second ports.The method of claim 14 or 15, wherein the inductance and regulator circuitry of the SIP together implement a switching regulator.The method of any of claims 14 to 16, wherein the regulator circuitry comprises switching circuitry for charging and discharging the inductor.The method of any of claims 14 to 17, wherein a second end of the inductor extends beyond the second side portion of the SIP.An apparatus, comprising: means for generating a regulated voltage signal by regulator circuitry implemented on a system in package (SIP), the SIP having an upper portion and a first side portion, the SIP coupled to an inductor via the upper portion of the SIP, the inductor having first and second terminals each located within a certain distance within a periphery formed by the ends of the inductor, the first and second terminals extending from a bottom of the inductor, the first and second terminals being physically directly connected to the upper portion of the SIP to form an empty space region between the bottom of the inductor and the upper portion of the SIP, wherein the void space region has a width corresponding to a distance between the first and second terminals and a height corresponding to a length of the first and second terminals, wherein the SIP is a first discrete component and the inductance is a second discrete component and the periphery formed by the ends of the inductance extends beyond a periphery of the SIP; and means for supplying the regulated voltage to a load.The apparatus of claim 19, wherein the inductance and regulator circuitry of the SIP together implement a switching regulator.The apparatus of claim 19 or 20, wherein the regulator circuitry comprises switching circuitry for charging and discharging the inductor.The apparatus of any of claims 19 to 21, wherein a second end of the inductor extends beyond the second side portion of the SIP.

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