Post-treatment processes for ion beam debridement of a magnetic tunnel contact and structures produced therewith

Abstract

MTJ device comprising: a column structure (150) comprising, from bottom to top, a lower electrode (126) and an MTJ structure (143, 146, 148) comprising a reference magnetization layer (143) with a first ferromagnetic material, a tunnel barrier layer (146) and a free magnetization layer (148) with a second ferromagnetic material; an upper electrode (158) arranged above the MTJ structure comprising a metallic material containing a non-magnetic metal element;and a dielectric metal oxide layer (154) extending from a side wall of the column structure (150) to a side wall of the upper electrode (158), wherein a lower part of the dielectric metal oxide layer (154), which contacts the side wall of the column structure (150), comprises a dielectric composite metal oxide material containing a metal oxide of the first ferromagnetic material, a metal oxide of the second ferromagnetic material, and a metal oxide of the non-magnetic metal element, wherein an average molar fraction of the metal oxide of the non-magnetic metal element in the lower part of the dielectric metal oxide layer (154) is 0.001 to 0.5, and wherein an upper part of the dielectric metal oxide layer (154), which contacts the upper electrode (158), contains the metal oxide of the non-magnetic metal element with an average molar fraction of 0.9 to 1.0.

Description

Related registration

[0001] The present application claims priority over the preliminary US patent application filed on July 17, 2020, with file number 63 / 053.025 and entitled “Ion Beam Etching (IBE) with post-treatment and MTJ structures thereof”, which is incorporated by reference into the present application. background

[0002] The magnetic tunnel resistance of a magnetic tunnel junction (MTJ) depends on the relative alignment of the magnetizations of a reference magnetization layer and a free magnetization layer. This property is used in MTJ storage devices to store information encoded as either a parallel or antiparallel alignment of magnetization directions between the reference and free magnetization layers. Key considerations in the fabrication of MTJ storage devices are yield and reliability. List of characters

[0003] Aspects of the present invention are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. Rather, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 is a vertical sectional view of an exemplary structure after the fabrication of a CMOS transistor (CMOS: complementary metal oxide semiconductor), metallic interconnect structures embedded in dielectric material layers, and a dielectric interconnect via layer according to an embodiment of the present invention. Fig. Figure 2 is a vertical sectional view of the exemplary structure after the fabrication of a matrix of interconnect via structures according to an embodiment of the present invention. Fig. Figure 3 is a vertical sectional view of the exemplary structure after the fabrication of a lower electrode material layer, a storage material layer stack and an upper electrode material layer according to an embodiment of the present invention. Fig. Figure 4 is a vertical sectional view of the exemplary structure after structuring the upper electrode material layer to form upper electrodes according to an embodiment of the present invention. Fig. Figure 5 is a vertical sectional view of the exemplary structure after a focused ion beam etching process in which, according to an embodiment of the present invention, a matrix of storage elements is produced. The Fig. 6A to Fig. Figure 6E shows successive vertical sectional views of a memory cell during a first exemplary sequence of structuring processes according to an embodiment of the present invention. Fig. Figure 7 is a vertical sectional view of the exemplary structure after the structuring process of Fig. 6E according to an embodiment of the present invention. Fig. Figure 8 is a vertical sectional view of the exemplary structure after generating a matrix of dielectric spacers according to an embodiment of the present invention. Fig. Figure 9 is a vertical sectional view of the exemplary structure after fabrication of a dielectric storage layer according to an embodiment of the present invention. Fig. Figure 10 is a vertical sectional view of the exemplary structure after the creation of integrated conductor and via openings through the dielectric storage layer according to an embodiment of the present invention. Fig. Figure 11 is a vertical sectional view of the exemplary structure after fabrication of metallic storage plane interconnect structures according to an embodiment of the present invention. The Fig. 12A to Fig. Figure 12E shows successive vertical sectional views of a memory cell during a second exemplary sequence of structuring processes according to an embodiment of the present invention. Fig. Figure 13A is a schematic vertical sectional view of a column structure after a focused ion beam etching process according to an embodiment of the present invention. Fig. Figure 13B is a schematic vertical sectional view of a column structure after the removal of a predominant part of a remaining by-product layer according to an embodiment of the present invention. Fig. Figure 14A is a schematic vertical sectional view of a column structure after a focused ion beam etching process according to an embodiment of the present invention. Fig. Figure 14B is a schematic vertical sectional view of a column structure after a recess reduction ion beam etching process according to an embodiment of the present invention. Fig. Figure 15 is a first flowchart showing a first sequence of processing steps for manufacturing an MTJ device of the present invention. Fig. Figure 16 is a second flowchart showing a second sequence of processing steps for manufacturing an MTJ device of the present invention. Detailed description

[0004] The following description provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. These are, of course, merely examples and are not intended to be limiting. For example, the fabrication of a first element above or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present invention.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0005] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0006] In general, the structures and methods of the present invention can be used to fabricate a memory cell and / or a matrix of memory cells. In particular, the structures and methods of the present invention can be used to fabricate an MTJ memory cell and / or a matrix of MTJ memory cells.

[0007] During MTJ structuring with a magnetized inductively coupled plasma (MICP), ions C, H, O can penetrate magnetic layers and form a defect or damaged layer, leading to a deterioration of the magnetic tunnel resistance (TMR) or coercivity (Hc). To prevent the formation of a defect layer, ion beam etching (IBE) can be used for MTJ structuring.

[0008] An MTJ structure fabricated by ion beam etching can exhibit numerous structural and electrical defects as collateral damage from the use of a high-energy ion beam. For example, various components within an MTJ can be electrically short-circuited by metal particles that are byproducts of the ion beam etching process. The occurrence of such electrical short circuits can be demonstrated by measuring the bit error rate, which indicates the error rate of memory bits that have physical magnetic tunnel contacts. Bit error rates on the order of approximately 100 ppm are not uncommon in the fabrication of MTJ devices.The present invention addresses the problem of electrical short circuits and other undesirable electrical properties that arise in MTJ structures by using an oxidation process that transforms a residual metal layer on a sidewall of an MTJ structure into a dielectric metal oxide layer, which becomes electrically inert, thereby eliminating electrical short-circuit paths from the sidewall of the MTJ structure. The various aspects of the present invention will now be described with reference to the accompanying drawings.

[0009] Fig. Figure 1 is a vertical sectional view of an exemplary structure after the fabrication of a CMOS transistor, metallic interconnect structures embedded in dielectric material layers, and a dielectric interconnect via layer according to an embodiment of the present invention. The exemplary structure comprises CMOS transistors and metallic interconnect structures fabricated in dielectric material layers. In particular, the exemplary structure comprises a substrate 9, which may be a semiconductor substrate, such as a commercially available silicon wafer. In an upper part of the substrate 9, STI structures 720 (STI: shallow trench insulation) comprising a dielectric material such as silicon oxide can be fabricated. In each region that may be laterally enclosed by a portion of the STI structures 720, suitable doped semiconductor wells, such as p- and n-wells, can be produced.Field-effect transistors can be fabricated on a top surface of the substrate 9. Each field-effect transistor can, for example, have: a source region 732; a drain region 738; a semiconductor channel 735 having a surface portion of the substrate 9 extending between the source region 732 and the drain region 738; and a gate structure 750. Each gate structure 750 can have a gate dielectric 752, a gate electrode 754, a capping gate dielectric 758, and a dielectric gate spacer 756. A source-side metal-semiconductor alloy region 742 can be fabricated on each source region 732, and a drain-side metal-semiconductor alloy region 748 can be fabricated on each drain region 738.Although the drawings depict planar field-effect transistors, embodiments in which the field-effect transistors may additionally or alternatively include fin field-effect transistors (FinFETs), gate-all-around field-effect transistors (GAA-FET transistors), or other types of field-effect transistors (FETs) are also expressly considered here.

[0010] The exemplary structure can have a memory matrix area 100, in which a matrix of memory elements can subsequently be fabricated, and a peripheral area 200 in which logic devices can be fabricated to support the operation of the memory element matrix. In one embodiment, devices (such as field-effect transistors) in the memory matrix area 100 can include lower-electrode access transistors that allow access to the lower electrodes of memory cells to be fabricated later. In this processing step, upper-electrode access transistors, which allow access to the upper electrodes of memory cells to be fabricated later, can also be fabricated in the peripheral area 200. Devices (such as field-effect transistors) in the peripheral area 200 can provide functions that may be required to operate the memory cell matrix to be fabricated later.In particular, devices in the peripheral area 200 can be configured to control a programming operation, an erase operation, and a read / write operation of the matrix of memory cells. The devices in the peripheral area 200 can include a sensor circuit and / or an upper electrode bias circuit. The devices fabricated on the top surface of the substrate 9 can include CMOS transistors and optionally other semiconductor devices (such as resistors, diodes, capacitors, etc.), and they are collectively referred to as a CMOS circuit 700.

[0011] Subsequently, various metallic interconnect structures embedded in dielectric material layers can be fabricated over the substrate 9 and the devices (such as field-effect transistors). The dielectric material layers can, for example, comprise a dielectric contact plane material layer 601, a first dielectric metal conduction plane material layer 610, a second dielectric conduction and via plane material layer 620, a third dielectric conduction and via plane material layer 630, and a fourth dielectric conduction and via plane material layer 640. The metallic interconnect structures can include: device contact via structures 612 fabricated in the dielectric contact plane material layer 601, which contact a respective component of the CMOS circuit 700;first metal conduction structures 618, which are fabricated in the first dielectric metal conduction layer material layer 610; first metal via structures 622, which are fabricated in a lower part of the second dielectric conduction and via layer material layer 620; second metal conduction structures 628, which are fabricated in an upper part of the second dielectric conduction and via layer material layer 620; second metal via structures 632, which are fabricated in a lower part of the third dielectric conduction and via layer material layer 630; third metal conduction structures 638, which are fabricated in an upper part of the third dielectric conduction and via layer material layer 630; third metal via structures 642, which are fabricated in a lower part of the fourth dielectric conduction and via layer material layer 640;and fourth metal conductor structures 648, which are manufactured in an upper part of the fourth dielectric conduction and via layer material 640. In one embodiment, the second metal conductor structures 628 can have source conductors which are connected to a source-side current source for a matrix of storage elements. The voltage provided by the source conductors can be applied to the lower electrodes via the access transistors provided in the storage matrix area 100.

[0012] The dielectric material layers (601, 610, 620, 630, 640) can each comprise a dielectric material such as undoped silicate glass, doped silicate glass, organosilicate glass, amorphous fluorocarbon, porous variants thereof, or combinations thereof. The metallic interconnect structures (612, 618, 622, 628, 632, 638, 642, 648) can each comprise at least one conductive material, which may be a combination of a metallic coating layer (such as a metal nitride or a metal carbide) and a metallic filler material. Each metallic coating layer can comprise TiN, TaN, WN, TiC, TaC, and WC, and each magnetic filler material component can comprise W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. Other suitable materials may also be used within the intended scope of protection of the invention.In one embodiment, the first metal via structures 622 and the second metal conductor structures 628 can be manufactured as integrated conductor and via structures using a dual damascene process, the second metal via structures 632 and the third metal conductor structures 638 can be manufactured as integrated conductor and via structures, and / or the third metal via structures 642 and the fourth metal conductor structures 648 can be manufactured as integrated conductor and via structures.Although the present invention is described with reference to an embodiment in which a matrix of memory cells is generated above the fourth dielectric conduction and via layer material 640, embodiments in which the matrix of memory cells can be generated on another metallic interconnect layer are also expressly considered here.

[0013] The dielectric material layers (601, 610, 620, 630, 640) can be arranged at a level lower than that of a memory cell matrix to be subsequently generated. Therefore, the dielectric material layers (601, 610, 620, 630, 640) are referred to here as lower-level dielectric layers, i.e., dielectric material layers arranged at a lower level than the memory cell matrix to be subsequently generated. The metallic interconnect structures (612, 618, 622, 628, 632, 638, 642, 648) are referred to here as metallic lower-level interconnect structures.A subset of the metallic interconnect structures (612, 618, 622, 628, 632, 638, 642, 648) comprises lower-level metal conductors (such as the fourth metal conductor structure 648) embedded in the dielectric lower-level layers and having top surfaces in a horizontal plane that contains a top surface of the dielectric lower-level layers. In general, the total number of metal conductor levels in the dielectric lower-level layers (601, 610, 620, 630, 640) can range from 1 to 10.

[0014] A dielectric capping layer 108 and a dielectric via layer 110 can be successively fabricated over the metallic interconnect structures and the dielectric material layers. The dielectric capping layer 108 can, for example, be fabricated on top surfaces of the fourth metal conductor structures 648 and on a top surface of the fourth dielectric conductor and via layer 640. The dielectric capping layer 108 comprises a dielectric encapsulation material that protects underlying metallic interconnect structures, such as the fourth metal conductor structures 648. In one embodiment, the dielectric capping layer 108 can comprise a material that offers high etch resistance, i.e.,, a dielectric material, and which can also act as an etch stop material during a subsequent anisotropic etching process in which the dielectric interconnect via layer 110 is etched. The dielectric capping layer 108 can, for example, comprise silicon carbide or silicon nitride and can have a thickness of 5 nm to 30 nm, but smaller and larger thicknesses can also be used.

[0015] The dielectric interconnect layer 110 can be made of a material suitable for the dielectric material layers (601, 610, 620, 630, 640). For example, the dielectric interconnect layer 110 can be undoped silicate glass or doped silicate glass deposited by cleavage of tetraethyl orthosilicate (TEOS). The thickness of the dielectric interconnect layer 110 can range from 50 nm to 200 nm, but smaller and larger thicknesses are also possible. The dielectric capping layer 108 and the dielectric interconnect layer 110 can be fabricated as planar (unstructured) protective layers, each with a planar top and bottom surface extending across the entire memory matrix area 100 and the peripheral area 200.

[0016] Fig. Figure 2 is a vertical sectional view of the exemplary structure after the fabrication of a matrix of interconnect via structures according to an embodiment of the present invention. Via openings can be created by the dielectric interconnect via layer 110 and the dielectric capping layer 108 of the exemplary structure. For example, a photoresist layer (not shown) can be applied over the interconnect via layer 110, which can be structured to create an opening in areas of the memory matrix area 100 that are located over each of the fourth metal conductor structures 648. The structure in the photoresist layer can be transferred to the interconnect via layer 110 and the dielectric capping layer 108 by anisotropic etching.The vias created by the anisotropic etching process are referred to here as down-electrode contact vias, since down-electrode interconnect vias are subsequently fabricated in these vias. The down-electrode contact vias can have conical or sloping sidewalls with a cone angle (relative to a vertical direction) of 1° to 10°. A top surface of a fourth metal conductor structure 648 can be physically exposed at the bottom surface of each down-electrode contact via. Subsequently, the photoresist layer can be removed, for example, by peeling.

[0017] Subsequently, a metallic barrier layer can be fabricated as a single material layer. The metallic barrier layer can cover physically exposed top surfaces of the fourth metal conductor structures 648, the conical side walls of the lower electrode contact via openings, and the top surface of the dielectric interconnect via layer 110 without a hole extending through them. The metallic barrier layer can comprise a conductive metal nitride such as TiN, TaN, and / or WN. Other suitable materials can also be used within the intended scope of protection of the present invention. The thickness of the metallic barrier layer can range from 3 nm to 20 nm, but smaller and larger thicknesses are also possible.

[0018] A metallic filler material such as tungsten or copper can be deposited in the remaining volumes of the lower electrode via holes. Portions of the metallic filler material and the metallic barrier layer located above the horizontal plane containing the top surface of the dielectric interconnect via layer 110 can be removed by a planarization process, such as chemical-mechanical planarization (CMP). Each remaining portion of the metallic filler material located in a given via hole has a metallic via filler portion 124. Each remaining portion of the metallic barrier layer in a given via hole has a metallic barrier layer 122.Each combination of a metallic barrier layer 122 and a metallic via-hole filler 124 that fills a via opening forms an interconnect via structure (122, 124). A matrix of interconnect via structures (122, 124) can extend in the dielectric interconnect via layer 110 onto lower-lying metallic interconnect structures. The matrix of interconnect via structures (122, 124) can contact top surfaces of a subset of the fourth metal conductor structures 648. In general, the matrix of interconnect via structures (122, 124) contacts top surfaces of a subset of lower-level metal conductors that are arranged on the top level of the dielectric lower-level layers (601, 610, 620, 630, 640).

[0019] Fig. Figure 3 is a vertical sectional view of the exemplary structure after the fabrication of a lower electrode material layer, a storage material layer stack, and an upper electrode material layer according to an embodiment of the present invention. A lower electrode material layer 126L, a storage material layer stack (130L, 140L, 146L, 148L), and an upper electrode material layer 158L can be fabricated above the dielectric interconnection via layer 110, and the matrix of interconnection via structures (122, 124) can be fabricated in the processing steps of Fig. 3 will be generated.

[0020] The lower electrode material layer 126L comprises at least one non-magnetic metallic material, such as TiN, TaN, WN, W, Cu, Al, Ti, Ta, Ru, Mo, Pt, an alloy thereof, and / or a combination thereof. Other suitable materials within the intended scope of protection of the invention may also be used. For example, the lower electrode material layer 126L may comprise and / or consist substantially of an elemental metal such as W, Cu, Ti, Ta, Ru, Mo, or Pt. The thickness of the lower electrode material layer 126L may range from 10 nm to 100 nm, but smaller and larger thicknesses may also be used.

[0021] In one embodiment, the storage material layer stack (130L, 140L, 146L, 148L) can comprise, from bottom to top, an optional non-magnetic metallic buffer material layer 130L, a synthetic antiferromagnetic layer 140L, a non-magnetic tunnel barrier material layer 146L, and a free magnetizing material layer 148L. The layers in the storage material layer stack (130L, 140L, 146L, 148L) can be deposited using either a CVD process (CVD: chemical vapor deposition) or a PVD process (PVD: physical vapor deposition). Each layer in the storage material layer stack (130L, 140L, 146L, 148L) can be deposited as a planar protective material layer with a uniform thickness throughout. In general, the storage material layer stack (130L, 140L, 146L, 148L) is produced between the lower electrode material layer 126L and the upper electrode material layer 158L.

[0022] The non-magnetic metallic buffer layer 130L comprises a non-magnetic material that can function as a seed layer. In particular, the non-magnetic metallic buffer layer 130L can provide a crystalline template structure that aligns polycrystalline grains of the materials of the synthetic antiferromagnetic layer 140L along directions that maximize the magnetization of a reference magnetizing layer in the synthetic antiferromagnetic layer 140L. The non-magnetic metallic buffer layer 130L can comprise Ti, a CoFeB alloy, a NiFe alloy, ruthenium, or a combination thereof. Other suitable materials are also within the intended scope of protection of the invention. The thickness of the non-magnetic metallic buffer layer 130L can range from 3 nm to 30 nm, but smaller and larger thicknesses can also be used.

[0023] The synthetic antiferromagnetic layer (SAF layer) 140L can comprise a layer stack consisting of a ferromagnetic hard layer 141, an antiferromagnetic coupling layer 142, and a reference magnetization layer 143. The ferromagnetic hard layer 141 and the reference magnetization layer 143 can each have a fixed magnetization direction. The antiferromagnetic coupling layer 142 establishes an antiferromagnetic coupling between the magnetization of the ferromagnetic hard layer 141 and the magnetization of the reference magnetization layer 143, such that the magnetization direction of the ferromagnetic hard layer 141 and the magnetization direction of the reference magnetization layer 143 remain fixed during operation of the memory cells to be manufactured subsequently. The ferromagnetic hard layer 141 can have a hard ferromagnetic material, such as PtMn, IrMn, RhMn, FeMn, OsMn or the like.The reference magnetization layer 143 can comprise a hard ferromagnetic material such as Co, CoFe, CoFeB, CoFeTa, NiFe, CoPt, CoFeNi, or the like. Other suitable materials within the intended scope of protection of the invention can also be used. The antiferromagnetic coupling layer 142 can comprise ruthenium or iridium. The thickness of the antiferromagnetic coupling layer 142 can be selected such that the exchange interaction induced by the antiferromagnetic coupling layer 142 stabilizes the relative magnetization directions of the ferromagnetic hard layer 141 and the reference magnetization layer 143 in opposite directions, i.e., in an antiparallel orientation. In one embodiment, net magnetization of the SAF layer 140L is achieved by matching the magnetization size of the ferromagnetic hard layer 141 to the magnetization size of the reference magnetization layer 143.The thickness of the SAF 140L layer can range from 5 nm to 30 nm, but smaller and larger thicknesses can also be used.

[0024] The non-magnetic tunnel barrier layer 146L can comprise a tunnel barrier material that is electrically insulating and has a thickness sufficient to allow electron tunneling. For example, the non-magnetic tunnel barrier layer 146L can comprise magnesium oxide (MgO), aluminum oxide (Al₂O₃), aluminum nitride (AlN), aluminum oxide nitride (AlON), hafnium oxide (HfO₂), or zirconium oxide (ZrO₂). Other suitable materials within the intended scope of protection of the invention can also be used. The thickness of the non-magnetic tunnel barrier layer 146L can range from 0.7 nm to 1.3 nm, but smaller and larger thicknesses are also possible.

[0025] The free magnetizing material layer 148L comprises a ferromagnetic material with two stable magnetization directions, which are parallel or antiparallel to the magnetization direction of the reference magnetizing layer 143. The free magnetizing material layer 148L comprises a hard ferromagnetic material such as Co, CoFe, CoFeB, CoFeTa, NiFe, CoPt, CoFeNi, or the like. Other suitable materials within the intended scope of protection of the invention may also be used. The thickness of the free magnetizing material layer 148L can be from 1 nm to 6 nm, but smaller and larger thicknesses can also be used.

[0026] The upper electrode material layer 158L comprises an upper electrode material, which can be a non-magnetic material that can be used for the lower electrode material layer 126L. Thus, the upper electrode material layer 158L comprises a non-magnetic metallic material containing a non-magnetic metallic element. Examples of non-magnetic metallic materials that can be used for the upper electrode material layer 158L include, but are not limited to, TiN, TaN, WN, W, Cu, Al, Ti, Ta, Ru, Mo, Pt, alloys thereof, and / or combinations thereof. Other suitable materials within the intended scope of protection of the invention can also be used. For example, the upper electrode material layer 158L can comprise and / or consist substantially of an elemental metal such as W, Cu, Ti, Ta, Ru, Mo, or Pt. The thickness of the upper electrode material layer 158L can range from 8 nm to 80 nm, e.g.The thickness ranges from 16 nm to 40 nm, but smaller and larger thicknesses can also be used. In one embodiment, the upper electrode material layer 158L can have a consistently homogeneous material composition.

[0027] The material layers, which are successively structured to form MTJ structures, are collectively referred to as MTJ material layers (143, 146L, 148L), and they comprise the reference magnetization layer 143, the non-magnetic tunnel barrier material layer 146L, and the free magnetization material layer 148L. In general, a layer stack can be fabricated with at least one lower electrode material layer 146L, MTJ material layers (143, 146L, 148L), and one upper electrode material layer 148L over the substrate 9. The upper electrode material layer 148L comprises a metallic material containing a non-magnetic metallic element.

[0028] Fig. Figure 4 is a vertical sectional view of the exemplary structure after structuring the upper electrode material layer into upper electrodes according to an embodiment of the present invention. A photoresist layer 177 can be applied over the upper electrode material layer 158L, which can be lithographically structured into a matrix of discrete photoresist material parts in the storage matrix area 100. Each structured part of the photoresist layer 177 can be arranged over one of the interconnection via structures (122, 124). Sidewalls of each structured part of the photoresist layer 177 can coincide with a periphery of a top surface of a lower interconnection via structure (122, 124) or be laterally offset outwards or laterally inwards from it.The side walls of each structured part of the photoresist layer 177 can have the shape of a circle, an ellipse, a rectangle or a rounded rectangle or a generally curved closed two-dimensional shape in a horizontal cross-section.

[0029] Unmasked portions of the upper electrode material layer 158L can be etched using an anisotropic etching process. In one embodiment, the topmost layer of the storage material layer stack (130L, 140L, 146L, 148L) can be used as an etch stop layer. Each structured portion of the upper electrode material layer 158L has an upper electrode 158. A two-dimensional matrix of upper electrodes 158 can be generated using the anisotropic etching process. Each upper electrode 158 can be a structured portion of the upper electrode material layer 158L. In one embodiment, the upper electrodes 158 can have and / or consist substantially of a conductive metallic nitride material (such as TiN, TaN, or WN).

[0030] In general, the upper electrode material layer 158L can be structured into a hard mask structure comprising at least one upper electrode 158, such as a two-dimensional matrix of upper electrodes 158. In one embodiment, the two-dimensional matrix of upper electrodes 158 can be generated as a two-dimensional periodic matrix. In another embodiment, the two-dimensional matrix of upper electrodes 158 can be generated as a rectangular periodic matrix with a first grid spacing along a first horizontal direction and a second grid spacing along a second horizontal direction perpendicular to the first horizontal direction. In another embodiment, the upper electrodes 158 can have substantially vertical or conical sidewalls extending vertically from a bottom to a top of each respective upper electrode 158.In one embodiment, the cone angle of the side walls of the upper electrodes 158, measured from a vertical direction perpendicular to the interfaces between the upper electrodes 158 and the MTJ material layers (143, 146L, 148L), can be 0° to 8°, e.g., 0.1° to 4°, but larger cone angles can also be used. After the anisotropic etching process, the photoresist layer 177 can be removed.

[0031] Fig. Figure 5 is a vertical sectional view of the exemplary structure after a focused ion beam etching process in which, according to an embodiment of the present invention, a matrix of storage elements 101 is produced. Fig. 6A is an enlarged representation of an area around a storage element 101 of Fig. 5. The Fig. 6A to Fig. Figure 6E shows successive vertical sectional views of a memory cell during a first exemplary sequence of structuring processes according to an embodiment of the present invention.

[0032] In the Fig. 5 and Fig. In 6A, the storage material layer stack (130L, 140L, 146L, 148L) and the lower electrode material layer 126L can be structured using a focused ion beam etching process. The matrix of upper electrodes 158 can be used as a hard mask structure for the focused ion beam etching process. A focused beam of ions with an energy of 300 eV to 600 eV can be used for the focused ion beam etching process, but lower and higher ion energies are also possible. The ion species that can be used for the focused ion beam etching process include gallium, silicon, chromium, iron, cobalt, nickel, germanium, indium, tin, gold, and lead. In one embodiment, ions of a non-magnetic element such as gallium can be used for the focused ion beam etching process.The focused ion beam can exhibit a first angular divergence in the direction of propagation, which can be induced, for example, by scanning. The first angular divergence of the beam angle, measured from a vertical direction perpendicular to the undersides of the upper electrodes 158, can range from 0° to 30°.

[0033] In the focused ion beam etching process, unmasked portions of the various material layers of the storage material layer stack (130L, 140L, 146L, 148L) and the lower electrode material layer 126L are etched sequentially. In the focused ion beam etching process, the storage material layer stack (130L, 140L, 146L, 148L), which comprises the MTJ material layers (143, 146L, 148L), and the lower electrode material layer 126L are structured into a structured form that includes at least one column structure 150. Each column structure 150 has a lower electrode 126 and a storage element 101. Each storage element 101 has an MTJ structure (141, 146, 148). In one embodiment, a two-dimensional matrix of upper electrodes 158 can be used as an etching mask in the entire focused ion beam etching process.In this embodiment, parts of the storage material layer stack (130L, 140L, 146L, 148L) and the lower electrode material layer 126L, which are not masked by the two-dimensional matrix of upper electrodes 158, can be etched using the focused ion beam etching process. The structured structure can comprise a two-dimensional matrix of column structures 150.

[0034] A combination of an upper electrode 158 and a column structure 150 forms a memory cell (158, 150). Thus, each memory cell (158, 150) has a vertical stack comprising an upper electrode 158, a memory element 101, and a lower electrode 126. In one embodiment, each memory cell (158, 150) can be an MTJ memory cell. Each MTJ memory cell can have a lower electrode 126, an MTJ structure (140, 146, 148), and an upper electrode 158. Each memory element 101 has a vertical stack comprising a synthetic antiferromagnetic structure 140, a tunnel barrier layer 146, and a free magnetization layer 148. Each memory element 101 can optionally include a non-magnetic metallic buffer layer and an MTJ structure (140, 146, 148).

[0035] Each MTJ structure (143, 146, 148) can include a reference magnetization layer 143 (which can be a component of a SAF structure 140), a tunnel barrier layer 146, and a free magnetization layer 148. In general, the ferromagnetic hard layer 141 and the antiferromagnetic coupling layer 142 in an SAF structure can be omitted, or they can be replaced by another magnetic structure that stabilizes the magnetization direction in the reference magnetization layer 143. A non-magnetic metallic buffer layer 130 can be provided between the lower electrode 126 and the MTJ structure (143, 146, 148). Each lower electrode 126 is a structured part of the lower electrode material layer 126L. Each SAF structure 140 can be a structured part of the SAF layer 140L. Each tunnel barrier layer 146 can be a structured part of the non-magnetic tunnel barrier material layer 146L.Each free magnetization layer 148 can be a structured part of the free magnetization material layer 148L. The synthetic antiferromagnetic structure 140 can comprise a stack of layers consisting of a ferromagnetic hard layer 141, an antiferromagnetic coupling layer 142, and a reference magnetization layer 143. In general, in embodiments where each memory element 101 comprises an MTJ memory element, each memory element 101 can have a reference magnetization layer 143, a tunnel barrier layer 146 in contact with the reference magnetization layer 143, and a free magnetization layer 148 in contact with the tunnel barrier layer 146.In general, each reference magnetization layer 143 has a first ferromagnetic material, and the free magnetization layer 148 has a second ferromagnetic material, which may be the same as the first ferromagnetic material or different from it.

[0036] The column structures 150 can be conical column structures with a conical side wall. The conical column structures can have side walls with a non-zero mean cone angle, i.e., a non-vertical surface. A "mean" angle is an angle measured across all relevant surfaces. Thus, a mean angle of a conical surface with different local cone angles can be calculated by averaging the local cone angles. The mean cone angle of the column structures 150 can vary from layer to layer and can generally be 2° to 12°, e.g., 30° to 10°, but smaller and larger mean cone angles can also be used.In general, the mean cone angle of side walls of lower parts of the upper electrodes 158 can be equal to the mean cone angle of the column structures 150, or it can be smaller than the mean cone angle of the column structures 150 at this processing stage.

[0037] Unmasked portions of the interconnect layer 110 can be vertically recessed using a focused ion beam etching process. In an alternative embodiment, an ion etching process can be used instead of the focused ion beam etching process. The matrix of interconnect structures (122, 124) can be arranged beneath the matrix of memory cells (158, 150) and can contact the underside of one of the respective lower electrodes 126. This ion beam etching process creates a shallow recess in the interconnect layer 110 between the column structures 150. This feature offers the advantage of providing a conical hard mask profile and a shallow recess depth, and a magnetized inductively coupled plasma (MCP) is used for cleaning and / or oxidizing metal ions.According to the present invention, the depth of the shallow recess is no more than 300 Å and is therefore shallower than a conventional recess.

[0038] The interconnect layer 110 is located beneath the matrix of column structures 150. Portions of the interconnect layer 110 not covered by the two-dimensional matrix of memory cells (158, 150) may be vertically recessed beneath the horizontal plane containing the interfaces between the matrix of interconnect structures (122, 124) and the matrix of memory cells (158, 150). The remaining portions of the interconnect layer 110 may have a recessed horizontal top surface adjacent to the lower peripheries of conical sidewalls of portions of the interconnect layer 110 located beneath the matrix of memory cells (158, 150). Therefore, the interconnect layer 110 has a matrix of mesa portions projecting upwards from a planar portion of the interconnect layer 110.The matrix of mesa parts of the interconnection via layer 110 contacts the matrix of column structures 150. In one embodiment, each mesa part of the interconnection via layer 110 can contact an annular portion of a bottom surface of a respective column structure 150. Each mesa part of the interconnection via layer 110 can have a conical side wall that adjoins a conical side wall of a column structure 150 and is referred to here as a conical column side wall.

[0039] In general, an upper electrode 158 is arranged above an MTJ structure (143, 146, 148) in each memory cell (158, 150). The upper electrodes 158 have a metallic material that includes a non-magnetic metal element. A connection via structure (122, 124) can be embedded in each mesa portion of the connection via layer 110 and can contact a central portion of the bottom of the column structure 150.

[0040] In general, a residual metal layer 151 is formed in the focused ion beam etching process on physically exposed sidewalls of the column structure 150 and in the upper parts of the conical sidewalls of the mesa parts of the interconnection via layer 110. The residual metal layer 151 contains metal particles that are leached from the upper electrodes 158, the metallic material layers in the storage material layer stack (130L, 140L, 146L, 148L) and the lower electrode material layer 126L during the focused ion beam etching process. Although a predominant proportion of the metal particles ejected from the upper electrodes 158 and the metallic material layers in the storage material layer stack (130L, 140L, 146L, 148L) during the focused ion beam etching process are removed from the side walls of the upper electrodes 158 and the column structures 150, the scattering directions of the ejected metal particles are statistically random.Some of the leached metal particles can be deposited on the physically exposed sidewalls of the upper electrodes 158 and the column structures 150. The thickness of the residual metal layer 151 can be 0.2 nm to 2 nm, e.g., 0.4 nm to 1.2 nm, but the residual metal layer 151 can also have a smaller or larger thickness. The residual metal layer 151 can be a continuous layer without openings, or it can have discrete openings, or it can be produced as discrete islands that are not interconnected, depending on the thickness.

[0041] Furthermore, a residual by-product layer 153, comprising a compound of ion beam species from the focused ion beam etching process, can form on the surfaces of the upper electrodes 158 and on the sidewalls of the column structures 150. For example, if a gallium ion beam is used in the focused ion beam etching process, the residual by-product layer 153 can contain atoms, compounds, and / or alloys of gallium. In one embodiment, the residual by-product layer 153 can contain compounds and / or alloys of the ion beam species from the focused ion beam etching process with materials from adjacent material parts in the column structure 150 or with the material of the upper electrode 158. The residual by-product layer 153 can be nested within or arranged on top of the residual metal layer 151. The thickness of the residual by-product layer 153 can range from 1 nm to 4 nm, e.g.,The thickness is typically 2 nm to 3 nm, but smaller and larger thicknesses are possible depending on the energy, ion beam species, and ion incidence during the focused ion beam etching process. Generally, surface portions of the upper electrodes 158 are etched during the focused ion beam etching process, and therefore the upper electrodes 158 are an important source of metallic material for the residual metal layer 151. Consequently, the residual metal layer 151 on one side wall of each column structure 150 contains the non-magnetic metallic element of the upper electrodes 158.

[0042] In one embodiment, the tunnel barrier material 146 (which may be a non-metallic material) can be etched at a higher etch rate than the metallic materials of the metallic material layers in the storage material layer stack (130L, 140L, 146L, 148L) in the focused ion beam etching process. In this embodiment, an annular lateral recess 147 can be created in each column structure 150, extending at vertex angles around the entire side wall of the tunnel barrier material 146. The vertical cross-sectional profile of such an annular lateral recess 147 can have a shape similar to the vertical cross-sectional shape of a bird's beak, referred to here as a beak profile.In this embodiment, each tunnel barrier layer 146 can have a beak-shaped profile in a vertical sectional view, wherein a portion of a side wall of the tunnel barrier layer 146 is recessed laterally inwards to provide the annular lateral recess 147, which is a continuous lateral recess extending around the side wall of the tunnel barrier layer 146. The depth of the annular lateral recess 147 (measured along a radial direction) can be from 1 nm to 4 nm, but smaller and larger depths are also possible. The height of the annular lateral recess 147 can be on the order of the thickness of the tunnel barrier layer 146.

[0043] In Fig. 6B and according to one aspect of the present invention, a predominant part (i.e., more than 50% of the volume) of the residual by-product layer 153 can be removed by performing an oblique ion beam bombardment process. While the oblique ion beam bombardment process is optional, it is preferred. During the oblique ion beam bombardment process, ions in a focused ion beam strike the residual by-product layer 153 at an angle with respect to a vertical direction greater than 30°. The vertical direction is defined as a direction perpendicular to the interfaces between the column structures 150 and the upper electrodes 158.

[0044] The process parameters for a focused ion beam during the oblique ion beam bombardment process can be selected to increase the proportion of material in the residual by-product layer 153. For example, the angle of incidence of the ion beam (measured as the angle of deflection from the vertical direction) in the oblique ion beam bombardment process can be 30° to 90°, and the energy of the ions in the oblique ion beam can be 50 eV to 200 eV, although lower and higher energies can also be used. Generally, the angle of incidence of the ion beam in the oblique ion beam bombardment process is greater than the angle of incidence of the ion beam in the focused ion beam etching process. The energy of the ion beam in the oblique ion beam bombardment process is lower than the energy of the ion beam in the focused ion beam etching process.The volume fraction of the portion of the residual by-product layer 153 that is removed during the oblique ion beam bombardment process can range from 0.5 to 0.99, e.g., 0.6 to 0.9, but smaller and larger volume fractions can also be used depending on the process parameters. Generally, the majority of the residual metal layer 151 tends to remain on the sidewalls of the column structures 150 and on the surfaces of the upper electrodes 158, as well as on the sidewalls of the mesa portions of the interconnection via layer 110.

[0045] In Fig. 6C and according to one aspect of the present invention, a cavity reduction ion beam etching process can be carried out. While the cavity reduction ion beam etching process is optional, it is preferred. Ions with lower energy than the ion energy during the focused ion beam etching process are directed towards the column structures 150 and the upper electrodes 158, thereby removing the metallic materials in the MTJ structures (143, 146, 148) at a higher etch rate than the tunnel barrier layer material 146. In other words, in the cavity reduction ion beam etching process, the first ferromagnetic material of the reference magnetization layer 143 and the second ferromagnetic material of the free magnetization layer 148 are removed at a higher etch rate than the tunnel barrier layer material 146.

[0046] The process parameters for a focused ion beam during the cavity reduction ion beam etching process can be selected such that the cavity depth of the annular lateral cavity 147 of each column structure 150 is reduced. For example, the angle of incidence of the ion beam (measured as an angle of deflection from the vertical direction) of the cavity reduction ion beam etching process can be 0° to 30°, and the energy of the ions in the ion beam of the cavity reduction ion beam etching process can be 50 eV to 200 eV, but lower and higher energies can also be used.In general, the angle of incidence of the ion beam in the recess reduction ion beam etching process can be the same as the angle of incidence of the ion beam in the focused ion beam etching process, and the energy of the ion beam in the recess reduction ion beam etching process is lower than the energy of the ion beam in the focused ion beam etching process. Generally, the majority of the residual metal layer 151 tends to remain on the sidewalls of the pillar structures 150 and on the surfaces of the upper electrodes 158, as well as on the sidewalls of the mesa portions of the interconnect via layer 110. The depth of the annular lateral recess 147 can be reduced by a percentage from 5% to 50%, e.g., 10% to 30%, but lower and higher percentages can also be used.

[0047] In Fig. 6D and according to one aspect of the present invention, a hard-mask trimming ion beam etching process can be carried out. The hard-mask trimming ion beam etching process is optional, but preferred. An ion beam having a second angular divergence can be directed onto the column structure 150 and the upper electrodes 158. The second angular divergence of the ion beam of the hard-mask trimming ion beam etching process can be smaller than the first angular divergence of the ion beam of the focused ion beam etching process, which is directed onto the processing stages of the Fig. 5 and Fig. 6A is used. Therefore, compared to the focused ion beam etching process, a higher percentage of ions strike the upper electrodes 158 than the sidewalls of the column structures 150 during the hard mask trimming ion beam etching process. The upper electrodes 158 are etched to create a sidewall with a larger cone angle relative to the vertical direction.

[0048] The process parameters for a focused ion beam in the hard-mask trimming ion beam etching process can be selected such that the mean cone angle of the side walls of the upper electrodes increases. For example, the angle of incidence of the ion beam (measured as an angle of deflection from the vertical direction) in the hard-mask trimming ion beam etching process can be 0° to 20°, e.g., 0° to 10°, and the energy of the ions in the ion beam of the hard-mask trimming ion beam etching process can be 300 eV to 600 eV, but lower and higher energies can also be used.In general, the angle of incidence of the ion beam in the hard mask trimming ion beam etching process can be at least 5° and / or 100 smaller than the angle of incidence of the ion beam in the focused ion beam etching process, and the energy of the ion beam in the hard mask trimming ion beam etching process can be approximately equal to the energy of the ion beam in the focused ion beam etching process.

[0049] Each upper electrode 158 can have a conical sidewall and a convex top. In general, the convex top abuts the conical sidewall at an angle, such that an annular boundary between the convex top and the conical sidewall can be precisely defined. The conical sidewalls of the upper electrodes 158 are referred to here as conical electrode sidewalls. The conical sidewalls of the column structures 150 are referred to here as conical column sidewalls. The mean cone angle of the conical sidewalls of the column structures 150 (i.e., the conical column sidewalls) is referred to here as a first mean cone angle α. The mean cone angle of the conical sidewalls of the upper electrodes 158 (i.e., the conical electrode sidewalls) is referred to here as a second mean cone angle β. The first mean cone angle α does not change significantly during the hard mask trimming ion beam etching process.In contrast, the second mean cone angle β increases by at least 0.5° during the hard mask trimming ion beam etching process. Normally, the second mean cone angle β is equal to the first mean cone angle α before the hard mask trimming ion beam etching process. The increase of the second mean cone angle β during the hard mask trimming ion beam etching process can range from 0.5° to 20°, e.g., from 30° to 15°. For example, the first mean cone angle α after the hard mask trimming ion beam etching process can range from 8° to 32°, and the second mean cone angle β after the hard mask trimming ion beam etching process can range from 2° to 12°.

[0050] In each memory cell (158, 150), an upper electrode 158 above an MTJ structure (143, 146, 148) has a conical electrode sidewall that adjoins a column structure 150 and, after the hard-mask trimming ion beam etching process, has the first mean cone angle α with respect to the vertical direction (which is perpendicular to an interface with the column structure 150). The column structure 150 may have a conical column sidewall extending from the top of the column structure 150 to its bottom, and the conical column sidewall may have a second mean cone angle β with respect to the vertical direction that is smaller than the first mean cone angle α. An upper periphery of the conical column sidewall may coincide with a lower periphery of the conical electrode sidewall of the upper electrode 158.The increase in the second cone angle β has the advantageous effect of increasing the supply of oxygen source gas to the side walls of the column structures 150 during a subsequent plasma oxidation process and increasing the effectiveness of the subsequent plasma oxidation process.

[0051] Fig. Figure 6E is a vertical sectional view of a memory cell 150 after an oxidation process in which a dielectric metal oxide layer 154 is produced. Fig. Figure 7 is a vertical sectional view of the exemplary structure after the structuring process of Fig. 6E according to an embodiment of the present invention.

[0052] In the Fig. 6E and Fig. 7. An oxidation process can be carried out to convert the residual metal layer 151, surface portions of the upper electrodes 158, and surface portions of the metallic materials in the column structures 150 into a dielectric metal oxide layer 154. The surface portions of the metallic materials in the column structures 150 comprise surface portions of metallic materials in the MTJ structures (143, 146, 148), i.e., the surface portions of the first ferromagnetic material of the reference magnetization layer 143 and the surface portions of the second ferromagnetic material of the free magnetization layers 148. Each dielectric metal oxide layer 154 can be produced on a respective memory cell (158, 150) and can have an upper portion in contact with an upper electrode 158 and a lower portion in contact with the conical column side wall (i.e.,, the side wall of the column structure 150) and a lower part in contact with conical surfaces of a mesa part of the interconnection via layer 110.

[0053] Due to the various metallic interconnect structures present in the dielectric material layers of the exemplary structure, the maximum temperature to which the exemplary structure can be exposed in BEOL (Back End of Line) processing steps is approximately 400 °C. Therefore, a thermal oxidation process is impractical. According to one aspect of the present invention, the oxidation process used at this processing stage is a plasma oxidation process. In one embodiment, methanol in a gas phase can be used as an oxygen source gas during the plasma oxidation process. To increase the efficiency of the plasma oxidation process, a MICP (magnetized inductively coupled plasma) oxidation process can be used.While the MICP oxidation process enables effective oxidation at a low processing temperature, its effectiveness and process uniformity can be compromised when the supply of oxygen source gas to the recessed areas during the MICP oxidation process is limited. The hard mask trimming ion beam etching process is used at the processing stage of... Fig. 6D has the effect of reducing the aspect ratio of recessed areas (i.e., areas near the recessed horizontal surface of the interconnection via layer 110) in the two-dimensional matrix of memory cells (158, 150). Thus, the hard mask trimming ion beam etching process can increase the process uniformity and the effectiveness of the MICP oxidation process.

[0054] Around each memory cell (158, 150), the metallic materials integrated into the dielectric metal oxide layer 154 have a composition variation across the different surfaces of the upper electrode 158, the column structure 150, and the mesa part of the interconnection via layer 110. This allows each dielectric metal oxide layer 154 to have a composition variation.

[0055] Each dielectric metal oxide layer 154 extends over a conical electrode sidewall and a conical column sidewall of the storage cell (158, 150). The material of the upper part of each dielectric metal oxide layer 154, which contacts the upper electrode 158, can be formed primarily by oxidation of the non-magnetic metal element of the upper electrode 158. Thus, the upper part of the dielectric metal oxide layer 154 can contain the metal oxide of the non-magnetic metal element of the upper electrode 158 with an average molar fraction of 0.9 to 1.0.

[0056] Each MTJ structure (143, 146, 148) can include a reference magnetization layer 143 with a first ferroelectric material, a tunnel barrier layer 146, and a free magnetization layer 148 with a second ferromagnetic material. In this embodiment, a lower part of each dielectric metal oxide layer 154 can be produced on a conical side wall of a respective column structure 150 and can comprise a dielectric composite metal oxide material containing a metal oxide of the first ferromagnetic material, a metal oxide of the second ferromagnetic material, and a metal oxide of the non-magnetic metal element. The atomic fraction of the non-magnetic metal element of the upper electrodes 158 in the residual metal layer 151 can vary depending on the machining process and process parameters and can range from 0.001 to 0.5, e.g., 0.01 to 0.3 and / or 0.1 to 0.2.The mean molar fraction of the metal oxide of the non-magnetic metal element in the lower part of the dielectric metal oxide layer 154 can be 0.001 to 0.5, e.g. 0.01 to 0.3 and / or 0.1 to 0.2, but depending on the process parameters lower and higher molar fractions are also possible.

[0057] In one embodiment, the composition of the lower part of each dielectric metal oxide layer 154, which is in contact with a conical column sidewall, can be varied along a vertical direction. For example, in each residual metal layer 151, the first ferromagnetic material can have a higher atomic fraction on a sidewall of the reference magnetization layer 143, the second ferromagnetic material can have a higher atomic fraction on a sidewall of the free magnetization layer 148, and the non-magnetic metal element of the upper electrodes 158 can have a higher atomic fraction on a sidewall of the tunnel barrier layer 146. In general, the atomic fraction of the non-magnetic metal element of the upper electrodes 158 in the residual metal layer 151 can change depending on the machining process and the process parameters.In one embodiment, a peak value of the molar fraction of the metal oxide of the non-magnetic metal element can be located in the lower part of the dielectric metal oxide layer 154 adjacent to the tunnel barrier layer 146, for example between a horizontal plane containing a top side of the tunnel barrier layer 146 and a horizontal plane containing a bottom side of the tunnel barrier layer 146.

[0058] In one embodiment, a lower part of each dielectric metal oxide layer 154 extends over an upper part of a conical side wall of a respective lower mesa part of the interconnection via layer 110. The lower part of the dielectric metal oxide layer 154 can contain the metal oxide of the non-magnetic metal element in a molar fraction of 0.2 to 1.0, e.g., 0.3 to 0.8 and / or 0.4 to 0.6, but smaller and larger molar fractions are also possible.

[0059] In each column structure 150, the tunnel barrier layer 146 can have a beak-shaped profile in a vertical cross-sectional view, wherein part of a side wall of the tunnel barrier layer 146 is recessed laterally inwards to create an annular lateral recess 147. The dielectric metal oxide layer 154 fills the annular lateral recess 147 at least partially and / or completely, such that an outer side wall of the dielectric metal oxide layer 154 has less lateral waviness above the tunnel barrier layer 146 in a vertical cross-sectional profile than an inner side wall of the dielectric metal oxide layer 154, which contacts the tunnel barrier layer 146, in the same vertical cross-sectional profile.

[0060] Due to changes in the material composition of the residual metal layer 151, variations in the thickness of the residual metal layer 151, and differences in the composition of the underlying material parts, and the resulting differences in the oxidation rate of these underlying material parts of the memory cells (158, 150), the thickness of the dielectric metal oxide layer 154 can vary across the different material parts of a memory cell (158, 150). Furthermore, the duration of the plasma oxidation process used to produce the dielectric metal oxide layer 154 also influences its thickness. Generally, the thickness of the dielectric metal oxide layer 154 can range from 0.5 nm to 6 nm, e.g., 1 nm to 3 nm, but smaller and larger thicknesses are also possible.In general, the dielectric metal oxide layer 154 can be produced as a continuous layer of material, rather than as discrete regions of separate material parts. By producing the dielectric metal oxide layer 154 as a continuous layer of material, electrically conductive paths on the conical column sidewalls of the column structures 150 can be eliminated.

[0061] Fig. Figure 8 is a vertical sectional view of the exemplary structure after the fabrication of a matrix of dielectric spacers 162 according to an embodiment of the present invention. A dielectric spacer material can be conformally deposited over the matrix of memory cells (158, 150). In one embodiment, the dielectric spacers 162 can comprise a dielectric diffusion barrier material, such as silicon nitride. The dielectric spacer material can be deposited by plasma-enhanced chemical vapor deposition (PECVD). The thickness of the dielectric spacer material can range from 2 nm to 20 nm, but smaller and larger thicknesses can also be used. Horizontal portions of the dielectric spacers 162 can be removed by an anisotropic etching process.The remaining parts of the dielectric spacer material comprise a matrix of dielectric spacers 162 that laterally surround the matrix of memory cells (158, 150). In one embodiment, the duration of the anisotropic etching process can be selected such that the dielectric metal oxide layers 154 are physically exposed over an upper part of each upper electrode 158. The maximum thickness of each dielectric spacer 162 can be from 2 nm to 20 nm, e.g., 4 nm to 10 nm, but smaller and larger thicknesses can also be used.

[0062] Fig. Figure 9 is a vertical sectional view of the exemplary structure after fabrication of a dielectric storage layer 170 according to an embodiment of the present invention. The dielectric storage layer 170 can be fabricated around and over the matrix of dielectric spacers 162 and the matrix of storage cells (158, 150). In one embodiment, the dielectric storage layer 170 surrounds the dielectric spacers 162 and is laterally spaced from the column structures 150 by the dielectric spacers 162. The dielectric storage layer 170 laterally surrounds and embeds each of the upper electrodes 158. In one embodiment, the dielectric storage layer 170 comprises a planarizable dielectric material, such as undoped silicate glass or doped silicate glass.The dielectric material of the dielectric storage layer 170 can be deposited using a conformal deposition process (e.g., chemical vapor deposition) or a self-planarizing deposition process (such as spin coating). The dielectric storage layer 170 can be fabricated with a planar top surface (as produced, for example, by spin coating), or it can be planarized using a planarization process (such as a CMP process) to provide a planar top surface. A minimum vertical distance between the planar top surface of the dielectric storage layer 170 and the upper electrodes 158 can be 30 nm to 300 nm, but smaller and larger minimum vertical distances can also be used.

[0063] Fig. Figure 10 is a vertical sectional view of the exemplary structure after the fabrication of integrated conduction and via openings through the dielectric storage layer according to an embodiment of the present invention. At least one lithographic structuring process and at least one anisotropic etching process can be used to create storage-layer interconnect openings (663, 665) in the dielectric storage layer 170. For example, a first photoresist layer (not shown) can be deposited over the dielectric storage layer 170, which can then be lithographically structured to create a matrix of discrete openings in the first photoresist layer. Via openings in the dielectric storage layer 170 can be created using a first anisotropic etching process.After the first photoresist layer has been removed, a second photoresist layer (not shown) can be applied over the dielectric storage layer 170. This second photoresist layer can then be lithographically structured to create linear openings. The linear openings in the dielectric storage layer 170 can be created using a second anisotropic etching process. The second photoresist layer can then be removed.

[0064] In the memory matrix area 100, first-level memory interconnect openings 663 can be generated, and in the peripheral area 200, second-level memory interconnect openings 665 can be generated. In one embodiment, the memory-level interconnect openings (663, 665) can be generated as integrated conductor and via openings. In this embodiment, each integrated conductor and via opening can comprise a conductor opening located in an upper part of the dielectric memory-level layer 170 and at least one via opening adjacent to a lower part of the conductor opening and extending vertically through an upper part of the dielectric memory-level layer 170 and downward to the top of a lower metallic structure.In particular, the first storage-level interconnect openings 663 extend vertically through an upper portion of a respective dielectric metal oxide layer 154, and a convex top surface of an upper electrode 158 can be physically exposed at a bottom surface of each first storage-level interconnect opening 663. The second storage-level interconnect openings 665 extend vertically through the dielectric storage-level layer 170, the dielectric interconnect via layer 110, and the dielectric capping layer 108, and a top surface of a metal conductor structure (such as a fourth metal conductor structure 648) can be physically exposed at a bottom surface of each second storage-level interconnect opening 665.In general, the first storage-level interconnect openings 663 can extend vertically between the top of the dielectric storage-level layer 170 and a top of a respective upper electrode 158, and the second storage-level interconnect openings 665 can extend vertically between the top of the dielectric storage-level layer 170 and a top of a respective lower metallic interconnect structure.

[0065] Fig. Figure 11 is a vertical sectional view of the exemplary structure after the fabrication of metallic storage-level interconnect structures according to an embodiment of the present invention. At least one metallic material can be deposited in the storage-level interconnect openings (663, 665). The at least one metallic material is referred to here as a metallic storage-level material. In one embodiment, a metallic barrier layer (such as a TiN layer, a TaN layer, and / or a WN layer) and a metallic filler material (such as W, Cu, Co, Ru, Mo, or an intermetallic alloy) can be deposited in the storage-level interconnect openings (663, 665) and above the dielectric storage-level layer 170.

[0066] The metallic storage plane material can be removed from the dielectric storage plane layer 170 by a planarization process, such as a CMP process. The CMP process allows the metallic storage plane material above the horizontal plane containing the top surface of the dielectric storage plane layer 170 to be removed. Remaining portions of the metallic storage plane material, which fills the storage plane interconnect openings (663, 665), feature metallic storage plane interconnect structures (664, 666). In one embodiment, the metallic storage plane interconnect structures (664, 666) can be integrated conductor and via structures, each comprising a metal conductor and a group of at least one metallic via structure.The metal conductors of the metallic storage plane interconnect structures (664, 666) can have top surfaces in the horizontal plane that contains the top surface of the dielectric storage plane layer 170.

[0067] The metallic storage-level interconnect structures (664, 666) comprise first metallic storage-level interconnect structures 664 and second metallic storage-level interconnect structures 666. The first metallic storage-level interconnect structures 664 can extend vertically through the dielectric storage-level layer 170 and can each have a contact via that contacts one of the upper electrodes 158. The second metallic storage-level interconnect structures 666 can extend vertically through the dielectric storage-level layer 170 and can each have a via that contacts one of the lower metallic interconnect structures.In general, at each memory cell (158, 150) in a two-dimensional matrix of memory cells (158, 150), a contact via structure (which may include part of a first metallic memory plane interconnect structure 664) contacts a convex top surface of an upper electrode 158, and it extends vertically through an opening in a dielectric metal oxide layer 154. Each contact via structure contacting an upper electrode 158 may extend through the dielectric memory plane layer 170 and may contact a convex top surface of the upper electrode 158.

[0068] Above the storage layer, further metallic interconnect structures (not shown) can be fabricated, extending vertically from the underside of the dielectric capping layer 108 to the top of the dielectric storage layer 170. These further metallic interconnect structures can be embedded in additional dielectric material layers (not shown). The metallic storage layer interconnect structures (664, 666) and the further metallic interconnect structures can be used to electrically connect the upper electrodes 158 of the memory cells (158, 150) to a respective electrical node of the CMOS circuit 700.

[0069] Data from tests of fabricated specimens with the exemplary structure, generated under the supervision of the inventors, show a reduction in the bit error rate caused by electrical short circuits in the memory cells (158, 150) by a factor of approximately 10 to 100 compared to data from reference specimens in which the oxidation process for producing dielectric metal oxide layers was omitted. Thus, the fabrication of the dielectric metal oxide layers 154 offers the advantageous effect of suppressing electrical short circuits in the column structures 150.

[0070] Various embodiments of the present invention can be derived from the embodiment described above by modifying one or more of the processing steps. Fig. 6A to Fig. 6D can be omitted. Furthermore, the sequence of the processing steps can be changed. Fig. 6B to Fig. 6D with different degrees of influence on the overall effectiveness in avoiding electrical short circuits between components of each memory cell (158, 150) and in improving the electrical properties of each memory cell (158, 150).

[0071] The Fig. 12A to Fig. Figure 12E shows successive vertical sectional views of a memory cell (158, 150) during a second exemplary sequence of structuring processes according to an embodiment of the present invention. In the second exemplary sequence of structuring processes, the hard mask trimming ion beam etching process can be performed prior to the oblique ion beam bombardment process.

[0072] In Fig. 12A is a memory cell (158,150) shown after the focused ion beam etching process, which corresponds to the processing step of Fig. 6A corresponds to this.

[0073] In Fig. 12B and according to one aspect of the present invention, a hard mask trimming ion beam etching process can be carried out. For the hard mask trimming ion beam etching process, the same group of process parameters can be used as for the hard mask trimming ion beam etching process of Fig. 6D are used. Each upper electrode 158 can have a conical sidewall and a convex top. In general, the convex top abuts the conical sidewall at an angle such that an annular boundary between the convex top and the conical sidewall can be precisely defined. The conical sidewalls of the upper electrodes 158 are referred to here as conical electrode sidewalls. The mean cone angle of the conical sidewalls of the column structures 150 (i.e., the conical column sidewalls) is referred to here as a first mean cone angle α. The mean cone angle of the conical sidewalls of the upper electrodes 158 (i.e., the conical electrode sidewalls) is referred to here as a second mean cone angle β. The first mean cone angle α does not change significantly during the hard mask trimming ion beam etching process.In contrast, the second mean cone angle β increases by at least 0.5° during the hard mask trimming ion beam etching process. Normally, the second mean cone angle β is equal to the first mean cone angle α before the hard mask trimming ion beam etching process. The increase in the second mean cone angle β during the hard mask trimming ion beam etching process can range from 0.5° to 20°, e.g., 30° to 15°. For example, the first mean cone angle α after the hard mask trimming ion beam etching process can range from 8° to 32°, and the second mean cone angle β after the hard mask trimming ion beam etching process can range from 2° to 12°.

[0074] In each memory cell (158, 150), an upper electrode 158 above an MTJ structure (143, 146, 148) has a conical electrode sidewall that adjoins a column structure 150 and, after the hard-mask trimming ion beam etching process, has the first mean cone angle α with respect to the vertical direction (which is perpendicular to an interface with the column structure 150). The column structure 150 may have a conical column sidewall extending from the top of the column structure 150 to its bottom, and the conical column sidewall may have a second mean cone angle β with respect to the vertical direction that is smaller than the first mean cone angle α. An upper periphery of the conical column sidewall may coincide with a lower periphery of the conical electrode sidewall of the upper electrode 158.The increase in the second cone angle β has the advantageous effect of increasing the supply of oxygen source gas to the side walls of the column structures 150 during a subsequent plasma oxidation process and improving the effectiveness of the subsequent plasma oxidation process.

[0075] In Fig. 12C and according to one aspect of the present invention, an oblique ion beam bombardment process can be carried out. For the oblique ion beam bombardment process of Fig. 12C can use the same set of process parameters as for the oblique ion beam bombardment process of Fig. 6B can be used.

[0076] In Fig. 12D and according to one aspect of the present invention, a recess reduction ion beam etching process can be carried out. For the recess reduction ion beam etching process of Fig. 12D can use the same set of process parameters as for the recess reduction ion beam etching process of Fig. 6D can be used.

[0077] In Fig. 12E and according to one aspect of the present invention, an oxidation process can be carried out to convert the residual metal layer 151, surface parts of the upper electrodes 158 and surface parts of the metallic materials in the column structures 150 into a dielectric metal oxide layer 154. For the oxidation process of Fig. 12E can use the same group of process parameters as for the oxidation process of the Fig. 6E and Fig. 7 can be used.

[0078] The processing steps of the Fig. 8 to Fig. 11 are carried out to provide the exemplary structure that is in Fig. 11 is shown.

[0079] Fig. Figure 13A is a schematic vertical sectional view of a column structure after a focused ion beam etching process, showing the processing steps of the Fig. 5, Fig. 6A and Fig. 12A according to an embodiment of the present invention. Fig. Figure 13B is a schematic vertical sectional view of a columnar structure after the removal of a predominant part of a residual by-product layer by performing the oblique ion beam bombardment process of the Fig. 6B or Fig. 12C according to an embodiment of the present invention. The oblique ion beam bombardment process offers the advantage that a predominant part of a residual by-product layer 153 is removed. In this example, the thickness of the residual by-product layer 153 decreases from 3.3 nm to less than 1.0 nm.

[0080] Fig. Figure 14A is a schematic vertical sectional view of a column structure after a focused ion beam etching process, showing the processing steps of the Fig. 5, Fig. 6A and Fig. 12A according to an embodiment of the present invention. Fig. Figure 14B is a schematic vertical sectional view of a columnar structure after a cavity reduction ion beam etching process by Fig. 6C or Fig. 12D according to an embodiment of the present invention. The recess reduction ion beam etching process offers the advantage of reducing the depth of an annular lateral recess 147 in a tunnel barrier layer 146. In this example, the annular lateral recess 147 of a tunnel barrier layer 146 had an initial depth Do of about 3.0 nm and an initial width Wo of about 2.3 nm before the recess reduction ion beam etching process. After the recess reduction ion beam etching process, the annular lateral recess 147 of the tunnel barrier layer 146 had a post-treatment depth Di of about 2.3 nm and a post-treatment width W1 of about 2.0 nm. Thus, the volume of the annular lateral recess 147 decreased after the recess reduction ion beam etching process.By reducing the volume of the annular lateral recess 147, the abnormal peripheral effects in the tunnel barrier layer 146 are reduced and the electrical properties of the MTJ structure (143, 146, 148) in a memory cell (158, 150) are improved.

[0081] Fig. Figure 15 is a first flowchart showing a first sequence of machining steps for manufacturing an MTJ device of the present invention. The first sequence includes optional machining steps of the Fig. 6B to Fig. 6D or the Fig. 12B to Fig. 12D omitted. In one step 1510 of the Fig. 1 to Fig. 3 A layer stack can be produced with a lower electrode material layer 126L, MTJ material layers (143, 146L, 148L) and an upper electrode material layer 158L over a substrate 9. The upper electrode material layer 158L has a metallic material that contains a non-magnetic metal element. In a step 1520 of Fig. 4 The upper electrode material layer 158L can be structured into a hard mask structure with an upper electrode 158 (such as a two-dimensional matrix of upper electrodes 158). In a step 1530 of the Fig. 5, Fig. 6A and Fig. In step 12A, the MTJ material layers (143, 146L, 148L) and the lower electrode material layer 126L are structured into a structured form using a focused ion beam etching process. This structure comprises a column structure 150 (such as a two-dimensional matrix of column structures 150). The column structure 150 includes a lower electrode 126 and an MTJ structure (143, 146, 148). During the focused ion beam etching process, surface portions of the upper electrode 158 are etched. A residual metal layer 151, containing the non-magnetic metal element, is located on a side wall of the column structure 150. In step 1540 of the Fig. 6E, Fig. 7 and Fig. 12E a dielectric metal oxide layer 154 can be produced by carrying out an oxidation process in which the residual metal layer 151 and surface parts of metallic materials in the MTJ structure (143, 146, 148) and the upper electrode 158 are oxidized.

[0082] Fig. Figure 16 is a second flowchart showing a second sequence of machining steps for manufacturing an MTJ device of the present invention. The second sequence shows the optional machining steps of the Fig. 6B to Fig. 6D or the Fig. 12B to Fig. 12D is used. Thus, the second sequence can be derived from the first sequence by inserting steps 1610, 1620, and 1630 between steps 1530 and 1540. It is understood that only one or only two of the three optional steps can be inserted. It is also understood that the order of the optional processing steps can be reversed between each pair of optional processing steps. In step 1610 of the Fig. 6B and Fig. 12C can be used in a hard mask trimming ion beam etching process, leading to the in Fig. The first sequence of processing steps shown in step 14 will be added. In step 1620 of the Fig. 6C and Fig. 12D can incorporate an oblique ion beam bombardment process into the Fig. The first sequence of processing steps shown in step 14 will be inserted. In step 1630 of the Fig. 6D and Fig. 12B can incorporate a recess reduction ion beam etching process into the Fig. The first sequence of processing steps shown in 14 will be inserted.

[0083] In all drawings and according to various embodiments of the present invention, an MTJ device is provided comprising: a column structure 15° comprising, from bottom to top, a lower electrode 126 and an MTJ structure (143, 146, 148) comprising a reference magnetization layer 143 with a first ferromagnetic material, a tunnel barrier layer 146 and a free magnetization layer 148 with a second ferromagnetic material; an upper electrode 158 arranged above the MTJ structure (143, 146, 148) comprising a metallic material containing a non-magnetic metal element;and a dielectric metal oxide layer 154 extending from a side wall of the column structure 150 to a side wall of the upper electrode 158, wherein a lower part of the dielectric metal oxide layer 154, which contacts the side wall of the column structure 150, comprises a dielectric composite metal oxide material containing a metal oxide of the first ferromagnetic material, a metal oxide of the second ferromagnetic material, and a metal oxide of the non-magnetic metal element.

[0084] In one embodiment, the mean molar fraction of the metal oxide of the non-magnetic metal element in the lower part of the dielectric metal oxide layer 154 is 0.001 to 0.5. In another embodiment, an upper part of the dielectric metal oxide layer 154, which contacts the upper electrode 158, has a mean molar fraction of the metal oxide of the non-magnetic metal element of 0.9 to 1.0. In yet another embodiment, the composition of the lower part of the dielectric metal oxide layer 154 changes along a vertical direction, and a peak value of the molar fraction of the metal oxide of the non-magnetic metal element in the lower part of the dielectric metal oxide layer 154 lies between a horizontal plane containing the upper side of the tunnel barrier layer 146 and a horizontal plane containing the lower side of the tunnel barrier layer 146.

[0085] In one embodiment, the MTJ device further comprises a contact via structure (which may include part of a first metallic storage plane interconnect structure 664 or may be a stand-alone metallic via structure) that contacts a convex top surface of the upper electrode 158 and extends vertically through an opening in the dielectric metal oxide layer 154.

[0086] In one embodiment, the MTJ device further comprises: a dielectric interconnect via layer 110 arranged beneath the pillar structure 150, having a mesa portion projecting upward from a planar portion of the interconnect via layer 110 and contacting an annular portion of the underside of the pillar structure 150; and an interconnect via structure (122, 124) embedded in the mesa portion and contacting a central portion of the underside of the pillar structure 150. In one embodiment, a lower portion of the dielectric metal oxide layer 154 extends over an upper portion of a conical sidewall of the mesa portion of the interconnect via layer 110, and the lower portion of the dielectric metal oxide layer 154 contains the metal oxide of the non-magnetic metal element with an average molar fraction of 0.2 to 1.0.

[0087] In one embodiment, the tunnel barrier layer 146 has a bird's beak profile in a vertical sectional view, wherein part of a side wall of the tunnel barrier layer 146 is recessed laterally inwards to provide an annular lateral recess 147; and the dielectric metal oxide layer 154 fills the annular lateral recess 147 at least partially, such that in a vertical cross-sectional profile an outer side wall of the dielectric metal oxide layer 154 has less lateral waviness over the tunnel barrier layer 146 than an inner side wall of the dielectric metal oxide layer 154 that contacts the tunnel barrier layer 146.

[0088] In one embodiment, the MTJ device further comprises: a dielectric spacer 162 that laterally surrounds the column structure 150; and a dielectric storage layer 170 that laterally surrounds the dielectric spacer 162 and is laterally spaced from the column structure 150 by the dielectric metal oxide layer 154 and the dielectric spacer 162.

[0089] According to a further aspect of the present invention, an MTJ device is provided comprising: a column structure 15° comprising, from bottom to top, a lower electrode 126 and an MTJ structure (143, 146, 148) comprising a reference magnetizing layer 143 with a first ferromagnetic material, a tunnel barrier layer 146 and a free magnetizing layer 148 with a second ferromagnetic material;and an upper electrode 158 arranged above the MTJ structure (143, 146, 148) and having a conical electrode sidewall adjacent to the column structure 150 and having a first mean cone angle α with respect to a vertical direction perpendicular to an interface with the column structure 150, wherein the column structure 150 has a conical column sidewall extending from a top of the column structure 150 to a bottom of the column structure 150, and the conical column sidewall has a second mean cone angle β with respect to the vertical direction, which is smaller than the first mean cone angle α. In one embodiment, the first mean cone angle α is 8° to 32°, and the second mean cone angle β is 2° to 12°.

[0090] In one embodiment, the upper electrode 158 has a metallic material containing a non-magnetic metal element; a dielectric metal oxide layer 154 extends over the conical electrode side wall and the conical column side wall; and a lower part of the dielectric metal oxide layer 154, which contacts the conical column side wall, has a dielectric composite metal oxide material containing a metal oxide of the first ferromagnetic material, a metal oxide of the second ferromagnetic material, and a metal oxide of the non-magnetic metal element.

[0091] In one embodiment, the MTJ device further comprises: a dielectric storage plane layer 170 that laterally surrounds the upper electrode 158; a contact via structure (which may comprise a via portion in a first metallic storage plane interconnect structure 664 or may be a standalone metallic via structure) that extends through the dielectric storage plane layer 170 and contacts a convex top surface of the upper electrode 158; a dielectric interconnect via layer 110 that is arranged below the column structure 150 and has a mesa portion that projects upward from a planar portion of the dielectric interconnect via layer 110 and contacts an annular portion of a bottom surface of the column structure 150;and a connecting via structure (122, 124) embedded in the mesa part and contacting a central part of the underside of the column structure 150, wherein the mesa part has a conical side wall adjacent to the conical column side wall.

[0092] Features of various embodiments have been described above so that those skilled in the art can better understand the aspects of the present invention. It should be clear to those skilled in the art that they can readily use the present invention as a basis for designing or modifying other methods and structures to achieve the same objectives and / or to obtain the same advantages as in the embodiments presented here. Those skilled in the art should also recognize that such equivalent designs do not deviate from the fundamental concept and scope of protection of the present invention and that they can make various changes, substitutions, and modifications without deviating from the fundamental concept and scope of protection of the present invention.

Claims

[1] MTJ device (MTJ: magnetic tunnel contact) with: a column structure comprising, from bottom to top, a bottom electrode and an MTJ structure containing a reference magnetization layer with a first ferromagnetic material, a tunnel barrier layer and a free magnetization layer with a second ferromagnetic material; an upper electrode positioned above the MTJ structure and comprising a metallic material containing a non-magnetic metallic element; and a dielectric metal oxide layer extending from a side wall of the column structure to a side wall of the upper electrode, wherein a lower part of the dielectric metal oxide layer contacting the side wall of the column structure comprises a dielectric composite metal oxide material containing a metal oxide of the first ferromagnetic material, a metal oxide of the second ferromagnetic material, and a metal oxide of the non-magnetic metal element. [2] MTJ device according to claim 1, wherein the mean molar fraction of the metal oxide of the non-magnetic metal element in the lower part of the dielectric metal oxide layer is 0.001 to 0.

5. [3] MTJ device according to claim 1 or 2, wherein an upper part of the dielectric metal oxide layer contacting the upper electrode contains the metal oxide of the non-magnetic metal element with an average molar fraction of 0.9 to 1.

0. [4] MTJ device according to any one of the preceding claims, wherein the composition of the lower part of the dielectric metal oxide layer changes along a vertical direction, and a peak value of a molar fraction of the metal oxide of the non-magnetic metal element in the lower part of the dielectric metal oxide layer lies between a horizontal plane containing a top of the tunnel barrier layer and a horizontal plane containing a bottom of the tunnel barrier layer 146. [5] MTJ device according to one of the preceding claims, further comprising a contact through-hole structure which contacts a convex top surface of the upper electrode and extends vertically through an opening in the dielectric metal oxide layer. [6] MTJ device according to any of the preceding claims further comprising: a dielectric interconnection via layer located beneath the pillar structure and comprising a mesa portion projecting upwards from a planar portion of the interconnection via layer and contacting an annular portion of a bottom of the pillar structure; and a through-hole connection structure embedded in the mesa part and contacting a central part of the underside of the column structure. [7] MTJ device according to claim 6, wherein a lower part of the dielectric metal oxide layer extends over an upper part of a conical side wall of the mesa part of the interconnection via layer, and The lower part of the dielectric metal oxide layer contains the metal oxide of the non-magnetic metal element with an average molar fraction of 0.2 to 1.

0. [8] MTJ device according to any one of the preceding claims, wherein In a vertical sectional view, the tunnel barrier layer has a bird's beak profile, with part of one side wall of the tunnel barrier layer recessed laterally inwards to provide an annular lateral recess, and The dielectric metal oxide layer at least partially fills the annular lateral recess, such that in a vertical cross-sectional profile an outer side wall of the dielectric metal oxide layer has a lower lateral waviness over the tunnel barrier layer than an inner side wall of the dielectric metal oxide layer that contacts the tunnel barrier layer. [9] MTJ device according to any of the preceding claims further comprising: a dielectric spacer that laterally surrounds the column structure; and a dielectric storage layer that laterally surrounds the dielectric spacer and is laterally spaced from the column structure by the dielectric metal oxide layer and the dielectric spacer. [10] MTJ device (MTJ: magnetic tunnel contact) with: a column structure comprising, from bottom to top, a lower electrode and an MTJ structure containing a reference magnetization layer with a first ferromagnetic material, a tunnel barrier layer, and a free magnetization layer with a second ferromagnetic material; and an upper electrode arranged above the MTJ structure and having a conical electrode sidewall adjacent to the column structure and having a first mean cone angle with respect to a vertical direction perpendicular to an interface with the column structure, wherein the column structure has a conical column side wall that extends from a top of the column structure to a bottom of the column structure, and the conical column side wall has a second mean cone angle with respect to the vertical direction, which is smaller than the first mean cone angle. [11] MTJ device according to claim 10, wherein the first mean cone angle is 8° to 32°, and the second mean cone angle is 2° to 12°. [12] MTJ device according to claim 10 or 11, wherein the upper electrode has a metallic material containing a non-magnetic metal element, a dielectric metal oxide layer extends over the conical electrode sidewall and the conical column sidewall, and a lower part of the dielectric metal oxide layer, which contacts the conical column side wall, has a dielectric composite metal oxide material containing a metal oxide of the first ferromagnetic material, a metal oxide of the second ferromagnetic material and a metal oxide of the non-magnetic metal element. [13] MTJ device according to any one of claims 10 to 12, further comprising: a dielectric storage layer that laterally surrounds the upper electrode; a contact via structure extending through the dielectric storage plane layer and contacting a convex top surface of the upper electrode; a dielectric interconnect via layer located beneath the pillar structure and comprising a mesa portion projecting upwards from a planar portion of the dielectric interconnect via layer and contacting an annular portion of a bottom surface of the pillar structure; and a through-hole interconnect structure embedded in the mesa part and contacting a central part of the underside of the column structure, wherein the mesa part has a conical side wall adjacent to the conical column side wall. [14] Method for manufacturing an MTJ device (MTJ: magnetic tunnel contact) comprising the following steps: Manufacturing a layer stack comprising a bottom electrode material layer, MTJ material layers and a top electrode material layer over a substrate, wherein the top electrode material layer comprises a metallic material containing a non-magnetic metal element; Structuring the upper electrode material layer into a hard mask structure that includes an upper electrode; Structuring the MTJ material layers and the lower electrode material layer into a structured structure having a column structure, using a focused ion beam etching process, wherein the column structure has a lower electrode and an MTJ structure, surface parts of the upper electrode are etched during the focused ion beam etching process, and a residual metal layer containing the non-magnetic metal element is located on a side wall of the column structure; and Producing a dielectric metal oxide layer by carrying out an oxidation process in which the residual metal layer and surface parts of metallic materials are oxidized in the MTJ structure. [15] Method according to claim 14, wherein The MTJ structure contains a reference magnetization layer with a first ferromagnetic material, a tunnel barrier layer, and a free magnetization layer with a second ferromagnetic material, and a lower part of the dielectric metal oxide layer, which is produced on the column structure, has a dielectric composite metal oxide material containing a metal oxide of the first ferromagnetic material, a metal oxide of the second ferromagnetic material and a metal oxide of the non-magnetic metal element. [16] Method according to claim 14 or 15, wherein In the oxidation process, surface parts of the upper electrode are converted into an upper part of the dielectric metal oxide layer, and the upper part of the dielectric metal oxide layer contains the metal oxide of the non-magnetic metal element with an average molar fraction of 0.9 to 1.

0. [17] Method according to any one of claims 14 to 16, wherein In the focused ion beam etching process, a residual by-product layer is formed, which has a compound of ion beam species from the focused ion beam etching process and is nested with or arranged on the residual metal layer, and The process further includes the removal of a predominant part of the residual by-product layer by performing an oblique ion beam bombardment process in which ions strike the residual by-product layer at an angle greater than 30° with respect to a vertical direction perpendicular to an interface between the column structure and the upper electrode. [18] Method according to any one of claims 14 to 17, wherein The tunnel barrier layer is manufactured with a bird's beak profile in a vertical section view, wherein part of a side wall of the tunnel barrier layer is recessed laterally inwards to provide an annular lateral recess, and The process further includes performing a recess reduction ion beam etching process in which ions having a lower energy than the ion energy during the focused ion beam etching process are directed at the column structure and remove the metallic materials in the MTJ structure at a higher etch rate than a tunnel barrier material. [19] Method according to any one of claims 14 to 18, wherein The focused ion beam etching process has a first angular divergence in one propagation direction of an ion beam, and The process further includes performing a hard mask trimming ion beam etching process in which an ion beam with a second angular divergence is directed at the column structure, etching the upper electrode to provide a side wall having a larger cone angle with respect to a vertical direction. [20] Method according to claim 19, wherein the oxidation process is carried out after the hard mask trimming ion beam etching process, and The oxidation process involves a plasma oxidation process using methanol as an oxygen source gas.

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