Silicon through-hole (TSV) key for superposition measurement, as well as semiconductor device and semiconductor package with TSV key

Abstract

A silicon via (TSV) key for overlay measurements, the TSV key (OTK1 to OTK11) comprising:a first TSV (110) extending through at least a portion of a substrate (101) in a first direction perpendicular to a top surface of the substrate (101); andat least one ring pattern (RP1 to RP11) which is separate from the first TSV (110) and surrounds the first TSV (110) in a second direction which is parallel to the top surface of the substrate (101), wherein the at least one ring pattern (RP1 to RP11) is arranged in a layer which is below a top surface of the first TSV (110) in the first direction,wherein an inner measurement point (IMP) corresponds to the first TSV (110), an outer measurement point (OMP1 to OMP4) corresponds to the at least one ring pattern (RP1 to RP11), and the inner measurement point and the outer measurement point are arranged to provide an overlay measurement of a TSV,wherein the first TSV (110) is not electrically operated and is not connected to a wiring line (174), and wherein the inner measuring point (IMP) corresponds to an outer portion of the first TSV (110) and the outer measuring point (OMP) corresponds to at least one of an inner portion, a middle portion, and an outer portion of the at least one ring pattern (RP1 to RP11).

Description

BACKGROUND1. Technical FieldEmbodiments relate to a key for overlay measurement and a semiconductor device including the key, and more particularly to a through silicon via (TSV) key for measuring overlay of a TSV and a semiconductor device including the TSV key.2. Description of the Prior ArtA general overlay measurement refers to detection of a degree of overlap or a degree of deviation between an upper layer pattern and a lower layer pattern using a key for overlay measurement prepared on a top surface of a wafer beforehand. For example, the degree of misalignment can be obtained by measuring a separation distance of an inner box formed simultaneously with an upper layer pattern from an outer box formed previously simultaneously with a lower layer pattern in up-and-down directions, or leftward or rightward directions.Published patent applications KR 10 2011 0 136 122 A, US 2009 / 0 008 790 A1 and US 2017 / 0 025 384 A1 disclose silicon through-contact (TSV) keys from the prior art.SUMMARYEmbodiments relate to a through silicon via (TSV) key for overlay measurements, the TSV key comprising: a first TSV extending over at least a portion of a substrate in a first direction that is perpendicular to a top surface of the substrate; and at least one ring pattern which is separate from the first TSV and surrounds the first TSV in a second direction which is parallel to the top surface of the substrate, wherein the at least one ring pattern is disposed in a layer which is below a top surface of the first TSV in the first direction, wherein an inner measurement point corresponds to the first TSV, an outer measurement point corresponds to the at least one ring pattern, and the inner measurement point and the outer measurement point are disposed to provide an overlay measurement of a TSV, wherein the first TSV is not electrically operated and is not connected to a wiring line, and wherein the inner measurement point corresponds to an outer portion of the first TSV and the outer measurement point corresponds to at least one of an inner portion, a middle portion and an outer portion of the at least one ring pattern.Embodiments also relate to a semiconductor device comprising: a substrate; an integrated circuit layer in the substrate; a multi-wiring layer on the integrated circuit layer; a silicon via (TSV) key configured for overlay measurements, comprising a first TSV extending through at least a portion of the substrate in a first direction and at least one ring pattern separate from the first TSV and surrounding the first TSV in a second direction, wherein the first direction is perpendicular to the top surface of the substrate, the second direction is parallel to the top surface of the substrate, and the at least one ring pattern is disposed in a lower layer as a top layer of the first TSV in the first direction; and a plurality of second TSVs extending through at least a portion of the substrate in the first direction, wherein an inner measurement point corresponds to the first TSV, an outer measurement point corresponds to the at least one ring pattern, and the inner measurement point and the outer measurement point are arranged to provide an overlay measurement of a TSV, wherein the first TSV is not electrically operated and is not connected to a wiring line, and wherein the inner measurement point corresponds to an outer portion of the first TSV and the outer measurement point corresponds to at least one of an inner portion, a middle portion, and an outer portion of the at least one ring pattern.Embodiments also relate to a semiconductor package comprising: a package substrate; and at least one semiconductor chip stacked on the package substrate, wherein the at least one semiconductor chip comprises: a semiconductor substrate; an integrated circuit layer in the semiconductor substrate; a multi-wiring layer on the integrated circuit layer; a silicon via (TSV) key for overlay measurements, comprising a first TSV extending through at least a portion of the semiconductor substrate in a first direction and surrounding at least one ring pattern separate from the first TSV and the first TSV in a second direction, wherein the first direction is perpendicular to the top surface of the semiconductor substrate, the second direction is parallel to the top surface of the semiconductor substrate, and the at least one ring pattern is disposed in a lower layer as a top surface of the first TSV in the first direction; and a plurality of the second TSVs extend through at least a portion of the semiconductor substrate in the first direction, and wherein an inner measurement point corresponds to the first TSV, an outer measurement point corresponds to the at least one ring pattern, and the inner measurement point and the outer measurement point are arranged to provide an overlay measurement of a TSV, wherein the first TSV is not electrically operated and is not connected to a wiring line, and wherein the inner measurement point corresponds to an outer portion of the first TSV and the outer measurement point corresponds to at least one of an inner portion, a center portion, and an outer portion of the at least one ring pattern.According to yet another aspect of the inventive concept, a through silicon via (TSV) key is provided for overlay measurements, the TSV key comprising: a first TSV on a substrate; and at least one ring pattern on the substrate, wherein the at least one ring pattern has a shape spaced apart from and surrounding the first TSV, wherein an inner measurement point corresponds to the first TSV, an outer measurement point corresponds to the at least one ring pattern, and the inner measurement point and the outer measurement point are arranged to provide an overlay measurement of a TSV, wherein the first TSV is not electrically operated and is not connected to a wiring line, and wherein the inner measurement point corresponds to an outer portion of the first TSV and the outer measurement point corresponds to at least one of an inner portion, a middle portion, and an outer portion of the at least one ring pattern.BRIEF DESCRIPTION OF THE DRAWINGSFeatures will become apparent to those skilled in the art from a detailed description of the example embodiments with reference to the accompanying drawings, wherein: FIGS. 1A to 1C are plan views and a cross-sectional view of a through silicon via (TSV) key for overlay measurements according to an example embodiment; FIGS. 2A to 2D are diagrams of a box-in-box (BIB) overlay key and cell patterns including TSVs of various sizes; FIG. 3 is a graph illustrating a degree of deterioration of TSV overlay measurement on cell patterns including TSVs of various sizes compared to a BIB overlay key; FIGS. 4A to 13 are plan and cross-sectional views of the TSV keys for overlay measurements according to an example embodiment; FIGS. 14A and 14B are a top view and a partial cross-sectional view, respectively, of a semiconductor device including a TSV key for overlay measurements according to an example embodiment; FIG. 15 is a cross-sectional view of a semiconductor package including a TSV key for overlay measurements according to an example embodiment; FIGS. 16A and 16B are a perspective view and a cross-sectional view, respectively, of a semiconductor device including a semiconductor package including a TSV key for overlay measurements, according to an example embodiment; and FIG. 17 is a cross-sectional view of a semiconductor device including a semiconductor package including a TSV key for overlay measurements, according to an example embodiment.DETAILED DESCRIPTIONFIGS. 1A to 1C are plan views and cross-sectional views of a via (TSV) key for overlay measurements according to an example embodiment, and in particular, FIG. 1B is a cross-sectional view taken along a line I-I' of FIG. 1A, and FIG. 1C is a plan view illustrating an inner measurement point and an outer measurement point in FIG. 1A. FIGS. 1A and 1C illustrate plan views of which an interlayer dielectric is omitted for simplicity, and the same applies to other plan views below.Referring to FIGS. 1A to 1C, a TSV key for overlay measurements OTK 1 (hereinafter, simply referred to as "TSV key") according to the present example embodiment may include a first TSV 110, an inner ring pattern 120, and an outer ring pattern 130.The first TSV 110 may have a horizontal cross section having a circular shape parallel to a top surface of a substrate 101. Here, the horizontal cross section may correspond to a plane (x-y plane) defined by a first direction (x direction) and a second direction (y direction). However, the shape of the horizontal cross section of the first TSV 110 is not limited to a circular shape. For example, the shape of a horizontal cross section of the first TSV 110 may be an elliptical shape or a polygonal shape.The horizontal cross section of the first TSV 110 may have a first diameter D 1, and the first diameter D 1 may be less than 7 μm. For example, in the TSV key OTK 1 of the present example embodiment, the horizontal cross section of the first TSV 110 may have a first diameter D 1 of about 5 μm or about 4 μm. However, the first diameter D 1 of the horizontal cross section of the first TSV 110 is not limited to the numerical values set forth above. When the shape of the horizontal cross section of the first TSV 110 is not a circular shape, the size of the horizontal cross section of the first TSV 110 may be defined by another concept, such as a minor axis, a minor side, a diagonal line, or an area. In addition, the first TSV 110 may be formed by etching the substrate 101 from one side to the other side thereof, and thus diameters of an upper portion and a lower portion of the first TSV 110 may slightly deviate from each other according to the example embodiments.As shown in FIG. 1B, the first TSV 110 may extend in a third direction (z-direction) that is perpendicular to the x-y plane and thus penetrate through at least a portion of the substrate 101. Additionally, the first TSV 110 may extend through an interlayer dielectric 160 on the substrate 101. A top surface of the first TSV 110 may be coplanar with a top surface of the interlayer dielectric 160. For example, the respective top surfaces of the first TSV 110 and the interlayer dielectric 60 may have a substantially same height, i.e., a second height H 2. The first TSV 110 is not connected to a wiring line. According to example embodiments, the first TSV 110 may penetrate through the multi-wiring layer 170.In the TSV key OTK 1 of the present example embodiment, the first TSV 110 may be formed together when a second TSV (see 110 aof FIG. 15, or the like) which is actually operated as a through electrode in a semiconductor device is formed. Accordingly, the first TSV 110 may have substantially the same structure as the second TSV 110 aand may include the same material as the second TSV 110 a. For example, the first TSV 110 may have a three-dimensional pillar shape, and may include a barrier film on an outer surface thereof and a conductive fill layer therein. The barrier film may include at least one material selected from Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, and NiB. The conductive fill layer may include at least one material selected from Cu, a Cu alloy such as CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe, or CuW, W, a W alloy, Ni, Ru, and Co. However, the respective materials of the barrier film and the conductive fill layer are not limited to the materials set forth above. A via insulating layer may be disposed between the first TSV 110 and the substrate 101, or between the first TSV 110 and the interlayer dielectric 160. The via insulating layer may include, for example, an oxide film, a nitride film, a polymer film, or a combination thereof.The inner ring pattern 120 may be formed on the substrate 101. As shown in FIG. 1A, the inner ring pattern 120 may have a ring shape surrounding the first TSV 110. In the TSV key OTK 1 of the present example embodiment, the inner ring pattern 120 may have a rectangular ring shape. However, the shape of the inner ring pattern 120 is not limited to the rectangular ring shape.For example, the inner ring pattern 120 may have various shapes such as an annular shape, an elliptical ring, a polygonal ring, and the like.The inner ring pattern 120 may be disposed separately from the first TSV 110 in a horizontal direction. For example, the inner ring pattern 120 may be disposed separated from the first TSV 110 by a first interval S 1 in the first direction (x direction) or the second direction (y direction). The first interval S 1 may be 2 μm or more. In the TSV key OTK 1 of the present embodiment, the first interval S 1 may be, for example, about 2.175 μm. However, the interval through which the inner ring pattern 120 is separated from the first TSV 110 is not limited to the numerical values set forth above. The inner ring pattern 120 may have a first width W 1 of 2 μm or more. In the TSV key OTK 1 of the present example embodiment, the first width W 1 may be about 2.170 μm, for example. However, the first width W 1 is not limited thereto.As illustrated in FIG. 1B, the inner ring pattern 120 may have a structure inserted or buried in the substrate 101. A top surface of the inner ring pattern 120 may be substantially the same level as the top surface of the substrate 101. Accordingly, the respective top surfaces of the inner ring pattern 120 and the substrate 101 may have substantially the same height, i.e., a base height H 0. However, the structure of the inner ring pattern 120 is not limited to the inserted structure. For example, the inner ring pattern 120 may have a structure protruding upward from the substrate 101.The inner ring pattern 120 may include, for example, an oxide film such as a silicon dioxide (SiO 2)- film. However, the material of the inner ring pattern 120 is not limited to the oxide film. For example, the inner ring pattern 120 may include an insulating film such as a nitride film, a carbide film, or a polymer film.The substrate 101 may include, for example, a semiconductor element such as silicon (Si) or germanium (Ge). In addition, the substrate 101 may include a semiconductor compound such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). The substrate 101 may have a silicon-on-insulator (SOI) structure. In an example embodiment, the substrate 101 may include a buried oxide (BOX) layer. The substrate 101 may include a conductive region, e.g., an impurity-doped well or an impurity-doped structure. The substrate 101 may include various device isolation structures, such as a shallow trench isolation (STI) structure.The inner ring pattern 120 may correspond to a type of the device isolation structure. Accordingly, the inner ring pattern 120 may be formed together when a device isolation structure is formed, and may include the same material as the device isolation structure. However, according to example embodiments, the inner ring pattern 120 may be formed separately from the device isolation structure. In such a case, the inner ring pattern 120 may include a material different from the device isolation structure.The outer ring pattern 130 may be formed on the substrate 101. As shown in FIG. 1A, the outer ring pattern 130 may have a ring shape surrounding the inner ring pattern 120, and may be disposed in contact with an outer side surface of the inner ring pattern 120. Accordingly, the outer ring pattern 130 may have a rectangular ring shape similar to the inner ring pattern 120. However, the shape of the outer ring pattern 130 is not limited to the rectangular ring shape. For example, the outer ring pattern 130 may have various shapes such as a circular ring, an elliptical ring, and a polygonal ring. In the TSV key OTK 1 of the present example embodiment, the outer ring pattern 130 may have a second width W 2 of about 1 μm. However, the second width W 2 of the outer ring pattern 130 is not limited to the numerical value set forth above.The outer ring pattern 130 may have a structure protruding upward from the substrate 101. Accordingly, a top surface of the outer ring pattern 130 may have a first height H 1 and may be higher than the base height H 0 of the top surface of the substrate 101. However, the structure of the outer ring pattern 130 is not limited to the protruding structure. For example, the outer ring pattern 130 may have a structure inserted into the substrate 101 similar to the inner ring pattern 120. The outer ring pattern 130 may include, for example, a polysilicon film. However, the material of the outer ring pattern 130 is not limited to the polysilicon film. According to the example embodiments, the outer ring pattern 130 may include a polysilicon multilayer, or a multilayer of a polysilicon film and an insulating film. Here, the insulating film may include an oxide film, a nitride film, an oxynitride film, or a combination thereof.The inner ring pattern 120 and the outer ring pattern 130 may form a first ring pattern RP 1 for overlay measurements. As shown in FIG. 1C, in the TSV key OTK 1 of the present example embodiment, an outer portion of the first TSV 110 may be an inner measurement point IMP, and a portion of the first ring pattern RP 1 may be an outer measurement point OMP. Specifically, a rectangular portion along a dash-double-dot line surrounding the first TSV 110 may correspond to the inner measurement point IMP, and a rectangular portion along a dash-double-dot line marked at the center of the inner ring pattern 120 may correspond to the outer measurement point OMP.In the TSV key OTK 1 of the present example embodiment, overlay measurement may be performed by the same principle as a box-in-box (BIB) key pattern measurement method using an outer box mark and an inner box mark, both corresponding to existing overlay keys. For example, the inner measurement point IMP may correspond to the inner box mark, and the outer measurement point OMP may correspond to the outer box mark. In addition, the inner measurement point IMP and the outer measurement point OMP may respectively correspond to portions that are the highest intensity and are well differentiated from each other with respect to overlay measurements. Accordingly, in the TSV key OTK 1 of the present example embodiment, superposition of the first TSV 110 can be measured by measuring the inner measurement point IMP and the outer measurement point OMP. In addition, superposition of second TSV 110 athat are actually operated may be accurately determined based on the superposition of the first TSV 110.A portion of the first ring pattern RP 1 used for the overlay measurement may be the inner ring pattern 120. The outer ring pattern 130 may be formed to prevent noise signals in the overlay measurement rather than for the overlay measurement. Accordingly, according to the example embodiment, the outer ring pattern 130 may be omitted.In the TSV key OTK 1 of the present example embodiment, assuming that the outer ring pattern 130 is included, the first diameter D 1 is 4 μm, the first interval S 1 is 2.175 μm, the first width W 1 is 2.175 μm, and the second width W 2 is 1 μm, a total size TKS of the TSV key OTK 1 may be about 14.69 μm. When the outer ring pattern 130 is excluded, a dummy exclusion size DES of the TSV key OTK 1 may be about 12.69 μm. In addition, a size ACTS of an active layer disposed inside the inner ring pattern 120 and surrounding the first TSV 110 may be about 8.35 μm. Here, the active layer may refer to an impurity-doped silicon layer in a silicon layer of the substrate 101. However, the total size TKS of the TSV key OTK 1, the dummy exclusion size DES of the TSV key OTK 1, and the size ACTS of the active layer are not limited to the numerical values set forth above.The TSV key OTK 1 of the present example embodiment may include the first TSV 110 and the first ring pattern RP 1, thereby allowing superposition of the first TSV 110 to be accurately measured even when the first TSV 110 has a fine size. For example, even when the diameter of the first TSV 110 is less than 7 μm, the superposition of the first TSV 110 can be accurately measured by using the first TSV 110 and the first ring pattern RP 1, and thus, superposition of the second TSV 110 awhich is an actually operated TSV can be accurately determined.For comparison, in existing semiconductor devices, overlay measurement is performed by measuring a distance between a TSV used for actual operation and a pattern of the underlying layer, that is, a width of an active layer between the TSV and the pattern of the underlying layer. However, as the size of a TSV decreases, it becomes difficult to measure the distance between the TSV and the pattern of the underlying layer using measurement equipment because the width of the active layer is small, and even if the distance therebetween is measured, many errors occur. Deterioration in overlay measurement due to a decrease in TSV size will be described in more detail below with reference to FIGS. 2A-3.The TSV key OTK 1 of the present example embodiment includes the first TSV 110 and the first ring pattern RP 1 surrounding the first TSV 110 while being separated from the first TSV 110 to a certain distance, e.g., the first interval S 1, and enables to perform superposition measurement using the first TSV 110 as an inner measurement point and using the first ring pattern RP 1 as an outer measurement point, thereby enabling to accurately measure the superposition of the first TSV 110 even when the first TSV 110 has a fine size, e.g., a diameter of less than 7 μm. In addition, the superposition of the second TSV 110 a, which is an operated TSV having substantially the same structure as the first TSV 110, can be accurately determined based on a result of the superposition measurement of the first TSV 110.FIGS. 2A to 2D are diagrams of a BIB overlay key and cell patterns including TSVs of various sizes, and specifically, FIG. 2A is a diagram of a general BIB overlay key, and FIGS. 2B to 2D are diagrams of cell patterns including TSVs having diameters of 7 μm, 5 μm, and 4 μm, respectively. FIG. 3 is a graph illustrating an amount of deterioration of the TSV overlay measurement on cell patterns including TSVs of various sizes as compared to a BIB overlay key, where the x-axis represents a BIB overlay key and TSVs of corresponding sizes, and the y-axis represents a total key size in units of μm.Referring to FIGS. 2A to 3, in the case of a general pattern layer, after a superposition key is formed in a scribe lane (S / L) and a superposition photolithography process is performed, when alignment is confirmed normally, a target process may be performed by returning this result to a subsequent batch. However, in the case of a TSV, although overlay measurement is performed by measuring an actually used TSV because an overlay pattern may not be formed in the S / L, because the TSV has a small size, it is difficult to perform normal alignment measurement due to a small interval between the TSV and the pattern of the underlying layer.In particular, the overall size of the BIB overlay key of FIG. 2A may have dimensions of about 16.6 μm x about 16.6 μm. Here, the total size of the BIB overlay key may be defined as the size of the outer box. In the cell patterns including the TSVs each having diameters of 7 μm, 5 μm, and 4 μm in FIGS. 2B to 2D, the total sizes of surrounding patterns (hereinafter, each referred to as "TSV surrounding pattern") that can be used for TSV overlay measurements each have dimensions of about 15.8 μm×about 15.8 μm, about 9 μm×about 9 μm, and about 6.3 μm x about 6.3 μm. Here, the total size of a pattern surrounding TSV may be defined as the size of a distinguishable rectangle in an outermost portion thereof.As can be seen from FIG. 2B and the graph of FIG. 3, in the case of the cell pattern including the TSV having a diameter of 7 μm, the overall size of the pattern surrounding TSV is similar to the size of the BIB overlay key, and the TSV can be clearly distinguished from rectangles outside thereof. Accordingly, similar to the BIB overlay key, overlay measurement can be performed using the pattern surrounding the TSV. On the other hand, as can be seen from FIGS. 2C and 2D and the graph of FIG. 3, in the case of the cell patterns including the TSVs having diameters of 5 μm and 4 μm, respectively, the sizes of the TSV surrounding patterns are reduced as much as 46.8% and 62.1%, respectively, compared to the size of the BIB overlay key, and each TSV is not clearly distinguished from rectangles outside thereof. Accordingly, in the case of the cell patterns including the TSV having diameters of 5 μm and 4 μm, overlay measurement using the TSV surrounding pattern may be difficult, and a result thereof may include a large error range.Therefore, when the size of the second TSV 110 awhich is an operating TSV is small, for example, when the size of the second TSV 110 ais smaller than 7 μm, the TSV key OTK 1 of the present example embodiment including the first TSV 110 may be formed separately from the second TSV 110 ain a semiconductor device chip for overlay measurement extra or intentionally. In addition, the TSV key OTK 1 of the present example embodiment may be disposed at different locations in the semiconductor device chip. Arrangement positions of the TSV key OTK 1 in the semiconductor device chip will be described in more detail below with reference to FIGS. 14A and 14B.FIGS. 4A to 13 are plan and cross-sectional views of the TSV keys according to an example embodiment. FIGS. 4B, 5B, 6B, 7B, and 12B illustrate cross-sectional views taken along a line II-II' of FIG. 4A, a line III-III' of FIG. 5A, a line IV-IV' of FIG. 6A, a line V-V' of FIG. 7A, and a line VI-VI' of FIG. 12A, respectively. The descriptions already given with reference to FIGS. 1A to 3 are briefly given or omitted.Referring to FIGS. 4A and 4B, a TSV key OTK 2 of the present example embodiment may be different from the TSV key OTK 1 of FIG. 1A in the structures of the outer ring patterns 130 and 150. Specifically, the TSV key OTK 2 of the present example embodiment may include the first TSV 110, the inner ring pattern 120, and the outer ring patterns 130 and 150. The outer ring patterns 130 and 150 may include a lower outer ring pattern 130 and an upper outer ring pattern 150. The lower outer ring pattern 130 may be substantially the same as the outer ring pattern 130 of the TSV key OTK 1 of FIG. 1A. Accordingly, the lower outer ring pattern 130 may include a polysilicon film. However, the material of the lower outer ring pattern 130 is not limited to the polysilicon film.The upper outer ring pattern 150 may be formed on the lower outer ring pattern 130, and may extend through the interlayer dielectric 160 in the third direction (z direction) as shown in FIG. 4B. A top surface of the upper outer ring pattern 150 may be exposed by the interlayer dielectric 160. As shown in FIG. 4A, although the upper outer ring pattern 150 has a three-layered line shape, the shape of the upper outer ring pattern 150 is not limited thereto. For example, the upper outer ring pattern 150 may have a single-layer line shape. The upper outer ring pattern 150 may include a metal, e.g., tungsten (W). However, the material of the upper outer ring pattern 150 is not limited to W.The inner ring pattern 120 and the outer ring patterns 130 and 150 may form a second ring pattern RP 2. Similar to the TSV key OTK 1 of FIG. 1A, the first TSV 110 may be the inner measurement point IMP, and the inner ring pattern 120 in the second ring pattern RP 2 may be the outer measurement point OMP. In addition, the outer ring patterns 130 and 150 may function to prevent noise signals. According to an example embodiment, the outer ring patterns 130 and 150 may be omitted.Referring to FIGS. 5A and 5B, a TSV key OTK 3 of the example embodiment may be different from the TSV key OTK 1 of FIG. 1A in a structure of a third ring pattern RP 3. Specifically, the TSV key OTK 3 of the present example embodiment may include the first TSV 110 and the third ring pattern RP 3. The third ring pattern RP 3 may be formed as a ring pattern without separation between an inner ring pattern and an outer ring pattern.The third ring pattern RP 3 may be disposed separately from the first TSV 110 by the first interval S 1, and may have a rectangular ring shape. The first interval S 1 may be, for example, 2 μm or more. In addition, the third ring pattern RP 3 may have a third width W 3. In the TSV key OTK 3 of the present example embodiment, each of the first interval S 1 and the third width W 3 may be, for example, 2.175 μm. However, the first interval S 1 and the third width W 3 are not limited to the numerical value set forth above.The third ring pattern RP 3 may include a lower third ring pattern 120 aand an upper third ring pattern 130 a. The lower third ring pattern 120 amay have a structure inserted into the substrate 101. The lower third ring pattern 120 amay include an oxide film, for example. The structure and the material of the lower third ring pattern 120 aare not limited to the employed structure and the oxide film, respectively, set forth above. The upper third ring pattern 130 amay have a structure protruding upward from the substrate 101. The upper third ring pattern 130 amay include, for example, a polysilicon film. However, the structure and the material of the upper third ring pattern 130 aare not limited to the protruding structure and the polysilicon film, respectively, which are set forth above. According to the example embodiments, the third ring pattern RP 3 may include a ring pattern including three or more layers.In the TSV key OTK 3 of the present example embodiment, the first TSV 110 may be the inner measurement point IMP, and the third ring pattern RP 3 may be an outer measurement point OMP 1. For example, a rectangular portion along a dash-double-dot line surrounding the first TSV 110 may correspond to the inner measurement point IMP, and a rectangular portion along a dash-double-dot line marked at the center of the third ring pattern RP 3 may correspond to the outer measurement point OMP 1. In addition, since the third ring pattern RP 3 is formed as a ring pattern and functions as the outer measurement point OMP 1, the third ring pattern RP 3 may correspond to the inner ring pattern 120 of the TSV key OTK 1 of FIG. 1A in terms of functionality, and the TSV key OTK 3 may not include a portion corresponding to the outer ring pattern 130 of the TSV key OTK 1 of FIG. 1A. Accordingly, in the TSV key OTK 3 of the present example embodiment, a total size TKS 1 of the TSV key OTK 3 and a dummy exclusion size DES 1 of the TSV key OTK 3 may be substantially equal to each other, that is, may be 12.69 μm. However, the total size TKS 1 of the TSV key OTK 3 and the dummy exclusion size DES 1 of the TSV key OTK 3 are not limited to the numerical value set forth above.Referring to FIGS. 6A and 6B, a TSV key OTK 4 of the present example embodiment may be different from the TSV key OTK 1 of FIG. 1A in a structure of the fourth ring pattern RP 4. Specifically, the TSV key OTK 4 of the present example embodiment may include the first TSV 110 and the fourth ring pattern RP 4. The fourth ring pattern RP 4 may be formed as a ring pattern without separation between an inner ring pattern and an outer ring pattern.The fourth ring pattern RP 4 may be disposed apart from the first TSV 110 by a second interval S 2, and may have a rectangular ring shape. The second interval S 2 may be, for example, 4 μm or more. In addition, the fourth ring pattern RP 4 may have a second width W 2. For example, in the TSV key OTK 4 of the present example embodiment, the second interval S 2 may be 4.345 μm, and the second width W 2 may be 1 μm. However, the second interval S 2 and the second width W 2 are not limited to the numerical values set forth above.The fourth ring pattern RP 4 may be formed in a single layer and may have a structure protruding upward from the substrate 101. The fourth ring pattern RP 4 may include, for example, a polysilicon film. However, the structure and the material of the fourth ring pattern RP 4 are not limited to the protruding structure and the polysilicon film set forth above, respectively.In the TSV key OTK 4 of the present example embodiment, the first TSV 110 may be the inner measurement point IMP, and the fourth ring pattern RP 4 may be an outer measurement point OMP 2. For example, a rectangular portion along a dash-double-dot line surrounding the first TSV 110 may correspond to the inner measurement point IMP, and a rectangular portion along a dash-double-dot line marked in the center of the fourth ring pattern RP 4 may correspond to the outer measurement point OMP 2. However, since the width of the fourth ring pattern RP 4 is small, the entire fourth ring pattern RP 4 may correspond to the outer measurement point OMP 2.Also, in the TSV key OTK 4 of the present example embodiment, the fourth ring pattern RP 4 may correspond to the inner ring pattern 120 of the TSV key OTK 1 of FIG. 1A in terms of functionality, and the TSV key OTK 4 may not include a portion corresponding to the outer ring pattern 130 of the TSV key OTK 1 of FIG. 1A. Accordingly, in the TSV key OTK 4 of the present example embodiment, the total size TKS of the TSV key OTK 4 and a dummy exclusion size DES 2 of the TSV key OTK 4 may be substantially equal to each other, that is, 14.69 μm. The total size TKS of the TSV key OTK 4 and the dummy exclusion size DES 2 of the TSV key OTK 4 are not limited to the numerical value set forth above.Referring to FIGS. 7A and 7B, a TSV key OTK 5 of the present example embodiment may be different from the TSV key OTK 4 of FIGS. 6A and 6B in a structure of a fifth ring pattern RP 5. Specifically, the TSV key OTK 5 of the present example embodiment may include the first TSV 110 and the fifth ring pattern RP 5. The fifth ring pattern RP 5 may be formed as a ring pattern without separation between an inner ring pattern and an outer ring pattern.The fifth ring pattern RP 5 may be disposed separately from the first TSV 110 by the second interval S 2, and may have a rectangular ring shape. The second interval S 2 may be, for example, 4 μm or more. In addition, the fifth ring pattern RP 5 may have a second width W 2. For example, in the TSV key OTK 5 of the present example embodiment, the second interval S 2 may be 4.345 μm, and the second width W 2 may be 1 μm. However, the second interval S 2 and the second width W 2 are not limited to the numerical values set forth above.The fifth ring pattern RP 5 may include a lower fifth ring pattern 120 band an upper fifth ring pattern 130 b. The lower fifth ring pattern 120 bmay have a structure inserted into the substrate 101. The lower fifth ring pattern 120 bmay include an oxide film, for example. However, the structure and the material of the fifth ring pattern 120 bare not limited to the employed structure and the oxide film, respectively, set forth above. The upper fifth ring pattern 130 bmay have a structure protruding upward from the substrate 101. The upper fifth ring pattern 130 bmay include, for example, a polysilicon film. However, the structure and material of the upper fifth ring pattern 130 bare not limited to the protruding structure and the polysilicon film set forth above, respectively. According to the example embodiments, the fifth ring pattern RP 5 may include a ring pattern including three or more layers.In the TSV key OTK 5 of the present example embodiment, the first TSV 110 may be the inner measurement point IMP, and the fifth ring pattern RP 5 may be the outer measurement point OMP 2. For example, a rectangular portion along a dash-double-dot line surrounding the first TSV 110 may correspond to the inner measurement point IMP, and a rectangular portion along a dash-double-dot line marked at the center of the fifth ring pattern RP 5 may correspond to the outer measurement point OMP 2. However, since the width of the fifth ring pattern RP 5 is small, the entire fifth ring pattern RP 5 may correspond to the outer measurement point OMP 2.In the TSV key OTK 5 of the present example embodiment, the fifth ring pattern RP 5 may correspond to the inner ring pattern 120 of the TSV key OTK 1 of FIG. 1A in terms of functionality, and the TSV key OTK 5 may not include a portion corresponding to the outer ring pattern 130 of the TSV key OTK 1 of FIG. 1A. Accordingly, in the TSV key OTK 5 of the example embodiment, the total size TKS of the TSV key OTK 5 and the dummy exclusion size DES 2 of the TSV key OTK 5 may be substantially equal to each other, that is, may be 14.69 μm. The total size TKS of the TSV key OTK 5 and the dummy exclusion size DES 2 of the TSV key OTK 5 are not limited to the numerical value set forth above.Referring to FIG. 8, a TSV key OTK 6 of the present example embodiment may be different from the TSV key OTK 4 or OTK 5 of FIG. 6A or 7A in terms of a material of a sixth ring pattern RP 6. Specifically, the TSV key OTK 6 of the present example embodiment may include the first TSV 110 and the sixth ring pattern RP 6. In addition, the sixth ring pattern RP 6 may be formed as a ring pattern without separation between an inner ring pattern and an outer ring pattern.The sixth ring pattern RP 6 may be formed in a single layer, like the fourth ring pattern RP 4 of the TSV key OTK 4 of FIG. 6A, and may include a metal film such as W. In addition, the sixth ring pattern RP 6 may also be formed in bilayers, as the fifth ring pattern RP 5 of the TSV key OTK 5 of FIG. 7A. In such a case, a lower sixth ring pattern may include an oxide film, and an upper sixth ring pattern may include a metal film such as W. In addition, according to the example embodiments, the sixth ring pattern RP 6 may include a ring pattern including three or more layers. In such a case, an uppermost layer of the ring pattern may comprise a metal film such as W. However, the material of the metal film is not limited to W.The sixth ring pattern RP 6 of the TSV key OTK 6 of the present example embodiment may have a structure covered by the interlayer dielectric 160. However, according to the example embodiments, the sixth ring pattern RP 6 may extend through the interlayer dielectric 160. Accordingly, a top surface of the sixth ring pattern RP 6 may be exposed through the interlayer dielectric 160.In addition, the descriptions regarding an interval of the sixth ring pattern RP 6 of the first TSV 110, the width of the sixth ring pattern RP 6, an inserted or protruding structure of the sixth ring pattern RP 6, inner and outer measurement points in the TSV key OTK 6, the total size and the dummy exclusion size of the TSV key OTK 6, and the like are the same as described regarding the TSV key OTK 4 or OTK 5 of FIG. 6A or 7A.Referring to FIG. 9, a TSV key OTK 7 of the present example embodiment may be different from the TSV key OTK 6 of FIG. 8 in a structure of a seventh ring pattern RP 7. Specifically, the TSV key OTK 7 of the present example embodiment may include the first TSV 110 and the seventh ring pattern RP 7. The seventh ring pattern RP 7 may have a structure in which quadrangular fine patterns are arranged separately from each other and collectively form a rectangular ring shape. Each of the fine patterns constituting the seventh ring pattern RP 7 may include a metal film such as W. However, the material of each fine pattern is not limited to the metal film. Each of the fine patterns is not limited to the quadrangular shape, and may have a circular shape, an elliptical shape, or a polygonal shape.The seventh ring pattern RP 7 may be arranged separately from the first TSV 110 by the second interval S 2, e.g., as determined at an inner edge of the fine patterns. The second interval S 2 may be, for example, 4 μm or more. In addition, each of the fine patterns constituting the seventh ring pattern RP 7 may have a second width W 2, and the second width W 2 may be, for example, 1 μm. The second interval S 2 and the second width W 2 are not limited to the numerical values set forth above. The seventh ring pattern RP 7 of the TSV key OTK 7 of the present example embodiment may have a structure covered by the interlayer dielectric 160. However, according to the example embodiments, the seventh ring pattern RP 7 may extend through the interlayer dielectric 160. Accordingly, a top surface of the seventh ring pattern RP 7, that is, top surfaces of the fine patterns may be exposed through the interlayer dielectric 160.In addition, the descriptions regarding an inserted or protruding structure of the seventh ring pattern RP 7, inner and outer measurement points in the TSV key OTK 7, the total size and the dummy exclusion size of the TSV key OTK 7, and the like are the same as described regarding the TSV key OTK 4 or OTK 5 of FIG. 6A or 7A.Referring to FIG. 10, a TSV key OTK 8 of the present example embodiment may be different from the TSV key OTK 7 of FIG. 9 in a structure of an eighth ring pattern RP 8. Specifically, the TSV key OTK 8 of the present example embodiment may include the first TSV 110 and the eighth ring pattern RP 8. The eighth ring pattern RP 8 may have a structure in which quadrangular fine patterns are arranged separately from each other and collectively form a rectangular ring shape. In addition, in the eighth ring pattern RP 8, the fine patterns may form a three-layer rectangular ring shape. However, in the eighth ring pattern RP 8, the rectangular ring shape is not limited to the three-layer structure by the fine patterns, and may have a two-layer structure or a four- or multi-layer structure. Each of the fine patterns constituting the eighth ring pattern RP 8 may include a metal film such as W. However, the material of each of the fine patterns is not limited to the metal film. Each of the fine patterns is not limited to the quadrangular shape, and may have a circular shape, an elliptical shape, or a polygonal shape. In addition, when the fine patterns have extremely fine sizes, the fine patterns can be treated as dots without distinguishing the shapes thereof.The eighth ring pattern RP 8 may be arranged separately from the first TSV 110 by a third interval S 3, e.g., as determined at an inner edge of the fine patterns. The third interval S 3 may be, for example, 3 μm or more. In addition, the entire width of the eighth ring pattern RP 8 may be a fourth width W 4, and the fourth width W 4 may be, for example, 2 μm. Further, each of the fine patterns constituting the eighth ring pattern RP 8 may have a width smaller than 0.5 μm. However, the third interval S 3, the fourth width W 4, and the widths of the fine patterns are not limited to the numerical values set forth above. The eighth ring pattern RP 8 of the TSV key OTK 8 of the present example embodiment may have a structure covered by the interlayer dielectric 160. However, according to the example embodiments, the eighth ring pattern RP 8 may extend through the interlayer dielectric 160. Accordingly, a top surface of the eighth ring pattern RP 8, that is, top surfaces of the fine patterns may be exposed through the interlayer dielectric 160.In the TSV key OTK 8 of the present example embodiment, the first TSV 110 may be the inner measurement point IMP, and the eighth ring pattern RP 8 may be an outer measurement point OMP 3. For example, a rectangular portion along a dash-double-dot line surrounding the first TSV 110 may correspond to the inner measurement point IMP, and a rectangular portion along a dash-double-dot line marked in the center of the eighth ring pattern RP 8 may correspond to the outer measurement point OMP 3.In addition, descriptions regarding an inserted or protruding structure of the eighth ring pattern RP 8, the total size and the dummy exclusion size of the TSV key OTK 8, and the like are the same as described regarding the TSV key OTK 4 or OTK 5 of FIG. 6A or 7A.Referring to FIG. 11, a TSV key OTK 9 of the present example embodiment may be different from the TSV key OTK 4, OTK 5, or OTK 6 of FIGS. 6A, 7A, or 8 in a structure of a ninth ring pattern RP 9. Specifically, the TSV key OTK 9 of the present example embodiment may include the first TSV 110 and the ninth ring pattern RP 9. The ninth ring pattern RP 9 may have a structure in which straight-line-shaped line patterns are arranged separately from each other and collectively form a rectangular ring shape. Each of the line patterns constituting the ninth ring pattern RP 9 may include an oxide film, a nitride film, an oxynitride film, a polysilicon film, or a metal film such as W. The material of each of the line patterns constituting the ninth ring pattern RP 9 is not limited to the materials set forth above. Each of the line patterns constituting the ninth ring pattern RP 9 may include a single layer or multiple layers.The ninth ring pattern RP 9 may be arranged separately from the first TSV 110 by the second interval S 2, and each of the line patterns constituting the ninth ring pattern RP 9 may have a second width W 2. The second interval S 2 may be, for example, 4 μm or more, and the second width W 2 may be, for example, 1 μm. However, the second interval S 2 and the second width W 2 are not limited to the numerical values set forth above. The ninth ring pattern RP 9 of the TSV key OTK 9 of the present example embodiment may have a structure covered by the interlayer dielectric 160. However, according to the example embodiments, the ninth ring pattern RP 9 may extend through the interlayer dielectric 160. Accordingly, a top surface of the ninth ring pattern RP 9, that is, top surfaces of the line patterns may be exposed through the interlayer dielectric 160.In addition, descriptions regarding an inserted or protruding structure of the ninth ring pattern RP 9, inner and outer measurement points in the TSV key OTK 9, the total size and dummy exclusion size of the TSV key OTK 9, and the like are the same as described regarding the TSV key OTK 4 or OTK 5 of FIG. 6A or 7A.Referring to FIGS. 12A and 12B, a TSV key OTK 10 of the present example embodiment may be different from the TSV key OTK 1 of FIG. 1A in a structure of a tenth ring pattern RP 10. Specifically, the TSV key OTK 10 of the present example embodiment may include the first TSV 110, an inner tenth ring pattern RP 10in, and an outer tenth ring pattern RP 10out. In addition, as shown in FIG. 12A, the inner tenth ring pattern RP 10in and the outer tenth ring pattern RP 10out each have rectangular ring patterns and may be arranged separately from each other. For example, the inner tenth ring pattern RP 10in may be arranged separately from the first TSV 110 by the first interval S 1. In addition, the outer tenth ring pattern RP 10out may be disposed separately from the inner tenth ring pattern RP 10in by the first interval S 1 while surrounding the inner tenth ring pattern RP 10in. The first interval S 1 may be 2 μm or more. Each of the inner tenth ring pattern RP 10in and outer tenth ring pattern RP 10out may have a second width W 2. In the TSV key OTK 10 of the present example embodiment, the first interval S 1 may be 2.175 μm, and the second width W 2 may be about 1 μm. However, the first interval S 1 and the second width W 2 are not limited to the numerical values set forth above.As shown in FIG. 12B, the inner tenth ring pattern RP 10in may include a lower inner tenth ring pattern 120in and an upper inner tenth ring pattern 130in. In addition, the outer tenth ring pattern RP 10out may include a lower outer tenth ring pattern 120out and an upper outer tenth ring pattern 130out.The lower inner tenth ring pattern 120 inand the lower outer tenth ring pattern 120 outmay have the same structure in a cross-sectional view and may include the same material. For example, each of the lower inner tenth ring pattern 120 inand the lower outer tenth ring pattern 120 outmay have an inserted structure and may include an oxide film. However, the structure and the material of each of the lower inner tenth ring pattern 120 inand the lower outer tenth ring pattern 120 outare not limited to the inserted structure and the oxide film, respectively. In addition, the upper inner tenth ring pattern 130in and the upper outer tenth ring pattern 130out may be formed in protruding structures on the lower inner tenth ring pattern 120in and the lower outer tenth ring pattern 120out, respectively, corresponding thereto, respectively, and may include polysilicon films, respectively. However, the structure and the material of each of the upper inner tenth ring pattern 130 inand upper outer tenth ring pattern 130 outare not limited to the above structure and the polysilicon film.According to the example embodiments, the upper inner tenth ring pattern 130 inand the upper outer tenth ring pattern 130 outmay each include a metal film such as W. According to the example embodiments, the upper inner tenth ring pattern 130 inand the upper outer tenth ring pattern 130 outmay extend through the interlayer dielectric 160, and accordingly, top surfaces of the upper inner tenth ring pattern 130 inand the upper outer tenth ring pattern 130 outmay be exposed through the interlayer dielectric 160. According to the example embodiments, the upper inner tenth ring pattern 130 inand the upper outer tenth ring pattern 130 outmay each have a structure covered by the interlayer dielectric 160. According to the example embodiments, the inner tenth ring pattern RP 10in and the outer tenth ring pattern RP 10out may each have a ring pattern structure including three or more layers. In such a structure, an uppermost ring pattern may be covered by the interlayer dielectric 160 or may extend through the interlayer dielectric 160 to have a top surface exposed by the interlayer dielectric 160.In the TSV key OTK 10 of the present example embodiment, the first TSV 110 may be the inner measurement point IMP, and a middle portion, e.g., a center line between the inner tenth ring pattern RP 10in and the outer tenth ring pattern RP 10out, may be an outer measurement point OMP 4. Specifically, a rectangular portion along a dash-double-dot line surrounding the first TSV 110 may correspond to the inner measurement point IMP, and a rectangular portion along a dash-double-dot line marked in the middle portion between the inner tenth ring pattern RP 10in and the outer tenth ring pattern RP 10out may correspond to the outer measurement point OMP 4.As described above, the inner tenth ring pattern RP 10in and the outer tenth ring pattern RP 10out may form the tenth ring pattern RP 10. In addition, a portion between the inner tenth ring pattern RP 10in and the outer tenth ring pattern RP 10out may be the outer measurement point OMP 4, and the outer tenth ring pattern RP 10out may function to prevent noise signals.According to the example embodiments, the outer tenth ring pattern RP 10out may be omitted.In the TSV key OTK 10 of the present example embodiment, assuming that the outer tenth ring pattern RP 10out is included, the first diameter D 1 is 4 μm, the first interval S 1 is 2.175 μm, and the second width W 2 is 1 μm, the total size TKS of the TSV key OTK 10 may be about 16.69 μm. When the outer tenth ring pattern RP 10out is excluded, a dummy exclusion size DES 3 of the TSV key OTK 10 may be about 14.69 μm. In addition, the width ACTS of the active layer disposed inside the inner tenth ring pattern RP 10in to surround the first TSV 110 may be about 8.35 μm. However, the total size TKS of the TSV key OTK 10, the dummy exclusion size DES 3 of the TSV key OTK 10, and the width ACTS of the active layer are not limited to the numerical values set forth above, respectively.Referring to FIG. 13, a TSV key OTK 11 of the example embodiment may be different from the TSV key OTK 10 of FIG. 12A in a structure of an eleventh ring pattern RP 11. Specifically, the TSV key OTK 11 of the present example embodiment may include the first TSV 110, an inner eleventh ring pattern RP 11in, and an outer eleventh ring pattern RP 11out. In addition, as shown in FIG. 13, each of the inner eleventh ring pattern PP 11in and outer eleventh ring pattern RP 11out may have a structure in which straight-line-shaped line patterns are arranged separately from each other and collectively form a rectangular ring shape. For example, the line patterns constituting the inner eleventh ring pattern RP 11in may be arranged separately from the first TSV 110 by the first interval S 1. In addition, the line patterns constituting the outer eleventh ring pattern RP 11out may be arranged separately from the corresponding line patterns constituting the inner eleventh ring pattern RP 11in by the first interval S 1 while surrounding the inner eleventh ring pattern RP 11in. The first interval S 1 may be 2 μm or more. The line patterns constituting each of the inner eleventh ring pattern RP 11in and outer eleventh ring pattern RP 11out may each have a second width W 2. In the TSV key OTK 11 of the present example embodiment, the first interval S 1 may be 2.175 μm, and the second width W 2 may be about 1 μm. However, the first interval S 1 and the second width W 2 are not limited to the numerical values set forth above.Each of the line patterns constituting the eleventh ring pattern RP 11 may include an oxide film, a nitride film, an oxynitride film, a polysilicon film, or a metal film such as W. The material of each of the line patterns constituting the eleventh ring pattern RP 11 is not limited to the materials set forth above. Each of the line patterns constituting the eleventh ring pattern RP 11 may include a single layer or multiple layers.The eleventh ring pattern RP 11 of the TSV key OTK 11 of the present example embodiment may have a structure covered by the interlayer dielectric 160. However, according to the example embodiments, the eleventh ring pattern RP 11 may extend through the interlayer dielectric 160. Accordingly, a top surface of the eleventh ring pattern RP 11, that is, top surfaces of the line patterns may be exposed by the interlayer dielectric 160.In addition, descriptions regarding an inserted or protruding structure of the eleventh ring pattern RP 11, inner and outer measurement points in the TSV key OTK 11, the total size and dummy exclusion size of the TSV key OTK 11, and the like are the same as described regarding the TSV key OTK 10 of FIG. 12A.FIGS. 14A and 14B are a plan view and a partial cross-sectional view, respectively, of a semiconductor device including a TSV key according to an example embodiment. The descriptions already given with reference to FIGS. 1A to 13 are briefly given or omitted.Referring to FIGS. 14A and 14B, a semiconductor device 100 including a TSV key (which will be referred to simply as a "semiconductor device" hereinafter) according to the present example embodiment may include a cell area CA and a periphery area PA. Various storage devices may be disposed in the cell area CA. For example, various memory devices such as a flash memory, a dynamic random access memory (DRAM), a static random access memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), a phase change random access memory (PRAM), a magneto-resistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), and a resistive random access memory (RRAM) may be disposed in the cell area CA.A peripheral circuit for operations of memory cells and / or a core circuit for computations and the like may be disposed in the peripheral area PA. All remaining areas except the cell area CA may refer to the peripheral area PA. However, according to the example embodiments, the peripheral area PA may be classified into a peripheral area in which peripheral circuits are arranged and a core area in which a core circuit is arranged. In addition, generally, a peripheral circuit surface may be disposed in an outer portion or a central portion of a chip, and the core circuit surface may be disposed between the cell surfaces CA. Hereinafter, the peripheral button and the core button will be collectively referred to as the peripheral button PA without distinctions therebetween.The semiconductor device 100 of the present example embodiment may include a plurality of TSVs 110 and 110 ain the peripheral surface PA. The TSVs 110 and 110 amay include a first TSV 110 included in the TSV key and a second TSV 110 athat is actually operated as a through electrode. The first TSV 110, along with a ring pattern, may be used for overlay measurement of a TSV as described with respect to the TSV key OTK 1 of FIG. 1A. In FIG. 14A, the first TSV 110 indicated by * may be disposed in an arbitrary area of the peripheral surface PA. Accordingly, the first TSV 110 may be disposed in the peripheral area PA in the central portion of the chip, in the peripheral area PA between the cell areas CA, in the peripheral area PA in an outermost portion of the chip, or the like. On the other hand, the second TSV 110 amay be arranged in a two-dimensional matrix structure in the peripheral surface PA in the central portion of the chip. However, the arrangement position of the second TSV 110 ais not limited to the peripheral area PA in the central portion of the chip.The semiconductor device 100 of the present example embodiment may include the substrate 101, an integrated circuit layer 105, a multi-wiring layer 170, a protective insulating layer 180, an external terminal 195, and a TSV key OTK. Descriptions regarding the substrate 101 are the same as those regarding the TSV key OTK 1 of FIG. 1A. Various memory devices may be disposed in the integrated circuit layer 105. For example, the semiconductor device 100 of the present example embodiment may be a DRAM memory device, and a plurality of DRAMs may be disposed in the integrated switching layer 105. The multi-wiring layer 170 may include an interlayer dielectric 172 and a wiring line 174. The protective insulating layer 180 may include an upper protective insulating layer 182 and a lower protective insulating layer 184. The external terminal 195 may be disposed on a pad 192 connected to the wiring line 174. The external terminal 195 may include both a pillar and a solder, or may include only a solder.The TSV key OTK may include a TSV 110 or 110 aand a first ring pattern RP 1. The TSV 110 or 110 amay extend through the substrate 101. The TSV 110 or 110 amay be the first TSV 110 or the second TSV 110 a. In other words, the TSV key OTK may be implemented by initially forming the first TSV 110 that is not operated and the ring pattern RP 1, or may be implemented by forming only the first ring pattern RP 1 around the second TSV 110 awhich is an operated TSV. One end of the TSV 110 or 110 amay be connected to a wiring line 171, e.g., an M 1 wiring line, and the other end may be connected to a lower pad 115 and a lower pad 115, respectively. According to example embodiments, the bottom pad 115 may be omitted when the TSV 110 or 110 ais the first TSV 110. The TSV 110 is not connected to the M 1 wiring line. Descriptions regarding the first ring pattern RP 1 are the same as those regarding the TSV key OTK 1 of FIG. 1A. In addition, the TSV key OTK may include the second to eleventh ring patterns RP 2 to RP 11 among the TSV keys OTK 2 to OTK 11 in FIGS. 4A to 13B instead of the first ring pattern RP 1.As described above, the first TSV 110 may be formed together with the second TSV 110 awhich is a powered TSV. Accordingly, the first TSV 110 may be substantially the same as the second TSV 110 ain terms of a structure, a size, a material, and the like. However, according to the example embodiments, the first TSV 110 may be formed separately from the second TSV 110 a, and thus the first TSV 110 may be different from the second TSV 110 ain at least one of a structure, a size, and a material. In particular, a recent trend is that the size of the second TSV 110 ais increasingly ultrafine, and when the first TSV 110 is formed to have the same structure and size as those of the second TSV 110 a, the first TSV 110 cannot function as a TSV key. Accordingly, in an example embodiment, the first TSV 110 may be formed to a size determined separately from the second TSV 110 a. As a specific example, even when the diameter of the second TSV 110 ais reduced to less than 4 μm, the first TSV 110 may be formed to still have a diameter of 4 μm or more.FIG. 15 is a cross-sectional view of a semiconductor package including a TSV key according to an example embodiment. The descriptions already given with reference to FIGS. 1A to 14B are briefly given or omitted.Referring to FIG. 15, a semiconductor package 1000 of the present example embodiment may include a base chip 200, four semiconductor chips 100- 1 to 100- 4 on the base chip 200, and a sealant 400.The base chip 200 may be formed based on a semiconductor material such as a silicon (Si) wafer. However, according to the example embodiments, the base chip 200 may include a printed circuit board (PCB), a glass substrate, or the like, which does not include a semiconductor material. Hereinafter, the base chip 200 based on a semiconductor material will be mainly described. The base chip 200 may include a substrate 201, an upper protection layer 203, an upper pad 205, a device layer 210, and an external terminal 220. However, when the base chip 200 includes a PCB, a glass substrate, or the like that does not include a semiconductor material, the base chip 200 may not include the device layer 210.In the semiconductor package 1000 of the present example embodiment, the base chip 200 may be, for example, an interface chip including a plurality of logic devices and / or a plurality of storage devices in the device layer 210. Accordingly, the base chip 200 may transmit signals from the four semiconductor chips 100- 1 to 100- 4 stacked on the base chip 200 to the outside thereof, and may transmit a signal and power from the outside thereof to the four semiconductor chips 100- 1 to 100- 4. The base chip 200 may perform both a logic function and a memory function by the logic devices and the memory devices. However, according to example embodiments, the base chip 200 may include only the logic devices and thus perform only a logic function.In the semiconductor package 1000 of the example embodiment, the base chip 200 may include a second TSV 230. Accordingly, the base chip 200 may include a TSV key, and a first TSV 110 of the TSV key may be formed in the base chip 200. However, in FIG. 15, only the second TSV 230 corresponding to an operated TSV is illustrated for simplicity.Each of the four semiconductor chips 100- 1 to 100- 4 may be the semiconductor device 100 of FIG. 14A. The four semiconductor chips 100- 1 to 100- 4 may be stacked on the base chip 200 or a corresponding underlying semiconductor chip via an adhesive film 300 and the external terminal 195. A fourth semiconductor chip 100- 4 at an uppermost position among the four semiconductor chips 100- 1 to 100- 4 may not include the second TSV 110 a. Accordingly, only the three semiconductor chips 100- 1 to 100- 3 may include the TSV key OTK 1 including the first TSV 110 and the first ring pattern RP 1. In addition, although the three semiconductor chips 100- 1 to 100- 3 include both the first TSV 110 and the second TSV 110 a, only the second TSV 110 ais illustrated for simplicity.In the semiconductor package 1000 of the present example embodiment, although the four semiconductor devices 100- 1 to 100- 4 are stacked on the base chip 200, the number of the semiconductor chips stacked on the base chip 200 is not limited to four. For example, one to three or five or more semiconductor chips may be stacked on the base chip 200. In the semiconductor package 1000 of the present example embodiment, the base chip 200 may be an interface chip, and each of the four semiconductor chips 100- 1 to 100- 4 may be a DRAM chip. Accordingly, the semiconductor package 1000 of the present example embodiment may be a high-bandwidth memory (HBM) package.FIGS. 16A and 16B are a perspective view and a cross-sectional view, respectively, of a semiconductor device including a semiconductor package including a TSV key, according to an example embodiment. FIG. 16B is a cross-sectional view taken along a line VII-VII' of FIG. 16A. The descriptions already given with reference to FIG. 15 are briefly given or omitted.Referring to FIGS. 16A and 16B, a semiconductor device 10000 of the present example embodiment may include a semiconductor package 1000 a, an interposer 600, a processor chip 700, and a package substrate 500.The semiconductor package 1000 amay be the semiconductor package 1000 of FIG. 15. Accordingly, the semiconductor package 1000 amay include the base chip 200 and the four semiconductor chips 100- 1 to 100- 4, and the base chip 200 and the three semiconductor chips 100- 1 to 100- 3 may include the TSV key OTK 1 including the first TSV 110 and the first ring pattern RP 1, respectively.In the semiconductor device 10000 of the present example embodiment, four semiconductor packages 1000 amay be stacked on the interposer 600 using the external terminal 220 and the adhesive film 300. However, the number of semiconductor packages 1000 astacked on the interposer 600 is not limited to four. For example, one to three, or five or more semiconductor packages 1000 amay be stacked on the interposer 600.The interposer 600 may include a substrate 601, an upper protection layer 603, an upper pad 605, a wiring layer 610, a dent 620, and a through electrode 630. The semiconductor package 1000 aand the processor chip 700 may be stacked on the package substrate 500 via the medium of the interposer 600. The interposer 600 may electrically connect both the semiconductor package 1000 aand the processor chip 700 to the package substrate 500.The substrate 601 may include, for example, one of a silicon, an organic, a plastic, and a glass substrate. However, the material of the substrate 601 is not limited to the materials set forth above. When the substrate 601 is a silicon substrate, the interposer 600 may be referred to as a silicon interposer. In addition, when the substrate 601 is an organic substrate, the interposer 600 may be referred to as a panel interposer.The through electrode 630 may extend from a top surface to a bottom surface of the substrate 601 and thus penetrate the substrate 601. In addition, the through electrode 630 may extend in the wiring layer 610 and thus be electrically connected to the wiring lines of the wiring layer 610. When the substrate 601 includes silicon, the through electrode 630 may be referred to as a TSV. According to example embodiments, the interposer 600 may include only a wiring layer therein and may not include a through electrode.In the semiconductor device 10000 of the present example embodiment, the interposer 600 may be used to convert or transmit electrical signals input thereto between the package substrate 500 and the semiconductor package 1000 aor the processor chip 700. Accordingly, the interposer 600 may not include elements such as active elements or passive elements.The processor chip 700 may be a GPU / CPU / SOC chip. According to types of devices included in the processor chip 700, the semiconductor device 10000 may be classified into server-oriented semiconductor devices, mobile-oriented semiconductor devices, and the like.Although not shown, the semiconductor device 10000 may include an internal sealant covering side surfaces and top surfaces of the semiconductor package 1000 aand the processor chip 700 on the interposer 600. In addition, the semiconductor device 10000 may include an external sealant covering the interposer 600 and the internal sealant on the package substrate 500. According to the example embodiments, the inner sealant and the outer sealant may be formed together and thus cannot be distinguished from each other. In addition, according to the example embodiments, the inner sealant may only cover the top surface of the processor chip 700 and may not cover the top surface of the semiconductor package 1000 a.An external terminal 510, such as a solder ball, may be disposed below the package substrate 500. Accordingly, the semiconductor device 10000 may be mounted on another external board such as a system board or a motherboard via the external terminal 510.For comparison, a structure of the semiconductor device 10000 according to the present example embodiment is referred to as a 2.5D package structure, and the 2.5D package structure may be a relative concept with respect to a 3D package structure in which all semiconductor chips are stacked together and there is no interposer. Both the 2.5D package structure and the 3D package structure may be included in a system-in-package (SIP) structure. The semiconductor device 10000 of the present example embodiment may also be a type of semiconductor package. However, since the semiconductor device 10000 includes the semiconductor package 1000 alike the semiconductor device 1000 of FIG. 15, the term "semiconductor device" is given to the semiconductor device 10000 to make a terminology discrimination between the semiconductor device 10000 and the semiconductor package 1000 a. The same concept may be applied to a semiconductor device 10000 aof FIG. 17 as well below.FIG. 17 is a cross-sectional view of a semiconductor device including a semiconductor package including a TSV key according to an example embodiment. The descriptions already given with reference to FIG. 15 are briefly given or omitted.Referring to FIG. 17, a semiconductor device 10000 aof the present example embodiment may include semiconductor packages 1000 aand 1000 b, a logic chip 700 a, the package substrate 500, and the sealant 400.The two semiconductor packages 1000 aand 1000 bmay be stacked on the logic chip 700 ausing the external terminal 220 and the adhesive film 300. The two semiconductor packages 1000 aand 1000 bmay be the same semiconductor package. For example, each of the two semiconductor packages 1000 aand 1000 bmay be the semiconductor package 1000 of FIG. 15. Accordingly, each of the two semiconductor packages 1000 aand 1000 bmay include the base chip 200 and the four semiconductor chips 100- 1 to 100- 4, and the base chip 200 and the three semiconductor chips 100- 1 to 100- 3 may include the TSV key OTK 1 including the first TSV 110 and the first ring pattern RP 1, respectively. According to the example embodiments, the two semiconductor packages 1000 aand 1000 bmay be different from the semiconductor packages from each other. For example, one of the two semiconductor packages 1000 aand 1000 bmay be a semiconductor package including another type of memory chip such as an SRAM chip except a DRAM chip.The logic chip 700 amay be mounted on the package substrate 500. The logic chip 700 amay include various types of processor chips, such as GPU / CPU / SOC chips. The sealant 400 may include an inner sealant 400 aand an outer sealant 400 b. The inner sealant 400 amay cover the semiconductor packages 1000 aand 1000 bon the logic chip 700 a. In addition, the outer sealant 400 bmay cover the logic chip 700 aon the package substrate 500, the semiconductor packages 1000 aand 1000 b, and the inner sealant 400 a. The external terminal 510, such as a solder ball, may be disposed below the package substrate 500. Accordingly, the semiconductor device 10000 amay be mounted on another external board such as a system board or a mother board via the external connection terminal 510. In the semiconductor device 10000 aof the present example embodiment, since the logic chip 700 ais disposed on the package substrate 500 and the semiconductor packages 1000 aand 1000 bare stacked on the logic chip 700 a, the semiconductor device 10000 acan correspond to a 3D package structure.In summary and in summary, semiconductor devices comprising TSVs may be used in semiconductor packages, and overlay measurements may be performed between TSVs and lower layers in such semiconductor devices.As described above, the example embodiments may provide a through silicon via (TSV) key for overlay measurements, which enables to accurately measure overlay of a TSV and a semiconductor device including the TSV key.The example embodiments have been disclosed herein and, although specific terms are used, they are used and are to be interpreted in a generic and descriptive sense only and not for the purpose of limitation. In some examples, as will be apparent to one of ordinary skill in the art upon filing the present application, features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless specifically stated otherwise. Accordingly, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as set forth in the following claims.

Claims

A through silicon via (TSV) key for overlay measurements, the TSV key (OTK1 to OTK11) comprising: a first TSV (110) extending through at least a portion of a substrate (101) in a first direction that is perpendicular to a top surface of the substrate (101); and at least one ring pattern (RP1 to RP11) separate from the first TSV (110) and surrounding the first TSV (110) in a second direction that is parallel to the top surface of the substrate (101), wherein the at least one ring pattern (RP1 to RP11) is disposed in a layer that is below a top surface of the first TSV (110) in the first direction, wherein an inner measurement point (IMP) corresponds to the first TSV (110), an outer measurement point (OMP1 to OMP4) corresponds to the at least one ring pattern (RP1 to RP11), and the inner measurement point and the outer measurement point are arranged to provide an overlay measurement of a TSV, wherein the first TSV (110) is not electrically operated and is not connected to a wiring line (174), and wherein the inner measurement point (IMP) corresponds to an outer portion of the first TSV (110) and the outer measurement point (OMP) corresponds to at least one of an inner portion, a middle portion and an outer portion of the at least one ring pattern (RP1 to RP11).The TSV key (OTK1 to OTK11) according to claim 1, wherein: a horizontal cross section of the first TSV (110) perpendicular to the first direction has a circular shape, and the at least one ring pattern (RP1 to RP11) has a shape of a circular ring, an elliptical ring, or a polygonal ring surrounding the first TSV (110).The TSV key (OTK1 to OTK11) according to claim 2, wherein: the at least one ring pattern (RP1 to RP11) comprises two ring patterns (RP1 to RP11) arranged separately from or in contact with each other in the second direction, an outer portion of the first TSV (110) corresponds to the inner measurement point, when the two ring patterns (RP1 to RP11) are arranged separately from each other, a portion between the two ring patterns (RP1 to RP11) corresponds to the outer measurement point (OMP1 to OMP4), and when the two ring patterns (RP1 to RP11) are arranged in contact with each other, an inner ring pattern (120) corresponds to, which is closer to the first TSV ( 110), the outer measurement point (OMP 1 to OMP 4).The TSV key (OTK1 to OTK11) according to claim 1, wherein: the at least one ring pattern (RP1 to RP11) has a shape in which a plurality of fine patterns surrounds the first TSV (110), and the plurality of fine patterns forms a single-layer ring pattern line or a two- or multi-layer ring pattern line.The TSV key (OTK1 to OTK11) according to claim 1, wherein: a horizontal cross section of the first TSV (110) perpendicular to the first direction has a circular shape, and a diameter of the circular shape is less than 7 μm.The TSV key (OTK1 to OTK11) according to claim 1, wherein a distance between the first TSV (110) and the at least one ring pattern (RP1 to RP11) in the second direction is equal to or greater than 2 μm.The TSV key (OTK1 to OTK11) of claim 1, wherein the at least one ring pattern (RP1 to RP11) comprises at least one of a metal film, a polysilicon film, an oxide film, a nitride film, and an oxynitride film.The TSV key (OTK1 to OTK11) according to claim 1, wherein: the TSV key (OTK1 to OTK11) is formed in a chip, and the chip comprises the substrate (101) and a plurality of second TSVs (110a) penetrating at least a portion of the substrate (101) and electrically operated.A semiconductor device comprising: a substrate (101); an integrated circuit layer in the substrate (101); a multi-wiring layer on the integrated circuit layer; a silicon via (TSV) key configured for overlay measurements, the TSV key (OTK1 to OTK11) comprising: a first TSV (110) extending through at least a portion of the substrate (101) in a first direction perpendicular to the top surface of the substrate (101), and at least one ring pattern (RP1 to RP11) separated from the first TSV (110) and surrounding the first TSV (110) in a second direction parallel to the top surface of the substrate (101), wherein the at least one ring pattern (RP1 to RP11) is disposed in a layer that is below a top surface of the first TSV (110) in the first direction; and a plurality of second TSVs (110 a) extending through at least a portion of the substrate (101) in the first direction, wherein an inner measurement point (IMP) corresponds to the first TSV (110), an outer measurement point (OMP 1 to OMP 4) corresponds to the at least one ring pattern (RP 1 to RP 11), and the inner measurement point and the outer measurement point are arranged to provide an overlay measurement of a TSV, wherein the first TSV (110) is not electrically operated and is not connected to a wiring line (174), and wherein the inner measurement point (IMP) corresponds to an outer portion of the first TSV (110), and the outer measurement point (OMP) corresponds to at least one of an inner portion, a center portion and an outer portion of the at least one ring pattern (RP 1 to RP 11).The semiconductor device according to claim 9, wherein: a horizontal cross section of the first TSV (110) perpendicular to the first direction has a circular shape, and the at least one ring pattern (RP1 to RP11) has a shape of a circular ring, an elliptical ring, or a polygonal ring surrounding the first TSV (110).The semiconductor device according to claim 9, wherein: the at least one ring pattern (RP1 to RP11) comprises two ring patterns (RP1 to RP11), and the two ring patterns (RP1 to RP11) are arranged in contact with each other in the second direction.The semiconductor device according to claim 9, wherein: a horizontal cross section of the first TSV (110) perpendicular to the first direction has a circular shape, a diameter of the circular shape is less than 7 μm, and a distance between the first TSV (110) and the at least one ring pattern (RP1 to RP11) in the second direction is equal to or greater than 2 μm.The semiconductor device according to claim 9, wherein: the plurality of second TSVs (110a) are connected to a wiring line of the multi-wiring layer and electrically operated, and the first TSV (110) is larger in planar area than each of the second TSVs (110a) of the plurality of second TSVs (110a).A semiconductor package, comprising: a package substrate (500); and at least one semiconductor chip (100-1 to 100-4) stacked on the package substrate (500), wherein the at least one semiconductor chip (100-1 to 100-4) comprises: a semiconductor substrate; an integrated circuit layer in the semiconductor substrate; a multi-wiring layer on the integrated circuit layer; a silicon via (TSV) key configured for overlay measurements, the TSV key (OTK 1 to OTK 11) comprising: a first TSV (110) extending through at least a portion of the semiconductor substrate in a first direction perpendicular to a top surface of the semiconductor substrate, and at least one ring pattern (RP 1 to RP 11) separate from the first TSV (110) and surrounding the first TSV (110) in a second direction parallel to the top surface of the semiconductor substrate, wherein the at least one ring pattern (RP 1 to RP 11) is disposed in a layer below a top surface of the first TSV (110) in the first direction; and a plurality of the second TSVs (110 a) extending through at least a portion of the semiconductor substrate in the first direction, wherein an inner measurement point (IMP) corresponds to the first TSV (110), an outer measurement point (OMP 1 to OMP 4) corresponds to the at least one ring pattern (RP 1 to RP 11), and the inner measurement point and the outer measurement point are arranged to provide an overlay measurement of a TSV, wherein the first TSV (110) is not electrically operated and is not connected to a wiring line (174), and wherein the inner measurement point (IMP) corresponds to an outer portion of the first TSV (110), and the outer measurement point (OMP) corresponds to at least one of an inner portion, a center portion and an outer portion of the at least one ring pattern (RP 1 to RP 11).The semiconductor package according to claim 14, wherein: a horizontal cross section of the first TSV (110) perpendicular to the first direction has a circular shape, the at least one ring pattern (RP1 to RP11) has a shape of a circular ring, an elliptical ring, or a polygonal ring surrounding the first TSV (110), and the at least one ring pattern (RP1 to RP11) comprises one ring pattern (RP1 to RP11) or two ring patterns (RP1 to RP11).The semiconductor package according to claim 14, wherein: a horizontal cross section of the first TSV (110) perpendicular to the first direction has a circular shape, a diameter of the circular shape is less than 7 μm, and a distance between the first TSV (110) and the at least one ring pattern (RP1 to RP11) in the second direction is equal to or greater than 2 μm.The semiconductor package of claim 14, further comprising an interposer chip on the package substrate (500), wherein: the at least one semiconductor chip (100-1 to 100-4) comprises a dynamic random access memory (DRAM) chip, and the semiconductor package is a high memory bandwidth package (HBM).A through silicon via (TSV) key for overlay measurements, the TSV key (OTK1 to OTK11) comprising: a first TSV (110) on a substrate (101); and at least one ring pattern (RP1 to RP11) on the substrate (101), the at least one ring pattern (RP1 to RP11) having a shape that is separate from the first TSV (110) and surrounds the first TSV (110), wherein an inner measurement point (IMP) corresponds to the first TSV (110), an outer measurement point (OMP1 to OMP4) corresponds to the at least one ring pattern (RP1 to RP11), and the inner measurement point and the outer measurement point are arranged, To provide superposition measurement of a TSV, wherein the first TSV (110) is not electrically operated and is not connected to a wiring line (174), and wherein the inner measurement point (IMP) corresponds to an outer portion of the first TSV (110), and the outer measurement point (OMP) corresponds to at least one of an inner portion, a middle portion, and an outer portion of the at least one ring pattern (RP 1 to RP 11).The TSV key (OTK1 to OTK11) according to claim 18, wherein: the first TSV (110) has a circular shape, and the at least one ring pattern (RP1 to RP11) has a shape of a circular ring, an elliptical ring, or a polygonal ring surrounding the first TSV (110).

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