METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

Abstract

A method for manufacturing a semiconductor device comprising: preparing a substrate (12) from a compound semiconductor containing a first element and a second element connected to the first element, the second element having an electronegativity 1.5 or more lower than that of the first element; causing an electric current to flow in the substrate (12) between a front surface (12a) and a rear surface (12b); and dividing the substrate (12) at a position containing a current region in which the electric current is caused to flow, and along a cleavage plane of the substrate (12).

Description

The present invention relates to a method of manufacturing a semiconductor device.As a method for manufacturing a semiconductor device, various techniques for separating and connecting a substrate made of a compound semiconductor have been proposed. For example, JP 2019-126 838 A discloses a technique for cutting a substrate containing gallium oxide in a method of manufacturing a semiconductor device. In the manufacturing method, first, a laser beam is applied to the substrate along a planned cutting line to form a modified region along the planned cutting line of the substrate. The modified region is more brittle than the other regions of the substrate. Then, the substrate is cut along the planned cutting line by means of a cutter. In this manufacturing method, since the substrate is cut at the modified region formed along the intended cutting line, the substrate can be cut at a higher speed than in conventional cutting.In the manufacturing method according to JP 2019-126 838 A, the laser beam is applied along the intended cutting line of the substrate so that the width of the modified region is larger than the width of the cutting edge. Therefore, when the substrate is cut by the cutting edge, the modified region remains on the cut surface. Since the modified region is damaged by the laser beam, the cut surface is not uniform, which may affect the performance of the semiconductor device.WO 2020 / 098 401 A1 discloses a method for manufacturing a gallium oxide semiconductor structure, comprising: providing a gallium oxide single crystal wafer having an implantation surface; performing ion implantation from the implantation surface into the gallium oxide single crystal wafer so that implanted ions reach a preset depth and an implantation defect layer is formed at the preset depth; bonding the implantation surface to a high thermal conductivity substrate to obtain a first composite structure; performing annealing treatment on the first composite structure so that the gallium oxide single crystal wafer in the first composite structure is peeled off along the implantation defect layer, thereby obtaining a second composite structure and a third composite structure; and performing a surface treatment on the second composite structure to remove a first damaged layer to obtain a gallium oxide semiconductor structure including a first gallium oxide layer and the high thermal conductivity substrate.US 2005 / 0 272 224 A1 discloses a method for dividing a substrate, with which each substrate is divided into chips having the same square shape, which can form all cleaved facets flat. At this time, an electron beam having an intensity causing dislocation inside the substrate is irradiated on a substrate surface to generate a crack from such dislocation, and a cleaved facet is formed to divide the substrate.JP 2014-203 953 A discloses a method for manufacturing a semiconductor element, comprising: preparing a semiconductor wafer in which a plurality of light emitting elements are formed on a GaO wafer substrate having first and second main surfaces that are (-201) planes or (101) planes; bonding a first support plate to the second main surface of the GaO wafer substrate by a peelable bonding material; bonding a second support plate to the first main surface of the GaO wafer substrate by the peelable bonding material to form a laminate; and forming grooves from the second support plate of the laminate reaching the center of the first support plate by cutting with a blade and cutting the GaO wafer substrate to divide the plurality of light emitting elements into unit elements.DE 693 32 465 T2 discloses a method for slicing an oxidic single crystal wafer comprising a superconducting oxide layer applied on the surface, comprising: scribing the wafer such that a groove forms along a cutting line, and applying a bending moment to the wafer, wherein the groove is scribed on a crystal surface of the wafer and the wafer is locally heated in the groove by means of a Pt heating wire.JP 2004-148 438 A discloses a method for cutting a brittle material by forming a slot by means of electrical discharges. The slit thus formed is heated and a thermal stress is generated within the slit to cut the brittle material by conducting another electric discharge.An object of the present invention is to provide a technique for preventing damage to a substrate made of a compound semiconductor by efficiently performing division of the substrate. The object is achieved by a method for producing a semiconductor device having the features of claim 1. The dependent claims are directed to advantageous further developments of the invention.According to a first aspect of the present invention, a method of manufacturing a semiconductor device includes: preparing a substrate made of a compound semiconductor including a first element and a second element connected to the first element and having electronegativity smaller than that of the first element by 1.5 or more; causing an electric current to flow in the substrate between a front surface and a back surface; and dividing the substrate at a position including a current region in or to which the electric current is caused to flow and along a gap plane.Electronegativity is a value indicating the ability of an atom in the molecule to attract an electron. In the present invention, electronegativity refers to Pauling electronegativity.In such a manufacturing method, the substrate is manufactured that is made of the compound semiconductor including the first element and the second element connected to the first element. It is known that when the difference in electronegativity between the first element and the second element is equal to or greater than 1.5, the connection between the first element and the second element exhibits a strong ionic connection. In a compound semiconductor exhibiting an ion-compound property, the charges generated when an electric current flows move within the compound semiconductor, so that the polarity within the crystal is likely to be easily disturbed. In addition, a thermal stress is likely to be generated by the flow of the electric current, and the crystal structure is likely to be easily destroyed. As described above, the crystal structure of the compound semiconductor having an ion-compound property is likely to change by causing the electric current to flow therethrough. In the manufacturing method, using this property, the electric current is caused to flow in the substrate made of the compound semiconductor having the ion-compound property to divide the substrate along the cleavage plane of the substrate. According to this manufacturing method, the substrate can be divided efficiently while avoiding damage to the divided surface.Features and advantages of the present invention will become apparent from the following detailed description with reference to the accompanying drawings, in which like parts are denoted by like reference numerals. The following are shown: FIG. 1 is a plan view of a semiconductor substrate in a manufacturing method according to a first embodiment; FIG. 2 is a cross-sectional view showing a process for introducing a dopant into the semiconductor substrate; FIG. 3 is a cross-sectional view showing a process for causing an electric current to flow through the semiconductor substrate; FIG. 4 is a cross-sectional view showing a state in which the semiconductor substrate is divided; FIG. 5 is a cross-sectional view showing a process of disposing an electrode on a semiconductor substrate in a manufacturing method according to a second embodiment; FIG. 6 is a cross-sectional view showing a state in which the semiconductor substrate is divided; FIG. 7 is a cross-sectional view showing a process of dividing a semiconductor substrate along a plane direction of the semiconductor substrate in a manufacturing method according to a modified example; FIG. 8 is a cross-sectional view showing a process of implanting ions into the surface of a semiconductor substrate in a manufacturing method according to a non-inventive embodiment; FIG. 9 is a cross-sectional view showing a process of stacking semiconductor substrates one on another; and FIG. 10 is a cross-sectional view showing a process for causing an electric current to flow through the semiconductor substrates.Hereinafter, embodiments of the present invention will be described with reference to the technical elements listed below. The following technical elements may be useful even when used independently.In an embodiment of the present invention, a method of manufacturing a semiconductor device includes the steps of: preparing a substrate made of a compound semiconductor including a first element and a second element connected to the first element and having electronegativity smaller than that of the first element by 1.5 or more; causing an electric current to flow in the substrate; and dividing the substrate at a position including a current region to which the electric current is caused to flow and along a cleavage plane of the substrate.Electronegativity is a value indicating the ability of an atom in a molecule to attract an electron. In the present invention, electronegativity refers to Pauling electronegativity.In such a manufacturing method, the substrate is manufactured that is made of the compound semiconductor including the first element and the second element connected to the first element and having electronegativity smaller than that of the first element by 1.5 or more. It is known that when the difference in electronegativity between the first element and the second element is 1.5 or more, the connection between the first element and the second element exhibits an ion-connecting property. In the compound semiconductor exhibiting the ion-compound property, the charges generated due to the flow of an electric current move within the compound semiconductor, so that the polarity within the crystal is likely to be easily disturbed. In addition, a thermal stress is likely to be generated due to the flow of the electric current, and the crystal structure is likely to be easily disturbed. That is, the crystal structure of the compound semiconductor exhibiting an ion-compound property is likely to be changed due to the flow of the electric current. In the manufacturing method according to the embodiment, using this property, an electric current is caused to flow in the substrate so that the substrate is divided along a cleavage plane of the substrate. Accordingly, the substrate can be divided efficiently while preventing damage to the divided surface.According to an embodiment of the present invention, for example, in the step of causing the electric current to flow in the substrate in the manufacturing method, a probe may be brought into contact with the substrate, and the electric current may be caused to flow between the substrate and the probe.With such a configuration, a current range in which the electric current flows in the substrate can be controlled by adjusting the position at which the probe is brought into contact with the substrate. Accordingly, the substrate can be easily divided along a cleavage plane of the substrate.According to an embodiment of the present invention, the manufacturing method may further include a step of forming an electrode on a surface of the current region of the substrate. In the step of causing the electric current to flow in the substrate, the electric current in the substrate may be caused to flow through the electrode.With such a configuration, the current range in which the electric current flows in the substrate can be controlled by adjusting the position at which the electrode is formed. Consequently, the substrate can be easily divided along the cleavage plane of the substrate.According to an embodiment of the present invention, in the manufacturing method in the electrode forming step, the electrode may be formed along the gap plane on the surface of the current region.In such a configuration, the electrode is formed on the surface of the substrate along the cleavage plane. Therefore, the electric current can easily flow along the cleavage plane, and thus it is easy to apply stress locally along the cleavage plane.According to an embodiment of the present invention, the manufacturing method may further include a step of introducing a dopant or dissimilar material other than the compound semiconductor into the current region to increase the resistance of the current region to be greater than that of an environmental region in the vicinity of the current region.With such a configuration, by introducing the dopant or the dissimilar material into the current region in which the electric current is caused to flow, the resistance in the current region is increased to be larger than that in the peripheral region. Therefore, when the electric current is caused to flow, the temperature in the current region is likely to rise to be higher than that in the surrounding region, and thus a large thermal stress can be applied to the current region.According to an embodiment of the present invention, the manufacturing method may further include a step of introducing a dopant or a dissimilar material other than the compound semiconductor into the current region to increase a thermal resistance of the current region to be greater than that of an environmental region in the vicinity of the current region.In such a configuration, the resistance in the current region is increased to be larger than that in the surrounding region by introducing the dopant or the dissimilar material into the current region in which the electric current is caused to flow. Therefore, when the electric current is caused to flow, heat tends to easily become stagnant in the current region, and thus the temperature in the current region is likely to increase to be higher than that in the surrounding region. Consequently, a large thermal stress can be applied to the current region.According to an embodiment of the present invention, the compound semiconductor in the manufacturing method may be an oxide semiconductor, and the first element may be oxygen. In addition, the compound semiconductor may be made of β-Ga 2 O 3. The cleavage plane may be a (100) crystal plane and / or a (001) crystal plane of β-Ga 2 O 3.In the connection conductor made of β-Ga 2 O 3 a gap is likely to occur along the (100) crystal plane or the (001) crystal plane. When the substrate is divided along the (100) crystal plane or the (001) crystal plane of β-Ga 2 O 3 the substrate can be easily divided.Hereinafter, exemplary embodiments of the present invention will be described with reference to the first to third embodiments.First EmbodimentHereinafter, a method of manufacturing a semiconductor device 10 of a first embodiment will be described with reference to the drawings. In the manufacturing method of the first embodiment, the semiconductor device 10 is manufactured using a semiconductor substrate 12 in the wafer state as shown in FIG. 1. The manufacturing method of the first embodiment is characterized by a process of dividing the semiconductor substrate 12 made of a specific material as described later. This manufacturing method can be applied to various semiconductor devices using the specific material and their semi-finished products. Hereinafter, the process for dividing the semiconductor substrate 12 will be mainly described, and the description of the other manufacturing processes will be omitted.The semiconductor substrate 12 shown in FIG. 1 is made of a compound semiconductor. Specifically, the semiconductor substrate 12 is made of β-Ga 2 O 3. However, the material of the semiconductor substrate 12 is not limited to β-Ga 2 O 3. As a material of the semiconductor substrate 12, a compound semiconductor including a first element and a second element which are connected to each other and in which a difference in electronegativity between the first element and the second element is equal to or greater than 1.5 may be used. Generally speaking, it is simply necessary that the semiconductor substrate 12 be made of a material having an ion-bonding property. In the case of β-Ga 2 O 3 O corresponds to the first element and has an electronegativity of 3.44, and Ga corresponds to the second element and has an electronegativity of 1.81. The compound semiconductor constituting the semiconductor substrate 12 may also include an element different from the first element and the second element. Examples of the compound semiconductor constituting the semiconductor substrate 12 other than β-Ga 2 O 3 may include gallium oxide semiconductors such as (Ga, Rh) 2 O 3, ( Ga, Ir) 2 O 3, ( Ga, Bi) 2 O; and ZnGa 2 O 4 and other oxide semiconductors.In FIG. 1, a plane including an X direction and a Z direction corresponds to a (100) crystal plane of β-Ga 2 O 3, and a plane including a Y direction and the Z direction corresponds to a (001) crystal plane of β-Ga 2 O 3. In addition, a plane including the X direction and the Y direction, i.e., a plane along a surface 12 acorresponds to a (010) crystal plane of β-Ga 2 O 3. In other words, in FIG. 1, the Y direction corresponds to a crystal orientation of

[100] , the X direction corresponds to a crystal orientation of

[001] , and the Z direction corresponds to a crystal orientation of

[010] .As shown in FIG. 1, the semiconductor substrate 12 includes a plurality of element regions 30 each formed with a semiconductor device 10, and a plurality of planar division regions 32 around the respective element regions 30. The scheduled division areas 32 correspond to areas that are cut later. The element regions 30 are arranged in a lattice pattern along the X direction and the Y direction.In the manufacturing method of the first embodiment, first, a dopant is introduced into the semiconductor substrate 12 by ion implantation. In this case, the dopant is selectively introduced along the scheduled splitting regions 32, as shown in Fig. 2. The dopant to be introduced is not particularly limited, and Fe or V may be used, for example. As a result, as shown in FIG. 2, the dopant is introduced into the inside of the semiconductor substrate 12, and thus a high-resistance region 34 is formed. The high resistance region 34 has a higher resistance than a peripheral region due to the introduction of the dopant, i.e., a higher resistance than the element regions 30.Subsequently, as shown in FIG. 3, probes 16 are brought into contact with a front surface 12 aand a back surface 12 bof the semiconductor substrate 12. Here, each probe 16 is brought into contact with the semiconductor substrate 12 within the scheduled division region 32. As shown in FIG. 3, in this process in which the front surface 12 aand the rear surface 12 bof the semiconductor substrate 12 are provided, respectively, the probe 16 may be brought into contact with only one location within the scheduled division areas 32 or with multiple locations within the scheduled division areas 32. In addition, the probe 16 may be brought into contact with the front surface 12 aand the rear surface 12 bat locations other than the scheduled division regions 32.Subsequently, an electric current is caused to flow in the semiconductor substrate 12 via each probe 16 brought into contact with the semiconductor substrate 12. Since the dopant has been introduced into the high resistance region 34 within the scheduled splitting region 32, the high resistance region 34 has a higher resistance than a surrounding region thereof. Therefore, when the electric current is caused to flow in the substrate 12, the temperature of the high resistance region 34 rises to a higher temperature than in the surrounding region thereof. Accordingly, when the electric current is caused to flow in the substrate 12, a large thermal stress is applied to the high-resistance region 34. Since the semiconductor substrate 12 is made of a compound semiconductor exhibiting an ion-compound property, the polarity inside the crystal is likely to be disturbed when the electric current flows in the semiconductor substrate 12. Since the scheduled division region 32 is provided along the (100) plane and the (001) plane of β-Ga 2 O 3 a gap is likely to easily occur. For these reasons, in this process, when an electric power exceeding about 800 W / cm 2 for example is applied to the semiconductor substrate 12, the semiconductor substrate 12 may be divided along the scheduled division regions 32, as shown in FIG. 4. As a result, the semiconductor substrate 12 is divided into a plurality of semiconductor devices 10.Second EmbodimentIn a manufacturing method of a second embodiment, the technique that causes the electric current to flow in the semiconductor substrate 12 is different from that of the first embodiment. In the manufacturing method of the second embodiment, the process up to the process shown in FIG. 2 is the same as in the first embodiment. In the second embodiment, after the process shown in FIG. 2, an electrode 18 is formed on the surface 12 aof the semiconductor substrate 12 as shown in FIG. 5. In this case, the electrode 18 is formed along the scheduled division region 32 on the surface 12 aof the semiconductor substrate 12. The electrode 18 may be, for example, an electrode that forms a Schottky contact with the semiconductor substrate 12. The electrode 18 may be formed to cover the entire surface of the scheduled division region 32 on the surface 12 aof the semiconductor substrate 12, or may be intermittently formed on the surface of the scheduled division region 32 on the surface 12 aof the semiconductor substrate 12.Subsequently, an electric current in the semiconductor substrate 12 is caused to flow through the electrode 18 disposed on the surface 12 aof the semiconductor substrate 12. For example, an electric current may be caused to flow between the electrode 18 or the electrodes 18 and the back surface 12 bof the semiconductor substrate 12. By applying an electric power exceeding about 800 W / cm 2 to the semiconductor substrate 12, the semiconductor substrate 12 can be divided along the scheduled division regions 32 as in the first embodiment, as shown in FIG. 6. As a result, the semiconductor substrate 12 is divided into a plurality of semiconductor devices 10.As described above, in the manufacturing method of the first embodiment and the second embodiment, the semiconductor substrate 12 can be easily divided by applying the electric current to the semiconductor substrate 12 and flowing it through the semiconductor substrate 12, respectively. Therefore, the semiconductor substrate 12 can be divided within a short time as compared with, for example, the technique of cutting by a blade conventionally used for dividing the semiconductor substrate. In addition, in the above-described embodiments, the semiconductor substrate 12 can be divided at a low cost without requiring a blade or a cutting tape for protecting the surface of the semiconductor substrate during the cutting.In the above-described first and second embodiments, since the semiconductor substrate 12 is divided using the gap of the compound semiconductor caused by the electric current flowing through the semiconductor substrate 12, no damage is likely to occur on the cut surface. Therefore, the cut surfaces are substantially uniform, and the semiconductor devices 10 can be manufactured at high yield.In the first and second embodiments described above, the entire semiconductor substrate 12 is made of β-Ga 2 O 3. Alternatively, in the semiconductor substrate 12, only the scheduled division regions 32 may be made of β-Ga 2 O 3. That is, an area other than the scheduled division areas 32 (for example, the element areas 30 or the like) may include an element other than O and Ga.In addition, in the above-described embodiments, a current flow is caused between the front surface 12 aand the back surface 12 bof the semiconductor substrate 12. According to another example, two or more probes or two or more electrodes 18 may be arranged at arbitrary positions on the front surface 12 aof the semiconductor substrate 12, and electric current flow may be caused only in the vicinity of the front surface 12 aof the semiconductor substrate, i.e., in the surface layer portion adjacent to the front surface 12 a. Alternatively, the electric current may be similarly caused to flow only in the vicinity of the back surface 12 bof the semiconductor substrate 12 in a similar manner.In the first and second embodiments described above, the high resistance region 34 is formed by ion implantation of the dopant. The formation of the high resistance region 34 is not limited to the ion implantation of the dopant. The high resistance region 34 may be formed by introducing the dopant by epitaxial growth. According to another example, the resistance of the scheduled division region 32 can be increased by introducing a dissimilar material different from the material constituting the semiconductor substrate 12 into the scheduled division region 32. For example, instead of the process shown in FIG. 2, a groove may be formed by etching from the surface 12 aalong the scheduled division region 32, and the inside of the groove may be filled with a dissimilar material (for example, SiO 2 or the like). With such a configuration, it is possible to form a high resistance region 34 extending from the surface 12 aof the semiconductor substrate 12 to a predetermined depth (i.e., the depth of the groove).Moreover, in the first and second embodiments, the high resistance region 34 is formed by introducing the dopant. According to another example, a high thermal resistance region having a higher thermal resistance than an environmental region thereof may be formed by introducing a dopant. The high thermal resistance region may be formed by introducing a dissimilar material as described above. In the high thermal resistance region, when the electric current is caused to flow, the heat tends to be stagnant even more easily than in the surrounding region, and the temperature is likely to rise more than in the surrounding region. Therefore, a large thermal stress can also be applied by forming such a region of high thermal resistance. However, the high resistance region 34 and the high thermal resistance region described above do not need to be formed. That is, in the technique described herein, it is not always necessary to perform a process for introducing a dopant or dissimilar material. Even in such a configuration, the semiconductor substrate 12 can be divided along the cleavage plane by causing the electric current to flow through the semiconductor substrate 12.In the first and second embodiments, the process of dividing the semiconductor substrate 12 into the semiconductor devices 10 has been mainly described. Alternatively, the techniques described in the first and second embodiments may also be used, for example, for a step of thinning the semiconductor substrate 12. For example, as shown in FIG. 7, a high resistance region 40 is selectively formed to a desired depth by ion implantation of a dopant from the surface 12 aof the semiconductor substrate 12. Then, the probes 16 are brought into contact with the front surface 12 aand the back surface 12 bof the semiconductor substrate 12, and an electric current is caused to flow in the semiconductor substrate 12 through the probes 16, so that the semiconductor substrate 12 can be divided along the high resistance region 40. By setting the surface along the high resistance region 40 to the (100) plane or the (001) plane of β-Ga 2 O 3, that is, by setting the surface to be divided to the (100) plane or the (001) plane of β-Ga 2 O 3, the semiconductor substrate 12 can be divided even more easily. In this way, the semiconductor substrate 12 can be formed thinner.The formation of the high resistance region 40 is not limited to the ion implantation of the dopant. For example, when the semiconductor substrate 12 is formed by epitaxial growth in the step of manufacturing the semiconductor substrate 12, a semiconductor material containing the dopant may epitaxially grow at a depth to which the high-resistance region 40 is to be formed. In addition, the semiconductor substrate 12 having the high resistance region 40 may be manufactured using other materials.In the first and second embodiments described above, the semiconductor substrate 12 is divided along the scheduled division regions 32 by applying the electric power exceeding about 800 W / cm 2 to the semiconductor substrate 12. In this process, in the course of increasing the electric power applied to the semiconductor substrate 12, a groove is formed from the surface 12 aof the semiconductor substrate 12 in the thickness direction of the semiconductor substrate 12 along the scheduled division region 32. That is, the technique of the present invention is also useful as a technique for forming a groove on the surface 12 aof the semiconductor substrate 12.Noninventive EmbodimentA production method according to an embodiment not according to the invention is described below. The manufacturing method of this embodiment is characterized by a process of bonding two semiconductor substrates 52 and 54 each made of a specific material described later to each other. The manufacturing method of this embodiment can be used for various semiconductor devices made of the specific material and their semi-finished products. Hereinafter, the process for bonding the semiconductor substrates 52 and 54 to each other will be mainly described, and the description of the other manufacturing processes will be omitted. The semiconductor substrate 52 and the semiconductor substrate 54 are examples of a "first substrate" and a "second substrate".The semiconductor substrates 52 and 54 are made of compound semiconductors similar to those in the first and second embodiments. That is, the semiconductor substrates 52 and 54 are made of β-Ga 2 O 3. However, the material of the semiconductor substrates 52 and 54 is not limited to β-Ga 2 O 3. As the material of the semiconductor substrates 52 and 54, a compound semiconductor including a first element and a second element connected to each other, wherein a difference in electronegativity between the first element and the second element is equal to or greater than 1.5, may be used. Generally speaking, it is simply necessary that the semiconductor substrate 12 be made of a material having an ion-bonding property. In β-Ga 2 O 3 O corresponds to the first element and has an electronegativity of 3.44, and Ga corresponds to the second element and has an electronegativity of 1.81. The compound semiconductor constituting the semiconductor substrate 12 may also include an element other than the first element and the second element. Examples of the compound semiconductor constituting the semiconductor substrate 12 may include gallium oxide semiconductors such as (Ga, Rh) 2 O 3, ( Ga, Ir) 2 O 3, ( Ga, Bi) 2 O 3 and ZnGa 2 O 4 as well as other oxide semiconductors.As shown in FIG. 8, first, a dopant is introduced into a surface 52 aof the semiconductor substrate 52 by ion implantation. In this case, the dopant is introduced over the entire surface 52 aof the semiconductor substrate 52. As a result, a high resistance region 56 in which ions are implanted is formed in a region facing the surface 52 aof the semiconductor substrate 52, i.e., in a surface layer portion of the surface 52 aof the semiconductor substrate 52. Subsequently, as shown in FIG. 9, the semiconductor substrate 54 is stacked on the surface 52 aof the semiconductor substrate 52.Subsequently, the stacked semiconductor substrates 52 and 54 are subjected to heat treatment (annealing, annealing, or the like) in an atmosphere containing oxygen. The atmosphere containing oxygen means an atmosphere containing oxygen as an element. The semiconductor substrates 52 and 54 are subjected to the heat treatment in an atmosphere such as oxygen gas (O2gas). As a result, the interface 55 between the semiconductor substrate 52 and the semiconductor substrate 54 has high resistance. That is, in this process, the resistance is further increased in the region of and / or near the interface 55 of the semiconductor substrates 52 and 54 including the high-resistance region 56.Thereafter, an electric current is caused to flow between the semiconductor substrate 52 and the semiconductor substrate 54. Specifically, as shown in FIG. 9, probes 59 are brought into contact with the front surface 54 aof the semiconductor substrate 54 and the back surface 52 bof the semiconductor substrate 52. Then, the electric current in the semiconductor substrates 52 and 54 is caused to flow via the probes 59. The high resistance region 56 was formed in the surface 52 aof the semiconductor substrate 52. In addition, the resistance in the vicinity of the interface 55 between the semiconductor substrate 52 and the semiconductor substrate 54 was increased by the heat treatment. Therefore, when the electric current is caused to flow through the stack of the semiconductor substrates 52 and 54, the temperature near the interface 55 rises to a temperature higher than the surrounding area. As a result, a melted layer 60 in which the semiconductor material is melted is formed in the vicinity of the interface 55, and the crystal structure in the melted layer 60 is disturbed. When the flow of the electric current is stopped thereafter, the disordered crystal structures are rearranged in the course of solidification of the molten layer 60, and the semiconductor substrate 52 and the semiconductor substrate 54 can be bonded to each other. As described above, in the manufacturing method of this embodiment, the semiconductor substrates 52 and 54 can be easily connected to each other by causing an electric current to flow in the stacked semiconductor substrates 52 and 54.In this embodiment, the entire semiconductor substrates 52 and 54 are formed of β-Ga 2 O 3. According to another example, only the region near the front surface 52 aof the semiconductor substrate 52 and the region near the back surface 54 bof the semiconductor substrate 54, i.e., only the regions facing the connection surface, may be made of β-Ga 2 O 3.In this embodiment, the high resistance region 56 is formed by ion implantation of the dopant. According to another example, the high-resistance region 56 may be formed by epitaxially growing a semiconductor material containing a dopant on the surface 52 aof the semiconductor substrate 52. According to another example, the high resistance region 56 may be formed by forming a dissimilar material (for example, SiO 2 or the like) different from the material forming the semiconductor substrate 52 on the surface 52 a.In this embodiment, the high resistance region 56 is formed in the surface layer portion adjacent to the front surface 52 aof the semiconductor substrate 52. According to another example, the high resistance region may be formed in the surface layer portion adjacent to the back surface 54 aof the semiconductor substrate 54. In addition, the high resistance region 56 may be formed in both the surface layer portion adjacent to the front surface 52 aof the semiconductor substrate 52 and the surface layer portion adjacent to the back surface 54 aof the semiconductor substrate 54.In this embodiment, the high-resistance region 56 is formed by ion implantation. Alternatively or in addition to the high-resistance region 56, a high-thermal-resistance region having a higher thermal resistance than the surrounding region thereof may be formed by ion implantation. The high thermal resistance region may be formed by the dopant or dissimilar material as described above. In the high thermal resistance region, when the electric current is caused to flow, heat tends to become stagnant more easily than in the surrounding region, and the temperature is likely to rise more than in the surrounding region. Therefore, a large thermal stress can be formed by forming the high thermal resistance region. The high thermal resistance region may be formed in the surface layer portion near the front surface 52 aof the semiconductor substrate 52, may be formed in the surface layer portion near the back surface 54 aof the semiconductor substrate 54, or may be formed in the surface layer portions of both the semiconductor substrate 52 and the semiconductor substrate 54. Similarly, the thermal resistance of the interface 55 between the semiconductor substrate 52 and the semiconductor substrate 54 may be increased by heat treatment, alternatively or in addition to the process of increasing the resistance of the interface 55 by heat treatment. The high resistance region 56 and the high thermal resistance region described above do not need to be formed. That is, in the technique described herein, it is not always necessary to provide the step of introducing a dopant or dissimilar material. In addition, it is not always necessary to provide the step of heat treatment. Even in such a configuration, the semiconductor substrates 52 and 54 can be connected to each other by causing the electric current to flow between the semiconductor substrates 52 and 54.

Claims

A method of manufacturing a semiconductor device, comprising: preparing a substrate (12) of a compound semiconductor including a first element and a second element connected to the first element and having electronegativity smaller than that of the first element by 1.5 or more; causing an electric current to flow in the substrate (12) between a front surface (12a) and a back surface (12b); and dividing the substrate (12) at a position including a current range in which the electric current is caused to flow and along a cleavage plane of the substrate (12).The method of claim 1, wherein in causing the electric current to flow, a probe (16) is brought into contact with the substrate (12) to cause the electric current to flow between the substrate (12) and the probe (16).The method of claim 1, further comprising: forming an electrode (18) on the front surface (12a) of the current region, wherein in causing the electric current to flow, the electric current is caused to flow through the electrode (18) into the substrate (12).The method of claim 3, wherein in forming the electrode (18), the electrode (18) is formed on the front surface (12a) of the current region along the cleavage plane.The method of any one of claims 1 to 4, further comprising: increasing a resistance of the current region to greater than that of an environmental region in the vicinity of the current region by introducing a dopant or a dissimilar material different from the compound semiconductor into the current region.The method according to any one of claims 1 to 5, further comprising: increasing a thermal resistance of the current region to higher than that of an environmental region in the vicinity of the current region by introducing a dopant or a dissimilar material different from the compound semiconductor into the current region.The method according to any one of claims 1 to 6, wherein the compound semiconductor is an oxide semiconductor; and the first element is oxygen.The method according to claim 7, wherein the compound semiconductor is composed of β-Ga 2 O 3 and the cleavage plane is a (100) crystal plane and / or a (001) crystal plane of β-Ga 2 O 3.

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