Semiconductor device and power conversion device

Abstract

Semiconductor device (202), comprising: - a large number of semiconductor chips (5 HU , 5 HV , 5 HW , 5 LU , 5 LV , 5 LW ); - a large number of control connections (2, 2 H , 2 L ), which are associated with the multitude of semiconductor chips (5 HU , 5 HV , 5 HW , 5 LU , 5 LV , 5 LW are connected; - a large number of main connections (3, 3 HU , 3 HV , 3 HW , 3 LU , 3 LV , 3 LW , 3 P ), which are associated with the multitude of semiconductor chips (5 HU , 5 HV , 5 HW , 5 LU , 5 LV , 5 LW ) are connected and have a greater width than the control connections (2, 2 H , 2 L exhibit; and - a sealing resin (1) that seals the multitude of semiconductor chips (5 HU , 5 HV , 5 HW, 5LU , 5 LV , 5 LW ), parts of the multitude of control connections (2, 2 H , 2 L ) and parts of the multitude of main connections (3, 3 HU , 3 HV , 3 HW , 3 LU , 3 LV , 3 LW , 3 P ) sealed, wherein: - the sealing resin (1) is rectangular in plan view and has a first lateral surface (1a) and a second lateral surface (1b) which are opposite to each other, - the large number of control connections (2, 2 H , 2 L ) is led out of the first lateral surface (1a) of the sealing resin (1), - the large number of main connections (3, 3 HU , 3 HV , 3 HW , 3 LU , 3 LV , 3 LW , 3 P ) is led out of the second lateral surface (1b) of the sealing resin (1), - each of the main connections (3, 3 HU , 3HV , 3 HW , 3 LU , 3 LV , 3 LW , 3 P ) in the sealing resin (1) a bonding section (9 HU 9 HV 9 HW ), which is connected to one of the semiconductor chips (5 HU , 5 HV , 5 HW , 5 LU , 5 LV , 5 LW ) wire-connected, a heat transfer section (6 HU , 6 HV , 6 HW ), which corresponds to the bonding section (9 HU 9 HV 9 HW ) adjacent, and an assembly section (8 HU , 8 HV , 8 HW ) includes the other of the semiconductor chips (5 HU , 5 HV , 5 HW , 5 LU , 5 LV , 5 LW ) is mounted, - a concave section (10) on the second lateral surface (1b) between the adjacent main connections (3, 3 HU , 3 HV , 3 HW , 3 LU , 3 LV , 3 LW , 3P ) is arranged, - a lateral surface of the heat transfer section (6 HU , 6 HV , 6 HW ) opposite the concave section (10), - a lateral surface of the bonding section (9 HU 9 HV 9 HW ) is not opposite the concave section (10), - the large number of main connections (3, 3 HU , 3 HV , 3 HW , 3 LU , 3 LV , 3 LW , 3 P ) includes a P main connector (3P), a variety of high-side main connectors (3HU, 3HV, 3HW) and a variety of low-side main connectors (3LU, 3LV, 3LW), - a distance between the P main terminal (3 P ) and the high-side main connector (3 HU , 3 HV , 3 HW ), which are adjacent to each other, and a distance between the adjacent high-side main connections (3 HU , 3 HV , 3 HW) are greater than a distance between the adjacent low-side main connectors (3 LU , 3 LV , 3 LW ) and - the concave section (10) between the P main connection (3 P ) and the high-side main connector (3 HU , 3 HV , 3 HW ), which are adjacent to each other, and between the adjacent high-side main connections (3 HU , 3 HV , 3 HW ) is arranged.

Description

Background of the invention: Area

[0001] The present invention relates to a semiconductor device and a power conversion device. background

[0002] A sealing resin of a semiconductor device comprises a first lateral surface and a second lateral surface that are opposite to each other. A plurality of control terminals to which a microvoltage is applied, such as signal terminals, are brought out from the first lateral surface, and a plurality of main terminals to which a high voltage is applied, such as output terminals, are brought out from the second lateral surface (see, for example, JP 2019-114 640 A (Patent Reference 1)).

[0003] US Patent 2021 / 0217741 A1 relates to a semiconductor device A1 comprising: a substrate, a conductive section formed on the substrate and comprising a conductive material, a lead located on the substrate, a semiconductor chip located on the lead, a control chip located on the substrate and electrically connected to the conductive section and the semiconductor chip for controlling the operation of the semiconductor chip, and a resin covering the semiconductor chip, the control chip, at least a portion of the substrate, and a portion of the lead. This configuration contributes to achieving a higher level of integration of the semiconductor device.

[0004] US Patent 2021 / 0217687A1 discloses a semiconductor module comprising a semiconductor switching element, multiple bases, the semiconductor switching element being mounted on at least one of them, a molded resin sealing the semiconductor switching element and the multiple bases, multiple terminals integrally formed with each of the multiple bases and extending from an outer circumferential side face of the molded resin, and a recessed or protruding section of such depth or height as to ensure a creepage distance between the multiple terminals and configured to bridge a gap between the multiple terminals, in a section of the outer circumferential side face of the molded resin between the multiple terminals.

[0005] JP 2014-154 780 A discloses a semiconductor device capable of suppressing the formation of voids. The semiconductor device comprises several semiconductor elements arranged in a first direction on a plane, a potting resin for encapsulating the semiconductor elements, several terminals electrically connected to the semiconductor elements, the portions of which protrude perpendicularly to the first direction from a predetermined plane of the potting resin when viewed perpendicular to the plane, and first and second recessed areas that are recessed towards the side of the semiconductor elements and are located on both sides of a resin injection port when the potting resin is injected. The first and second recessed areas are each arranged opposite one of the semiconductor elements when viewed perpendicular to the plane, between terminals that protrude from the resin injection port on one of the semiconductor element sides.The first and second recessed parts point to a penetration part for penetrating the potting resin in the direction perpendicular to the plane and a step part which is formed on the semiconductor element side of the penetration part and is recessed to a predetermined depth from an upper plane of the potting resin to the plane. Summary

[0006] By placing a concave section on the second lateral surface of the sealing resin between adjacent main leads, it is possible to ensure creepage distance between these leads. However, bonding sections of the main leads, which are wire-bonded to a semiconductor chip, are located on the inside of the sealing resin in such a way that they face the second lateral surface between the adjacent main leads. Since the size of the bonding sections to be wire-bonded cannot be reduced, a space for the concave section cannot be guaranteed in the area between leads.

[0007] The present invention was created to solve the problems described above, and one object of the present invention is to provide a semiconductor device and a power conversion device whose size can be reduced.

[0008] The problem underlying the invention is solved according to the invention in a semiconductor device by the features of claim 1 and in a device for converting electrical power by the features of claim 12. Advantageous embodiments are the subject of the respective dependent claims.

[0009] The semiconductor device according to the present invention comprises: a plurality of semiconductor chips; a plurality of control terminals connected to the plurality of semiconductor chips; a plurality of main terminals connected to the plurality of semiconductor chips and having a greater width than the control terminals; and a sealing resin sealing the plurality of semiconductor chips, parts of the plurality of control terminals, and parts of the plurality of main terminals, wherein the sealing resin is rectangular in plan view and has a first lateral surface and a second lateral surface that are opposite to each other, the plurality of control terminals being brought out of the first lateral surface of the sealing resin, and the plurality of main terminals being brought out of the second lateral surface of the sealing resin.Each of the main terminals in the sealing resin comprises a bonding section that is wire-connected to one of the semiconductor chips, a heat transfer section adjacent to the bonding section, and a mounting section on which the other of the semiconductor chips is mounted. A concave section is located on the second lateral surface between the adjacent main terminals. One lateral surface of the heat transfer section faces the concave section, and one lateral surface of the bonding section does not face the concave section.

[0010] The multitude of main terminals comprises a P-terminal, a multitude of high-side main terminals, and a multitude of low-side main terminals. The distance between adjacent P-terminal and high-side main terminals, and the distance between adjacent high-side main terminals, is greater than the distance between adjacent low-side main terminals. The concave section is located between adjacent P-terminal and high-side main terminals, and between adjacent high-side main terminals.

[0011] In the present invention, the bonding section is not located in an area opposite the second lateral surface between the adjacent main connections, and the heat transfer section is located there. Since the width of the heat transfer section that is not wire-bonded can be reduced, a space for the concave section can be provided in an area between the adjacent main connections. Even if the space between the adjacent main connections is reduced, a creepage distance can be ensured by the depth of the concave section on the second lateral surface. Therefore, the size of a product can be reduced by reducing the distance.

[0012] Other and further tasks, features and advantages of the invention are shown in more detail in the following description. Brief description of the drawings Fig. Figure 1 is a top view illustrating a semiconductor device according to a first embodiment. Fig. Figure 2 is a top view illustrating the interior of the semiconductor device according to the first embodiment. Fig. Figure 3 is a top view illustrating the interior of a semiconductor device according to the comparative example. Fig. Figure 4 is an enlarged view of a P-connector. Fig. Figure 5 is a top view showing the interior of a semiconductor device according to an embodiment which illustrates the technical background of the present invention. Fig. Figure 6 is a block diagram illustrating a configuration of an electrical power conversion system for which the electrical power conversion device according to the third embodiment is used. Description of the embodiments

[0013] A semiconductor device and a power conversion device according to the embodiments of the present invention, and the technical background of the invention, are described with reference to the drawings. The same components are designated by the same symbols, and their repeated description can be omitted. First embodiment

[0014] Fig. Figure 1 is a top view illustrating a semiconductor device according to a first embodiment. The semiconductor device is a three-phase inverter. A sealing resin 1 is rectangular in plan view and comprises a first lateral surface 1a and a second lateral surface 1b, which are opposite each other. A plurality of control terminals 2 extend from the first lateral surface 1a of the sealing resin 1. A plurality of main terminals 3 extend from the second lateral surface 1b of the sealing resin 1. The main terminals 3 have a greater width than the control terminals 2. Specifically, it is desired that the width of the control terminals 2 is 0.65 ± 0.2 mm and the width of the main terminals 3 is 2 ± 0.2 mm in the root portions projecting from the sealing resin 1.

[0015] The multitude of control connections 2 includes a multitude of high-side control connections 2. H and a variety of low-side control connectors 2 L . To the high-side control ports 2 H A higher potential is available than at the low-side control ports 2. L installed. The multitude of main connections 3 includes a P main connection 3. P , three high-side main connectors 3 HU , 3 HV and 3 HW and three low-side main connectors 3 LU , 3 LV and 3 LW . To the high-side main connectors 3 HU , 3 HV and 3 HW A higher potential is achieved than at the low-side main connectors 3. LU , 3 LV and 3 LW installed. The P-connection 3 P , the high-side main connectors 3 HU , 3 HV and 3 HW and the low-side main connectors 3 LU , 3 LVand 3 LW are arranged side by side in sequence on the second lateral surface 1b.

[0016] The high-side main connectors 3 HU , 3 HV and 3 HW These correspond to a U-phase, a V-phase, or a W-phase of a three-phase inverter. The low-side main connections 3 LU , 3 LV and 3 LW These correspond to the U-phase, the V-phase, and the W-phase, respectively. The three-phase terminals can be arranged in any order. For example, the three-phase terminals can be arranged in the order of the U-, V-, and W-phases, in the order of the U-, W-, and V-phases, or in the order of the W-, V-, and U-phases. It is desirable to use the high-side main terminals 3 HU , 3 HV and 3 HW and the low-side main connectors 3 LU , 3 LV and 3 LWto arrange them in the same order. However, it is unnecessary to arrange the high-side main connectors 3 HU , 3 HV and 3 HW and the low-side main connectors 3 LU , 3 LV and 3 LW always to arrange them in the same order.

[0017] Fig. Figure 2 is a top view illustrating the interior of the semiconductor device according to the first embodiment. A control chip 4 H is equipped with a multitude of high-side control ports 2 H Wire-connected. Gate electrodes of semiconductor chips 5 HU , 5 HV and 5 HW are equipped with the control chip 4 H wired connection. The control chip 4 H controls the semiconductor chips 5 HU , 5 HV and 5 HW each according to the high-side control ports 2 H fed-in signals. A control chip 4 Lis equipped with a multitude of low-side control ports 2 L Wire-connected. Gate electrodes of semiconductor chips 5 LU , 5 LV and 5 LW are equipped with the control chip 4 L connected. The control chip 4 L controls the semiconductor chips 5 LU , 5 LV and 5 LW each according to the low-side control ports 2 L The signals fed in. Note that the control chips are 4 H and 4 L can be configured as a control chip. The control chips 4 H and 4 L can be bonded to a mounting section of a ladder frame integrally designed with the multitude of control connections 2.

[0018] The sealing resin 1 seals the control chips 4. H and 4 L , the semiconductor chips 5 HU , 5 HV , 5 HW , 5 LU , 5 LV and 5 LW, a portion of the multiple control connections 2 and a portion of the multiple main connections 3. The P main connection 3 P The sealing resin 1 includes a heat transfer section 6. P and an assembly section 8 P , which via a connecting section 7 P with the heat transfer section 6 P is connected.

[0019] The high-side main connector 3 HU The sealing resin 1 includes a bonding section 9. HU , a heat transfer section 6 HU , which corresponds to the bonding section 9 HU adjacent, and an assembly section 8 HU , which via a connecting section 7 HU with the heat transfer section 6 HU is connected. Subsections of the high-side main connector 3 HU , which are led to the outside of the sealing resin 1 or out of it, that is, the bonding section 9 HU, the heat transfer section 6 HU , the connecting section 7 HU and assembly section 8 HU They are configured by a wire referred to as an integrated conductor frame. These sections form a path for supplying a main current. The conductor frame is made of a copper material, for example.

[0020] Similarly, the high-side main connector comprises 3 HV inside the sealing resin 1 a bonding section 9 HV , a heat transfer section 6 HV , which corresponds to the bonding section 9 HV adjacent, and an assembly section 8 HV , which via a connecting section 7 HV with the heat transfer section 6 HV is connected. The high-side main connectors 3 HW The sealing resin 1 includes a bonding section 9. HW , a heat transfer section 6 HW , which corresponds to the bonding section 9 HWadjacent, and an assembly section 8 HW , which is via connecting section 7 HW with the heat transfer section 6 HW is connected.

[0021] Electrodes on the lower surface of the semiconductor chips 5 HU , 5 HV and 5 HW are attached to mounting section 8 by soldering or similar means P of the P main connection 3 P bonded. Electrodes on the lower surface of the semiconductor chips 5 LU , 5 LV and 5 LW are attached to the mounting sections 8 by soldering or the like HU , 8 HV or 8 HW the high-side main connectors 3 HU , 3 HV and 3 HW bonded. Electrodes on the upper surface of the semiconductor chips 5 HU , 5 HV and 5 HW are each with the bonding sections 9 HU 9 HV and 9 HW the high-side main connectors 3 HU , 3 HV and 3HW wire-connected electrodes on the upper surface of the semiconductor chips 5 LU , 5 LV and 5 LW are each connected to the low-side main connectors 3 LU , 3 LV and 3 LW wire-connected.

[0022] At least four concave sections 10 are arranged on the second lateral surface 1b of the sealing resin 1 between the adjacent main connections 3. Specifically, one concave section 10 is located between the P main connection 3 P and the high-side main connector 3 HU , which are adjacent to each other, are arranged, two concave sections 10 between the adjacent high-side main connections 3 HU , 3 HV and 3 HW arranged and is a concave section 10 between the high-side main connection 3 HW and the low-side main connector 3 LU, which are adjacent to each other. Note that, since there is a creepage distance between the low-side main connections 3 LU , 3 LV and 3 LW , to which no high voltage is applied, is small, the concave sections 10 between the low-side main terminals 3 LU , 3 LV and 3 LW are not arranged for a reduction in the size of the device.

[0023] Lateral surfaces of the heat transfer sections 6 P , 6 HU , 6 HV and 6 HW The floor surfaces of the concave sections 10 are opposite each other. That is, the heat transfer sections 6 P , 6 HU , 6 HV and 6 HW are adjacent to the concave sections 10 of the sealing resin 1. Heat generated by excitation in the semiconductor chips 5 HU , 5 HV , 5 HW , 5 LU , 5 LV and 5 LWEach component is generated via assembly sections 8 P , 8 HU , 8 HV , and 8 HW and the connecting sections 7 P , 7 HU , 7 HV and 7 HW to the heat transfer sections 6 P , 6 HU , 6 HV and 6 HW transferred. Since the heat transfer surface is increased by the concave sections 10, the heat transfer sections 6 can be compared to the heat transfer sections 6. P , 6 HU , 6 HV and 6 HW Heat transferred via air cooling is allowed to escape from the concave sections 10 to the outside. Therefore, heat dissipation is improved. Note that the lateral surfaces of the connecting sections 7 HU , 7 HV and 7 HW do not face the concave sections 10.

[0024] The bonding sections 9 HU 9 HV and 9 HWare each arranged on extended lines, on which the high-side main connectors 3 are located HU , 3 HV and 3 HW extend from the outside into the interior of the sealing resin 1. Lateral surfaces of the bonding sections 9 HU 9 HV and 9 HW They are not opposite the concave sections 10. The bonding section 9 HU and the heat transfer section 6 HU They are connected in an L-shape and are generally integrated or one-piece. The width of the bonding section is 9. HU is larger than the width of the heat transfer section 6 HU in a direction perpendicular to the second lateral surface 1b. Consequently, even if a semiconductor chip 5 HU outgoing wire essentially perpendicular to the wire bonding section 9 HU The wire bonding must be carried out sufficiently. The same applies to bonding sections 9. HV and 9HW and the heat transfer sections 6 HV and 6 HW .

[0025] The effects of this embodiment are described below in comparison with a comparative example. Fig. Figure 3 is a top view illustrating the interior of a semiconductor device according to the comparison example. In the comparison example, the bonding sections are shown in Figure 9. HU 9 HV and 9 HW arranged so that they face the second lateral surface 1b between the adjacent main terminals 3. Since the size of the bonding sections to be bonded with wire 9 HU 9 HV and 9 HWSince the creepage distance cannot be reduced, sufficient space for the concave section 10 cannot be ensured in the area between the adjacent main connections 3. Therefore, a creepage distance between the adjacent main connections 3 cannot be guaranteed. It is necessary to increase the distance between the adjacent main connections 3. Therefore, the size of the device is increased.

[0026] In contrast, in this embodiment, the bonding sections 9 are located in an area opposite the second lateral surface 1b between the adjacent main terminals 3. HU 9 HV and 9 HW not arranged and the heat transfer sections are 6 P , 6 HU , 6 HV and 6 HW arranged. Since the width of the heat transfer sections is 6 P , 6 HU , 6 HV and 6 HWTo reduce the distance between components that are not to be wire-bonded, a space in which the concave section 10 is provided can be ensured in an area between the adjacent main terminals 3. A creepage distance can be ensured, even if the interval between the adjacent main terminals 3 is reduced, by the depth of the concave section 10 on the second lateral surface 1b. Therefore, the size of a product can be reduced by reducing the center-to-center distance or pitch. Not only the size of a long side, but also of a short side of the sealing resin 1 can be reduced by reducing the width of the heat transfer sections 6. P , 6 HU , 6 HV and 6 HW reduced.

[0027] In Fig. 1 is a distance D1 between the P main terminal 3 P and the high-side main connector 3 HU, which are adjacent to each other, 4±0.2 mm. A distance D2 between the adjacent high-side main terminals 3 HU , 3 HV and 3 HW is 6.1 ± 0.2 mm. A distance D3 between the high-side main connector 3 HW and the low-side main connector 3 LU The distance between adjacent low-side main terminals is 6.1 ± 0.2 mm. A distance D4 between adjacent low-side main terminals 3 LU , 3 LV and 3 LW is 3.5 ± 0.2 mm. Since there is a high potential difference between the P-main terminal 3 P and the adjacent high-side main connectors 3 HU , 3 HV and 3 HW If this occurs, the distances D1, D2, and D3 on the high-side are set to be larger than the distance D4 on the low-side. The distance between adjacent terminals refers to the distance between the centerlines in a top view of the adjacent terminals.

[0028] As in Fig. As illustrated in Figure 1, the main P-connection is 3. P , the high-side main connectors 3 HU , 3 HV and 3 HW and the low-side main connectors 3 LU , 3 LV and 3 LW in this order on the second lateral surface 1b. In addition, the P main connection 3 P , the low-side main connectors 3 LU , 3 LV and 3 LW and the high-side main connectors 3 HU , 3 HV and 3 HW in this order on the second lateral surface 1b. In this case, a concave section 10 is located between the P-main connection 3. P and the low-side main connector 3 LU , which are adjacent to each other, are arranged, two concave sections 10 between the adjacent high-side main connections 3 HU , 3 HV and 3 HWarranged and is a concave section 10 between the low-side main connection 3 LW and the high-side main connector 3 HU , which are adjacent to each other, arranged. Since the low-side main connectors are 3 LU , 3 LV and 3 LW with a low potential next to the main P-terminal 3 P However, if the connections are arranged at a high potential, insulation is slightly more difficult than if the main connections are in the Fig. 1 are arranged in the illustrated order.

[0029] If the operating voltage of the semiconductor device is 560 to 630 V, a creepage distance of 3 mm must be maintained between the adjacent high-side main terminals. HU , 3 HV and 3 HW of 4 mm or more. By making the concave sections 10 with a depth of 0.5 mm or more between the high-side main terminals 3 HU , 3 HV and 3 HWtherefore, the distance between the adjacent high-side main connectors can be 3 HU , 3 HV and 3 HW to less than 4 mm. Consequently, it is possible to achieve a sufficient reduction in the size of the semiconductor device.

[0030] The higher the voltage applied to the terminals, the greater the required spacing between the terminals and the greater the required terminal width. For the same applied voltage, a greater terminal width results in a larger spacing. Specifically, a distance D5 between adjacent low-side control terminals 2 L smaller than the distance D4 between the adjacent low-side main connectors 3 LU , 3 LV , and 3 LW A distance D6 between the adjacent high-side control terminals 2 His smaller than the distance D1 between the P main terminal 3 P and the high-side main connector 3 HU , which are adjacent to each other, and the distance D2 between the adjacent high-side main connectors 3 HU , 3 HV and 3 HW is greater than the distance D4 between the adjacent low-side main connectors 3 LU , 3 LV and 3 LW This means that D5 < D4 < D6 < D1, D2. A reduction in the size of the entire semiconductor device is made possible by a combination of optimizing the connection distances and the concave sections 10.

[0031] The distance of the P main connection 3 P and the high-side main connector 3 HU, which are adjacent to each other, is equal to or greater than the distance between the other adjacent main terminals 3 and the distance between the adjacent control terminals 2. By taking the distance between the P main terminal 3 P and the high-side main connector 3 HU By determining the largest possible distance between adjacent terminals, an insulation distance can be ensured even if the thickness of the P-main terminal is 3 P is increased. That is, since the thickness of the P-main connection is 3 P By increasing the number of available spaces, the flexibility in design can be increased.

[0032] Fig. Figure 4 is an enlarged view of a P-terminal. Sometimes current flows to the main P-terminal. P an electric current that is 1.4 times greater than the electric current flowing to the other terminals 3. Therefore, the width of the P main terminal 3 Pgreater than the width of the P-main connection 3 P The width of the various main terminals 3 and the control terminals 2 is defined. The width of the P main terminal 3 P is preferably equal to 1.3 times the width w of the other main terminals 3 or larger. Since heat cannot be transferred to the P main terminal 3 via a wire. P The P main connection has 3 when the data is transmitted. P At this width, a sufficient temperature-reducing effect is achieved. Specifically, in the root section areas protruding from the sealing resin 1, the width of the P-main connection 3 is P The width of the P-main connection 3 is set to 2.6 ± 0.2 mm. P The dimensions of the various main terminals 3 are specified as 2 ± 0.2 mm, and the width of the control terminals 2 is specified as 0.65 ± 0.2 mm. Consequently, it is possible to prevent self-heating of the P main terminal 3. P, to which an excitation current predominantly flows, and to further reduce a temperature increase of the connection. Design and technical background

[0033] Fig. Figure 5 is a top view illustrating the interior of a semiconductor device according to a second embodiment to explain the technical background of the present invention. In the first embodiment, the concave section 10 is arranged on the second lateral surface 1b between the adjacent main terminals 3. In this embodiment, however, to explain the technical background of the present invention, a convex section 11 is arranged instead of the concave section 10. A creepage distance can be ensured by the height of the convex section 11 on the second lateral surface 1b, even if the distance between the adjacent main terminals 3 is reduced. Therefore, the size of a product can be reduced by reducing the pitch.

[0034] The formation of the convex sections 11 is not affected, even if the wide bonding sections 9 HU9 HV and 9 HW are arranged between the adjacent main connections 3. Therefore, the heat transfer sections 6 can be HU , 6 HV and 6 HW can be omitted and the bonding sections 9 can be omitted. HU 9 HV and 9 HW The convex sections 11 are created adjacent to each other. In the semiconductor chips 5 LU , 5 LV and 5 LW Heat generated by excitation is dissipated via the assembly sections 8 HU , 8 HV and 8 HW and the connecting sections 7 HU , 7 HV and 7 HW to the bonding sections 9 HU 9 HV and 9 HW transferred. Since the heat transfer surface is increased by the convex sections 11, the area corresponding to the bonding sections 9 can be transferred. HU 9 HV and 9 HWThe transferred heat is dissipated from the convex sections 11 to the outside by means of air cooling. Note that the heat transfer sections 6 HU , 6 HV and 6 HW as in the first embodiment and can be created adjacent to the convex sections 11.

[0035] If the operating voltage of the semiconductor device is 560 to 630 V, a creepage distance of 3 mm must be maintained between the adjacent high-side main terminals. HU , 3 HV and 3 HW of 4 mm or more. By positioning the convex sections 11 with a projection height of 0.5 mm or more between the high-side main terminals 3 HU , 3 HV and 3 HW Therefore, the distance between the adjacent high-side main connectors can be 3 HU , 3 HV and 3 HWThe size can be reduced to less than 4 mm. Consequently, it is possible to achieve a sufficient reduction in the size of the semiconductor device. The remaining components and effects are the same as in the first embodiment.

[0036] Note that in the first embodiment of the present invention, and in the second embodiment for the purpose of explaining the technical background of the present invention, a concave section or a convex section may be provided on the first lateral surface 1a between the adjacent control terminals 2. The semiconductor chips 5 HU , 5 HV , 5 HW , 5 LU , 5 LV and 5 LW are mounted on the conductor frame. However, the semiconductor chips can be 5 HU , 5 HV , 5 HW , 5 LU , 5 LV and 5 LWThey are mounted on an insulating substrate. The insulating substrate has a structure in which metal plates are bonded to both surfaces of an insulating layer. The semiconductor chips 5 HU , 5 HV , 5 HW , 5 LU , 5 LV and 5 LW They are mounted on the metal plates. Wires extend from heat transfer sections, similar to those in the conductor frame. The wires are bonded to the metal plates by soldering or ultrasonic vibration.

[0037] The semiconductor chips 5 HU , 5 HV , 5 HW , 5 LU , 5 LV and 5 LVVThese are RC-IGBTs, which are obtained by integrating IGBTs and diodes onto a single chip. Accordingly, it is possible to reduce the size of the semiconductor device compared to mounting the IGBTs and diodes separately. Note that the IGBTs and diodes can be mounted separately. In this case, three IGBTs and three diodes are located on mounting section 8. P of the P main connection 3 P Assembled. An IGBT and a diode are mounted on each of the 8 mounting sections. HU , 8 HV and 8 HW the high-side main connectors 3 HU , 3 HV and 3 HW assembled.

[0038] The semiconductor chips 5 HU , 5 HV , 5 HW , 5 LU , 5 LV and 5 LWSemiconductor devices are not limited to silicon-based semiconductors; they can instead be made from a wide-bandgap semiconductor with a wider bandgap than silicon. Examples of wide-bandgap semiconductors include silicon carbide, gallium nitride-based materials, and diamond. A semiconductor chip made from such a wide-bandgap semiconductor exhibits high voltage withstand capability and high allowable current density, and can therefore be miniaturized. Using such a miniaturized semiconductor chip enables the miniaturization and high integration of the semiconductor device in which it is integrated. Furthermore, because the semiconductor chip has high thermal resistance, a heat sink's heat sink fin can be miniaturized, and a water-cooled component can be air-cooled, leading to further miniaturization of the semiconductor device.Since the semiconductor chip has low power loss and high efficiency, a highly efficient semiconductor device can be achieved. Third embodiment

[0039] In this embodiment of the present invention, the semiconductor devices according to the first embodiment of the present invention or the second embodiment (for technical background) described above are used for an electrical power conversion device. The electrical power conversion device is, for example, an inverter, a converter, a servo amplifier, or a power supply unit. Although the present invention is not limited to a specific power conversion device, a case in which the present invention is used for a three-phase inverter is described below.

[0040] Fig.Figure 6 is a block diagram illustrating a configuration of an electrical power conversion system for which the electrical power conversion device according to the third embodiment of the present invention is used. This electrical power conversion system comprises a power supply 100, an electrical power conversion device 200, and a load 300. The power supply 100 is a DC power supply and provides DC power to the electrical power conversion device 200. The power supply 100 can consist of various components. For example, the power supply 100 can consist of a DC system, a solar cell, or a storage battery, or it can consist of a rectifier or an AC / DC converter connected to an AC system.Alternatively, the power supply 100 can consist of a DC / DC converter that converts DC power supplied by a DC system into a predetermined power.

[0041] The electrical power conversion device 200 is a three-phase inverter connected at a node between the power supply 100 and the load 300. It converts DC power supplied by the power supply 100 into AC power and supplies the AC power to the load 300. The electrical power conversion device 200 includes a main conversion circuit 201, which converts DC power into AC power and supplies the AC power, and a control circuit 203, which outputs a control signal to the main conversion circuit 201 for controlling the main conversion circuit 201.

[0042] The Last 300 is a three-phase electric motor driven by AC power supplied by the Device 200 for converting electrical power. The Last 300 is not limited to a specific application. It can be used as an electric motor mounted on various electrical devices, such as a hybrid vehicle, an electric vehicle, a rail vehicle, a lift, or an air conditioner.

[0043] Next, the electrical power conversion device 200 is described in detail. The main conversion circuit 201 includes a switching device and a reflux diode (not illustrated). When the switching device is switched, the main conversion circuit 201 converts DC power supplied by the power supply 100 into AC power and provides the AC power to the load 300. The main conversion circuit 201 can have various types of specific circuit configurations. The main conversion circuit 201 according to this embodiment is a three-phase, two-level full-bridge circuit, which can consist of six switching devices and six reflux diodes connected antiparallel to the respective switching devices.Each switching device and each reflux diode of the main conversion circuit 201 consists of a semiconductor device 202 corresponding to one of the first embodiment of the present invention described above or to the second embodiment (for technical background). Two switching devices of the six switching devices are connected in series to form a vertical arm. Each vertical arm forms one phase (U-phase, V-phase, W-phase) of the full bridge circuit. The output terminals of each vertical arm, i.e., three output terminals of the main conversion circuit 201, are connected to the load 300.

[0044] Furthermore, the main conversion circuit 201 includes a (not illustrated) control circuit that controls each switching device. The control circuit may be integrated into the semiconductor device 202. Alternatively, a different control circuit may be provided. The control circuit generates a control signal to actuate each switching device of the main conversion circuit 201 and provides the generated control signal to a control electrode of each switching device of the main conversion circuit 201. Specifically, the control circuit outputs to the control electrode of each switching device a control signal to turn on each switching device and a control signal to turn off each switching device according to the control signal output by the control circuit 203, which is described later.When the ON state of each switching device is maintained, the control signal is a voltage signal (ON signal) with a voltage equal to or higher than the threshold voltage of the switching device. When the OFF state of each switching device is maintained, the control signal is a voltage signal (OFF signal) with a voltage equal to or lower than the threshold voltage of the switching device.

[0045] The control circuit 203 controls each switching device of the main conversion circuit 201 to supply the desired power to the load 300. Specifically, the control circuit 203 calculates a period (ON period) during which each switching device of the main conversion circuit 201 is in the ON state, based on the power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by means of a PWM controller to modulate the ON period of each switching device depending on the output voltage. Furthermore, the control circuit 203 sends a control command (a control signal) to the control circuit contained in the main conversion circuit 201, so that at any given time the ON signal is sent to each switching device to be switched on and an OFF signal is sent to each switching device to be switched off.The control circuit outputs the ON signal or OFF signal as the control signal according to the control signal to the control electrode of each switching device.

[0046] In the electrical power conversion device according to this embodiment, the semiconductor device according to the first embodiment of the present invention or the second embodiment (for technical background) is used as the semiconductor device 202. Accordingly, it is possible to achieve a miniaturization of the electrical power conversion device.

[0047] While this embodiment illustrates an example in which the present invention is used for a two-level three-phase inverter, the present invention is not limited to this and can be used for various electrical power conversion devices. Although this embodiment illustrates a two-level electrical power conversion device, the present invention can also be used for an electrical power conversion device with three or more levels. When power is supplied to a single-phase load, the present invention can be used for a single-phase inverter. The present invention can also be used for a DC / DC converter or an AC / DC converter when power is supplied to a DC load or the like.

[0048] Furthermore, in the electrical power conversion device for which the present invention is used, the aforementioned load is not limited to an electric motor. For example, the load can also be used as a power supply device for an electrical discharge machine, a laser beam machine, a cooking appliance with induction heating, or a system for non-contact device power supply. Alternatively, the electrical power conversion device can also be used as a power conditioner for a photoelectric power generating system, an electricity storage system, or the like.

Claims

[1] Semiconductor device (202) comprising: - a large number of semiconductor chips (5 HU , 5 HV , 5 HW , 5 LU , 5 LV , 5 LW ); - a large number of control connections (2, 2 H , 2 L ), which are associated with the multitude of semiconductor chips (5 HU , 5 HV , 5 HW , 5 LU , 5 LV , 5 LW are connected; - a large number of main connections (3, 3 HU , 3 HV , 3 HW , 3 LU , 3 LV , 3 LW , 3 P ), which are associated with the multitude of semiconductor chips (5 HU , 5 HV , 5 HW , 5 LU , 5 LV , 5 LW ) are connected and have a greater width than the control connections (2, 2 H , 2 L exhibit; and - a sealing resin (1) that seals the multitude of semiconductor chips (5 HU , 5 HV , 5 HW, 5LU , 5 LV , 5 LW ), parts of the multitude of control connections (2, 2 H , 2 L ) and parts of the multitude of main connections (3, 3 HU , 3 HV , 3 HW , 3 LU , 3 LV , 3 LW , 3 P ) sealed, wherein: - the sealing resin (1) is rectangular in plan view and has a first lateral surface (1a) and a second lateral surface (1b) which are opposite to each other, - the large number of control connections (2, 2 H , 2 L ) is led out of the first lateral surface (1a) of the sealing resin (1), - the large number of main connections (3, 3 HU , 3 HV , 3 HW , 3 LU , 3 LV , 3 LW , 3 P ) is led out from the second lateral surface (1b) of the sealing resin (1), - each of the main connections (3, 3 HU , 3HV , 3 HW , 3 LU , 3 LV , 3 LW , 3 P ) in the sealing resin (1) a bonding section (9 HU 9 HV 9 HW ), which is connected to one of the semiconductor chips (5 HU , 5 HV , 5 HW , 5 LU , 5 LV , 5 LW ) wire-connected, a heat transfer section (6 HU , 6 HV , 6 HW ), which corresponds to the bonding section (9 HU 9 HV 9 HW ) adjacent, and an assembly section (8 HU , 8 HV , 8 HW ) includes the other of the semiconductor chips (5 HU , 5 HV , 5 HW , 5 LU , 5 LV , 5 LW ) is mounted, - a concave section (10) on the second lateral surface (1b) between the adjacent main connections (3, 3 HU , 3 HV , 3 HW , 3 LU , 3 LV , 3 LW , 3P ) is arranged, - a lateral surface of the heat transfer section (6 HU , 6 HV , 6 HW ) opposite the concave section (10), - a lateral surface of the bonding section (9 HU 9 HV 9 HW ) is not opposite the concave section (10), - the large number of main connections (3, 3 HU , 3 HV , 3 HW , 3 LU , 3 LV , 3 LW , 3 P ) includes a P main connector (3P), a variety of high-side main connectors (3HU, 3HV, 3HW) and a variety of low-side main connectors (3LU, 3LV, 3LW), - a distance between the P main terminal (3 P ) and the high-side main connector (3 HU , 3 HV , 3 HW ), which are adjacent to each other, and a distance between the adjacent high-side main connections (3 HU , 3 HV , 3 HW) are greater than a distance between the adjacent low-side main connectors (3 LU , 3 LV , 3 LW ) and - the concave section (10) between the P main connection (3 P ) and the high-side main connector (3 HU , 3 HV , 3 HW ), which are adjacent to each other, and between the adjacent high-side main connections (3 HU , 3 HV , 3 HW ) is arranged. [2] Semiconductor device (202) according to claim 1, wherein the heat transfer section (6HU, 6HV, 6HW) is not wire-bonded. [3] Semiconductor device (202) according to claim 1 or 2, wherein a width of the bonding section (9HU, 9HV, 9HW) is greater than a width of the heat transfer section (6HU, 6HV, 6HW) in a direction perpendicular to the second lateral surface (1b). [4] Semiconductor device (202) according to one of claims 1 to 3, wherein the bonding section (9HU, 9HV, 9HW) is arranged on an extended line on which the main terminal (3) extends from the outside into the interior of the sealing resin (1). [5] Semiconductor device (202) according to any one of the preceding claims, wherein: - the operating voltage of the semiconductor device (202) is 560 to 630 V, - the concave section (10) has a depth of 0.5 mm or more and - an interval between the adjacent high-side main connectors (3 HU , 3 HV , 3 HW ) less than 4 mm. [6] Semiconductor device (202) according to any one of the preceding claims, wherein: - the large number of control connections (2, 2 H , 2 L ) a variety of high-side control ports (2 H ) and a variety of low-side control ports (2 L) includes, - a distance between the adjacent low-side control terminals (2 L ) is smaller than the distance between the adjacent low-side main connectors (3 LU , 3 LV , 3 LW ) and - a distance between the adjacent high-side control connectors (2 H ) is smaller than the distance between the P main terminal (3 P ) and the high-side main connector (3HU, 3HV, 3HW) that are adjacent to each other, and the distance between the adjacent high-side main connectors (3 HU , 3 HV , 3 HW ) and is greater than the distance between the adjacent low-side main connectors (3 LU , 3 LV , 3 LW ). [7] Semiconductor device (202) according to any one of the preceding claims, wherein: - the distance between the P main terminal (3 P ) and the high-side main connector (3HU , 3 HV , 3 HW ), which are adjacent to each other, equal to or greater than a distance between the other adjacent main connections (3, 3 HU , 3 HV , 3 HW , 3 LU , 3 LV , 3 LW , 3 P ) and a distance between the adjacent control terminals (2, 2 H , 2 L ) is and - a width of the P main connection (3P) greater than a width of the main connections (3, 3) different from the P main connection (3P). HU , 3 HV , 3 HW , 3 LU , 3 LV , 3 LW , 3 P ) and a width of the control ports (2, 2 H , 2 L ) is. [8] Semiconductor device (202) according to claim 7, wherein a width of the P main terminal (3 P ) equal to or greater than 1.3 times the width of the other main connection. [9] Semiconductor device (202) according to one of the preceding claims, wherein the P main terminal (3 P ), the multitude of high-side main connectors (3 HU , 3 HV , 3 HW ) and the multitude of low-side main connectors (3 LU , 3 LV , 3 LW ) are arranged in this order on the second lateral surface (1b). [10] Semiconductor device (202) according to one of the preceding claims, wherein the semiconductor chips (5 HU , 5 HV , 5 HW , 5 LU , 5 LV , 5 LW ) an RC-IGBT with an IGBT and a diode integrated into one chip. [11] Semiconductor device (202) according to one of the preceding claims, wherein the semiconductor chip (5 HU , 5 HV , 5 HW , 5 LU , 5 LV , 5 LW ) is created from a wide bandgap semiconductor. [12] Device (200) for converting electrical power, comprising: - a main conversion circuit (201) comprising the semiconductor device (202) according to any of the preceding claims, converts input power and outputs converted power; and - a control circuit (203) which outputs a control signal to the main conversion circuit (201) for controlling the main conversion circuit (201).

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