A PACKAGE AND A COMMUNICATION DEVICE FOR AN RF APPLICATION

Abstract

Having one package (100): a printed circuit board (102); an interposer (104) which is coupled to the printed circuit board (102), wherein the interposer (104) contains: a substrate (202) which contains at least one via (224); a multilayer structure (204) arranged above the substrate (202), wherein the multilayer structure (204) contains an upper layer with an array (210); a plurality of passive devices (110) which are integrated into at least one of the substrate (202) or dielectric (208) of the multilayer structure (204), wherein the at least one via (224) couples the plurality of passive devices (110) to the printed circuit board (102); and a track (212) which is arranged above the multilayer structure (204) and connects at least one passive device (110) of the plurality of passive devices (110) to a pad (222) which is arranged above the multilayer structure (204); wherein the array (210) contains a property which is defined by the at least one passive device (110) which is connected to the track (212); a chip (106) which is coupled to the pad (222); and wherein the printed circuit board (102) defines a cavity (402) wherein the interposer (104) is arranged in the cavity (402).

Description

Technical field

[0001] The present invention relates generally to semiconductor devices and more specifically to interposers. background

[0002] An RF module can contain a chip that is configured by setting one or more properties of one or more passive devices. These passive devices can be discrete passive components or components that are picked and placed onto a printed circuit board. After placement, the discrete passive devices can be soldered during reflow manufacturing. The size of the discrete passive devices may be limited by the placement and reflow manufacturing processes. In this regard, the placement machine must have a certain accuracy to position the discrete passive devices. Similarly, the reflow manufacturing machine may create unwanted bridges if the spacing between discrete passive devices is too small.Therefore, a minimum distance must be maintained between the discrete passive devices to prevent unintentional connection.

[0003] A key factor in RF module design is size miniaturization. With the advent of 5G and miniaturization trends, there is a need to reduce the dimensions of RF packages. Unfortunately, the size of discrete passive devices is approaching a physical limit. Furthermore, discrete passive components, due to their footprint and spacing requirements, prevent further package size reduction. However, such discrete passive devices may be essential for achieving the desired chip configuration. Thus, discrete passive devices can be a limiting factor in reducing the size of an RF module. Integrating a chip-based filter with a printed circuit board (PCB) requires a large number of discrete passive devices. In some cases, these discrete passive devices can occupy more space than the filter itself.Additionally, the discrete passive devices cannot be placed on the printed circuit board under the chip. Instead, the discrete passive devices are placed on the printed circuit board surrounding the chip. Document US 2020 / 0 219 861 A1 concerns a so-called RF front-end system or module with an acoustic wave resonator described on an interposer substrate. An example of an integrated system includes an active chip, wherein the active chip has a semiconductor substrate with a plurality of active circuits therein. Furthermore, an interposer is included, which has an acoustic wave resonator. A sealing frame couples the active chip to the interposer, wherein the sealing frame surrounds the acoustic wave resonator and hermetically seals the acoustic wave resonator between the active chip and the interposer. Document US 2010 / 0 044 853 A1 concerns a so-calledA system-in-package comprising an integration substrate less than 100 micrometers thick and numerous vias with an aspect ratio greater than 5. A chip is mounted on the integration substrate and positioned between the substrate and a support suitable for mechanically supporting the substrate during processing and handling. Summary

[0004] A package according to one or more embodiments of the present disclosure is disclosed. In one exemplary embodiment, the package includes a printed circuit board. In another exemplary embodiment, the package includes an interposer coupled to the printed circuit board. In another exemplary embodiment, the interposer includes a substrate containing at least one via. In another exemplary embodiment, the interposer includes a multilayer structure arranged above the substrate. In another exemplary embodiment, the multilayer structure includes an upper layer with an array containing a plurality of passive devices integrated into at least one of the substrate or a dielectric of the multilayer structure.In another exemplary embodiment, the at least one via couples the plurality of passive devices to the printed circuit board. In another exemplary embodiment, the interposer includes a trace arranged above the multilayer structure and connecting at least one passive device from the plurality of passive devices to a pad arranged above the multilayer structure. In another exemplary embodiment, the array includes a property defined by the at least one passive device connected to the trace. In another exemplary embodiment, the package includes a chip coupled to the pad.

[0005] An interposer according to one or more embodiments of the present disclosure is disclosed. In one exemplary embodiment, the interposer comprises a substrate with at least one via. In another exemplary embodiment, the interposer comprises a multilayer structure arranged above the substrate. In another exemplary embodiment, the multilayer structure comprises an upper layer with an array containing a plurality of passive devices integrated into at least one of the substrate or a dielectric of the multilayer structure. In yet another exemplary embodiment, the at least one via couples the plurality of passive devices to a printed circuit board via a first pad on a bottom surface of the substrate, by means of which the interposer is configured.In another exemplary embodiment, the interposer includes a trace arranged above the multilayer structure, connecting at least one passive device from the plurality of passive devices to a second pad arranged above the multilayer structure by means of which the interposer is configured to couple to a chip. In another exemplary embodiment, the array includes a property defined by the device connected to the trace.

[0006] A communication device according to one or more embodiments of the present disclosure is described. In one exemplary embodiment, the communication device comprises a mainboard. In another exemplary embodiment, the communication device comprises a radio frequency module. In another exemplary embodiment, the radio frequency module comprises a printed circuit board coupled to the mainboard. In another exemplary embodiment, the radio frequency module comprises an interposer coupled to the printed circuit board. In yet another exemplary embodiment, the interposer comprises a substrate containing at least one via.In another exemplary embodiment, the interposer includes a multilayer structure arranged above the substrate. The multilayer structure includes an upper layer with an array containing a plurality of passive devices integrated into at least one of the substrate or a dielectric of the multilayer structure. In another exemplary embodiment, the at least one via couples the plurality of passive devices to the printed circuit board. In another exemplary embodiment, the interposer includes a trace arranged above the multilayer structure that connects at least one of the plurality of passive devices to a pad arranged above the multilayer structure. In another exemplary embodiment, the array includes a property defined by the passive device connected to the trace.In another exemplary embodiment, the radio frequency module contains a chip which is coupled to the track. Brief description of the drawings

[0007] Implementations of the concepts revealed here will be more readily understood if the following detailed description is taken into account. This description includes references to the accompanying drawings, which are not necessarily to scale and in which some features may be exaggerated, some features omitted, or some shown schematically for clarity. Identical reference numbers in the drawings may represent and refer to the same or similar elements, features, or functions. In the drawings: Fig. Figure 1 shows a side view of a package according to one or more exemplary embodiments of the present disclosure. Fig. 2A shows a top view of an interposer of a package with a chip coupled to the interposer, according to one or more embodiments of the present disclosure. Fig. 2B shows a top view of an interposer of a package containing passive devices integrated into one or more layers of the interposer, accessible from an upper surface of the interposer, according to one or more embodiments of the present disclosure. Fig. Figure 2C shows a simplified cross-sectional view of an interposer which contains passive devices which are integrated into one or more layers of the interposer which are accessible from an upper surface of the interposer, according to one or more embodiments of the present disclosure. Fig. Figure 2D shows a simplified cross-sectional view of an interposer containing trench capacitors integrated into a substrate of the interposer, accessible from an upper surface of the interposer, according to one or more embodiments of the present disclosure. Fig. Figure 3 shows a top view of an interposer with an extended track for adjusting a property of a capacitor array, according to one or more embodiments of the present disclosure. Fig. Figure 4 shows a side view of a package containing an interposer arranged in a cavity of a printed circuit board, according to one or more embodiments of the present disclosure. Fig. Figure 5 shows a side view of a package containing a chip coupled to passive components of an interposer by means of a bond wire, according to one or more embodiments of the present disclosure. Fig. Figure 6A shows a simplified cross-sectional view of an interposer which includes a through-hole coupled to a passive device which is integrated into an upper surface of the interposer, according to one or more embodiments of the present disclosure. Fig. Figure 6B shows a top view of an interposer which includes a through-opening coupled to a passive device which is integrated into an upper surface of the interposer, according to one or more embodiments of the present disclosure. Fig. Figure 7 shows a simplified scheme of a communication device containing a package, according to one or more embodiments of the present disclosure. Detailed description of the invention

[0008] Before one or more embodiments of the disclosure are described in detail, it should be clarified that the application of these embodiments is not limited to the details of the design and arrangement of components, steps, or methodologies detailed in the following description or shown in the drawings. Numerous specific details are provided in the following detailed description of embodiments to offer a more comprehensive understanding of the disclosure. However, it is obvious to a person skilled in the art, who has the benefit of this description, that the embodiments disclosed herein can be practiced without some of these specific details. In other cases, known features may not be described in order to avoid unnecessarily complicating the present description.

[0009] As used here, a letter following a reference numeral is intended to refer to an embodiment of a feature or element that may be similar, but not necessarily identical, to a previously written element or feature bearing the same reference numeral (e.g., 1, 1a, 1b). Such abbreviations are used for the sake of simplicity only and are not to be construed as limiting the disclosure in any way, unless otherwise stated.

[0010] Furthermore, unless otherwise stated, "or" refers to an inclusive or and not an exclusive or. For example, a condition A or B is satisfied by any of the following: A is true (or present) and B is false (or not present), A is false (or not present) and B is true (or present), and both A and B are true (or present).

[0011] Additionally, the use of "a" or "an" may be employed to describe elements and components of embodiments disclosed herein. This is done only for the sake of simplicity, and "a" and "an" are intended to include "one" or "at least one," with the singular also including the plural unless it is obvious that otherwise intended.

[0012] Finally, any reference to “an embodiment” or “some embodiments” as used herein means that a particular element, feature, structure, or property described in connection with the embodiment is included in at least one embodiment disclosed herein. The uses of the phrase “in some embodiments” at various points in the description do not necessarily all refer to the same embodiment, and embodiments may include one or more of the features expressly described or inherently present herein, or any combination or partial combination of two or more such features, together with any other features not necessarily expressly described or inherently present in this disclosure.

[0013] The disclosed subject matter, illustrated in the accompanying drawings, will now be discussed in detail. Embodiments of the present disclosure generally relate to providing an interposer with integrated passive devices, which are also referred to herein as integrated passives, passive devices, or integrated passive components. As used herein, the term integrated, integrating, and similar terms may refer to forming a component (e.g., a passive component) in one or more sections of a suitable device, for example, a metal layer, a dielectric, a multilayer structure, a substrate, and the like, an interposer, or any other device. Integrating the passive devices into the interposer may be advantageous for reducing one dimension in the plane of the package.Furthermore, an array of integrated passive devices can be integrated into one or more layers of the interposer, accessible from an upper layer. This accessibility from the upper layer allows a trace connecting the integrated passive devices to a pad to be formed during a masking step to achieve a desired property. This property can include, but is not limited to, capacitance, resistance, or inductance. Thus, the chip can be configured without requiring a redesign of the interposer. Instead, the interposer can achieve the desired property by masking the trace into a different arrangement. The interposer can then be coupled with a chip and a printed circuit board to form a package.For example, the package may contain, but is not limited to, a radio frequency (RF) module, an RF front end, and similar components. As used here, the terms "coupled," "coupling," "connected," "linking," and similar terms may permit intervening layers, devices, or structures unless otherwise specified (e.g., "directly coupled").

[0014] Generally referring to the Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6 to Fig. In Figure 7, a Package 100 is described according to one or more embodiments of the present disclosure. The Package 100 can contain one or more components (e.g., passive, active, etc.) in an electronic system which influence electrons in the electronic system, so that the Package can be considered an electronic package. As described in Fig. Figure 1, which relates to an exemplary embodiment, shows that the package 100 can contain one or more printed circuit boards 102 (PCBs), an interposer 104, and one or more chips 106. The interposer 104 can be coupled to the printed circuit board 102. Similarly, the chip 106 can be coupled to the interposer 104. In this respect, the interposer 104 can be arranged between the chip 106 and the printed circuit board 102. The interposer 104 can thus form an interface positioned between the chip 106 and the printed circuit board 102 for routing signals between the chip 106 and the printed circuit board 102. The interposer 104 can also be referred to as an interposer when configured to be interposed between the chip 106 and the printed circuit board 102, even when the interposer 104 is not currently forming an interface between them.The components of the package 100 can be coupled in any way, for example, but not limited to, one or more connections 108 (e.g., copper pillars, solder protrusions, gold protrusions, etc.), solder balls 112, and the like, for coupling the interposer 104 to the printed circuit board 102, and for coupling the chip 106 to the interposer 104. For example, the solder balls 112 and the connections 108 can be coupled between traces, pads, and the like, which may be arranged on a surface of the associated printed circuit board 102, the interposer 104, or the chip 106.

[0015] Package 100 can contain several chips 106 coupled to the interposer 104. Package 100 can also contain one or more chips 106 stacked on top of each other. Stacking the chips can reduce the footprint of Package 100. Furthermore, Package 100 can contain any number of additional chips that can be directly coupled to the printed circuit board 102.

[0016] The chip 106 can contain, but is not limited to, a filter, a power amplifier, and the like. The package 100 can therefore be used in a number of RF applications, for example, as a radio frequency (RF) module of a mobile phone or other communication device, but is not limited to these. In such RF applications, the design of the package 100 may be sensitive to size and cost requirements. The chip 106 can be electrically coupled to a number of passive devices to achieve a desired degree of tuning. In embodiments, the interposer 104 includes passive devices 110, which are used to tune the chip 106.

[0017] In embodiments, the interposer 104 includes one or more passive devices 110. The passive devices 110 are integrated into the interposer during its fabrication. The interposer 104 can be fabricated using wafer-level technology. In this case, the passive devices 110 can be integrated into one or more layers of a wafer. The wafer can then be sliced ​​to form the interposer 104. The passive devices 110 can be advantageous in reducing the size of the passive devices for the package 100 compared to discrete passive components placed on the printed circuit board 102. Reducing the size of the passive devices 110 can be advantageous in reducing the space required for mounting the chip 106.By integrating the passive devices 110 into the interposer 104, the interposer 104, along with the integrated passive devices, can also be placed under the chip 106. This can be advantageous compared to discrete passive components, which cannot be placed under the chip 106 due to height limitations. Since the passives are integrated into the interposer, their spacing is no longer a concern. Additionally, the minimum distance between the integrated passive devices can be reduced compared to using discrete passive components, due to a reduced risk of the integrated passive devices unintentionally bonding during the fabrication of the metal layers. Therefore, placing the passive devices in the interposer 104 can reduce the required length of the printed circuit board 102.

[0018] The passive devices 110 can contain one or more resistors (e.g., thin-film resistors (TFR), etc.), capacitors (e.g., metal-insulator-metal (MIM) capacitors, deep trench (TC) capacitors, metal-oxide-semiconductor (MOS) capacitors, metal-edge capacitors, etc.), or inductors (e.g., planar spiral inductors, etc.). As can be seen, the passive devices 110 can generally contain any passive device suitable for integration into the interposer 104. Furthermore, the passive devices 110 can contain any material, shape, and size to achieve the desired properties. The various described passive devices can be integrated into the interposer during one or more wafer fabrication steps.A property, such as, but not limited to, a resistance, a capacitance, or an inductance, can be selectively controlled based on the passive devices 110.

[0019] The interposer 104 can contain the passive devices 110 without active components (e.g., a transistor, diodes, etc.), so that the interposer 104 is considered a passive interposer. The interposer 104 can then be connected to the chip 106, which contains a number of passive and active components, so that the chip 106 is considered an active chip or an integrated circuit (IC) chip.

[0020] Now, referring to the Fig. Figures 2A to 2D describe one or more structures of the interposer 104 according to one or more embodiments of the present disclosure. The interposer can comprise a substrate 202 and a multilayer structure 204 arranged above the substrate 202. The substrate 202 can be a semiconductor material, such as, but not limited to, a silicon substrate or a glass substrate. The multilayer structure 204 can comprise a number of layers, each containing a metal trace surrounded by a dielectric 208. The metal trace can generally comprise any metal, such as, but not limited to, copper, aluminum, and the like. The dielectric 208 can be an organic material, such as, but not limited to, benzocyclobutene (BCB) and the like. The multilayer structure 204 can comprise any number of layers.The layers can be designated based on the layer's position relative to the substrate 202: a first metal layer can be designated as a Metal 1 (M1) layer, a second layer can be designated as a Metal 2 (M2) layer, and so on. For example, the multilayer structure 204 can contain five metal layers (M1 to M5) or more (see . Fig. 6A), although this is not to be considered restrictive. Connections can be made across the substrate 202 and one or more layers of the multilayer structure 204 by means of one or more vias 224. The vias 224 can be provided to connect the printed circuit board 102 to the chip 106 by means of one or more pads 206 located on a bottom side of the interposer 104 and one or more pads 222 on a top side of the interposer 104. The pads 206 configure the interposer 104 to couple with the printed circuit board 102 (e.g., by means of the solder balls 112). The pads 222 configure the interposer to couple with the chip 106 (e.g., by means of the connections 108). The vias 224 can be provided for routing between the pads and the various metal layers of the interposer 104.For example, the vias 224 can connect the passive devices 110 to the printed circuit board 102 directly or indirectly via the metal layers. As can be understood, the specific routing can be based on the desired circuit connection, so the various figures provided here should not be considered restrictive. The interposer 104 can contain significantly fewer layers than the chip 106. For example, the interposer can contain between four and five layers, or more, compared to the chip 106, which contains considerably more layers. In this respect, the layers of the chip 106 can be provided for the various active devices of the chip 106.

[0021] The passive devices 110 can be integrated into one or more of the substrate 202 and one or more layers of the multilayer structure 204. In embodiments, the passive devices 110 are integrated into an upper layer of the multilayer structure 204. The passive devices 110 can be arranged on the upper surface to form an array 210. Although not shown, the vias 224, together with one or more metallization layers, can couple the passive devices 110 of the array 210 to the printed circuit board 102. As used here, coupling by means of a via is not intended to be limited to a direct connection between the via and the associated component(s). For example, the vias can connect to pads and subsequently to the associated component(s). In another case, multiple vias can be connected by traces and the like.The via can therefore be coupled to the component(s) in any number of ways.

[0022] The array 210 can contain a collection of passive devices 110, which are grouped together on an upper surface of the interposer 104. Any number of integrated passive devices 110 can be formed in the array during a wafer processing step. Furthermore, several types of passive devices can be integrated in the same layer. The array 210 can generally contain any suitable arrangement of the passive devices 110. For example, the array can be a rectangular array with a first number of passive devices 110 along the width of the array and a second number of passive devices 110 along the length of the array. It is also considered that arrays of other dimensions may be suitable for the array 110, so the mention of the rectangular array should not be considered restrictive.The size, position, and arrangement of the passive devices in the array are not to be considered limiting. The array 210 can be positioned at any number of positions on the upper surface of the interposer 104. The interposer 104 can also contain any number of arrays 210. Furthermore, the passive devices 110 in the array 210 can contain values ​​(e.g., resistances, capacitances, inductances) that are substantially similar or they can contain values ​​that are different. The passive devices 110 in the array 210 can also contain one or more resistors, inductors, and capacitances. As shown, the resistors, inductors, and capacitors can be grouped into arrays that share a common resistance, inductance, or capacitance indicator shaft, although this is not to be considered limiting.The resistors, inductors, and capacitors can also be grouped into arrays that do not share a common property. For example, any number of resistors, inductors, and capacitors can be grouped in array 210 to achieve a property that includes capacitance, resistance, and / or inductance.

[0023] One or more of the passive devices 110 of the array 210 can be connected by means of a track 212. The track 212 can be formed on the top layer by mask lithography or a similar manufacturing process. The track 212 can contain any track material, for example, a copper track, but is not limited to this. The track 212 can connect the passive devices 110 to one or more pads 222 to which the chip 106 is coupled. The track 212 can contain a serial and / or parallel connection between any number of the passive devices 110. The property of the array 210 can thus be set based on the arrangement of the track 212, which connects the passive devices 110 in parallel and / or serially. Any number of arrays 210 can be connected to achieve the desired property.Track 212 can also connect to only a section of the passive devices contained in array 210. The remaining components of the array can then be left unused on the interposer.

[0024] The array 210 can also contain a number of passive devices 110 that are not connected via track 212 (also referred to as connected out). These passive devices 110, which are not connected via track 210, can be provided to adjust the properties of the array 210 during additional mask fabrication without modifying an underlying layer of the interposer 104. Thus, the passive devices 110 can be integrated into the interposer 104 and used to modify the properties of the array 210 and subsequently to adjust the performance of the chip 106.The ability to adjust the properties of the array 210 is particularly advantageous in radio frequency (RF) applications, as it allows for faster adjustment of the properties to achieve improved RF performance without requiring redesign and remanufacturing of the chip 106. In this respect, RF applications can utilize iterative tuning, which can be accomplished more quickly by using the interposer 104 and modifying its upper mask.

[0025] The passive devices 110 can be arranged to form one or more types of arrays, such as, but not limited to, an array 210a containing one or more resistors, an array 210b containing one or more capacitors, or an array 210c containing one or more inductors. The array 210a can contain one or more thin-film resistors 214 and the like. The array 210b can contain one or more deep-trench capacitors 216, MIM capacitors 218, a metal-oxide-semiconductor (MOS) capacitor, metal-edge capacitors, and the like. For example, the MIM capacitor 218 can contain two metal plates (e.g., electrodes), each on a separate layer of the multilayer structure. The metal plates can be separated by a dielectric layer.The dielectric layer separating the metal plates can be made of a material with a different dielectric constant than the dielectric 208 of the multilayer structure. The metal plates can be made of the same material as the metal sheet or of a different material. Although the capacitor array is described as containing MIM capacitors, this is not to be considered a limitation of the present disclosure. In another example, the deep-trench capacitor 216 can contain a two-sided trench made of a metallic material (e.g., electrodes) filled with a dielectric material, extending between the upper layer through one or more lower layers. Thus, a trench can be formed in the substrate 202 with the two sides of the metallic material and the dielectric. The array 210c can contain one or more coils, for example, planar spiral coils 220 and the like.The coils can be provided over one or more metal layers. For example, the coil can have a two-dimensional ring structure or a three-dimensional ring structure. The three-dimensional ring structure can be provided over multiple metal layers, which can be connected between the metal layers by vias. Where the passive device 110 contains a coil, the coil can generally have any shape to generate an inductance value, as is understandable. Thus, array 210a, array 210b, and array 210c can be provided with adjustable properties, including the resistance, capacitance, and inductance of chip 106.

[0026] Integrating the passive devices 110 into the upper layer of the interposer 104 can be advantageous for reducing the package height. To reduce the package height, one or more of the passive devices 110 can be placed under the chip 106. For example, [the figure] shows Fig. 2A one or more thin-film resistors 214 of the array 210a are arranged under the chip 106.

[0027] Although the passive devices 110 are described as being integrated into the upper layer of the interposer 104, this is not to be considered a limitation of the present disclosure. The multilayer structure 204 can also contain any number of the passive devices 110, which are integrated into one or more deeper layers of the multilayer structure 204 beneath the upper layer and / or in the substrate 202. For example, the deeper layers of the multilayer structure 204 can contain a MIM capacitor, a deep-trench capacitor, a thin-film resistor, an inductor, or another passive device, which may be formed from one or more of the metal layers. Furthermore, the substrate 202 can contain one or more of the passive devices 110. For example, the substrate 202 can contain a deep-trench capacitor or another passive device.If the passive devices 110 are provided beneath the top layer, such passive devices 110 can then be connected between the printed circuit board 110 and the chip 106 to form a circuit connection. For example, the passive devices 110 can be connected to the substrate in the lower metallization layers during the fabrication of the metallization layers.

[0028] As in Fig. As shown in Figure 2D, the substrate 202 can contain any number of trench capacitors 216. The trench capacitors 216 can be arranged to form one or more arrays 210, for example, a capacitor array. For instance, the trench capacitors 216 are shown as four groups, each with three trench capacitors arranged in parallel, although this is not to be considered restrictive. As is evident, the interposer 104 can generally contain any number of these groups. Furthermore, the interposer 104 can contain any arrangement of the trench capacitors in series and / or parallel to achieve a desired capacitance value. The trench capacitors 216 in the substrate 202 can be coupled to the pad 206 by means of one or more vias (e.g., a through-hole connected to an electrode of the trench capacitor).Similarly, the trench capacitors 216 can be routed to the top surface of the interposer 104 via one or more tracks and vias 224 in the dielectric of the multilayer structure 204. For example, the electrodes of the trench capacitor 216 can be connected to the top surface. By designing the metal layers in the multilayer structure 204, the trench capacitor arrays can be connected in parallel or in series. In some cases, one or more of the trench capacitors 216 can be routed in parallel or in series to a position on the top surface of the multilayer structure 204. The capacitor array can then be connected to the pads 222 on the top surface via the track 212. Advantageously, the capacitance value of the interposer 104 can be changed by adjusting the path of the track 212.

[0029] Now, referring to Fig. 3. The value of array 210b is to be changed to configure chip 106. The value can be changed by adding a new mask to the top of interposer 104, thereby extending track 212 to form track 302. Advantageously, additional passive devices 110 can be added in series or parallel to achieve the new feature without modifying the underlying metallization layers beneath the top layer. Interposer 104 can thus provide a means of rapidly assembling and manufacturing package 100.

[0030] Now, referring to Fig. Section 4 describes the package 100 according to one or more embodiments of the present disclosure. In embodiments, the printed circuit board 102 may contain a cavity 402. The cavity 402 may be formed in any manner, such as, but not limited to, routing, lamination, or the like. The interposer 104 may be coupled to the printed circuit board 102 within the cavity 402. Coupling the interposer 104 within the cavity 402 may be advantageous for reducing the height of the package 100. In this respect, the depth of the cavity 402 may be based on the thickness of the interposer 104, although this is not to be considered a limitation. In some cases, the cavity 402 has sufficient depth such that the upper surface of the interposer 104 is below the upper surface of the printed circuit board 102. In this respect, the interposer 104 can be considered as embedded in the printed circuit board 102.It is further considered that fewer layers of the printed circuit board 102 may be removed, so that the upper surface of the interposer 104 is positioned above the upper surface of the printed circuit board 102. In this respect, the interposer 104 can be considered as being partially embedded in the printed circuit board 102. One or more chips from the chip 106 can then be stacked on the interposer 104. Although it is described that the printed circuit board 102 contains the cavity 402, this is not to be considered a limitation of the present disclosure. Thus, the interposer 104 can be placed on the printed circuit board 102 or in the cavity 402. Furthermore, the interposer 104 can cover a partial area of ​​the printed circuit board 102 or the entire area of ​​the printed circuit board 102.

[0031] Now, referring to the Fig. In Figures 5 to 6B, the package 100 is further described according to one or more embodiments of the present disclosure. In embodiments, one or more of the passive devices 110 of the array 210 are used to serve as an additional chip 502. For example, the additional chip 502 can be coupled to the printed circuit board 102. The additional chip 502 can be coupled to the upper or lower surface of the printed circuit board 102. Supplying the additional chip 502 by means of the array 210 can be advantageous when using the passive devices 110, which are not currently connected to the track 212 and would otherwise not be used by the chip 106.

[0032] As in Fig. As shown in Figure 5, the unused passive devices can be connected to one or more of the printed circuit board 102 or the additional chip 502 by means of a bond wire 504. Connecting the unused passive devices of the array 210 to the additional chip 502 by means of the bond wire 504 can provide a connection of relatively low complexity for disconnecting the otherwise unused passive devices. In some cases, the interposer 104 can be embedded in the printed circuit board, thus reducing the length of the bond wire 504 and minimally affecting the package performance due to impedance.

[0033] As in the Fig. As shown in Figures 6A to 6B, the interposer 104 can include a through-hole 602. The through-hole 602 can be connected from the upper surface to the lower surface of the interposer 104. The through-hole 602 can be provided in the interposer 104 as a reserve for outgoing connections and for repurposing the passive devices 110 of the array 210 that are not used by the chip 106. A trace 604 can then be added to the upper surface, connecting the through-hole 602 and one or more of the passive devices 110 on the upper surface of the interposer 104. The through-hole 602 can also be coupled to the pad 206, which is located on the underside of the substrate 202, by means of which the interposer 104 is coupled to the printed circuit board 102.In this respect, the passive devices 110, which are not used by the chip 106, instead serve the additional chip 502 via the through-hole 602 and the printed circuit board 102. The ability to serve the additional chip 502 can be advantageous both in reusing passive devices that would otherwise go unused and in reducing the need for discrete passive components that would otherwise be coupled to the printed circuit board 102. Similarly, the values ​​of the passive devices 110 coupled to the additional chip 502 can be controlled by modifying the track 604. Thus, the passive devices 110 on the upper layer of the interposer 104 can be coupled to the additional chip 502 via the bond wire 504, the through-hole 602 with the track 604, and similar means.

[0034] Now, referring to Fig. A communication device 700 according to one or more embodiments of the present disclosure is described in Figure 7. In some cases, the package 100 can be coupled to a main board 702 of the communication device 700. The printed circuit board 102 can be coupled to the main board 702 by means of pads arranged on the underside of the printed circuit board 102. In some cases, the package 100 can contain a radio frequency (RF) module for filtering or amplifying a signal from the communication device 700, so that the package 100 can be considered a component of an RF front end. The chip 106 can thus be configured to filter a radio frequency signal or to amplify the power of the radio frequency signal from the main board 702. It is further considered that the package 100 can perform one or more additional functions for the communication device 700.It is further considered that various embodiments of the package 100 may be usable outside the context of the communication device 700. The communication device 700 may generally contain any type of device configured to communicate by sending or receiving a signal (e.g., digital, analog, etc.) over a medium (e.g., wired, wireless, etc.), such as, but not limited to, a mobile phone, a modem, a network interface, and the like. In some cases, the communication device 700 is configured to communicate via the RF front end.

[0035] Generally referring again to the Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6 to Fig.7. Although much of the present disclosure relates to the passive devices 110 integrated into the interposer 104, this is not to be considered a limitation of the present disclosure. In this respect, the printed circuit board 102 may contain one or more passives, for example, discrete passive components or integrated passive devices. However, the ability to integrate the passive devices into the interposer 104 may reduce the requirement for the printed circuit board 102 to contain the discrete passive components. Similarly, the chip 106 may contain one or more passive components. However, providing the passive devices 110 in the interposer 104 may be advantageous when adjusting the chip 106 without having to remanufacture the chip 106 for adjustment purposes.

[0036] The printed circuit board 102 can contain one or more metal layers separated by one or more insulating layers (not shown). The metal layers can be made of any electrically conductive material compatible with printed circuit board manufacturing, such as, but not limited to, copper, gold, silver, aluminum, and the like. Similarly, the insulating layers can be made of any electrically insulating material compatible with printed circuit board manufacturing, such as, but not limited to, a resin material (e.g., FR-4) and the like. The metal layers can generally be manufactured using any printed circuit board manufacturing process.The printed circuit board 102 can also contain several layers of metal layers and insulating layers, so that the printed circuit board 102 can be considered a multilayer PCB.

[0037] The interposer 104 can fan out a pitch from the chip 106 to the printed circuit board 102. Fanning out the pitch can be advantageous for interconnection purposes. In this respect, the chip 106 can contain contacts with a significantly smaller pitch or size compared to the contacts on the printed circuit board 102. The interposer 104 can fan out the signal lines from a fine pitch to a coarse pitch in any manner known in the prior art. For example, the vias 224 can contain through-silicon vias (TSV), but are not limited to this. The printed circuit board 102 can thus communicate various signals between itself and the chip 106.

[0038] As is understandable, the various figures shown here are not to scale but are provided for illustrative purposes only. For example, the metallization layers of the interposer 104 can be layered with thicknesses ranging from 10 µm to 100 µm. The thickness of the metal layers can also decrease with changes in wafer fabrication technology. Furthermore, the thickness and spacing between the metal layers can vary across the layers. Moreover, the various figures provided here are only illustrative of the different embodiments described herein.

[0039] It is assumed that the present disclosure and many of its associated advantages will be understood from the preceding description, and it will be clear that various changes can be made to the form, construction, and arrangement of the components without deviating from the disclosed subject matter or sacrificing all of its significant advantages. The described form is for illustrative purposes only.

Claims

[1] Having a package (100): a printed circuit board (102); an interposer (104) which is coupled to the printed circuit board (102), wherein the interposer (104) contains: a substrate (202) which contains at least one via (224); a multilayer structure (204) arranged above the substrate (202), wherein the multilayer structure (204) contains an upper layer with an array (210); a plurality of passive devices (110) which are integrated into at least one of the substrate (202) or dielectric (208) of the multilayer structure (204), wherein the at least one via (224) couples the plurality of passive devices (110) to the printed circuit board (102); and a track (212) which is arranged above the multilayer structure (204) and connects at least one passive device (110) of the plurality of passive devices (110) to a pad (222) which is arranged above the multilayer structure (204); wherein the array (210) contains a property which is defined by the at least one passive device (110) which is connected to the track (212); a chip (106) which is coupled to the pad (222); and wherein the printed circuit board (102) defines a cavity (402) wherein the interposer (104) is arranged in the cavity (402). [2] The package (100) according to claim 1, wherein the array (210) has at least one additional passive device (110) which is not connected to the pad (222) by means of the track (212), wherein the property of the array (210) is adjustable by connecting the at least one passive device (110) to the at least one additional passive device (110) for adjusting the chip (106) by means of the track (212). [3] The package (100) according to claim 1 or 2, further comprising an additional chip (106) which is coupled to the printed circuit board (102); wherein the array (210) includes at least one additional passive device (110) which is not connected to the pad (222) by means of the track (212), wherein the at least one additional passive device (110) is coupled to the additional chip (106). [4] The package (100) according to claim 3, wherein the at least one additional passive device (110) is coupled to the additional chip (106) by means of a bond wire (504). [5] The package (100) according to claim 3 or 4, wherein the interposer (104) includes a through-hole (602) and an additional track (604) arranged over the multilayer structure (204); wherein the additional track (604) connects the through-hole (602) and the at least one additional passive device (110); wherein the at least one additional passive device (110) is coupled to the additional chip (106) by means of the through-hole (602). [6] The package (100) according to any one of claims 1 to 5, wherein the interposer (104) is a passive interposer. [7] The package (100) according to any one of claims 1 to 6, wherein the chip (106) is coupled to the pad (222) by means of a connection (108). [8] The package (100) according to any one of claims 1 to 7, wherein the package comprises a radio frequency module. [9] The package (100) according to claim 5, wherein the at least one via (224) couples the plurality of passive devices (110) to a further pad (206) which is arranged on a bottom side of the substrate (202) by means of which the interposer (104) is configured to couple to the printed circuit board (102). [10] The package (100) according to claim 9, wherein the through-hole (602) is connected to the further pad (206) which is arranged on the underside of the substrate (202). [11] The package (100) according to any one of claims 1 to 10, wherein the substrate (202) is a silicon substrate or a glass substrate. [12] The package (100) according to any one of claims 1 to 11, wherein the property of the array (210) is a resistor, wherein the at least one passive device (110) contains a thin-film resistor. [13] The package (100) according to any one of claims 1 to 11, wherein the property of the array (210) is a capacitance, wherein the at least one passive device (110) includes a metal-insulator-metal capacitor integrated into the dielectric (208) or a deep trench capacitor integrated into the substrate (202). [14] The package (100) according to any one of claims 1 to 11, wherein the property of the array (210) is an inductance, wherein the at least one passive device (110) contains a coil. [15] The package (100) according to any one of claims 1 to 14, wherein the substrate (202) further comprises one or more additional passive components. [16] The package (100) according to claim 15, wherein the one or more additional passive components include a deep trench capacitor. [17] Having a communication device (700): a mainboard (702); and a radio frequency module which contains: a printed circuit board (102) which is coupled to the main board (702); an interposer (104) which is coupled to the printed circuit board (102), wherein the interposer (104) contains: a substrate (202) which contains at least one via (224); a multilayer structure (204) arranged above the substrate (202), wherein the multilayer structure (204) contains an upper layer with an array (210); a plurality of passive devices (110) which are integrated into at least one of the substrate (202) or dielectric (208) of the multilayer structure (204), wherein the at least one via (224) couples the plurality of passive devices (110) to the printed circuit board (102); and a track (212) which is arranged above the multilayer structure (204) and connects at least one passive device of the plurality of passive devices (110) to a pad (222) which is arranged above the multilayer structure (204); wherein the array (210) contains a property which is defined by the passive device (110) which is connected to the track (212); a chip (106) which is coupled to the track (212); and wherein the printed circuit board (102) defines a cavity (402) wherein the interposer (104) is arranged in the cavity (402). [18] The communication device (700) according to claim 17, wherein the chip (106) is configured for at least one of filtering a radio frequency signal of the main board (702) or amplifying a power of the radio frequency signal.

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