COMPOSITE SUBSTRATE WITH A TRANSMISSION FILM WITH POROUS SILICON CARBIDE LAYER AND METHOD FOR PRODUCE A SEMICONDUCTOR DEVICE

Abstract

A method for fabricating a silicon carbide device comprises forming a transfer film (110) containing a porous silicon carbide layer (116). A composite substrate (100) is formed, comprising the transfer film (110) and a support substrate (190), wherein the transfer film (110) and the support substrate (190) are brought into contact and bonded together. An epitaxial layer (120) is formed on a side of the porous silicon carbide layer (116) opposite the support substrate (190). The composite substrate (100) is divided into a device substrate (150) and a recovery substrate (160), wherein the device substrate (150) contains the epitaxial layer (120) and the recovery substrate (160) contains the support substrate (190).

Description

TECHNICAL FIELDExamples of the present disclosure relate to a composite substrate including a transfer film having a porous silicon carbide layer and a method of manufacturing a power semiconductor device. The method uses a transfer foil to transfer a porous silicon carbide layer to a carrier substrate. The composite substrate comprises a transfer film and a carrier substrate. The power semiconductor device can be obtained from the composite substrate.BACKGROUNDThe production of semiconductor wafers typically involves forming crystal ingots by vertical zone melting or by pulling a seed crystal rod from a crucible filled with molten semiconductor material and slicing the crystal ingots. Typical slicing processes destroy significant portions of the previously produced crystal. An alternative technique achieves typical semiconductor epitaxial wafers by forming a thin separation layer near a front side of a reusable seed semiconductor wafer, epitaxially growing a semiconductor layer on the front side, and then mechanically separating the epitaxially grown semiconductor layer from the seed wafer via the separation layer. For example, an epitaxially grown semiconductor wafer is cleaved from a single-crystalline base substrate along a separation layer formed by laser radiation.US 2023 / 0 127 556 A1 describes the formation of a porous layer on a front side of an at least partially monocrystalline silicon carbide wafer with 4H-SiC, 3C-SiC or 6H-SiC by anodic porosification (anodic porosification). An epitaxial layer grows on the porous layer. Electronic components are formed in the epitaxial layer. The silicon carbide wafer is split along the porous layer into a device layer including the electronic devices formed in the epitaxial layer and a reusable wafer portion. On the back side of the component layer, a part of the porous layer is retained. A rear side metallization is applied to the rear side of the component layer.U.S. Pat. No. 6,326,279 B1 relates to the production of an SOI wafer. A porous layer is produced on the front side of a first silicon substrate by anodic porosification in aqueous HF solution. An epitaxial layer is grown on the porous layer and a first oxide layer is grown on the epitaxial layer. A second oxide layer is grown on the front side of a second silicon substrate. The two silicon substrates are bonded together by bonding the two oxide layers. The resulting substrate composite is cleaved along the porous layer. The second silicon substrate with the two bonded oxide layers and the epitaxial layer resting on the bonded oxide layers forms an SOI wafer. In the publication DE 697 28 022 T2, the porous layer for separating the epitaxial layer is cleaved by means of a flexible film, which is bonded to the surface of the epitaxial layer and subsequently mechanically bent.The document DE 10 2018 132 447 A1 describes the formation of frame structures which laterally frame semiconductor components. The frame structures result from a grid-shaped forming structure during the singulation of the semiconductor components, which is produced by filling a grid-shaped trench in the kerf region of the device layer of a semiconductor wafer.There is a constant need for methods that economically provide semiconductor wafers.SUMMARYAn embodiment of the present disclosure relates to a method of manufacturing a silicon carbide device. The method includes forming a transfer film including a porous silicon carbide layer. A composite substrate is formed, which comprises the transfer film and a carrier substrate, wherein the transfer film and the carrier substrate are brought into contact with one another and are connected to one another. An epitaxial layer is formed on a side of the porous silicon carbide layer opposite to the support substrate. The composite substrate is divided into a device substrate and a recovery substrate (recovery substrate), wherein the device substrate includes the epitaxial layer and the recovery substrate includes the support substrate.The method decouples a process in which a suitable epitaxial seed is provided from the actual epitaxial process and simplifies the production of thin silicon carbide substrates for power semiconductor devices. A high quality starting substrate provides the epitaxial seed, and a low cost supporting substrate can be used for the epitaxial process. The porous silicon carbide layer first transfers the epitaxial seed to the inexpensive support substrate and then enables efficient separation of a device substrate having electronic components formed therein from the inexpensive support substrate.Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and upon viewing the accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGSThe accompanying drawings are provided to better understand the embodiments and are an integral part of the specification. The drawings illustrate embodiments of a power semiconductor device, a composite substrate, and a method for manufacturing a semiconductor device, and together with the description serve to explain the embodiments. The following detailed description and claims contain further embodiments. FIGS. 1A to 1D show schematic vertical cross-sectional views of a transfer film, a composite substrate, a device substrate, and a recovery substrate at various stages of a method of manufacturing a semiconductor device including transferring and horizontally cleaving a porous silicon carbide layer according to an embodiment. FIGS. 2A to 2D show schematic vertical cross-sectional views of a transfer film, a composite substrate, a device substrate, and a recovery substrate at various stages of a method for manufacturing a semiconductor device including transferring and horizontally cleaving a porous silicon carbide layer according to an embodiment concerning a transfer film including an auxiliary layer. FIGS. 3A to 3D show schematic vertical cross-sectional views of a composite substrate and a device substrate at various stages of a method for manufacturing a semiconductor device, comprising transferring and horizontally cleaving a porous silicon carbide layer according to an embodiment concerning the formation of electronic components before cleaving the porous silicon carbide layer. FIGS. 4A to 4C show schematic vertical cross-sectional views of a starting substrate and a transfer film at various stages of a method for manufacturing a semiconductor device, comprising transferring and horizontally cleaving a porous silicon carbide layer according to an embodiment including forming a porous silicon carbide layer for a transfer film on a starting substrate. FIG. 5 is a schematic vertical cross-sectional view of a composite substrate including a porous silicon carbide layer and a silicon carbide recycling substrate according to an embodiment, wherein the porous silicon carbide layer is directly bonded to the silicon carbide recycling substrate. FIG. 6 is a schematic vertical cross-sectional view of a composite substrate including a porous silicon carbide layer and a silicon carbide recycling substrate according to an embodiment having an interfacial layer formed between the porous silicon carbide layer and the silicon carbide recycling substrate. FIG. 7 is a schematic vertical cross-sectional view of a silicon carbide power diode with a laterally homogeneously doped porous silicon carbide region. FIG. 8 is a schematic vertical cross-sectional view of a silicon carbide power transistor with a laterally homogeneously doped porous silicon carbide region.DETAILED DESCRIPTIONIn the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which specific embodiments are shown by way of illustration in which a composite wafer, a power semiconductor device, and a method of manufacturing a semiconductor device may be practiced. Other embodiments may be utilized and structural or logical changes may be made without departing from the concept of the present disclosure. Features illustrated or described for one embodiment may be utilized on or in conjunction with other embodiments to arrive at yet another embodiment. The present disclosure is intended to include such modifications and variations. The embodiments are described in a manner which should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. Corresponding elements are provided with the same reference numerals in the different drawings, unless stated otherwise.The terms "have," "include," "comprise," "have," and the like are open ended terms, and the terms indicate the presence of certain structures, elements, or features, but do not exclude the presence of additional elements or features. The indefinite articles and the definite articles are intended to include both the plural and the singular, unless the context clearly indicates otherwise.The term "directly electrically connected" describes a permanent low-ohmic connection between the directly electrically connected elements, e.g. a direct contact between the relevant elements or a low-ohmic connection via a metal and / or a highly doped semiconductor material. The terms "electrically coupled" and "signal connected" include the direct electrical connection and additionally allow further electrical elements in a signal path or power supply path between the electrically connected or signal connected elements.The term "power semiconductor device" refers to active semiconductor devices such as diodes and transistors having a high voltage blocking capability of at least 30 V, for example 48 V, 100 V, 600 V, 1.6 kV, 3.3 kV or more, and having a nominal inrush current or forward current of at least 200 mA, for example 1 A, 10 A or more.Ranges given for physical dimensions include the margin values. For example, a range for a parameter y reads from a to b as a ≤ y ≤ b. The same applies to ranges having an edge value such as "at most" and "at least".The main components of a layer or structure of a chemical compound or alloy are those elements whose atoms form the chemical compound or alloy.The term "on" is not to be construed as meaning only "directly on". Rather, if an element is positioned "on" another element (e.g., a layer is "on" another layer or "on" a substrate), another component (e.g., another layer) may be positioned between the two elements (e.g., another layer may be positioned between a layer and a substrate if the layer is "on" the substrate).According to an aspect of the disclosure, a method of manufacturing a semiconductor device may include forming a transfer film including a porous silicon carbide layer. A composite substrate is formed, which comprises the transfer film and a carrier substrate, wherein the transfer film and the carrier substrate are brought into contact with one another and are connected to one another. An epitaxial layer is formed on a side of the porous silicon carbide layer opposite to the support substrate. The composite substrate is divided into a device substrate and a recovery substrate, wherein the device substrate includes the epitaxial layer and the recovery substrate includes the support substrate.The transfer film may have two parallel film surfaces and a uniform thickness given by a distance between the two film surfaces. In the following, two surfaces or planes may be considered "parallel" if the (e.g. imaginary) extents of the two surfaces or planes include an angle of less than 5° or less than 3° or less than 1°.The transfer sheet may be a rigid film which may be composed of the porous silicon carbide layer or may be a layer stack containing at least one auxiliary layer in addition to the porous silicon carbide layer. The auxiliary layer(s) may contain or consist of a material different from porous monocrystalline silicon carbide. If the layer stack contains a single auxiliary layer, the auxiliary layer can contain or consist of an organic material or an inorganic material. If the layer stack comprises two or more auxiliary layers, all auxiliary layers may contain or consist of an organic material, all auxiliary layers may contain or consist of an inorganic material or at least one of the auxiliary layers contains or consists of an organic material and at least one of the other auxiliary layers contains or consists of an inorganic material. For example, the auxiliary layer or at least one auxiliary layer is based on silicon and contains a silicon oxide and / or silicon nitride. The auxiliary layer or at least one auxiliary layer may be based on silicon carbide. The auxiliary layer or at least one auxiliary layer may be based on carbon. The auxiliary layer may include a glass, a ceramic, or a resin.A lateral extension of the transfer foil may be sufficiently large to completely cover a planar main surface of a standard wafer. In particular, the transfer film may be shaped such that the transfer film covers a circle having a diameter of at least 4 inches (inches), 150 mm, 200 mm, or 300 mm. A shape of the transfer film in a horizontal plane may be a circle or a polygon, e.g. a rectangle, a square or a hexagon.The porous silicon carbide layer may have two parallel main surfaces. A thickness of the porous silicon carbide layer given by a distance between the two main surfaces may be uniform along the porous silicon carbide layer. It may also be possible that the thickness of the porous silicon carbide layer varies along the porous silicon carbide layer by up to 35% (or up to 10% or up to 5%) of an average thickness of the porous silicon carbide layer. The thickness of the porous silicon carbide layer may be in a range of 1 nm to 50 μm.The porous silicon carbide layer includes a single crystal 3D support structure ("skeletal structure") having closed and / or interconnected (e.g., communicating) pores. The main surfaces of the porous silicon carbide layer may be covered with functional groups such as Si-O-Si, Si-F 2 and / or C-H x.When a porosity of a layer is defined as the ratio of the void volume (i.e., the "void volume") in the layer to the total volume of the layer, an average porosity of the porous silicon carbide layer is in a range of 10% to 80%, for example, in a range of 30% to 60%. A local porosity determined with respect to a unit volume that is greater than a maximum pore size may vary from 1% to 80%.In the porous silicon carbide layer, the local porosity may be homogeneous. Alternatively, the porosity of the porous silicon carbide layer may be uniform only along directions parallel to the main surfaces and may change in a direction orthogonal to the main surfaces. For example, the porosity may increase gradually or in steps with increasing distance from one main surface or both main surfaces or decrease with increasing distance from both main surfaces. The porous silicon carbide layer may include vertically stacked partial layers of different porosity. For example, the porous silicon carbide layer may comprise a coarse-porous partial layer and a fine-porous partial layer, wherein the porosity of the coarse-porous partial layer is greater than the porosity of the fine-porous partial layer. For example, the coarse-porous sub-layer may contain large pores having an average diameter greater than 50 nm, e.g. in a range from 50 nm to 200 nm, and a high total porosity of at least 30% and at most 80%, e.g. in a range from 40% to 60%. The fine-porous sub-layer may contain small pores having an average diameter of at most 50 nm, e.g. less than 40 nm, and a low total porosity of at most 50%, e.g. in a range from 5% to 35%.The porous silicon carbide layer may contain a skin layer portion (skin layer portion), wherein the skin layer portion contains pores with a porosity of less than 5% or is almost pore-free. The skin layer portion may directly adjoin one of the main surfaces of the porous silicon carbide layer.The transfer sheet can be obtained by forming a porous surface layer along an upper surface of a base substrate made of single crystal silicon carbide and peeling the porous surface layer or a portion of the porous surface layer from the base substrate.Forming the porous surface layer may include metal assisted photochemical etching (MAPCE). The metal assisted photochemical etching may use a noble metal layer as an electrode.Alternatively, the porous surface layer may be formed by electrochemical etching that induces anodic decomposition of the starting substrate. For example, the starting substrate may come into contact with a fluorine-containing electrolyte, e.g., hydrofluoric acid (HF) and a surfactant (surfactant). The surfactant may include tetramethylammonium hydroxide (TMAH), potassium hydroxide (KOH) and / or ethanol. Alternatively, the electrolyte may be an aqueous HF solution. A cathode electrode may be immersed in the electrolyte, and an electric potential may be applied between the cathode electrode and the output substrate constituting the anode electrode. The electrochemical etch may be a dark process or may be a photo-electrochemical etch assisted by light.The transfer film containing the porous silicon carbide layer can be detached from the starting substrate by mechanical forces. For example, a stressor layer may be deposited on an upper surface of the porous surface layer and a mechanical stress induced by the stressor layer into the starting substrate may cause the porous silicon carbide layer to crack along a horizontal plane. The stressor layer may be part of the transfer film. The stressor layer may be removed before or after the formation of the composite substrate.The transfer film and the support substrate are brought into contact with each other and bonded to each other, whereby a stable and durable chemical bond can be formed between a first main surface (bonding surface) of the porous silicon carbide layer and a process surface of the support substrate. The support substrate is made of a support material different from the material of the base substrate or includes an uppermost layer made of a substrate material different from a base material of a base substrate from which the porous silicon carbide layer is obtained.The process surface of the carrier substrate extends along two orthogonal horizontal (lateral) directions. A normal to the process surface defines a vertical direction.The substrate material and the starting substrate can have the same main components silicon and carbon, but different microstructures (microstructures). The carrier substrate may be a substrate other than a defect-free or nearly defect-free single crystal silicon carbide substrate and may be cheaper than the starting substrate from which the porous silicon carbide layer is obtained.By bonding the transfer film and the support substrate together, a one-piece composite substrate is formed.The epitaxial layer may be directly formed on a second main surface (epitaxial surface) of the porous silicon carbide layer of the transfer film. For example, the epitaxial layer may be formed directly on a skin layer portion of the porous silicon carbide layer. Forming the epitaxial layer includes a deposition process and, optionally, a thermal treatment to recrystallize the deposited material to obtain the 4H-SiC. The deposition process may include chemical vapor deposition (CVD), metalorganic chemical vapor deposition (MOCVD), metalorganic vapor epitaxy (OMVPE), and / or molecular beam epitaxy (MBE). The epitaxial layer forms a silicon carbide single crystal, wherein the atoms of the single crystal continue the crystal lattice of the porous silicon carbide layer.The dividing of the composite substrate may include horizontally splitting the porous silicon carbide layer into two regions, e.g., horizontally splitting the porous silicon carbide layer, separating the composite substrate into a device substrate and recovery substrate. The device substrate includes the epitaxial layer and may further include a device region of the cleaved porous silicon carbide layer. The recovery substrate includes the support substrate, and may further include a recovery region of the cleaved porous silicon carbide layer.The device substrate is separated in one piece from the recovery substrate. The recovery portion of the split silicon carbide porous layer remains bonded to the support substrate.The recovery region of the cleaved porous silicon carbide layer may form a continuous layer or may contain laterally separated islands. The device region of the cleaved porous silicon carbide layer may form a continuous layer or may contain laterally separated islands.The division of the composite substrate may include a mechanical stress of the composite substrate in a manner in which splitting processes in the porous silicon carbide layer relieve the mechanical stresses before another portion of the composite substrate is mechanically damaged. The mechanical tension may act in a horizontal transverse direction, in a horizontal radial direction, in the vertical direction, and / or as torsional shear stress. Generating the mechanical stress may include generating temperature differences along the vertical direction, exploiting differences in thermal expansion coefficients between the composite substrate and at least one auxiliary structure fixedly connected to one of the main surfaces of the composite substrate, twisting and / or pulling a chuck fixedly connected to one of the main surfaces of the composite substrate, and / or applying a leverage force to peel off the device substrate.Alternatively or additionally, the division of the composite substrate may comprise physically and / or chemically selectively damaging the skeletal structure of the porous silicon carbide layer until the device substrate separates from the recovery substrate or until application of a comparatively weak mechanical force is sufficient to separate the device substrate from the composite substrate. For example, a horizontal fluid beam, a horizontal particle beam or horizontal radiation may be directed onto an exposed lateral surface of the porous silicon carbide layer in order to remove material from the skeletal structure and weaken the skeletal structure of the porous silicon carbide layer. Alternatively or additionally, damaging the skeletal structure may include filling the pores with an auxiliary fill material and exploiting the physical properties of the auxiliary fill material to damage the skeletal structure. Alternatively or additionally, the damage to the skeletal structure may use the large surface area of the pores for highly selective chemical decomposition or chemical conversion of the silicon carbide in the porous silicon carbide layer into volatile components and / or mechanically less stable compounds.The epitaxial layer may be separated from the base region along the porous structure after doped regions, insulator structures and / or conductive structures of electronic elements have been formed on and / or in the epitaxial layer. For example, the epitaxial layer may be separated from the base region after forming semiconducting regions of semiconductor devices in the epitaxial layer. The separation process may include separating (e.g., splitting) the porous structure along an approximately horizontal plane by a coarse-porous layered region.After removing the recovery portion of the cleaved porous silicon carbide layer, the recovery substrate can be reused as a supporting substrate. The device substrate may be used for manufacturing semiconductor devices, wherein the device region of the cleaved porous silicon carbide layer may be completely removed. Alternatively, the device region of the cleaved porous silicon carbide layer may be smoothed and / or flattened, e.g. planarized.The method decouples epitaxy to a high degree from porosification and enables cost effective manufacture of thin silicon carbide device substrates such as those suitable for power semiconductor devices.According to an embodiment, the carrier substrate may comprise a polycrystalline silicon carbide substrate, a single crystal silicon carbide wafer of a polytype different from a polytype of the porous silicon carbide layer, or a single crystal silicon carbide recycling substrate.The polycrystalline silicon carbide layer may be an unprocessed or nearly unprocessed polycrystalline silicon carbide wafer. The single crystal silicon carbide substrate of a polytype different from the polytype of the porous silicon carbide layer may include or consist of 2H-SiC, 3C-SiC and / or 6H-SiC when the porous silicon carbide layer is formed of 4H-SiC.The single crystal silicon carbide recycling substrate may include single crystal silicon carbide of any poly type, but is not suitable for obtaining defect-free standard silicon carbide semiconductor devices on an economical scale. The recycling substrate may be a 4H-SiC single crystal wafer that does not meet at least one of the relevant specifications set for wafers for manufacturing power semiconductor devices. The single crystal silicon carbide recycling wafer contains, for example, more impurity atoms and / or more crystal defects, has a resistivity outside a certain range, or a surface orientation outside a certain range. The carrier substrate may be cheaper than the starting substrate.According to an embodiment, forming the composite substrate may include bonding the porous silicon carbide layer and the carrier substrate together. A permanent bond is formed between the porous silicon carbide layer and the carrier substrate.The permanent connection can be an adhesiveless connection or an adhesive connection. An adhesiveless connection is formed by direct bonding or fusion bonding (fusion bonding). An adhesive bond is formed by applying an adhesive.The bonding surface of the porous silicon carbide layer may be directly bonded to the process surface of the carrier substrate, for example. In this case, no adhesive material or material other than the material of the support substrate and the porous silicon carbide layer need be present along an interface between the porous silicon carbide layer and the support substrate. Direct bonding may be based on chemical bonds directly between two bonding elements. For example, the two bonding elements may be two of the following: (i) the carrier substrate, (ii) the porous silicon carbide layer, (iii) an (optional) non-adhesive bonding layer on the carrier substrate, (iv) an (optional) non-adhesive bonding layer on the porous silicon carbide layer. The non-adhesive bonding layer may include or consist of a semiconducting material and / or a metallic material.Fusion bonding may include pre-bonding at ambient temperature and annealing at elevated temperatures. The previous bonding brings the bonding surface of the porous silicon carbide layer into physical contact with the process surface of the carrier substrate. The annealing may activate and / or reinforce chemical bonds between the carrier substrate and the porous silicon carbide layer. Direct bonding (fusion bonding) may be supported by applying a silicon carbide-based liquid, a liquid silicon carbide precursor, or amorphous silicon to the processing surface of the carrier substrate and / or the bonding surface of the porous silicon carbide layer before the previous bonding.Alternatively, the porous silicon carbide layer of the transfer foil may be bonded to the process surface of the carrier substrate with adhesive via an intermediate adhesive layer. The bonding is based on chemical bonds between the cured adhesion layer and the carrier substrate and chemical bonds between the cured adhesion layer and the porous silicon carbide layer.The adhesive bonding may include applying a curable adhesive to the process surface of the carrier substrate and / or to the bonding surface of the porous silicon carbide layer, pressing the carrier substrate and the transfer sheet against each other with the curable adhesive therebetween, and curing the adhesive, wherein the adhesive cures and forms the cured adhesive layer. The curable adhesive can be applied, for example, as a liquid, as a tape or as a layer on a tape.Generally, surface pretreatment or surface conditioning may be performed prior to bonding. For example, such pretreatment or conditioning may include treatment with a plasma and / or a wet chemical solution.According to an embodiment, the porous silicon carbide layer may have a bonding surface having a C-surface, and forming the composite substrate includes bonding the bonding surface of the porous silicon carbide layer to the carrier substrate.The bonding surface having a C surface can facilitate direct bonding of the transfer foil to a Si surface of a single crystal recycling substrate of the same polytype as the porous silicon carbide layer. By bonding the C-surface of the porous silicon carbide layer to the carrier substrate, the Si-surface of the porous silicon carbide layer can remain accessible for further processing.According to an embodiment, the porous silicon carbide layer may have an epitaxial surface having a Si surface, and the epitaxial layer is formed on the epitaxial surface of the porous silicon carbide layer.The porous silicon carbide layer may be formed with a significantly lower porosity along a surface having the Si face than along a surface having the C face.Growing an epitaxial layer on an epitaxial surface having a Si surface may be less complicated than growing an epitaxial layer on a C surface.According to an embodiment, an electronic element may be formed in and / or on the epitaxial layer before the composite substrate is divided.The electronic element may be an active semiconductor element. For example, the electronic element is a semiconductor diode or a transistor. Doped semiconductor regions of the electronic element, such as an anode region of a semiconductor diode or the source / emitter region of a transistor, may be formed in the epitaxial layer. An anode electrode of a semiconductor diode or the source / emitter electrode of a transistor may be formed on the epitaxial layer. A gate electrode of a transistor may be formed on the epitaxial layer or in trenches extending into the epitaxial layer from a front side.According to an embodiment, the method may include backside processing an exposed backside surface of the device substrate.The division of the composite substrate includes cleaving the porous silicon carbide layer, separating the back surface of the device substrate from a front surface of the recovery substrate. The exposed back surface is formed by the device region of the cleaved porous silicon carbide layer.The backside processing may include a CMP planarizing and / or resetting the device region of the cleaved porous silicon carbide layer, wherein the device region of the cleaved porous silicon carbide layer may be completely removed from the device substrate, or wherein a planarized device region of the cleaved silicon carbide layer forms a porous backside layer of the device substrate. Alternatively or additionally, the backside processing may comprise introducing dopants through the exposed backside surface, a selective thermal treatment and / or deposition of a material, e.g. the deposition of a metal layer.According to an embodiment, a metal layer may be formed on an exposed back surface of the device substrate.The metal layer may be a homogeneous layer or may be a layer stack comprising two or more vertically stacked sub-layers of different composition and / or structure.According to an embodiment, an ohmic contact may be formed on a back side of the device substrate.Forming the ohmic contact may include introducing impurities through the back surface exposed of the device substrate to form a heavily doped contact layer along the back surface, and forming a metal layer on the heavily doped contact layer, wherein the metal layer and the heavily doped contact layer form an ohmic contact. The introduction of the impurities may include implanting dopants through the back surface of the device substrate. Forming the ohmic contact may include a local backside surface heat treatment, e.g., laser thermal annealing (LTA).The metal layer may form an electrode of a vertical semiconductor device with a current flow between the front side and the back side in a forward mode of a semiconductor diode or in an on state of a power transistor.According to an embodiment, forming the transfer film may include forming a porous surface layer on a front side of a single crystal silicon carbide base substrate and separating a film portion of the porous surface layer from the base substrate, the film portion forming the porous silicon carbide layer of the transfer film.The starting substrate has a planar first main surface which extends along two orthogonal horizontal (lateral) directions. A normal to the first main surface defines a vertical direction.The film portion is removed in one piece from the rest of the starting substrate. A substrate portion of the porous surface layer may remain bonded to the non-porosified non-porous substrate portion of the starting substrate. The substrate region may form a continuous layer or may include laterally separated islands.Separating the film portion from the porous surface layer horizontally splits the porous surface layer into two portions and may include a mechanical stress on the starting substrate in such a manner that splitting processes in the porous surface layer relieve the mechanical stresses before another portion of the starting substrate is mechanically damaged. The mechanical tension may act in a horizontal transverse direction, in a horizontal radial direction, in the vertical direction, or as torsional shear stress. Generating the mechanical stress may include generating temperature differences along the vertical direction, exploiting differences in thermal expansion coefficients between the starting substrate and at least one auxiliary structure fixedly connected to one of the main surfaces of the starting substrate, twisting and / or pulling a chuck fixedly connected to one of the main surfaces of the starting substrate, and / or applying a leverage force to peel off the film area.Alternatively or additionally, separating the film portion of the porous surface layer from the starting substrate may include physically and / or chemically selectively damaging the skeletal structure of the porous surface layer until the film portion of the porous surface layer peels off a substrate portion or until application of a comparatively weak mechanical force is sufficient to peel the film portion off the starting substrate. For example, a horizontal fluid beam, a horizontal particle beam, or horizontal radiation may be directed at an exposed lateral surface of the porous surface layer to remove material from the skeletal structure and weaken the skeletal structure of the porous surface layer. Alternatively or additionally, damage to the skeletal structure may include filling the pores with an auxiliary fill material and exploiting the physical properties of the auxiliary fill material to damage the skeletal structure. Alternatively or additionally, the damage to the skeletal structure may exploit the large surface area of the pores for highly selective chemical decomposition or chemical conversion of the silicon carbide in the porous surface layer into volatile components and / or mechanically less stable compounds.The transfer film may include an auxiliary layer applied to one of the main surfaces of the porous silicon carbide layer. For example, the auxiliary layer may be formed or deposited on the porous surface layer before the porous surface layer is divided. Alternatively or additionally, an auxiliary layer may be applied to at least one of the main surfaces of the porous silicon carbide layer after the film region has been separated from the starting substrate.A recovery portion of the base substrate including the substrate portion of the porous surface layer and the nonporous substrate portion of the base substrate may be post-processed. For example, the substrate region of the porous surface layer can be planarized or completely removed in such a way that, in a next cycle, a further porous surface layer can be formed in the post-processed recovery region of the starting substrate.According to an embodiment, forming the porous surface layer may include a metal assisted photochemical etch (MAPCE).MAPCE may form the porous silicon carbide layer on the C surface of the starting substrate.According to an embodiment, the dividing of the composite substrate may include generating a horizontal mechanical stress in the porous silicon carbide layer.A horizontal mechanical tension can be generated by radial, transverse and / or by torsion forces. The mechanical stress may generate and / or promote horizontal crack growth in vertical columns of the skeletal structure in the porous silicon carbide layer until the composite substrate is separated into two parts.Generating a horizontal mechanical stress may include forming or fixedly attaching, e.g., bonding, a stressor layer on a main surface of the composite substrate and subjecting the composite substrate to a thermal treatment wherein different degrees of thermal expansion in the composite substrate and the stressor layer generate a radial mechanical stress in the composite substrate. The stress may have a maximum in a horizontal layer part having the highest porosity.According to another aspect of the disclosure, a composite substrate may include a carrier substrate containing single crystal silicon carbide. A single crystal porous silicon carbide layer is located on a process surface of the carrier substrate, wherein a polytype of the carrier substrate is different from a polytype of the porous silicon carbide layer and / or the carrier substrate is a recycling wafer. An epitaxial layer may be formed on a side of the porous silicon carbide layer opposite to the carrier substrate.The carrier substrate may include a non-porous single crystal silicon carbide layer or may be comprised of non-porous single crystal silicon carbide.According to an embodiment, the single crystalline porous silicon carbide layer may be in direct contact with the process surface of the carrier substrate. For example, the monocrystalline porous silicon carbide layer is directly bonded to a nonporous monocrystalline silicon carbide layer of the carrier substrate or to a carrier substrate consisting of nonporous monocrystalline silicon carbide. Chemical bonds, e.g. silicon-carbon bonds, are formed between the monocrystalline porous silicon carbide layer and the carrier substrate.According to an embodiment, the epitaxial layer may be in direct contact with the porous silicon carbide layer. The porous silicon carbide layer may for example comprise a skin layer region with low porosity with a porosity of less than 5% and a thickness of at most 300 nm. The epitaxial layer may be in direct contact with the skin layer region of low porosity.According to another aspect of the present disclosure, a power semiconductor device may include a single crystal porous silicon carbide region having laterally homogeneous porosity. A non-porous silicon carbide region is in direct contact with a main surface of the porous silicon carbide region. An active semiconductor element includes semiconducting regions formed in the nonporous silicon carbide region. A first load electrode is formed on a front side of the nonporous silicon carbide region opposite the porous silicon carbide region. A second load electrode is formed on a back side of the porous silicon carbide region opposite to the main surface of the porous silicon carbide region.According to an embodiment, the single crystalline porous silicon carbide region may have a laterally constant gradient of the dopant concentration.In the skeletal structure of the silicon carbide porous region, the dopant concentration does not change along the lateral directions.A doping level in the porous silicon carbide region and a doping level in the nonporous silicon carbide region may be the same or at least similar, wherein the doping level in the porous silicon carbide region falls below or exceeds the doping level in the nonporous silicon carbide region by at most 50% of the doping level in the nonporous silicon carbide region. Alternatively, the doping level in the porous silicon carbide region falls below or exceeds the doping level in the nonporous silicon carbide region by more than 50% of the doping level in the nonporous silicon carbide region.FIGS. 1A to 1D relate to an embodiment with a transfer foil 110 comprising no more than one porous silicon carbide layer 116, as illustrated in FIG. 1A.The porous silicon carbide layer 116 has two parallel main surfaces 111, 112. The main surfaces 111, 112 are planar or at least approximately planar and have a lateral extent along two orthogonal horizontal directions. A first main surface 111 at a first side of the porous silicon carbide layer 116 may have a carbon (C) surface. A second main surface 112 at the second side of the porous silicon carbide layer 116 may have a silicon (Si) surface.The lateral extent may be sufficiently large to completely cover a front side of a standard wafer having a diameter of at least 4 inches (inches), 150 mm, 200 mm, or 300 mm. A horizontal shape of the porous silicon carbide layer 116 may be rectangular or circular, for example. The distance between the first main surface 111 and the second main surface 112 corresponds to a thickness th 1 along a vertical direction orthogonal to the horizontal directions. The thickness th 1 of the porous silicon carbide layer 116 may be in a range from 5 nm to 100 μm, e.g. 10 μm to 30 μm.The porous silicon carbide layer 116 contains closed and / or interconnected pores embedded in a single crystalline solid support structure (skeletal structure). The single crystal support structure has the 4H polytype. A dopant concentration in the single crystal support structure is uniform in the horizontal directions and may be uniform along the vertical direction or exhibit a smooth or stepped variation.A porosity of the porous silicon carbide layer is constant in the horizontal directions. In the vertical direction, the porosity of the porous silicon carbide layer is constant or has a continuously variable or stepped variation. An average porosity of the porous silicon carbide layer is in a range of 10% to 80%, for example, in a range of 30% to 60%. Along the second main surface 112, the porosity may be less than 5%, e.g. less than 1%. Along the first main surface 111, the porosity may be higher than along the second main surface 112, e.g. higher than 50%.The first main surface 111 and / or the second main surface 112 of the porous silicon carbide layer may / may be covered with functional groups such as Si-O-Si, Si-F 2 and / or C-H x.The porous silicon carbide layer 116 is brought into contact with a planar process surface 191 of a carrier substrate 190. A stable and durable chemical bond is formed between the porous silicon carbide layer 116 and the carrier substrate 190.The carrier substrate 190 contains or consists of a non-porous substrate material, wherein a thermal expansion coefficient of the substrate material and a thermal expansion coefficient of the porous silicon carbide layer 116 may be the same or may deviate from one another by not more than 5% from the average value of the two thermal expansion coefficients.The lateral extent of the carrier substrate 190 may correspond to a standard wafer of at least 4 inches (inches), 150 mm, 200 mm, or 300 mm.The material of the carrier substrate 190 is different from a nonporous silicon carbide single crystal substrate having the polytype of the porous silicon carbide layer 116 and satisfying the specifications for a starting substrate for manufacturing power semiconductor devices in terms of resistivity, crystal orientation, crystal defect density, dopant concentration, hydrogen content and / or oxygen content, for example. For example, the substrate material of the carrier substrate 190 may be single crystal 3C-SiC, 2H-SiC or 6H-SiC or polycrystalline silicon carbide. Alternatively, the support substrate is a recycling wafer that does not meet specifications for a starting substrate for manufacturing the power semiconductor devices.The bonding of the porous silicon carbide layer 116 and the carrier substrate 119 may include a direct bonding or melt bonding with or without applying liquid silicon carbide to the process surface 191 of the carrier substrate 190 and / or the first main surface 111 (bonding surface) of the porous silicon carbide layer 116 before the bonding surface 111 of the porous silicon carbide layer 116 and the process surface 191 of the carrier substrate 190 are brought into contact with each other.FIG. 1B shows a one-piece composite substrate 100 comprising the porous silicon carbide layer 116 and the carrier substrate 190.An epitaxial layer 120 is formed directly on the second main surface 112 (epitaxial surface) of the porous silicon carbide layer 116. Forming the epitaxial layer 120 includes a deposition process and, optionally, a heat treatment for recrystalizing the deposited material to obtain the 4H-SiC. The deposition process may include chemical vapor deposition (CVD), metal organic vapor deposition (MOCVD), metal organic vapor deposition (OMVPE), and / or molecular beam epitaxy (MBE). The epitaxial layer 120 grows in accordance with the crystal lattice of the porous silicon carbide layer 116. An initial phase of epitaxy may be controlled to allow some lateral over-growth across gaps in the epitaxial surface 112 of the porous silicon carbide layer 116.In FIG. 1C, the one-piece composite substrate 100 includes the carrier substrate 190, the porous silicon carbide layer 116, and the epitaxial layer 120 grown on the epitaxial surface 112 of the porous silicon carbide layer 116. The epitaxial layer 120 forms a single crystal, wherein the atoms of the single crystal continue the lattice structure of the porous silicon carbide layer 116. The porous silicon carbide layer 116 may include a low-porous skin layer along the epitaxial surface 112, wherein the skin layer forms before epitaxy and / or in an initial phase of epitaxy.One or more active electrical elements may be formed in and / or on the epitaxial layer 120. The porous silicon carbide layer 116 is then cleaved in an approximately horizontal cleavage region 115. The gap region 115 may include a roughly porous layered region of the porous silicon carbide layer 116. In particular, the gap region 115 may include a vertical highly porous sub-layer of the porous silicon carbide layer 116, wherein the porosity of the porous silicon carbide layer 116 has a maximum in the highly porous sub-layer. A vertical extension of the gap portion 115 may be small with respect to the thickness th 1 of the porous silicon carbide layer 116. The gap region 115 may be spaced apart from both the epitaxial layer 120 and the carrier substrate 190 or may directly adjoin the carrier substrate 190.The cleavage of the porous silicon carbide layer 116 may include attaching a stressor substrate having a coefficient of thermal expansion different from the coefficient of thermal expansion of the composite substrate 100 to at least one of the major surfaces of the composite substrate 100, and then cooling or heating the composite comprising the stressor substrate and the composite substrate 100 to generate a thermomechanical stress in the porous silicon carbide layer 116 along a horizontal radial direction.Alternatively, the thermomechanical stress may be induced in the porous silicon carbide layer 116 by creating a vertical temperature gradient in the composite substrate 100. Any type of cracking process as discussed above may be used.As shown in FIG. 1D, the composite substrate 100 of FIG. 1C is separated into a device substrate 150 and a recovery substrate 160. The device substrate 150 includes the epitaxial layer 120 and a device region 118 of the porous silicon carbide layer 116. The recovery substrate 160 includes a recovery region 119 of the porous silicon carbide layer 116 and the support substrate 190.The device substrate 150 may be further processed. For example, the device region 118 of the porous silicon carbide layer 116 may be removed from the device substrate 150. Removal of the device region 118 may include mechanical, chemical, physical polishing, or a combination of various polishing methods, such as chemical mechanical polishing (CMP). The CMP may expose a back surface of the epitaxial layer 120. A metal layer may be deposited on the back surface of the epitaxial layer 120. From the device substrate 150, semiconductor dies of power semiconductor devices are obtained by dicing.The recovery region 119 of the split silicon carbide porous layer 116 is removed from the recovery substrate 160. The recovery substrate 160 may then be reused as another support substrate 190, and the process of transferring a porous silicon carbide layer 116 to a support substrate, growing an epitaxial layer on the porous silicon carbide layer 116, and cleaving a device substrate from the obtained composite substrate may be repeated.In FIGS. 2A to 2D, the transfer film 110 includes an auxiliary layer 117 formed on or attached to the epitaxial surface 112 of the porous silicon carbide layer 116, as illustrated in FIG. 2A.The auxiliary layer 117 may be a homogeneous layer or a layer stack including at least two vertically stacked layers of different composition and / or microstructure. The auxiliary layer 117 may comprise an adhesive tape and / or a solid carrier layer.An interfacial layer 130 may be formed on the process surface 191 of the carrier substrate 190. The interface layer 130 includes a silicon-containing layer. For example, the interface layer 130 includes or consists of silicon nitride.The porous silicon carbide layer 116 is brought into contact with a planar process surface 131 of the interface layer 130. A stable and durable chemical bond is formed between the porous silicon carbide layer 116 and the interfacial layer 130. The auxiliary layer 117 is removed.FIG. 2B shows the porous silicon carbide layer 116 with the bonding surface 111 directly bonded to the interface layer 130. Without the interfacial layer 130, the porous silicon carbide layer 116 is directly bonded to the carrier substrate 190.FIGS. 2C and 2D show the growth of an epitaxial layer 120 on the epitaxial surface 112 of the porous silicon carbide layer 116 and the splitting of the composite substrate 100 along a splitting region 115 of the porous silicon carbide layer 116, as was described above with reference to FIGS. 1C and 1D, with the difference that the interface layer 130 is formed between the porous silicon carbide layer 116 and the carrier substrate 190.FIGS. 3A to 3D illustrate a method of obtaining semiconductor dies 200 from a device substrate 150 cleaved from a composite substrate 100 using a porous silicon carbide layer 116 deposited over a transfer film 110.A composite substrate 100 is formed by bonding a transfer foil 110 including a porous silicon carbide layer 116 to a process surface 191 of a carrier substrate 190 and growing a low n-doped epitaxial layer 120 on an epitaxial surface 112 of the porous silicon carbide layer 116 by epitaxy.Semiconducting regions, conductive structures, and electronic component insulating structures 210 are formed in and / or on the epitaxial layer 120.As shown in FIG. 3A, the epitaxial layer 120 includes a plurality of equally sized device regions 220 arranged along two orthogonal horizontal directions. In each device region 220, the same type of electronic component 210 is formed.In the illustrated embodiment, acceptor atoms are implanted through a main surface 121 at a front side of the epitaxial layer 120 opposite the porous silicon carbide layer 116 to form a p-doped anode region 281 in each device region 220. Depositing and patterning a metal layer or metal layer stack forms an anode electrode 282 in each device region 220, with the anode electrode 282 and the anode region 281 forming an ohmic contact. Depositing and patterning an insulator layer or an insulator layer stack forms a passivation structure 283 that covers, among other things, a sidewall of the anode electrode 282 in each device region 220.The composite substrate 100 is divided into a device substrate 150 and a recovery substrate as described with reference to FIG. 1D.FIG. 3B shows the device substrate 150 including the epitaxial layer 120 and the device region 118 of the porous silicon carbide layer.A polishing process removes the device region 118 of the porous silicon carbide layer and exposes the epitaxial layer 120 at the back side of the device structure 150.As illustrated in FIG. 3C, the back surface 152 of the device substrate 150 exposes the epitaxial layer 120.Donor atoms may be introduced, e.g., implanted, through the back surface 152 of the device substrate 150. One or more metal-containing layers are deposited on the back surface 152 of the device substrate 150. Before or after the deposition of the one or more metal-containing layers, a local heat treatment activates the introduced donor atoms.The activated donor atoms form a highly doped contact layer 122 along the back surface 152 of the device substrate 150. The one or more deposited metal-containing layers form a metal layer structure 170.The highly doped contact layer 122 and the metal layer structure 170 form an ohmic contact.A dicing process laterally separates the device regions 220 of the device structure 150 from each other, each separated device region 220 forming the semiconductor die 200 of a vertical power semiconductor diode with a cathode electrode formed from a portion of the metal layer structure 170. A forward current of the power semiconductor diode flows between the anode electrode 282 at the front side and the cathode electrode at the back side of the semiconductor die 200.Instead of power semiconductor diodes, vertical transistors, for example, MOSFETs or IGBTs, may be formed in the semiconductor dies 200. Instead of completely removing the device region 118 of the porous silicon carbide layer 116 and forming the metal layer structure 170 on a surface of the epitaxial layer 120, CMP may remove only a portion of the device region 118 of the porous silicon carbide layer structure 116, and the metal layer structure 170 is formed on a recessed and planarized surface of the device region 118 of the porous silicon carbide layer 116.FIGS. 4A to 4C illustrate a process for forming a transfer film 110 including a single-crystal porous silicon carbide layer 116.FIG. 4A shows a starting substrate 300 made of nonporous monocrystalline silicon carbide. The starting substrate 300 is a single-crystal wafer or ingot (mold) and has two parallel main surfaces 301, 302. The polytype of silicon carbide is 4H. A first major surface 301 may have an off-axis section of about 4 degrees against the

[0001] major crystal plane. The first main surface 301 at the front side of the initial substrate 300 has a C-surface.On the first main surface 301 of the initial substrate 300, a porous surface layer 310 is formed by MAPCE. MAPCE porosifies (makes porous) a surface layer of the starting substrate 300 below the first surface 301.FIG. 4B shows the porous surface layer 310 formed by the MAPCE and the nonporous substrate region 390 of the starting substrate 300. The porous surface layer 310 is formed in a section of the initial substrate 300 directly below the first main surface 301.A separation process divides the porous surface layer 310 into a film region 316 and a substrate region 315. The film region 316 comprises a first layer region of the porous surface layer 310 and forms the porous silicon carbide layer 316 of a transfer film 110. The substrate portion 315 includes a second layer portion of the porous surface layer 316. The substrate portion 315 of the porous surface layer 310 and the nonporous substrate portion 390 form a recovery portion 360 of the starting substrate 300.Before or after separating the film portion 316 and the substrate portion 315, an auxiliary layer may be formed on or attached to a front side of the film portion 316, such that the transfer film 110 includes the porous silicon carbide layer 116 and the auxiliary layer.The recovery portion of the starting substrate, which includes the substrate portion of the divided porous surface layer and the nonporous substrate portion of the starting substrate, is post-processed. For example, the substrate region of the porous surface layer is planarized or completely removed, so that in a next cycle a further porous surface layer can be formed in the post-processed recovery region of the starting substrate.FIGS. 5 and 6 show composite substrates 100 comprising a carrier substrate 190 containing single crystal silicon carbide. A monocrystalline porous silicon carbide layer 116 of the 4H-polytype is present on a process surface 191 of the carrier substrate 190. The carrier substrate 190 is a recycling wafer or has a polytype different from 4H.An epitaxial layer 120 is formed on an epitaxial surface 112 of the porous silicon carbide layer 116 opposite the carrier substrate 190. The epitaxial layer 120 is in direct contact with the porous silicon carbide layer 116. The porous silicon carbide layer 116 contains a low-porous skin layer region with a porosity of less than 5%. The epitaxial layer 120 is in direct contact with the low-porous skin layer region.In FIG. 5, the single crystalline porous silicon carbide layer 116 is in direct contact with the process surface 191 of the carrier substrate 190. Silicon-carbon bonds are formed between the single-crystalline porous silicon carbide layer 116 and the carrier substrate 190.In FIG. 6, the single crystal porous silicon carbide layer 116 is in direct contact with an interfacial layer 130 formed on the process surface 191 of the carrier substrate 190. Chemical bonds are formed between the single crystal porous silicon carbide layer 116 and the interfacial layer 130. Chemical bonds are also formed between the interfacial layer 130 and the support substrate 190. The interfacial layer 130 may contain nitrogen atoms.FIGS. 7 and 8 show semiconductor dies 200 of power semiconductor devices 501, 502 that may be obtained from the composite substrate of FIG. 6.The semiconductor die 200 includes a single crystal silicon carbide body 230 having a planar front surface 231 at a front side and an opposing planar back surface 232. The front surface 231 and the back surface 232 are parallel to each other and extend horizontally. A distance between the front surface 231 and the back surface 232 defines a thickness of the silicon carbide body. A vertical direction is defined orthogonally to the horizontal directions.The silicon carbide body 230 comprises a single crystalline silicon carbide porous region 270 and a non-porous silicon carbide region 280 between the silicon carbide porous region 270 and the front surface 231. The non-porous silicon carbide region 280 is in direct contact with a planar horizontal main surface 271 of the porous silicon carbide region 270.A first load electrode 291 is formed on a front side of the nonporous silicon carbide region 280 opposite to the porous silicon carbide region 270. A second load electrode 292 is formed on a back side of the porous silicon carbide portion 270 opposite to the main surface 271 of the porous silicon carbide portion 270. The first and second load electrodes 291, 292 include one or more metal layers. An insulating passivation structure 283 covers a portion of the front surface 231 adjacent to the first load electrode 291, a portion of the first load electrode 291, and a sidewall of the first load electrode 291.The semiconductor body 230 includes a highly doped contact region 222 formed along the back surface 232 of the semiconductor body 230 and a lightly doped drift region between a front surface 231 and the contact region 222. The contact region 222 is obtained from a contact layer 122 of a device substrate 150 as illustrated in FIG. 3D. In the illustrated embodiments, the contact region 222 is entirely formed in the porous silicon carbide region 270. The contact region 222 and the second load electrode 292 form an ohmic contact.FIG. 7 shows a power semiconductor diode 501 having the first load electrode 291 constituting an anode electrode 282 and the second load electrode 292 constituting a cathode electrode. The anode electrode 282 forms or is connected to an anode terminal A. The cathode electrode forms a cathode terminal K or is connected to such a terminal. The contact region 222 is heavily n-doped. A p-doped anode region 281 is formed along the front surface 231 of the semiconductor body 230. The anode region 281 and the anode electrode 282 form an ohmic contact. The anode region 281 and the drift region 235 form a pn-junction.FIG. 8 shows a power transistor 502 having the first load electrode 291 forming a source electrode and the second load electrode 292 forming a drain electrode. The source electrode forms a source terminal S or is connected to such a terminal. The drain electrode forms a drain terminal D or is connected to such a terminal. The contact region 222 is heavily n-doped. A transistor control region 284 is formed along a front surface 231 of the semiconductor body 230. The transistor control region 284 includes n-doped source regions of transistor cells TC and one or more p-doped wells separating the source regions and the n-doped drift region 235. The source electrode forms ohmic contacts with the source regions and the p-doped well.The porosity of the porous silicon carbide portion 270 does not change along the lateral directions. The porosity is constant along the lateral directions. The porosity decreases as the distance to the back surface 232 of the silicon carbide body 230 increases along the vertical direction.A dopant concentration in the silicon carbide porous region 270 does not change along the lateral directions. The dopant concentration is constant along the lateral directions.

Claims

A method of manufacturing a semiconductor device, the method comprising: forming a transfer film (110) comprising a porous silicon carbide layer (116); then forming a composite substrate (100) comprising the transfer film (110) and a support substrate (190), wherein the transfer film (110) and the support substrate (190) are brought into contact with each other and joined to each other; forming an epitaxial layer (120) on a side of the porous silicon carbide layer (116) opposite to the support substrate (190); and dividing the composite substrate (100) into a device substrate (150) and a recovery substrate (160), wherein the device substrate (150) comprises the epitaxial layer (120) and the recovery substrate (160) comprises the support substrate (190).The method of claim 1, wherein the carrier substrate (190) comprises a polycrystalline silicon carbide substrate, a substrate containing single crystal silicon carbide of a polytype different from a polytype of the porous silicon carbide layer, and / or a silicon carbide recycling substrate.The method of claim 1, wherein forming the composite substrate (100) comprises bonding the transfer film (110) to the carrier substrate (190).The method of any one of claims 1 to 3, wherein the porous silicon carbide layer (116) has a bonding surface (111) having a C-surface, and forming the composite substrate (100) comprises bonding the bonding surface (110) of the porous silicon carbide layer (116) to the carrier substrate (190).The method of any one of claims 1 to 4, wherein the porous silicon carbide layer (116) has an epitaxial surface (112) having a Si surface, and wherein the epitaxial layer (120) is formed on the epitaxial surface (112) of the porous silicon carbide layer (116).The method of any of claims 1 to 5, further comprising: forming semiconducting regions (281, 284) of an electronic element (210) in and / or on the epitaxial layer (120) before dividing the composite substrate (100).The method of any of claims 1 to 6, further comprising: backside processing an exposed backside surface of the device substrate (150).The method of any of claims 1 to 7, further comprising: forming a metal layer structure (170) on an exposed back surface of the device substrate (150).The method of any of claims 1 to 8, further comprising: forming an ohmic contact on a back side of the device substrate (150).The method of any one of claims 1 to 9, wherein forming the transfer film (110) comprises forming a porous surface layer (310) on a front side of a single crystal silicon carbide base substrate (300) and separating a film portion (316) of the porous surface layer (310) from the base substrate (300), wherein the film portion (316) forms the porous silicon carbide layer (116) of the transfer film (110).The method of claim 10, wherein forming the porous surface layer (310) comprises metal assisted photochemical etching.The method of any one of claims 1 to 11, wherein dividing the composite substrate (100) comprises inducing a horizontal mechanical stress in the porous silicon carbide layer (116).A composite substrate, comprising: a carrier substrate (190) comprising single crystal silicon carbide; a single crystal silicon carbide porous layer (116) on a process surface (191) of the carrier substrate (190), wherein a poly type of the carrier substrate (190) is different from a poly type of the silicon carbide porous layer (116) and / or the carrier substrate (190) is a recycling wafer that does not meet specifications for a starting substrate for manufacturing power semiconductor devices; and an epitaxial layer (120) formed on a side of the silicon carbide porous layer (116) opposite to the carrier substrate (190).The composite substrate according to the preceding claim, wherein the single crystalline porous silicon carbide layer (116) is in direct contact with the process surface (191) of the carrier substrate (190).The composite substrate according to any one of the two preceding claims, wherein the epitaxial layer (120) is in direct contact with the porous silicon carbide layer (116).

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