REFERENCE POINTS WITH ASSOCIATE LOW-DENSITY METAL ZONES

Abstract

A device comprising an integrated circuit device comprising a reference point region of a first layer, wherein the reference point region comprises a metal region and a metal-free region; and a plurality of zones that are metal-free in multiple layers adjacent to the first layer, wherein the zones are defined by a base area based on the reference point region of the first layer and a second reference point region of a second integrated circuit device, wherein the base area comprises multiple slots.

Description

BACKGROUNDHybrid bonding is a packaging technology that includes an electrical and mechanical connection between two semiconductor devices. In order to bond two semiconductor components to one another, surfaces of the components are brought together under applied pressure and / or at elevated temperature. Hybrid bond bonding enables the integration of heterogeneous semiconductor devices (e.g., using different technology nodes or materials) onto a single wafer or package using various bonding methodologies, such as dielectric-to-dielectric bonding and metal-to-metal bonding.The devices involved in a hybrid bonding process may include one or more reference points (e.g., a structure used for alignment and positioning during manufacturing and assembly processes). The relative positioning of the reference points may be detected and used to provide an indication of whether the devices have been properly aligned.BRIEF DESCRIPTION OF THE DRAWINGSFIGS. 1A-1B and 2A-2B illustrate example integrated circuit devices including reference points. FIG. 3 illustrates a schematic illustration of a cross-sectional view of an example integrated circuit device. FIG. 4 illustrates example reference point structures that form a footprint for low density metal zones. FIG. 5 illustrates a cross-section of first and second integrated circuit devices. FIG. 6 illustrates a cross-section of first and second integrated circuit devices. FIG. 7 illustrates additional example reference point structures. FIG. 8 illustrates additional example reference point structures. FIG. 9 illustrates additional example reference point structures. FIG. 10 illustrates a process for forming low density metal zones and reference points. FIG. 11 is a top view of a wafer and dies, possibly including reference points with associated low density metal zones. FIG. 12 is a cross-sectional side view of an integrated circuit device, possibly including reference points with associated low density metal zones. FIGS. 13A-13D are simplified perspective views of example planar, FinFET, gate all around, and stacked gate all around transistors. FIG. 14 is a cross-sectional side view of an integrated circuit device assembly that may include reference points with associated low density metal zones. FIG. 15 is a block diagram of an example electrical device that may include reference points with associated low density metal zones. FIG. 16 illustrates additional example reference point structures. FIG. 17 illustrates a cross-section of first and second integrated circuit devices. FIGS. 18-21 illustrate additional example reference point structures.DETAILED DESCRIPTIONFIGS. 1A-1B illustrate example integrated circuit devices 102 and 104 including reference points 106 and 108. An integrated circuit device may represent any suitable device (apparatus) including semiconductor devices, interlayer dielectrics, and metal interconnects, such as a die or wafer including a plurality of dies. The devices may be bonded together as shown in FIG. 1B using a hybrid bonding process.In some embodiments, hybrid bonding may be performed on a wafer level (wafer-to-wafer bonding), i.e., individual wafers are hybrid bonded before being separated into dies. In other embodiments, hybrid bonding may be performed on a die-level (die-to-die bonding), i.e., the dies of individual wafers are hybrid bonded after the wafers are separated into dies. In still other embodiments, dies of a wafer may be die separated and then hybrid bonded to a wafer before the latter is die separated (die-to-wafer bonding).In various embodiments, the devices 102 and 104 may be bonded to one another using a bonding material. In some embodiments, the devices may be heterogeneous. For example, they may have been manufactured by different manufacturers using different materials and / or different manufacturing techniques. For each device, the terms "bottom surface" or "back side" of the device may refer to the back portion (back) of the device, e.g., bottom surface of the support structure of a given device, while the terms "top surface" or "front side" of the device may refer to the opposite other surface. When the top surface of the first IC device is bonded to the top surface of the second IC device (as depicted in FIG. 1B ), the devices are described as being bonded face-to-face (f2f). When the top surface of the first IC device is bonded to the bottom surface of the second IC device or the bottom surface of the first IC device is bonded to the top surface of the second IC device, the devices are described as being face-to-back (f2b) bonded. When the bottom surface of the first IC device is bonded to the bottom surface of the second IC device, the devices are described as being "back-to-back" (b2b) bonded. The embodiments described herein may be used with any of these bonding types.In some embodiments, bonding the surfaces of the first and second IC devices may be performed using insulator-insulator bonding, e.g., oxide-oxide bonding, where an insulating material of the first IC device is bonded to an insulating material of the second IC device. In some embodiments, a bonding material may be present between the surfaces of the first and second IC devices bonded together. The bonding material may be applied to one or both surfaces of the first and second IC devices that should be bonded, and then the first and second IC devices are assembled, possibly using appropriate pressure and heating the assembly to an appropriate temperature. In some embodiments, the bonding process typically occurs at room temperature. The IC devices are then treated at a higher temperature (e.g., in the range of 250 to 450 degrees Celsius to form covalent bonds between the dielectrics and the metal-to-metal bonds between the joining metals. In some embodiments, the bonding material may comprise an adhesion material and / or an etch stop material. In some embodiments, no bonding material is used, but bonding interface may still result from bonding the first and second IC devices together. In some embodiments, other types of bonding may be employed (e.g., metal-to-metal bonding or other suitable bonding). After bonding, conductive contacts (e.g., bumps) on the first device may be electrically connected to corresponding conductive contacts on the second device.In hybrid bonding, bump spacings may be much narrower than spacings used in other forms of bonding, e.g., solder-based bonding or C4 bonding. The distances may be, for example, less than 10 microns (or even less than 1 micron in some cases). Accordingly, the accuracy of alignment between dies is of vital importance to ensure proper connectivity between conductive contacts of a first IC device (e.g., die) and conductive contacts of a second IC device (e.g., die).As depicted in FIG. 1A, reference points 106, 108, and 112 are formed on or near the front sides of the respective devices. To enable high accuracy bonding, the hybrid bonding process may use reference points on the IC devices. Reference points may also be used during a post-bond inspection process step to measure bond overlay alignment accuracy. The alignment accuracy information may be fed back to the hybrid bonding equipment so that the equipment may make any suitable adjustments to improve the alignment accuracy for other devices and be fed forward (fed forward) to indicate whether a device is defective based on the bonding results.In various implementations, the alignment metrology uses infrared (IR) light to pass through the device (e.g., through silicon and an inter-layer dielectric (ILD) stack of a die), and compare bonded reference points in either a reflective or transmissive (transmissive) mode. FIG. 1B illustrates a reflective mode in which a light source provides IR light that passes down through devices 102 and 104. A portion of this light is reflected back to a detector by metal present in devices 102 and 104 (e.g., metal present at reference points 106, 108, and 112). The detector may use the detected light to identify the position of reference point 106 on the top device 102 and the position(s) of reference points 108 and / or 112 on the base device 104, and determine registration errors based on a comparison of the positions.In the embodiment of FIG. 1B, the components may be considered to be aligned when reference point 106 is aligned above reference point 108 and / or when reference point 106 is offset from reference point 112 (e.g., in the x and / or y directions by the proper distances). Thus, in various embodiments, the reference points (e.g., 106 and 112) may be offset from each other (e.g., in the x and / or y directions) and the orientation is based on how much the position differences between the reference points vary from the desired offset. FIGS. 2A-2B illustrate other example semiconductor devices 202 and 204 including reference points 206 and 208 that are offset from each other (as well as reference point 216 aligned with reference point 206). FIG. 2B also illustrates another mode (transmissive mode) of the alignment measurement technique, where IR light from a light source passes through both devices and is detected on the other side of the devices. The light may pass through metal-free regions and may be at least partially blocked by metallization.FIG. 3 provides a schematic illustration of a cross-sectional view of an example integrated circuit device (e.g., die) 300, in accordance with some embodiments of the present disclosure.Embodiments described herein may include front-end-of-line (FEOL) semiconductor processing and structures. FEOL may be a first portion of an IC fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in the semiconductor substrate or layer. FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers. After the last FEOL operation, the result is usually an insulated transistor wafer (e.g., without any wires).Embodiments described herein may also include back end of line (BEOL) semiconductor processing and structures. BEOL is the second portion of an IC fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are connected to wiring on the wafer, e.g., the metallization layer or layers. BEOL may include contacts, insulating layers (dielectrics), metal planes, and bond locations for chip-to-package interconnects. In the BEOL part of the fabrication stage, contacts (pads), bond wires, vias, and dielectric structures are formed.Embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. More specifically, although an example processing scheme may be illustrated using an FEOL processing scenario, such approaches may also be applicable to BEOL processing. Similarly, although an example processing scheme using a BEOL processing scenario may be illustrated, such approaches may also be applicable to FEOL processing.As shown in FIG. 3, the IC device 300 may include a front side 330 including an FEOL portion 310 including various logic layers, circuits, and devices for driving (drive) and controlling a logic IC. These circuits and devices may be configured for any number of functions, such as logic or computational transistors, input / output (I / O) transistors, access or switching transistors, and / or radio frequency (RF) transistors, to name a few examples. According to some embodiments, in addition to these devices and circuits, the FEOL portion 310 may include, for example, one or more other layers or structures associated with the semiconductor devices and circuits. The FEOL portion 310 may also include, for example, a substrate and one or more dielectric layers surrounding active and / or conductive portions of the device and circuits. The FEOL portion may also include one or more conductive contacts that provide electrical contact to transistor elements, such as gate structures, drain regions, or source regions. The FEOL portion may also include local interconnects (e.g., vias or lines) for connecting contacts to interconnect features within the BEOL portion 320.The front side 330 of the IC device 300 also includes a BEOL portion 320 including various metal interconnect layers (e.g., metal 1 to metal n, where n is any suitable integer) and thick metal layer(s) 350 including one or more metal layers having one or more thicknesses greater than the thicknesses of the lower metal layers (e.g., metal 1 to metal n). Different metal layers of the BEOL portion 320 may be used to connect the different inputs and outputs of the FEOL portion 310.In general, each of the metal interconnect layers of the BEOL portion 320, e.g., each of the layers M1-Mn and thick metal layer(s) 350 (sometimes referred to as giant metal layers) shown in FIG. 3, may include a via portion and a trench / interconnect portion. Typically, the trench portion of a metal layer is over the via portion, but in other embodiments, a trench portion may be provided under a via portion of any given metal layer of the BEOL portion 320. The trench portion of a metal layer may be configured for transmission of signals and power along metal lines (sometimes also referred to as "trenches") extending in the x-y plane (e.g., in the x or y direction), while the via portion of a metal layer may be configured for transmission of signals and power through metal vias extending in the z direction, e.g., to any of the adjacent metal layers above or below. Accordingly, vias connect metal structures (e.g., metal lines or vias) from one metal layer to metal structures of an adjacent metal layer. Although referred to as "metal" layers, various layers of the BEOL portion 320, e.g., layers M1-Mn, or thick metal layer(s) 350 shown in FIG. 3, may include certain structures of conductive metals, e.g., copper (Cu), aluminum (Al), tungsten (W), or metal alloys, or more generally structures of an electrically conductive material formed in an insulating medium, such as an interlayer dielectric (ILD). The isolation medium may include any suitable ILD materials, such as silicon oxide, silicon nitride, silicon carbon nitride, silicon carbide, aluminum oxide, and / or silicon oxynitride. In various embodiments, the isolation medium may have sufficient transparency that IR light (in some embodiments, the IR light may have a wavelength of 1-2 microns) may pass through to enable detection of reference points. In various embodiments, any one or more of these layers may additionally include active devices (e.g., transistors, diodes) and / or passive devices (e.g., capacitors, resistors, inductors).In various embodiments, a bonding layer 360 may be formed on the top surface of the IC device 300. For example, the bonding layer 360 may include various electrical contacts (e.g., bumps, pads, etc.) that may be electrically connected to corresponding electrical contacts of another IC device in a hybrid bonding process. In some embodiments, the bonding layer 360 may also include one or more dielectric materials to form the bond between the IC devices (e.g., the dielectric material may be placed between the electrical contacts).In various embodiments, a reference point 370 may be placed on or near a surface (e.g., a front side) of an IC device. For example, a reference point 370 may be placed in the bonding layer 360. Additionally or alternatively, a reference point 370 may be placed in one or more of the thick metal layer(s) 350. In some embodiments, the same reference point 370 may be formed in both the bond layer 360 and a thick metal layer 350. In some embodiments, the same reference point 370 may be formed in multiple layers of the thick metal layer(s) 350. In other embodiments, a reference point 370 may be formed in another suitable layer proximate to the bond layer 360 (e.g., one of the other upper metal layers). In some embodiments, a portion of a reference point may be formed in one layer and another portion of the reference point may be formed in another layer.The IC device 300 may also include a back side 340. For example, the backside 340 may be formed on the opposite side of a wafer from the front side 330. In various embodiments, the back side 340 may include any suitable elements to aid in the operation of the IC device 300. For example, the back side 340 may include various metal layers to provide power to logic of the FEOL portion 310. In some embodiments, transistors or other circuit elements may be formed on the back side 340 of the IC device 300.In various embodiments, reference point 370 may include a structure formed by a metal, such as copper, aluminum, tantalum, or another type of metal (e.g., used in a routing layer). The structuring in the reference point can have any suitable dimensions. The patterning may be thick enough to reflect and / or block IR light. For example, the patterning may be between 025 micrometers and 5 micrometers thick. Typical reference points used in hybrid bonding may be on the order of 30x30 micrometers to 120x120 micrometers. If the stack of layers in a device has a metal interconnect grid below a standard reference point, then the IR light may be blocked by the metal of the grid. Accordingly, a metal-free zone in the reference point footprint below the reference point for the alignment metrology is preferred so as not to distort the detection of the reference point (as used herein, a footprint may refer to an area in the x-y plane that may be extended upward and / or downward in the z-direction). In FIGS. 1 and 2, metal-free zones (or other low density metal zones) are bounded by dashed lines and reference points and are depicted as 110, 112, 210, 212, and 214. In some embodiments, the metal-free region (or other low density metal region) may consist of the full stack on the base device 104, 204 for the transmissive mode (e.g., as shown by 212 and 214) or only thicker metals for the reflective mode (e.g., as shown by 112).In various embodiments, the area below the base of the reference point 370 (possibly including the layers below the reference point and possibly referred to herein as a "zone") may not be completely metal-free in order for sufficient IR light to pass through the layers for alignment metrology purposes. In some embodiments, the area below the footprint may be a "low density metal zone" such that the density of the metal through the zone is low enough that sufficient IR light passes for the detection of the pattern of the reference point (and therefore could include a no metal zone or a zone with sufficiently low total metal density in the layers). For example, in some low density metal zones, one or more of the thinnest metal layers (e.g., the lowest metal layers) may be allowed to have a first threshold percentage of metal density (e.g., 20%, 30%, etc.), one or more of the next thinner metal layers may be allowed to have a second threshold percentage (e.g., 10%, 15%, etc.) of metal density that is lower than the first threshold percentage, and so forth (e.g., other thresholds may be employed for other metal layers), while some of the thicker layers (e.g., thick metal layer(s) 350 and / or other higher metal layers below the layer(s) with the reference point) may need to be metal-free within the base of the reference point.Large low density metal (e.g., metal-free) zones may be problematic. For example, such regions having a large size corresponding to the size of a reference point (e.g., in the range of 30x30 micrometers to 120x120 micrometers) may create problems during manufacturing process steps (e.g., chemical mechanical planarization (CMP) and plating) due to resulting metal density variations across the device.In various embodiments of the present disclosure, low density metal regions in an IC device are present in narrow slots within the footprint of a reference point area as defined by the size and geometry of the reference points. In various embodiments, the reference point range may be defined by the expected outer perimeter of metal in a pair of corresponding reference points (e.g., a reference point on an upper IC device and a reference point on a base IC device) at perfect alignment. Within the reference point range, there may be a plurality of empty slots in the combined reference point structure (where the combined reference point structure refers to the combined structure when one reference point of the pair is superimposed on the other reference point). The empty slits may correspond to no metal areas in the layers where the reference points are formed. The base of the empty slots may define a low density metal region on the first IC device through which IR light may pass. In some embodiments, the footprint of the empty slots may also define a low density metal region through at least a portion of the second IC device.Accordingly, in some embodiments, a large metal-free zone is avoided below the entire footprint of the reference point area. Various embodiments may provide technical advantages, such as reduced reference point footprint or reduced process (e.g., CMP topography, plating) issues.FIG. 4 illustrates reference point structures 402, 412, and 416. The structures are shown as plan views extending across the x and y directions. Structure 402 may be implemented on a first IC device (e.g., a top die) and structure 412 may be implemented on a second IC device (e.g., a base die), or vice versa. In some embodiments, the reference point represented by structure 402 may be formed on multiple layers of the first IC device (e.g., the reference point may be duplicated on multiple layers, such as a bond layer and a thick metal layer or on two thick metal layers) or may be formed over multiple layers (e.g., a portion of the reference point may be formed on one layer and another portion of the reference point may be formed on another layer). The reference point represented by structure 412 may be similarly formed on the second integrated circuit device.Structure 416 illustrates structure 402 overlaid on structure 412 (and therefore may represent the structure that may be detected responsive to the application of IR light during an alignment metrology when the first IC device and the second IC device are perfectly aligned, because the detected IR light passing through the void regions will be distinguished from light blocked or reflected from metal regions).The reference point structures are bounded by a reference point base 404 which, in some examples, may be defined by the outer perimeter of the outermost metal of the pair of reference points at one orientation (e.g., the outer perimeter of metal region 414 in this case). In some embodiments, the reference point base 404 may be extended beyond the outer perimeter of the outermost metal of the pair of reference points, e.g., to provide an extended low density metal zone within the base to enable detection of one or more edges of the outermost metal when the outermost metal is on the reference point of the base die.The reference point structure 402 of the first IC device includes a first metal region 406 (including a fixed square), a first empty region 410, a second metal region 408 (including a square shaped ring), and an empty region 411. The second metal portion 408 may include an outer periphery having a square shape and an inner periphery having a square shape with metal formed in the region between the outer periphery and the inner periphery. Herein, the term ring may be used to refer to such a structure defined by an inner periphery and an outer periphery having the same shape, regardless of the shape. The empty areas 410 and 411 are also depicted as square shaped rings.The second IC device reference point structure 412 includes an empty region 413 shaped as a fixed square and a metal region 414 (including a square shaped ring). The combined reference point structure 416 includes metal region 406, metal region 408, and metal region 414. The combined reference point structure 416 also includes blank areas 418 and 420 (each blank area being in the form of a square shaped ring).In various embodiments, the empty areas within the base of the combined reference point 416 may include a plurality of slots. The void portion 418 may include, for example, four slots (each slot corresponding to a side of the square shaped ring). Each slot of the void region 418 may define a low density metal zone extending through other layers of the first IC device (e.g., multiple adjacent metal interconnect layers below and / or adjacent to a layer of the reference point), as shown in FIG. 5. Indeed, the void regions of the combined structure may form a lateral cross-section (e.g., in the x and y directions) or a footprint through which the low density metal regions may extend in the z direction through the IC device. In various embodiments, the low density metal zones may have a larger footprint than that shown by the empty areas of the combined reference point 416. For example, to ensure that the inner edge of the metal region 414 can be detected, the footprint for the low density metal zone may occupy the region shown by 418, as well as a portion of the region shown as occupied by metal region 414. This concept is more clearly illustrated in Figure 5.FIG. 5 illustrates a cross-section of a first IC device 502 and a second IC device 504. The first IC device 502 includes a first portion 505 and a second portion 506. The first portion 505 may include one or more materials (e.g., silicon) that allow passage of IR light during a reference point detection. In some embodiments, the first portion 505 may represent an FEOL portion or portion thereof. The second portion 506 may comprise one or more materials (e.g., metals) that reflect and / or block IR light applied during a reference point detection. To ensure that during a reference point detection sufficient IR light passes through in the respective zones, low density metal zones corresponding to the slits of the empty areas of the combined structure 416 may be defined in the second portion 506 of the first IC device 502.In the depicted embodiment, the reference point structure 402 may be implemented in a bonding layer of IC device 502, which may be on the bottom side of the device (e.g., after device fabrication, it may be flipped over before bonding). A cross-section (e.g., taken through the center of the reference point) is shown in FIG. 5. As depicted, metal region 406 is shown, as well as left and right portions of metal region 408. Low density metal regions 508 are formed through different layers of the second portion 506 of the IC device 502 in the z-direction. Any of the low density metal zones 508 may be formed based on the footprints of the slits of the empty regions 418 and 420 of the combined reference point pattern 416.For example, low density metal zone 508A is formed based on the footprint of the slot corresponding to the left side of empty region 418, low density metal zone 508B is formed based on the footprint of the slot corresponding to the left side of empty region 420, low density metal zone 508C is formed based on the footprint of the slot corresponding to the right side of empty region 420, and low density metal zone 508D is formed based on the footprint of the slot corresponding to the right side of empty region 418. Similar low density metal regions (now shown due to the location of the depicted cross-section) may be similarly formed for the upper and lower portions of the void regions 418 and 420.Accordingly, the low density common metal regions formed in the base of the slits of the void portion 418 may be a square shaped ring extending through different layers in the z direction. Similarly, the low density common metal regions formed in the base of the slits of the void region 420 may be a smaller square shaped ring extending through the same layers in the z direction. In the low density metal zones, at least some of the layers (e.g., the layers closer to the reference point, possibly comprising thicker metal compounds) may be completely metal free in the area covered by the zones.The second IC device 504 may also include a first portion 509 and a second portion 510. In the depicted embodiment, the reference point pattern 412 may be implemented in a bonding layer of IC device 504, which may be on top of the device. As depicted, two portions of the metal region 414 (corresponding to portions of the left side and right side of the square shaped ring) are shown on an upper layer of the second IC device 504.The low density metal regions 508 may allow IR light to pass through the first IC device 502 to the second integrated device 504 when the two devices are bonded together. Passing this light may allow for detection of portions of metal region 414 when first IC device 502 and second IC device 504 are misaligned (e.g., misalignment will result in less empty region being detected because metal region 414 may move within the footprint of low density metal regions 508 and block or reflect light that would otherwise be detected). Indeed, the detected dimensions of blank areas (corresponding to light that has not been blocked or reflected) may indicate the degree of misalignment in one or both of the x or y directions.In the depicted embodiment, the low density metal zones 508A and 508D are wider (opposite) than the corresponding empty slot 418 to allow sufficient margin (illumination) for detecting the edge of the metal 414 during an alignment measurement technique. Accordingly, in FIG. 5, the inner edges of metal 414 are shown as aligning in the center of low density metal regions 508A and 408D.FIG. 6 illustrates an embodiment similar to that shown in FIG. 5, but in FIG. 6, the second IC device 604 also includes low density metal zones based on the footprint of the void areas of the combined structure 416 in the second portion of the second IC device 604. Such an embodiment may be compatible with alignment measurement using a transmissive mode where the IR light is detected at the bottom of the second device, while the embodiment of FIG. 5 is compatible with alignment measurement using a reflective mode.FIG. 7 illustrates additional reference point structures 702, 704, and 706 that may serve as the basis for the footprint of low density metal regions in one or both of first and second IC devices. The structures are shown as plan views. Structure 702 may be implemented on a first IC device (e.g., a top die) and structure 704 may be implemented on a second IC device (e.g., a base die), or vice versa. Structure 702 includes a metal region 708 comprising a square shaped ring having an outer perimeter defining the reference point base 710 for the pair of reference points. Inside metal region 708 is an empty region 712 comprising a fixed square.Structure 704 includes a metal region 714 including a fixed square in the center and an empty region 716 between the metal region 714 and the perimeter defined by the reference point footprint 710.Combined structure 706 represents structure 702 overlaid on structure 704 (and therefore may represent the structure that may be detected responsive to application of IR light during an alignment measurement technique when the first IC device and the second IC device are perfectly aligned). The combined structure 706 includes an empty region 718 formed between the metal region 714 and the metal region 708. Similar to the void areas 418 and 420, the slits of the void area 718 may form footprints for low density metal regions of a first and / or second IC device to be hybrid bonded together.FIG. 8 illustrates additional reference point structures 802, 804, and 806, which may serve as the basis for the footprint of low density metal regions in one or both of first and second IC devices. The structures are shown as plan views. Structure 802 may be implemented on a first IC device (e.g., a top die) and structure 804 may be implemented on a second IC device (e.g., a base die), or vice versa. Structure 802 includes a metal region 808 comprising a square shaped ring having an outer perimeter defining the reference point base 810 for the pair of reference points. Structure 802 also includes a metal region 812 including a fixed square inside metal region 808 (in various embodiments, the metal regions of a reference point or a combined reference point structure may be concentric, although in other embodiments they may have different centers). Structure 802 also includes a void region 814 that is between metal region 812 and metal region 808.Structure 804 includes a metal region 816 comprising a solid square at the center and a metal region 818 comprising a square shaped ring around metal region 816. Structure 804 also includes an empty region 820 between metal region 818 and metal region 816, and an empty region 822 between the outer perimeter of metal region 818 and reference point footprint 810.Combined structure 806 represents structure 802 overlaid on structure 804 (and therefore may represent the structure that may be detected responsive to the application of IR light during an alignment measurement technique when the first IC device and the second IC device are perfectly aligned). The combined structure 806 is similar to the combined structure 416 described above. The slits of the void regions 824 and 826 may each form a footprint for a respective low density metal region of a first and / or second IC device to be hybrid bonded together (similar to the void regions 418 and 420 described above).FIG. 9 illustrates additional reference point structures 902, 904, and 906 that may serve as the basis for the footprint of low density metal regions in one or both of first and second IC devices. The structures are shown as plan views. Structure 902 may be implemented on a first IC device (e.g., a top die) and structure 904 may be implemented on a second IC device (e.g., a base die), or vice versa. Structure 902 includes a metal region 908 comprising a plus shaped ring having an outer perimeter defining the reference point base surface 910 for the pair of reference points. Structure 902 also includes an empty region 912 comprising a fixed plus shape in metal region 908.Structure 904 includes a metal region 914 comprising a fixed plus shape in the center and a blank region 916 between the outer perimeter of the metal region 914 and reference point base 910.Structure 906 illustrates structure 902 overlaid on structure 904 (and therefore may represent the structure that may be detected responsive to application of IR light during an alignment metrology when the first IC device and the second IC device are perfectly aligned). Structure 906 includes a void 918 having different slots (e.g., a slot for each of the twelve sides of void 918) that form footprints for low density metal regions of a first and / or second IC device to be hybrid bonded together.As shown in FIG. 9, the bases for the low density metal regions formed in an IC device are not limited to the slits of square shaped rings. Rather, the blank area forming the bases may take any suitable shapes that may include slots, such as squares (e.g., as shown in FIGS. 4 and 7-8), lines, rectangles, triangles, pentagonals, hexagon, octagons, circles, X, + (e.g., as shown in FIG. 9) or other shapes, rings corresponding to such shapes (e.g., shapes bounded by an inner perimeter and outer perimeter having the same shape), or groups of similarly or differently sized shapes (e.g., smaller squares or rectangles). In various embodiments, the metal regions within each of the reference points are concentric (and therefore the combined structure is expected to be concentric when perfectly aligned, while deviations from such concentricity as detected by the alignment metrology may indicate the degree of misalignment in the x and y directions).FIG. 16 illustrates additional reference point structures 1602, 1612, and 1616 that may serve as the basis for the footprint of low density metal regions in one or both of first and second IC devices. The structures are shown as plan views. Structure 1602 may be implemented on a first IC device (e.g., a top die) and structure 1612 may be implemented on a second IC device (e.g., a base die), or vice versa. Structure 1602 includes a metal region 1608 comprising a square shaped ring. Structure 1602 also includes metal region 1606 comprising a fixed square inside metal region 1608. Between metal region 1608 and metal region 1606 is an empty region 1610 comprising a square shaped ring.Structure 1612 includes a metal region 1614 including a fixed square at the center and an empty region 1613 between the metal region 1614 and the perimeter defined by the reference point base 1604. In this embodiment, the square of metal region 1614 is larger than the square of metal region 1606.Combined structure 1616 represents structure 1602 overlaid on structure 1612 (and therefore may represent the structure that may be detected responsive to application of IR light during an alignment measurement technique when the first IC device and the second IC device are perfectly aligned). The combined structure 1616 includes an empty region 1620 formed between the metal region 1614 and the metal region 1608. The slits of the void 1620 may form footprints for low density metal regions of a first and / or second IC device to be hybrid bonded together.FIG. 17 illustrates a cross-section of a first IC device 1702 and a second IC device 1704 (e.g., similar to devices 502 and 504). To ensure that sufficient IR light passes through in the respective zones during a reference point detection, low density metal zones 1708A and 1708B corresponding to the slits of the void areas of the combined structure 1616 may be defined in the second portion of the first IC device 1702.A cross-section (e.g., taken through the center of the reference point) is shown in FIG. 17. As depicted, metal region 1606 is shown, as well as left and right portions of metal region 1608. Low density metal regions 1708A and 1708B are formed through different layers of the second portion of the IC device 1702 in the z-direction. Any of the low density metal zones 1708 may be formed based on the footprints of the slits of the empty regions 1620 of the combined reference point pattern 416. For example, the low density metal zones 1708 together may have a cross-section in the x-y plane, equal to the area of the void 1620. As another example, the low density metal zones 1708 together may have a cross-section in the x-y plane including the void region 1620 but larger than the void region 1620 (e.g., to include additional margin for detecting an edge of the metal region 1614).In some embodiments, portions of the empty regions shown above in the reference point structures for the first or second IC device could include regions that may or may not include metal. For example, for the portions of the void areas of the first or second IC device that do not overlap with the void areas of the combined structure (defining the footprints for the low density metal zones), these portions may be either metal or metal-free because they would not negatively impact the resulting image during alignment detection (unless these portions need to be metal-free or other low density metal zones to enable detection of an edge of metal in the top die reference point).FIG. 18 illustrates a system 1800 including a portion of a first IC device 1806 and a portion of a second IC device 1808 hybrid-bonded together. View 1802 depicts a top view corresponding to a reference point region of the system when the first and second IC devices are perfectly aligned (e.g., this view may represent the view that could be detected by alignment metrology), and view 1804 depicts a side view of a cross-section taken along line 1814.The reference point region 1818 of the first IC device 1806 includes a plurality of slots 1810, each defining a footprint for a low density metal region 1830 through the first IC device 1806. One or more of these slots (e.g., 1810c) do not have underlying metal regions in the second IC device reference point region 1820, while one or more other slots (e.g., 1810a, 1810b) have underlying metal regions (e.g., 1812a, 1812b) in the reference point region 1820. In the depicted embodiment, the slots defining low density metal regions having underlying metal regions have a footprint that is larger than the underlying metal regions (e.g., a respective underlying metal region 1812 may be nested within a corresponding footprint of the corresponding low density metal region 1830). In various embodiments, the reference point region of the first IC device may include one or more slits 1810 that are orthogonal to one or more other slits.During an alignment metrology, the edges of any number of the low density metal zones corresponding to slots 1810 may be detected as a reference point mark (mark). For example, the low density metal region 1830a corresponding to a slot 1810c may appear different than the area around the low density metal region (as this area may include metal blocking or reflecting of the IR light).For the low density metal zones that include underlying metal (e.g., 1830 aand 1812 a), the edges of the underlying metal may be detected as a reference point mark during an alignment metrology and may be compared to one or more other detected reference point marks to determine alignment metrics.FIG. 19 illustrates a system 1900 similar to system 1800, but in which some of the metal-free zones (e.g., 1930) corresponding to slits (e.g., 1910) include metal 1916 in a reference point region of the first IC device (e.g., on a top layer or near the top layer). During an alignment metrology, this metal may be detected as a reference point mark.FIG. 20 illustrates a system 2000 similar to system 1800, but in which the low density metal zones having metal underlying in the reference point region of the second IC device are even smaller (since the corresponding slots include rectangular shaped rings). In this system, the other slots are solid rectangles and do not have associated metallization in the reference point area of the first IC device (similar to system 1800).FIG. 21 illustrates a system 2100 similar to system 2000, but in which the fixed rectangular slots do not have an associated metallization in the reference point area of the first IC device (similar to system 1900).In various embodiments, the shorter dimensions of the slots may be between 1 and 10 micrometers, while the longer dimensions of the slots may be between 5 micrometers to 30 micrometers, although other dimensions may be used in other embodiments.In other embodiments, the groups of slots depicted in FIGS. 18-21 may have any other suitable shapes (such as those described herein).In various embodiments, the total reference point footprint may be any suitable size, such as within the range of 30x30 micrometers to 100x100 micrometers (the reference point footprint area not being limited to the shape of a square). In various embodiments, the width of the slits in the empty region forming the bases for the low density metal zones (and thus the widths of the low density metal zones themselves) may be between 1-10 micrometers, for example. In some embodiments, the width of one or more rings in the combined reference point may be the same as the width of slot-empty areas in the combined reference point (in other embodiments, these widths may differ). In various embodiments, the width of the rings may be between 1 and 10 micrometers.In one embodiment, the reference point footprint is about 50x50 micrometers and the width of the slits and rings within the reference point are about 5 micrometers.The slots (and their corresponding low density metal zones) may be relatively long and narrow. For example, a length of a particular slot may be more than 2x, 3x, or 5x of the respective width.As described above, the metal of the reference points may comprise any suitable metal such as copper, aluminum, tungsten, or metal alloy. In some embodiments, the metal of the reference points may comprise a metal used for metal interconnects on the same or a different layer as the reference point. The underlying low density metal regions may comprise an ILD material, for example.FIG. 10 illustrates a process for forming reference points with associated low density metal zones. At 1002, metal interconnects and low density metal regions 1002 are formed on metal interconnect layers of a first and / or second IC device. In various embodiments, this may include omitting a metal pattern within any portions of the layers that are within the low density metal zones. At 1004, a reference point is formed on a first IC device. At 1006, a reference point is formed on a second IC device. The reference point of the second IC device is associated with the reference point of the first IC device, but may not match the design of the reference point of the first IC device.Although FIG. 10 shows example blocks of process 1000, in some implementations, process 1000 may include additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted in FIG. 10. Additionally or alternatively, two or more of the blocks of the process 1000 may be performed in parallel.FIG. 11 is a top view of wafer 1100 and dies 1102, wherein individual dies may include reference points with associated low density metal zones as described herein. The wafer 1100 may be composed of a semiconductor material and may include one or more dies 1102 having integrated circuit structures formed on a surface of the wafer 1100. The individual dies 1102 may be a repeating unit of an integrated circuit product that includes any suitable integrated circuit. After the manufacture of the semiconductor product is completed, the wafer 1100 may be subjected to a dicing process in which the dies 1102 are separated from each other to provide discrete "chips" of the integrated circuit product. Die 1102 may include one or more transistor-supporting circuitry to route electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other integrated circuit components. In some embodiments, wafer 1100 or die 1102 may include a memory device (e.g., a random access memory (RAM) device, such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive-bridging RAM (CBRAM) device, etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 1102. For example, a memory array formed by multiple memory devices may be formed on a same die 1102 as a processor unit (e.g., processor unit 1502 of FIG. 15 ) or other logic configured to store information in the memory devices or execute instructions stored in the memory array. Various microelectronic assemblies disclosed herein may be fabricated using a die-to-wafer assembly technique in which some dies are attached to a wafer 1100 including other dies and the wafer 1100 is subsequently singulated.FIG. 12 is a cross-sectional side view of an integrated circuit device 1200, possibly including reference points with associated low density metal zones as described herein. One or more of the integrated circuit devices 1200 may be included in one or more dies 1102 (FIG. 11 ). The integrated circuit device 1200 may be formed on a die substrate 1202 (e.g., the wafer 1100 of FIG. 11 ) and may be included in a die (e.g., the die 1102 of FIG. 11 ). The die substrate 1202 may be a semiconductor substrate composed of semiconductor material systems including, for example, N-type or P-type material systems (or a combination of both). The die substrate 1202 may include, for example, a crystalline substrate formed using a bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate 1202 may be formed using alternative materials that may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as Group II-VI, III-V, or IV may also be used to form the die substrate 1202. Although some examples of materials from which the die substrate 1202 may be formed are described herein, any material that may serve as a base for an integrated circuit device 1200 may be used. The die substrate 1202 may be part of a singulated die (e.g., the dies 1102 of FIG. 11 ) or a wafer (e.g., the wafer 1100 of FIG. 11 ).The integrated circuit device 1200 may include one or more device layers 1204 disposed on the die substrate 1202. The device layer 1204 may include features of one or more transistors 1240 (e.g., metal oxide semiconductor field effect transistors (MOSFETs)) formed on the die substrate 1202. Transistors 1240 may include, for example, one or more source and / or drain (S / D) regions 1220, a gate 1222 to control current flow between S / D regions 1220, and one or more S / D contacts 1224 to route electrical signals to / from S / D regions 1220. Transistors 1240 may include additional features not depicted for clarity, such as device isolation regions, gate contacts, and the like. The transistors 1240 are not limited to the type and configuration depicted in FIG. 12, and may have a wide variety of other types and configurations, such as planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors, such as dual-gate transistors or tri-gate transistors, as well as wrap-around (wrap-around) or all-round (all-round) gate transistors, such as nanoribbon, nanolayer, or nanowire transistors. Examples of non-planar transistors will be described in more detail in connection with FIGS. 13A-13D.A transistor 1240 may include a gate 1222 formed of at least two layers, a gate dielectric and a gate electrode. The gate dielectric may include a layer or a stack of layers. The one or more layers may comprise silicon oxide, silicon dioxide, silicon carbide and / or a high-k dielectric material.The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an anneal process may be performed on the gate dielectric to improve its quality when a high-k material is used.The gate electrode may be formed on the gate dielectric and may include at least one of a P-type work function metal and an N-type work function metal depending on whether the transistor 1240 is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may be a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these materials, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning) are not limited thereto.In some embodiments, when viewed as a cross-section of the transistor 1240 along the source-channel-drain direction, the gate electrode may be a U-shaped structure including a bottom portion substantially parallel to the surface of the die substrate 1602 and two sidewall portions substantially perpendicular to the top surface of the die substrate 1602. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the die substrate 1202 and does not include sidewall portions substantially perpendicular to the top surface of the die substrate 1202. In other embodiments, the gate electrode may consist of or comprise a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of or comprise one or more U-shaped metal layers formed on top of one or more planar, non-U-shaped layers.In some embodiments, a pair of sidewall spacers may be formed on opposite sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon and silicon oxynitride. Processes for forming sidewall spacers are known in the art and generally include deposition and etch process steps. In some embodiments, a plurality of spacer pairs may be used; for example, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.S / D regions 1220 may be formed within die substrate 1202 adjacent to gate 1222 of individual transistors 1240. The S / D regions 1220 may be formed using, for example, an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion implanted into the die substrate 1202 to form the S / D regions 1220. An anneal process that activates the dopants and causes them to diffuse further into the die substrate 1202 may follow the ion implantation process. In the later process, the die substrate 1202 may be first etched to form recesses at the locations of the S / D regions 1220. An epitaxial deposition process may then be performed to fill the recesses with material used to form the S / D regions 1220. In some implementations, the S / D regions 1220 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorus. In some embodiments, the S / D regions 1220 may be formed using one or more alternative semiconductor materials, such as germanium or a / r Group III-V material or alloy. In further embodiments, one or more layers of metal and / or metal alloys may be used to form the S / D regions 1220.Electrical signals, such as power and / or input / output (I / O) signals, may be routed to and / or from the devices (e.g., transistors 1240) of device layer 1204 through one or more interconnect layers disposed on device layer 1204 (as shown as interconnect layers 1206- 1210 in FIG. 12 ). For example, electrically conductive features of the device layer 1204 (e.g., the gate 1222 and the S / D contacts 1224) may be electrically coupled to the interconnect structures 1228 of the interconnect layers 1206- 1210. The one or more interconnect layers 1206- 1210 may form a metallization stack (also referred to as an "II,D stack") 1219 of the integrated circuit device 1200.The interconnect structures 1228 (e.g., lines) may be arranged within the interconnect layers 1206- 1210 to route electrical signals according to a wide variety of designs; in particular, the arrangement is not limited to the particular configuration of interconnect structures 1228 depicted in FIG. 12. Although a particular number of interconnect layers 1206- 1210 are depicted in FIG. 12, embodiments of the present disclosure include integrated circuit devices having more or fewer interconnect layers than depicted.In some embodiments, the interconnect structures 1228 may include lines 1228 aand / or vias 1228 bbeing filled with an electrically conductive material, such as a metal. The lines 1228 amay be arranged to route electrical signals in a direction of a plane substantially parallel to a surface of the die substrate 1202 on which the device layer 1204 is formed. For example, the lines 1228 amay route electrical signals in a direction into and out of the page and / or in a direction across the page. The vias 1228 bmay be arranged to route electrical signals in a direction of a plane substantially perpendicular to the surface of the die substrate 1202 on which the device layer 1204 is formed. In some embodiments, vias 1228 bmay electrically couple lines 1228 aof different interconnect layers 1206- 1210 to each other.The interconnect layers 1206- 1210 may include a dielectric material 1226 disposed between the interconnect structures 1228, as in FIG. 12. In some embodiments, the dielectric material 1226 disposed between the interconnect structures 1228 in different ones of the interconnect layers 1206- 1210 may have different compositions; in other embodiments, the composition of the dielectric material 1226 between different interconnect layers 1206- 1210 may be the same. The device layer 1204 may include a dielectric material 1226 also disposed between the transistors 1240 and a bottom layer of the metallization stack. The dielectric material 1226 included in the device layer 1204 may have a different composition than the dielectric material 1226 included in the interconnect layers 1206- 1210; in other embodiments, the composition of the dielectric material 1226 in the device layer 1204 may be the same as a dielectric material 1226 included in any of the interconnect layers 1206- 1210.A first interconnect layer 1206 (referred to as metal 1 or "M1") may be formed directly on the device layer 1204. In some embodiments, the first interconnect layer 1206 may include lines 1228 aand / or vias 1228 bas shown. The lines 1228 aof the first interconnect layer 1206 may be coupled to contacts (e.g., the S / D contacts 1224) of the device layer 1204. Vias 1228 bof first interconnect layer 1206 may be coupled to lines 1228 aof a second interconnect layer 1208.The second interconnect layer 1208 (referred to as metal 2 or "M 2") may be formed directly on the first interconnect layer 1206. In some embodiments, the second interconnect layer 1208 may include via 1228 bto couple the interconnect structures 1228 of the second interconnect layer 1208 to the lines 1228 aof a third interconnect layer 1210. Although the lines 1228 aand the vias 1228 bare structurally bounded by a line within individual interconnect layers for clarity, in some embodiments, the lines 1228 aand the vias 1228 bmay be structurally and / or materially continuous (e.g., simultaneously filled during a dual damascene process).The third interconnect layer 1210 (referred to as metal 3 or "M3") (and additional interconnect layers, as desired) may be sequentially formed on the second interconnect layer 1208 according to similar techniques and configurations described in connection with the second interconnect layer 1208 or the first interconnect layer 1206. In some embodiments, the interconnect layers that are "higher up" (e.g., further away from device layer 1204) in metallization stack 1219 in integrated circuit device 1200 may be thicker than the interconnect layers that are lower in metallization stack 1219, with lines 1228 aand vias 1228 bin the higher interconnect layers being thicker than those in the lower interconnect layers.The integrated circuit device 1200 may include a solder resist material 1234 (e.g., polyimide or a similar material) and one or more conductive contacts 1236 formed on the interconnect layers 1206- 1210. In FIG. 12, the conductive contacts 1236 are shown in the form of bond pads. The conductive contacts 1236 may be electrically coupled to the interconnect structures 1228 and configured to route the electrical signals of the transistor or transistors 1240 to other external devices. For example, solder bonds may be formed on the one or more conductive contacts 1236 to mechanically and / or electrically couple an integrated circuit die comprising the integrated circuit device 1200 to another component (e.g., a printed circuit board). The integrated circuit device 1200 may include additional or alternative structures to route the electrical signals from the interconnect layers 1206- 1210; for example, the conductive contacts 1236 may include other analog features (e.g., pillars) that route the electrical signals to external components.In some embodiments where integrated circuit device 1200 is a double-sided die, integrated circuit device 1200 may include another metallization stack (not shown) on the opposite side of device layer(s) 1204. This metallization stack may include multiple interconnect layers as discussed above with respect to interconnect layers 1206- 1210 to provide conductive paths (e.g., including conductive lines and vias) between the device layer(s) 1204 and additional conductive contacts (not shown) on the opposite side of the integrated circuit device 1200 from the conductive contacts 1236.In other embodiments where integrated circuit device 1200 is a double-sided die, integrated circuit device 1200 may include one or more through silicon vias (TSVs) through die substrate 1202; these TSVs may make contact with device layer(s) 1204 and may provide conductive paths between device layer(s) 1204 and additional conductive contacts (not shown) on the opposite side of integrated circuit device 1200 from conductive contacts 1236. In some embodiments, TSVs extending through the substrate may be used to route power and ground signals from conductive contacts on the opposite side of the integrated circuit device 1200 from the conductive contacts 1236 to the transistors 1240 and any other components integrated into the integrated circuit device (e.g., die) 1200, and the metallization stack 1219 may be used to route I / O signals from the conductive contacts 1236 to the transistors 1240 and any other components integrated into the integrated circuit device (e.g., die) 1200.Multiple integrated circuit devices 1200 may be stacked, with one or more TSVs in the individual stacked devices providing a connection between one of the devices to any of the other devices in the stack. For example, one or more high-bandwidth memory (HBM) integrated circuit dies may be stacked on a base integrated circuit die, and TSVs in the HBM dies may provide a connection between the individual HBM and the base integrated circuit die. Conductive contacts may provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts may be fine pitch (fine pitch) solder bumps (micro bumps).FIGS. 13A-13D are simplified perspective views of example planar, FinFET, gate all around, and stacked gate all around transistors. The transistors shown in Figures 13A-13D are formed on a substrate 1316 having a surface 1308. Isolation regions 1314 separate the source and drain regions of the transistors from other transistors and from a bulk region 1318 of substrate 1316.FIG. 13A is a perspective view of an example planar transistor 1300 including a gate 1302 that controls current flow between a source region 1304 and a drain region 1306. Transistor 1300 is planar in that source region 1304 and drain region 1306 are planar with respect to substrate surface 1308.FIG. 13B is a perspective view of an example FinFET transistor 1320 including a gate 1322 that controls current flow between a source region 1324 and a drain region 1326. Transistor 1320 is non-planar in that source region 1324 and drain region 1326 include "fins" extending upward from substrate surface 1308. Since the gate 1322 includes three sides of the semiconductor fin extending from the source region 1324 to the drain region 1326, the transistor 1320 may be considered a tri-gate transistor. FIG. 13B illustrates an S / D fin extending through the gate 1322, but multiple S / D fins may extend through the gate of a FinFET transistor.FIG. 13C is a perspective view of a gate-all-around (GAA) transistor 1340 including a gate 1342 that controls current flow between a source region 1344 and a drain region 1346. Transistor 1340 is non-planar in that source region 1344 and drain region 1346 are raised (elevated) from substrate surface 1308.FIG. 13D is a perspective view of a GAA transistor 1360 including a gate 1362 that controls current flow between a plurality of raised source regions 1364 and a plurality of raised drain regions 1366. Transistor 1360 is a stacked GAA transistor because the gate controls current flow between multiple stacked raised S / D regions. Transistors 1340 and 1360 are considered gate-all-around transistors because the gates include all sides of the semiconductor portions extending from the source regions to the drain regions. Transistors 1340 and 1360 may alternatively be referred to as nanowire, nanolayer, or nanoband transistors, depending on the width (e.g., widths 1348 and 1368 of transistors 1340 and 1360, respectively) of the semiconductor portions extending through the gate.FIG. 14 is a cross-sectional side view of an integrated circuit device assembly 1400, possibly including reference points with associated low density metal zones as described herein. Integrated circuit device assembly 1400 includes a number of components disposed on a circuit board 1402 (which may be a motherboard, system board, motherboard, etc.). Integrated circuit device assembly 1400 includes components disposed on a first surface 1440 of circuit board 1402 and an opposing second surface 1442 of circuit board 1402; in general, components may be disposed on one or both surfaces 1440 and 1442.In some embodiments, circuit board 1402 may be a printed circuit board (PCB) that includes multiple metal (or interconnect) layers separated from each other by layers of dielectric material and connected by electrically conductive vias. The individual metal layers comprise conductive tracks. Any one or more of the metal layers may be formed in a desired circuit structure to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1402. In other embodiments, circuit board 1402 may be a non-PCB substrate. The integrated circuit device assembly 1400 illustrated in FIG. 14 includes a package-on-interposer structure 1436 coupled to the first surface 1440 of the circuit board 1402 by coupling components 1416. The coupling components 1416 may electrically and mechanically couple the package-on-interposer structure 1436 to the circuit board 1402, and may include solder balls (as shown in FIG. 14 ), pins (e.g., as part of a pin grid array (PGA), contacts (e.g., as part of a land grid array (LGA)), plug and socket, an adhesive, an underfill material, and / or any other suitable electrical and / or mechanical coupling structure.The package-on-interposer structure 1436 may include an integrated circuit component 1420 coupled to an interposer 1404 by coupling components 1418. The coupling components 1418 may take any suitable form for the application, such as the forms discussed above with respect to the coupling components 1416. Although a single integrated circuit component 1420 is shown in FIG. 14, multiple integrated circuit components may be coupled to the interposer 1404; indeed, additional interposers may be coupled to the interposer 1404. The interposer 1404 may provide an intervening substrate that is used to bridge the circuit board 1402 and the integrated circuit component 1420.The integrated circuit component 1420 may be a packaged or unpackaged integrated circuit product comprising one or more integrated circuit dies (e.g., die 1102 of FIG. 11, integrated circuit device 1200 of FIG. 12 ) and / or one or more other suitable components. A packaged integrated circuit component includes one or more integrated circuit dies mounted on a package substrate, wherein the integrated circuit dies and the package substrate are encapsulated in a package material such as a metal, plastic, glass, or ceramic. In an example of an unpackaged integrated circuit component 1420, a single monolithic integrated circuit die includes solder bumps attached to contacts on the die. The solder bumps allow the die to be directly mounted on the interposer 1404. The integrated circuit component 1420 may include one or more computing system components, such as one or more processor units (e.g., system-on-a-chip (SoC), processor core, graphics processor unit (GPU), accelerator, chipset processor), I / O controller, memory, or network interface controller. In some embodiments, integrated circuit component 1420 may include one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, ESD (electrostatic discharge) devices, and memory devices.In embodiments where integrated circuit component 1420 includes multiple integrated circuit dies, the dies may be of the same type (a homogeneous multi-die integrated circuit component) or of two or more different types (a heterogeneous multi-die integrated circuit component). A multi-die integrated circuit component may be referred to as a multi-chip package (MCP) or multi-chip module (MCM).In addition to including one or more processing units, integrated circuit component 1420 may include additional components such as embedded DRAM, high bandwidth stacked memory (HBM), shared cache memory, input / output (I / O) controllers, or memory controllers. Any of these additional components may be located on the same integrated circuit die as a processor unit or on one or more integrated circuit dies that are separate from the integrated circuit dies comprising the processor units. These separate integrated circuit dies may be referred to as "chiplets.". In embodiments where an integrated circuit component includes multiple integrated circuit dies, interconnects between dies may be provided through the package substrate, one or more silicon interposers, one or more silicon bridges embedded in the package substrate (such as Intel® embedded multi-die interconnect bridges (EMIBs)), or combinations thereof.Generally, the interposer 1404 may propagate a connection to another distance or redirect a connection to a different connection (reroute). For example, interposer 1404 may couple integrated circuit component 1420 to a set of ball grid array (BGA) contacts of coupling components 1416 to couple them to circuit board 1402. In the embodiment illustrated in FIG. 14, the integrated circuit component 1420 and the circuit board 1402 are attached to opposite sides of the interposer 1404; in other embodiments, the integrated circuit component 1420 and the circuit board 1402 may be attached to a same side of the interposer 1404. In some embodiments, three or more components may be connected using the interposer 1404.In some embodiments, the interposer 1404 may be formed as a PCB comprising a plurality of metal layers separated from each other by layers of dielectric material and connected by electrically conductive vias. In some embodiments, the interposer 1404 may be formed of an epoxy resin, a fiberglass reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some embodiments, interposer 1404 may be formed of alternating rigid or flexible materials, which may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other Group III-V and Group IV materials. The interposer 1404 may include metal interconnects 1408 and vias 1410 including, but not limited to, through-hole vias 1410A (extending from a first surface 1450 of the interposer 1404 to a second surface 1454 of the interposer 1404), dummy vias 1410B (extending from the first or second surface 1450 or 1454 of the interposer 1404 to an internal metal layer), and buried vias 1410C (connecting internal metal layers).In some embodiments, the interposer 1404 may include a silicon interposer. Through silicon vias (TSVs) extending through the silicon interposer may connect interconnects on a first surface of a silicon interposer to an opposing second surface of the silicon interposer. In some embodiments, an interposer 1404 comprising a silicon interposer may further comprise one or more routing layers to route connections on a first surface of the interposer 1404 to an opposing second surface of the interposer 1404.The interposer 1404 may further include embedded devices 1414 including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, ESD devices, and memory devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices, may also be formed on interposer 1404. The package-on-interposer structure 1436 may take the form of any of the package-on-interposer structures known in the art.Integrated circuit device assembly 1400 may include an integrated circuit component 1424 coupled to first surface 1440 of circuit board 1402 by coupling components 1422. The coupling components 1422 may take the form of any of the embodiments discussed above with respect to the coupling components 1416, and the integrated circuit component 1424 may take the form of any of the embodiments discussed above with respect to the integrated circuit component 1420.The integrated circuit device assembly 1400 illustrated in FIG. 14 includes a package-on-package structure 1434 coupled to the second surface 1442 of the circuit board 1402 by coupling components 1428. The package-on-package structure 1434 may include an integrated circuit component 1426 and an integrated circuit component 1432 coupled together by coupling components 1430 such that the integrated circuit component 1426 is disposed between the circuit board 1402 and the integrated circuit component 1432. The coupling components 1428 and 1430 may take the form of any of the embodiments of the coupling components 1416 discussed above, and the integrated circuit components 1426 and 1432 may take the form of any of the embodiments of the integrated circuit component 1420 discussed above. The package-on-package structure 1434 may be formed according to any of the package-on-package structures known in the art.FIG. 15 is a block diagram of an example electrical device 1500 that may include reference points with associated low density metal zones as described herein. For example, any suitable ones of the components of the electrical device 1500 may include one or more of the integrated circuit dies 1102 disclosed herein, integrated circuit devices 1200, integrated circuit device assemblies 1400, integrated circuit components 1420, or other components. A number of components are shown in FIG. 15 as included in the electrical device 1500, however, one or more of these components may be omitted or duplicated, depending on what is suitable for the application. In some embodiments, some or all of the components included in the electrical device 1500 may be attached to one or more motherboards, motherboards, or system boards. In some embodiments, one or more of these components are fabricated on a single system-on-a-chip (SoC) die.Additionally, in various embodiments, the electrical device 1500 may include no or no more of the components illustrated in FIG. 15, but the electrical device 1500 may include interface circuitry for coupling to the one or more components. For example, the electrical device 1500 may not include a display 1506, but may include display interface circuitry (e.g., a connector and driver circuitry) to which a display 1506 may be coupled. In another set of examples, the electrical device 1500 may not include an audio input device 1524 or audio output device 1508, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 1524 or audio output device 1508 may be coupled.The electrical device 1500 may include one or more processing units 1502 (e.g., one or more processing units). As used herein, the terms "processor unit", "processing unit", or "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to convert that electronic data to other electronic data that may be stored in registers and / or memory. The processor unit 1502 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general-purpose GPUs (GPGPUs), accelerated processing units (APUs), field-programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs; The processing units may include data processors), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), control cryptoprocessors (specialized processors executing cryptographic algorithms within hardware), server processors, controllers, or any other suitable type of processing units. Therefore, the processing unit may also be referred to as an XPU (or xPU).The electrical device 1500 may include a memory 1504, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)), nonvolatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based nonvolatile memories), solid state memory, and / or a hard disk drive. In some embodiments, memory 1504 may include memory residing on the same integrated circuit die as processor unit 1502. This memory may be used as a cache memory (e.g., level 1 (L1), level 2 (L2), level 3 (L3), level 4 (L4), last level cache (LLC)), and may include an embedded dynamic random-access memory (eDRAM) or a spin transfer torque MRAM (STT-MRAM).In some embodiments, the electrical device 1500 may include one or more processing units 1502 that are heterogeneous or asymmetric to another processing unit 1502 in the electrical device 1500. There may be a variety of differences between processing units 1502 in a system with respect to a spectrum of metrics of quality factors including architectural, microarchitectural, thermal, power consumption characteristics, and the like. These differences may manifest themselves effectively as asymmetry and heterogeneity between the processing units 1502 in the electrical device 1500.In some embodiments, the electrical device 1500 may include a communication component 1512 (e.g., one or more communication components). For example, communication component 1512 may manage wireless communications for the transmission of data to and from electrical device 1500. The term "wireless" and its derivatives may be used to describe circuits, devices / devices (devices), methods, techniques, communication channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term "wireless" does not imply that the associated devices do not comprise any wires, although in some embodiments they may not.The communication component 1512 can implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineer (IEEE) standards including Wi-Fi (IEEE 1202.11 family), IEEE 1202.16 standards (e.g., IEEE 1202.16-2005 Amendment), the Long-Term Evolution (LTE) project along with any supplements, updates, and / or revisions (e.g., Advanced LTE Project, Ultra Mobile Broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE 1202.16 compatible broadband wireless access (BWA) networks are commonly referred to as WiMAX networks, an acronym standing for Worldwide Interoperability for Microwave Access, which is a meritorious for products that pass compliance and compatibility tests for the IEEE 1202.16 standards. The communication component 1512 can operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication component 1512 can operate in accordance with enhanced data for GSM evolution (EDGE), GSM EDGE radio access network (GERAN), universal terrestrial radio access network (UTRAN), or evolved UTRAN (E-UTRAN). The communication component 1512 can operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are referred to as 3G, 4G, 5G, and beyond. Communication component 1512 may operate according to other wireless protocols in other embodiments. The electrical device 1500 may include an antenna 1522 for facilitating wireless communications and / or for receiving other wireless communications (such as amplitude modulation (AM) or frequency modulation (FM) radio transmissions).In some embodiments, communication component 1512 can manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., IEEE 1202.3 Ethernet standards). As mentioned above, the communication component 1512 can include multiple communication components. For example, a first communication component 1512 may be dedicated to shorter range wireless communication such as Wi-Fi or Bluetooth and a second communication component 1512 may be dedicated to longer range wireless communication such as GPS (global positioning system), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication component 1512 can be dedicated to wireless communications and a second communication component 1512 can be dedicated to wired communications.The electrical device 1500 may include battery / power circuitry 1514. The battery / power circuitry 1514 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of the electrical device 1500 to a power source separate from the electrical device 1500 (e.g., AC line power).The electrical device 1500 may include a display device 1506 (or corresponding interface circuitry as discussed above). The display device 1506 may include one or more embedded or wired or wirelessly connected external visual indicators, such as a head-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.The electrical device 1500 may include an audio output device 1508 (or corresponding interface circuitry as discussed above). Audio output device 1508 may include any embedded or wired or wirelessly connected external device that generates an audible indicator, such as speakers, headsets, or earphones.The electrical device 1500 may include an audio input device 1524 (or corresponding interface circuitry as discussed above). The audio input device 1524 may include any embedded or wired or wirelessly connected device that generates a signal representing sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments with a MIDI (musical instrument digital interface) output). The electrical device 1500 may include a global navigation satellite system (GNSS) device 1518 (or corresponding interface circuitry as discussed above), such as a global positioning system (GPS) device. The GNSS device 1518 may be in communication with a satellite-based system and may determine a geolocation of the electrical device 1500 based on information received from one or more GNSS satellites, as is known in the art.The electrical device 1500 may include another output device 1510 (or corresponding interface circuitry as discussed above). Examples of the other output device 1510 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.The electrical device 1500 may include another input device 1520 (or corresponding interface circuitry as discussed above). Examples of the other input device 1520 may include an accelerometer, a gyroscope, a compass, an image capture device (e.g., a monoscopic or stereoscopic camera), a trackball, a track pad, a touchpad, a keyboard, a cursor control device such as a mouse, a stylus, a touchscreen, a proximity sensor, a microphone, a barcode reader, a quick response (QR) code reader, an electrocardiogram (ECG) sensor, a photoplethysmogram (PPG) sensor, a galvanic skin response sensor, any other sensor or radio frequency identification (RFID) reader.The electrical device 1500 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a mobile phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a 2-in-1 convertible computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA; The personal digital assistant), an ultra-mobile personal computer, a portable game console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., blade, tray, or sled computing systems), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a stationary game console, a smart television, a vehicle control unit, a digital camera, a digital video recorder, a portable electrical device, or an embedded computing system (e.g., computing systems that are part of a vehicle, smart home appliance, entertainment electronics product or device, or manufacturing equipment). In some embodiments, the electrical device 1500 may be any other electronic device that processes data. In some embodiments, the electrical device 1500 may include multiple discrete physical components. Given the spectrum of devices as which the electrical device 1500 may be represented in various embodiments, in some embodiments, the electrical device 1500 may be referred to as a computing device or computing system.Throughout this specification, plural examples may implement components, operations, or structures described as a singular example. Although individual operations of one or more methods are illustrated and described as separate operations, one or more of the individual operations may be performed simultaneously, and nothing requires the operations to be performed in the order illustrated. Structures and functionality shown as separate components in example configurations may be implemented as a combined structure or component. Similarly, structures and functionality shown as a single component may be implemented as separate components. These and other variations, modifications, additions and improvements fall within the scope of the subject matter herein.It should also be understood that although the terms "first,r,s", "second,r,s", etc. may be used herein to describe various elements, these elements are not intended to be limited by these terms. These terms are used only to distinguish one element from another, and it is not intended that it imply that the objects so described must be in a given order, either temporarily, spatially, ranked, or in any other manner. For example, a first contact could be referred to as a second contact and, similarly, a second contact could be referred to as a first contact without departing from the scope of the present embodiments. The first contact and the second contact are both contacts, but they are not the same contact.As used in the description of the embodiments and the appended examples, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It is also to be understood that the term "and / or" as used herein refers to and encompasses all possible combinations of one or more of the associated listed items. For example, the phrase "A and / or B" denotes (A), (B), or (A and B), while the phrase "A, B, and / or C" denotes (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).As used in this specification and claims, a list of elements joined by the term "at least one of" or "one or more of" may mean any combination of the listed terms.It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Further, the terms "comprise", "comprise", "have" and the like as used herein with respect to embodiments of the present disclosure are synonymous.The description may use the terms "in one embodiment," "in some embodiments," "in embodiments," or "in embodiments," which may each refer to one or more of the same or different embodiments.As used herein, the term "module" refers to being part of or including an ASIC, an electronic circuit, a system-on-a-chip, a processor (shared, dedicated, or group), a solid-state device, a memory (shared, dedicated, or group) that executes one or more software or firmware programs, a combinational logic circuit, and / or other suitable components that provide the described functionality.As used herein, "electrically conductive" may refer, in some examples, to a property of a material having an electrical conductivity greater than or equal to 10 7 siemens per meter (S / m) at 20 degrees Celsius. Examples of such materials include Cu, Ag, Al, Au, W, Zn and Ni.The word "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal.Throughout the specification and in the claims, the word "connected" means a direct connection, such as an electrical, mechanical or magnetic connection between the things that are connected, without any intermediary devices. The word "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices.The description may use perspective-based descriptions such as top / bottom, on / off, over / under, and the like. Such descriptions are used only to facilitate the discussion and are not intended to limit the application of embodiments described herein to any particular orientation.The terms "over," "under," "between," and "on" as used herein refer to a relative position of a component or material with respect to other components or materials where such physical relationships are noteworthy. For example, in the context of materials, a material or layer may be in direct contact over or under each other or may include one or more intervening materials. Additionally, a material disposed between two materials or layers may be directly in contact with the two materials / layers, or may have one or more intervening materials / layers. In contrast, a first material or layer "on" a second material or layer means that at least a portion of the first material or layer is in direct physical contact with at least a portion of that / r second material / layer. Similar distinctions are to be made in the context of component arrangements.As used herein, "A is adjacent to B" means that at least a portion of A is in direct physical contact with at least a portion of B.As used herein, "A is proximate to B" may mean that A is adjacent to B or A is otherwise proximate to B.Unless otherwise indicated in the specific context of use, the term "major" means greater than 50% or greater than half. For example, a composition that is primarily a first component means that more than half of the composition (e.g., by volume) is the first component (e.g., >50 at %). The term "primary" means most, or most, of the material. For example, a composition that is primarily a first component means that the composition has more of the first component (e.g., by volume) than any other component. A composition that is primarily first and second components means that the composition has more of the first and second components than any other component. The term "substantially" means that there is only a random deviation. For example, a composition that is substantially a first component means that the composition may further comprise <1% of any other component. A composition that is substantially first and second ingredients means that the composition may further comprise <1% of any ingredient that replaces either the first or second ingredients.The words "substantially," "substantially," "near," "about," "near," and "about" generally refer to being within + / - 10% of a target value (except as otherwise specified).Unless otherwise indicated in the explicit context of their use, the terms "substantially equal," "about equal," or "about equal" mean that there is no more than one random deviation between two things so described. In the prior art, such a deviation is typically not more than + / -10% of a predetermined target value.In the corresponding drawings of the embodiments, signals, currents, electric bias voltages, or magnetic or electric polarities may be represented by lines. Some lines may be thicker to indicate more constituent signal paths and / or have arrows at one or more ends to indicate the primary direction of information flow. Such references are not intended to be limiting. Rather, the lines are used in conjunction with one or more example embodiments to facilitate easier understanding of a circuit or logic unit. Any signal, polarity, current, voltage, etc., as represented / e, as dictated by design requirements or preferences, may actually comprise one or more signals that may move in both directions and may be implemented with any suitable type of signal scheme.The material described herein is illustrated by way of example and not limitation in the accompanying figures. For simplicity and clarity of illustration, the elements depicted in the figures are not necessarily drawn to scale. For example, the dimensions of some elements relative to other elements may be exaggerated for clarity. Further, where appropriate, reference numerals have been repeated in the figures to indicate corresponding or similar elements.Although the figures may represent embodiments in which structures are substantially aligned with Cartesian axes (e.g., device structures having substantially vertical sidewalls), positive and negative (re-essential) sloped feature sidewalls often occur in practice. For example, manufacturing non-idealities may result in one or more structural features having sloped sidewalls. The attributes shown are therefore only idealized in order to clearly describe the prominent features. It should be appreciated that schematics may not reflect real process constraints that may result in the features not looking as "ideal" when any of the structures described herein is examined using, for example, scanning electron microscopy (SEM) images or transmission electron microscopy (TEM) images. In such images of real structures, possible processing defects could also be visible, e.g., imperfect straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers, occasional threading, edge or combination dislocations within the crystalline region, and / or occasional dislocation defects of individual atoms or atomic clusters. There may be other defects not listed here, but which frequently occur within the device fabrication region.Example 1 includes an apparatus comprising an integrated circuit device, the integrated circuit device comprising a reference point region in a first layer of the integrated circuit, the reference point region comprising at least one metal region and at least one metal-free region, and a zone below a portion of the at least one metal-free region of the reference point region, the zone having a lateral cross-section of a slot through a plurality of layers comprising a metal interconnect of the integrated circuit device, the zone allowing infrared (IR) light to pass through the cross-section of the plurality of layers.Example 2 includes the subject matter of Example, and wherein the integrated circuit device includes a plurality of zones below portions of the at least one metal-free region of the reference point region, each zone having a lateral cross-section of a slot through the plurality of metal layers of the integrated circuit, the zones each enabling infrared IR light to pass through the respective cross-section of the plurality of metal layers of the integrated circuit.Example 3 includes the subject matter of any of Examples 1 and 2, and further including a second integrated circuit device, the second integrated circuit device including a second reference point region in a second layer of the second integrated circuit, the second reference point region including at least one metal region and at least one metal-free region, wherein superposition of the reference point region over the second reference point region includes a non-metal region defining the slits of the zones.Example 4 includes the subject matter of any of Examples 1-3, and wherein the slots for the lateral cross-sections of the zones together form a ring.Example 5 includes the subject matter of any of Examples 1-4, and wherein the ring is a square shaped ring.Example 6 includes the subject matter of any of Examples 1-5, and wherein a metal portion of the at least one metal portion has a shape of a solid square.Example 7 includes the subject matter of any of Examples 1-6, and wherein a second metal portion of the at least one metal portion has a shape of a square shaped ring.Example 8 includes the subject matter of any of Examples 1-7, and wherein the zone is metal-free.Example 9 includes the subject matter of any of Examples 1-8, and wherein the apparatus further includes a printed circuit board attached to the integrated circuit device and the second integrated circuit device.Example 10 includes the subject matter of any of Examples 1-9, and wherein the apparatus further includes a third integrated circuit device coupled to the printed circuit board.Example 11 includes a system comprising a printed circuit board; and a package coupled to the printed circuit board, the package comprising a first integrated circuit device comprising a reference point region of a first layer, the reference point region comprising a metal region and a metal-free region; and a plurality of zones that are metal-free in multiple layers adjacent to the first layer, the zones being defined by a footprint having a plurality of slots, the footprint being within the metal-free region of the reference point region.Example 12 includes the subject matter of Example 11, and wherein the package further includes a second integrated circuit device including a second reference point region of a second layer, wherein the reference point region includes a second metal region and a second metal-free region, wherein the footprint is based on the metal region of the reference point region and the second metal region of the second reference point region.Example 13 includes the subject matter of any of Examples 11 and 12, and wherein the second integrated circuit device includes a plurality of second zones that are metal-free in multiple layers adjacent to the second layer, the second zones also being defined by the footprint.Example 14 includes the subject matter of any of Examples 11-13, and wherein the first integrated circuit device is hybrid bonded to the second integrated circuit device.Example 15 includes the subject matter of any of Examples 11-14, and further including a third integrated circuit device coupled to the printed circuit board.Example 16 includes the subject matter of any of Examples 11-15, and wherein the plurality of slots together form a ring.Example 17 includes the subject matter of any of Examples 11-16, and wherein the ring is a square shaped ring.Example 18 includes the subject matter of any of Examples 11-17, and wherein the metal region has a shape of a solid square.Example 19 includes the subject matter of any of Examples 11-18, wherein the metal region has a shape of a square shaped ring.Example 20 includes an apparatus comprising an integrated circuit device comprising a reference point region of a first layer, the reference point region comprising a metal region and a metal-free region; and a plurality of zones that are metal-free in multiple layers adjacent to the first layer, the zones being defined by a footprint based on the reference point region of the first layer and a second reference point region of a second integrated circuit device, the footprint comprising multiple slots.Example 21 includes the subject matter of Example 20, and wherein the metal region of the reference point region and a second metal region of the second reference point region are concentric.Example 22 includes the subject matter of any of Examples 20 and 21, and wherein the metal region of the reference point region has a first fixed shape and a second metal region of the reference point region has a shape of a ring.Example 23 includes the subject matter of any of Examples 20-22, and further including the second integrated circuit device.Example 24 includes the subject matter of any of Examples 20-23, and wherein the second integrated circuit device includes a plurality of zones that are metal-free in multiple layers adjacent to a second layer including the reference point region, wherein the zones of the second integrated circuit device are defined by the footprint.Example 25 includes the subject matter of any of Examples 20-24, and wherein the plurality of slots together form a ring.Example 26 includes the subject matter of any of Examples 20-25, and wherein the ring is a square shaped ring.Example 27 includes the subject matter of any of Examples 20-26, and wherein the metal region has a shape of a solid square.Example 28 includes the subject matter of any of Examples 20-27, and wherein the metal region has a shape of a square shaped ring.Example 29 includes a method comprising forming an integrated circuit device having a reference point region of a first layer, the reference point region including a metal region and a metal-free region; and forming a plurality of zones that are metal-free in multiple layers adjacent to the first layer, the zones being defined by a footprint based on the reference point region of the first layer and a second reference point region of a second integrated circuit device, the footprint including multiple slots.Example 30 includes the subject matter of Example 29, and wherein the metal region of the reference point region and a second metal region of the second reference point region are concentric.Example 31 includes the subject matter of any of Examples 29 and 30, and wherein the metal region of the reference point region has a first fixed shape and a second metal region of the reference point region has a shape of a ring.Example 32 includes the subject matter of any of Examples 29-31, and further including the second integrated circuit device.Example 33 includes the subject matter of any of Examples 29-32, and wherein the second integrated circuit device includes a plurality of zones that are metal-free in multiple layers adjacent to a second layer including the reference point region, wherein the zones of the second integrated circuit device are defined by the footprint.Example 34 includes the subject matter of any of Examples 29-33, and wherein the plurality of slots together form a ring.Example 35 includes the subject matter of any of Examples 29-34, and wherein the ring is a square shaped ring.Example 36 includes the subject matter of any of Examples 29-35, and wherein the metal region has a shape of a solid square.Example 37 includes the subject matter of any of Examples 29-36, and wherein the metal portion has a shape of a square shaped ring.The foregoing description has been presented for purposes of explanation with reference to specific embodiments. However, the above illustrative discussions are not intended to be considered complete or limit the possible embodiments to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings. The embodiments were chosen and described in order to best describe the principles involved and their practical applications, to thereby enable others skilled in the art to best utilize the various embodiments with various modifications as are suited to the particular use contemplated.

Claims

An apparatus comprising: an integrated circuit device, the integrated circuit device comprising: a reference point region in a first layer of the integrated circuit, the reference point region comprising at least one metal region and at least one metal-free region; and a zone below a portion of the at least one metal-free region of the reference point region, the zone having a lateral cross-section of a slot through a plurality of layers comprising a metal bond of the integrated circuit device, the zone permitting infrared (IR) light to pass through the cross-section of the plurality of layers.The apparatus of claim 1, wherein the integrated circuit device comprises a plurality of zones below portions of the at least one metal-free region of the reference point region, each zone having a lateral cross-section of a slot through the plurality of metal layers of the integrated circuit, the zones each enabling infrared IR light to pass through the respective cross-section of the plurality of metal layers of the integrated circuit.The apparatus of any of claims 1-2, further comprising a second integrated circuit device, wherein the second integrated circuit device comprises: a second reference point area in a second layer of the second integrated circuit, wherein the second reference point area comprises at least one metal area and at least one metal-free area, wherein superposition of the reference point area over the second reference point area comprises a non-metal area defining the slits of the zones.The device according to any of claims 1-3, wherein the slits for the lateral cross sections of the zones together form a ring.The device of claim 4, wherein the ring is a square shaped ring.The apparatus of any of claims 1-5, wherein a metal portion of the at least one metal portion has a shape of a solid square.The device of any of claims 1-6, wherein a second metal portion of the at least one metal portion has a square shaped ring shape.The apparatus of any of claims 1-7, wherein the zone is metal-free.The apparatus of any of claims 3-8, wherein the apparatus further comprises a printed circuit board attached to the integrated circuit device and second integrated circuit device.The apparatus of claim 9, further comprising a third integrated circuit device coupled to the printed circuit board.A system, comprising: a printed circuit board; and a package coupled to the printed circuit board, the package comprising a first integrated circuit device, comprising: a reference point area of a first layer, the reference point area comprising a metal area and a metal-free area; and a plurality of zones that are metal-free in multiple layers adjacent to the first layer, the zones being defined by a footprint having a plurality of slots, the footprint being within the metal-free area of the reference point area.The system of claim 11, wherein the package further comprises a second integrated circuit device comprising a second reference point region of a second layer, the reference point region comprising a second metal region and a second metal-free region, wherein the footprint is based on the metal region of the reference point region and the second metal region of the second reference point region.The system of claim 12, wherein the second integrated circuit device comprises a plurality of second zones that are metal-free in multiple layers adjacent to the second layer, the second zones also being defined by the footprint.The system of any of claims 12-13, wherein the first integrated circuit device is hybrid bonded to the second integrated circuit device.The system of any of claims 12-14, further comprising a third integrated circuit device coupled to the printed circuit board.An apparatus comprising: an integrated circuit device having a reference point region of a first layer, the reference point region comprising a metal region and a metal-free region; and a plurality of zones that are metal-free in multiple layers adjacent to the first layer, the zones being defined by a footprint based on the reference point region of the first layer and a second reference point region of a second integrated circuit device, the footprint comprising multiple slots.The apparatus of claim 16, wherein the metal region of the reference point region and a second metal region of the second reference point region are concentric.The apparatus of any of claims 16-17, wherein the metal region of the reference point region has a first fixed shape and a second metal region of the reference point region has a shape of a ring.The apparatus of any of claims 16-18, further comprising the second integrated circuit device.The apparatus of any of claims 16-19, wherein the second integrated circuit device comprises a plurality of zones that are metal-free in multiple layers adjacent to a second layer comprising the reference point area, wherein the zones of the second integrated circuit device are defined by the footprint.A method comprising: forming an integrated circuit device having a reference point region of a first layer, the reference point region comprising a metal region and a metal-free region; and forming a plurality of zones that are metal-free in multiple layers adjacent to the first layer, the zones being defined by a footprint based on the reference point region of the first layer and a second reference point region of a second integrated circuit device, the footprint comprising multiple slots.The method of claim 21, wherein the metal region of the reference point region and a second metal region of the second reference point region are concentric.The method of any of claims 21-22, wherein the metal region of the reference point region has a first fixed shape and a second metal region of the reference point region has a shape of a ring.The method of any of claims 21-23, wherein the second integrated circuit device comprises a plurality of zones that are metal-free in multiple layers adjacent to a second layer comprising the reference point region, the zones of the second integrated circuit device being defined by the footprint.The method of any of claims 21-24, wherein the plurality of slots together form a ring.

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