SEMICONDUCTOR DEVICE

Abstract

A semiconductor device comprises a substrate with a medium-voltage (MV) region and a one-time programmable (OTP) capacitor region, an MV device within the MV region, and an OTP capacitor within the OTP capacitor region. Preferably, the MV device comprises a first dielectric gate layer on the substrate, a first gate electrode on the first dielectric gate layer, and shallow trench insulation (STI) adjacent to two sides of the first gate electrode. The OTP capacitor comprises a ribbed structure on the substrate, a doped region within the ribbed structure, a second gate electrode within the doped region, and a second gate electrode on the second gate electrode layer.

Description

BACKGROUND OF THE INVENTION1. Field of the InventionThe invention relates to a semiconductor device, and more particularly to a semiconductor device for integrating a medium voltage (MV) device and a one-time programmable (OTP) device.2. Description of the Prior ArtSemiconductor memory devices, including nonvolatile memory devices, are widely used in various electronic devices such as cellular phones, digital cameras, personal digital assistants (PDAs), and other applications. Typically, non-volatile memory devices include multi-programmable (MTP) devices and one-time programmable (OTP) devices. Unlike rewritable memories, one-time programmable (OTP) devices offer the advantage of low manufacturing cost and easy storage. However, one-time programmable (OTP) devices could only perform a single data recording, so that when certain memory cells of a certain memory block were stored with a writing program, these memory cells could not be rewritten.Since current one-time programmable (OTP) devices still have the drawback of weak read current and longer timing in the programming mode, the improvement of the current architecture for OTP memory devices has become an important task in this area.US 2016 / 0 190 145 A1 describes a semiconductor component having a substrate and an element formed on the substrate. The substrate has a p-type region formed on a main surface side of a support substrate and a layer formed on the p-type region.US 2019 / 0 043 725 Al describes a method of manufacturing a semiconductor device comprising forming a gate dielectric layer on a substrate, forming a gate material layer on the gate dielectric layer, and removing a portion of the gate material layer and a portion of the gate dielectric layer to form a gate electrode.SUMMARY OF THE INVENTIONA semiconductor device includes a substrate having a medium voltage (MV) region and a one-time programmable (OTP) capacitor region, an MV device in the MV region, and an OTP capacitor in the OTP capacitor region. According to the invention, the MV device comprises a first gate dielectric layer on the substrate, a first gate electrode on the first gate dielectric layer, a spacer adjacent to the first gate electrode, and a shallow trench isolation (STI) adjacent to two sides of the first gate electrode. The first gate dielectric layer includes a lower portion on the shallow trench isolation and the substrate and an upper portion on the lower portion.According to another aspect of the present invention, a semiconductor device includes a substrate having a medium voltage (MV) region, a one-time programmable (OTP) capacitor region and a core region, an MV device in the MV region, an OTP capacitor in the OTP capacitor region, and a metal oxide semiconductor (MOS) transistor in the core region. According to the invention, the MV device comprises a first gate dielectric layer on the substrate, a first gate electrode on the first gate dielectric layer, a spacer adjacent to the first gate electrode, and a shallow trench isolation (STI) adjacent to two sides of the first gate electrode. The first gate dielectric layer includes a bottom portion on the shallow trench isolation and the substrate and a top portion on the bottom portion.These and other features of the present invention will become apparent to those skilled in the art upon reading the following detailed description of the preferred embodiment shown in the various figures and drawings.Brief Description of the FiguresFIGS. 1 to 11 illustrate a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 12 is a general diagram of the semiconductor device according to an embodiment of the present invention.Detailed DescriptionReferring to FIGS. 1 to 11, FIGS. 1 to 11 illustrate a method of manufacturing a semiconductor device according to an embodiment of the present invention. As shown in FIG. 1, a substrate 12 such as a silicon-on-insulator (SOI) substrate is provided, and a high voltage (HV) region 14, a medium voltage (MV) region 16, an input / output (I / O) region 18, a core region 20, and an OTP capacitor region 22 are defined on the substrate 12, wherein the HV region 14 and the MV region 16 are used to fabricate HV devices and MV devices with planar-type metal oxide semiconductor field effect transistors (MOSFETs), the I / O region 18 and the core region 20 are used to fabricate HV devices and MV devices with planar-type metal oxide semiconductor field effect transistors (MOSFETs), However, low voltage (LV) devices such as non-planar fin field effect transistors (FinFETs) are fabricated, and the OTP capacitor region 22 is used to fabricate OTP capacitors.In this embodiment, the HV region 14, the MV region 16, the I / O region 18, the core region 20, and the OTP capacitor region 22 may include transistor regions of the same or different conductivity type. For example, each of the HV regions 14, the MV region 16, the I / O region 18, the core region 20, and the OTP capacitor region 22 could include a PMOS region and / or an NMOS region, and the five regions could be predetermined to produce gate structures having the same or different threshold voltage in the later process. In this embodiment, it would be desirable to first perform an ion implantation process to form a deep p-well 42 in the HV region 14, and then form a deep n-well 44 in the MV region 16, the I / O region 18, the core region 20, and the OTP capacitor region 22. However, the conductivity of the deep wells in each region may be adjusted according to the requirements of the process.Then, bases 24 are formed on the substrate 12 of the HV region 14 and the MV region 16, and a plurality of rib-shaped structures 26 are formed on the substrate 12 of the I / O region 18, the core region 20, and the OTP capacitor region 22. For example, a layout structure is first input into a computer system and modified by suitable calculations. The modified layout is then defined as a mask and transferred to a sacrificial layer on a substrate by a photolithography and an etching process. In this way, a plurality of sacrificial layers are formed on a substrate, which are distributed at the same distance and the same width. Each of the sacrificial layers may be rod-shaped. Subsequently, a deposition process and an etching process are performed such that spacers are formed on the sidewalls of the patterned sacrificial layers. In a next step, the sacrificial layers may be completely removed by an etching process. The etching process may transfer the pattern defined by the spacers to the underlying substrate, and additional fin cutting processes may provide desired pattern structures, such as a ridge-shaped structure forming a stripe pattern.Alternatively, the ridge-shaped structures 26 may also be obtained by first forming a patterned mask (not shown) on the substrate 12 and transferring the pattern of the patterned mask to the substrate 12 by an etching process to form the ridge-shaped structures 26. Moreover, the formation of the fin structures 26 could also be accomplished by first forming a patterned hardmask (not shown) on the substrate 12 and growing a silicon germanium semiconductor layer from the substrate 12 through exposed patterned hardmask via a selective epitaxial growth process to form the fin structures 26. These processes for forming the rib-shaped structures 26 are all within the scope of the present invention.In this embodiment, at least one liner 28 and hard mask 30 could be disposed on the surface of the base 24 and the rib-shaped structures 26 during the aforementioned oxidation process, where the liner 28 could comprise silicon oxide and / or silicon nitride, while the hard mask 30 preferably contains silicon oxide. Moreover, it would be desirable to perform an additional photo-etching process to remove a portion of the substrate 12 in the MV region 16 before forming the rib-shaped structures 26 and then forming the rib-shaped structures 26. The result is that the top surface of the base 24 in the MV region 16 is slightly lower than the top surface of the base 24 and the rib-shaped structures 26 in other regions.After the fin structures 26 are formed, another photo-etching process could be performed to remove a portion of the substrate 12 in the HV region 14 and the MV region 16 to form a plurality of deeper trenches (not shown). Next, as shown in FIG. 2, a flowable chemical deposition (FCVD) process is performed to form an insulating layer of silicon oxide and fill the trenches, and a planarization process such as a chemical mechanical polishing (CMP) process is performed to remove a portion of the insulating layer, a portion of the hard mask 30, and a portion of the liner 28 such that the top layer of the remaining insulating layer is planar with the top surface of the substrate 12 in each region and simultaneously forms a deeper shallow trench isolation (STI) 32 in the HV region 14 and the MV region 16 and a shallower STI 32 in the I / O region 18, the core region 20, and the OTP capacitor region 22.Next, as shown in FIG. 3, the remaining hard mask 30 and liner 28 in the MV region 16 are removed to expose the surface of the base 24, and then an ion implantation process is performed to form a doped region 34 adjacent two sides of the base 24 in the HV region 14, where the doped region 34 could serve as a lightly doped drain (LDD) 34 for the HV device in the later process. Next, an oxide growth process, e.g., a rapid thermal oxidation (RTO) process, using a mask, could be performed to form a gate dielectric layer 36 of silicon oxide based 24 of the HV region 14. Subsequently, an LDD 38 is formed in the MV region 16, and another oxidation process for forming a gate dielectric layer 40, also made of silicon oxide, is performed on the basis 24 of the MV region 16. Note that, when the hard mask 30 and the liner 28 are removed in the MV region 16, a part of the STI 32 is also removed simultaneously to form recesses, so that the gate dielectric layer 40 formed subsequently is formed not only on the surface of the substrate 12 but also in the recess of the STI 32.Next, as shown in FIG. 4, a patterned mask 46, e.g., a patterned resist layer, is formed on the regions outside the OTP capacitor region 22 to expose the surface of the substrate 12 or the ridge-shaped structure 26 in the OTP capacitor region 22, and an ion implantation process 48 or a heavy doping process is performed to implant dopants into the ridge-shaped structure 26 in the OTP capacitor region 22 to form a doped region 50. At this stage, the dopant concentrations of the substrate 12 in the HV region 14, MV region 16, I / O region 18, and core region 20 are all less than the dopant concentration of the rib-shaped structure 26 in the OTP capacitor region 22, in which the doped region 50 preferably serves as the bottom electrode for the OTP capacitor. In this embodiment, the implanted dopants for forming the doped region 50 preferably comprise arsenic (As), the energy of the ion implantation process is between 5 and 20 KeV, and the dosage of the dopants is between 1.0×10 15 atoms / cm 2 and 1.0×10 16 atoms / cm 2, and the concentration of the dopants is about 1.0×10 18 atoms / cm 3 to 1.0×10 20 atoms / cm 3.Next, as shown in FIG. 5, the patterned mask 46 is removed and an anneal process is performed to drive the implanted dopants into the ridge-shaped pattern 26 in the OTP capacitor region 22, a patterned mask (not shown) such as a patterned resist is formed in the HV region 14 and the MV region 16, an etch process is performed to remove a portion of the STI 32 in the I / O region 18, the core region 20, and the OTP capacitor region 22, Next, an oxidation process such as an RTO process or an in situ vapor generation (ISSG) process is performed to form a gate dielectric layer 52 of silicon oxide on the surface of the exposed fin 26 in each of the I / O regions 18, core region 20, and OTP capacitor region 22.Next, as shown in FIG. 6, gate structures 54 could be formed on the bases 24 and the ridge-shaped structure 26 in the HV region 14, the MV region 16, the I / O region 18, the core region 20, and the OTP capacitor region 22, the gate structures 54 in the HV region 14, the MV region 16, the I / O region 18, and the core region 20 could serve as gate electrodes for each region, while the gate structure 54 in the OTP capacitor region 22 could serve as an upper electrode for the OTP capacitor, and the formation of the gate structures 54 by a gate first process, a high-k last process or a high-k last process could be performed.Because this embodiment relates to a high-k last process, a gate material layer 56 of polysilicon and a selective hard mask 58 could be formed sequentially on the substrate 12, and a photo-etching process is then performed using a patterned resist (not shown) as a mask to remove a portion of the hard mask 58, a portion of the gate material layer 56, and a portion of the gate oxide layer 52 by single or multiple etching processes. After stripping the patterned resist, gate structures 54 are formed in each of the regions, each of which consists of a patterned material layer 56 and a patterned hard mask 58, where the patterned resist layer 56 may serve as gate electrodes 60 for the HV device, the MV device, the I / O device, and the core region, as well as a top electrode for the OTP capacitor.Next, as shown in FIG. 7, at least one spacer 62 is formed on the sidewalls of each of the gate structures 54, and then a patterned mask 64 is formed in the HV region 14, the I / O region 18, the core region 20, and the OTP capacitor region 22 to expose the dielectric layer 40 adjacent to two sides of the gate structure 54 in the MV region 16. In this embodiment, the spacer 62 could be a single spacer or a composite spacer, such as, but not limited to, a spacer that includes an offset spacer and a main spacer. Preferably, the spacer and the main spacer may comprise the same material or different materials, wherein both the spacer and the main spacer may be made of a material including, but not limited to, SiO 2, SiN, SiON, SiCN, or a combination thereof, for example.Next, as shown in FIG. 8, an etching process is performed in which the patterned mask 64 is used as a mask to remove a part of the gate dielectric layer 40 adjacent to two sides of the gate pattern 54 in the MV region 16 so that the remaining gate dielectric layer 40 forms an inverted T shape. Specifically, the gate dielectric layer 40 modified by the etching process in the MV region 16 includes a bottom portion 68 simultaneously disposed on the substrate 12 and the shallow trench isolation 32, and a top portion 70 disposed on the bottom portion 68. Preferably, the width of the upper portion 70 is less than the width of the lower portion 68, the upper surface of the upper portion 70 could be the same as the upper surface of the rib-shaped structures 26 in the core region 20 and the OTP capacitor region 22 and / or the upper surface of the doped region 50 in the OTP capacitor region 22, the sidewalls of the upper portion 70 are aligned with the sidewalls of the alignment device 62, and the thickness of the lower portion 68 is less than the thickness of the upper portion 70. for example, the thickness of the lower portion 68 could be less than 90%, 80%, 70%, 60%, or 50% of the thickness of the upper portion 70, but the upper surface of the lower portion 68 is less than the uppermost surface of the STI 32 in the MV region 16, could be greater, The STI 32 may be uniformly or lower than the upper surface of the I / O region 18, core region 20, and OTP capacitor region 22.Next, source / drain regions 72 and / or epitaxial layers (not shown) are formed in the bases 24 or fin-shaped structures 26 adjacent to two sides of the spacers 62 in the HV region 14, MV region 16, I / O region 18 and core region 20, and selective silicide layers (not shown) could be formed on the surface of the source / drain regions 72 and / or epitaxial layers. The source / drain region 72 and the epitaxial layer may include different dopants or different materials depending on the type of device to be fabricated. Thus, the source / drain region 72 could include n-type or p-type dopants, and the epitaxial layers could include silicon germanium (SiGe), silicon carbide (SiC), or silicon phosphide (SiP). Since a capacitor is formed in the OTP capacitor region 2, the source / drain regions 72 are formed only in the substrate 12 adjacent to two sides of the gate structures 54 in the HV region 14, MV region 16, I / O region 18 and core region 20, while no source / drain region and / or epitaxial layer is formed in the fin-shaped structures 26 adjacent to two sides of the gate structure 54 (or upper electrode) in the OTP capacitor region 22.Next, as shown in FIG. 9, an interlayer dielectric layer (ILD) 74 is formed on the gate structures 54, and a planarization process such as CMP is performed to remove a portion of the ILD layer 74 to expose the hard masks 58 such that the top surface of the hard masks 58 is planar with the top surface of the ILD layer 76.A replacement metal gate process (RMG) is then performed to convert the gate material layers 56 of polysilicon in the HV region 14, MV region 16, I / O region 18, core region 20, and OTP capacitor region 22 into metal gates. The RMG process could be accomplished, for example, by first performing a selective dry etch or wet etch process using etchants including, for example, ammonium hydroxide (NH 4 OH) or tetramethylammonium hydroxide (TMAH) to remove the hard masks 58 and the gate material layers 56 in the HV region 14, MV region 16, I / O region 18, core region 20, and OTP capacitor region 22 and form recesses that expose the gate dielectric layers 36, 40, 52 in each region.Next, a patterned mask 76, e.g., a patterned resist, is formed in the HV region 14, the MV region 16, and the I / O region 18 to expose the gate dielectric layers 52 in the core region 20 and the OTP capacitor region 22, and then an etching process is performed using the patterned mask 76 as a mask to remove the gate dielectric layers 52 in the core region 20 and the OTP capacitor region 22 and expose the surface of the fin-shaped structures 26.Subsequently, referring to FIGS. 10 to 11, FIGS. 10 to 11 illustrate a method for forming metal gates in the HV region 14, the MV region 16, the I / O region 18, the core region 20, and the OTP capacitor region 22 according to the RMG method performed in FIG. 9, wherein FIGS. 9 to 10 show views under the same cross section of the HV region 14, the MV region 16, the I / O region 18, the core region 20, and the OTP capacitor region 22, the HV region 14 and the MV region 16 of FIG. 11 are shown with the same cross-sectional views as in FIGS. 9 to 10, and the I / O region 18, the core region 20 and the OTP capacitor region 22 are cross-sectional views shown from a different angle. For example, ridge-shaped structures 26 can be seen in the I / O region 18, the core region 20 and the OTP capacitor region 22 in FIG. 10 according to the RMG method, while source / drain regions 72 can be seen in the I / O region 18 and the core region 20 in FIG. 11, while no source / drain region can be seen in the OTP capacitor region 22.As shown in FIGS. 10 to 11, an interface layer 78 of a silicon oxide film is formed on the surface of the substrate 12 of the core region 20 and the OTP capacitor region 22, the patterned mask 76 is removed, a high-k dielectric layer 82, a work function metal layer 84, and a low-resistance metal layer 86 are formed in the recesses of each region, and then a planarization process such as CMP is performed to remove a part of the low-k metal layer 86, a part of the work function metal layer 84, and a part of the high-k dielectric layer 82 to form metal gates 88. Since this embodiment is a high-k process, each of the metal gates 88 preferably includes a high-k U-shaped dielectric layer 82, a U-shaped work function metal layer 84, and a low-resistance metal layer 86.Although the interface layer 78 in the core region 20 and the OTP capacitor region 22 and the gate dielectric layer 52 in the I / O region 18 are both made of silicon oxide, the thickness of the interface layer 78 is slightly less than the thickness of the gate dielectric layer 52, more specifically, the thickness of the interface layer 78 is less than half the thickness of the gate dielectric layer 52 in the I / O region 18. Instead of forming interface layers 78 of equal thickness in the core region 20 and the OTP capacitor region 22 as disclosed in this embodiment, it would also be desirable according to another embodiment of the present invention to perform an additional oxidation process for forming interface layers both made of silicon oxide, However, the thicknesses of the interface layer in the core region 20 and the OTP capacitor region 22 are different, the thickness of the interface layer in the OTP capacitor region 22 in this case being less than the thickness of the interface layer in the core region 20, while the thickness of the interface layer in the core region 20 is less than the thickness of the gate dielectric layer 52 in the I / O region 18.In this embodiment, the high-k dielectric layer 82 is preferably selected from dielectric materials whose dielectric constant (k value) is greater than 4. The high-k dielectric layer 82 may be selected from, for example, hafnium oxide (HfO 2), hafnium silicon oxide (HfSiO 4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al 2 O 3), lanthanum oxide (La 2 O 3), tantalum oxide (Ta 2 O 5), yttrium oxide (Y 2 O 3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), Zirconium silicon oxide (ZrSiO 4), hafnium zirconium oxide (HfZrO 4), strontium bismuth tantalate (SrBi 2 Ta 2 O 9, SBT), lead zirconate titanate (PbZr x Ti 1-x O 3, PZT), barium strontium titanate (Ba x Sr 1-x TiO3, BST), or a combination thereof.In this embodiment, the work function metal layer 84 is formed to adjust the work function of the metal gate according to the conductivity of the device. For an NMOS transistor, the work function metal layer 48 having a work function between 3.9 eV and 4.3 eV may include, but is not limited to, titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or titanium aluminum carbide (TiAlC). For a PMOS transistor, the work function metal layer 84 having a work function between 4.8 eV and 5.2 eV may include, but is not limited to, titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC). An optional barrier layer (not shown) could be formed between the work function metal layer 84 and the low resistance metal layer 86, wherein the material of the barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). Moreover, the material of the low resistance metal layer 86 may include copper (Cu), aluminum (Al), titanium aluminum (TiAl), cobalt tungsten phosphide (CoWP), or any combination thereof.Next, a portion of the high-k dielectric layer 82, a portion of the work function metal layer 84, and a portion of the low-resistance interlayer dielectric layer 86 are removed to form recesses (not shown), and a hard mask 92 is formed in each of the recesses so that the top surfaces of the hard masks 92 and the ILD layer 74 are coplanar. Preferably, the hard masks 92 may include SiO 2, SiN, SiON, SiCN, or a combination thereof.A photo-etching process is then performed using a patterned mask (not shown) as a mask to remove a portion of the ILD layer 74 in the area adjacent to the metal gates 88 to form contact holes (not shown) exposing the underlying source / drain regions 72. Next, conductive materials including a barrier layer selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta) and tantalum nitride (TaN), and a metal layer selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminide (TiAl) and cobalt tungsten phosphide (CoWP) are deposited in the contact holes, and a planarization process such as CMP is performed to remove a part of the above barrier layer and low resistance metal layer to form contact plugs (not shown) that electrically connect the source / drain region. Thus, the manufacturing of a semiconductor device according to an embodiment of the present invention is completed.Referring to FIGS. 10 to 11, FIGS. 10 to 11 further illustrate structural views of a semiconductor device incorporating an HV device, an MV device, an I / O device, a core device, and an OTP capacitor according to an embodiment of the present invention. As shown in FIGS. 10 to 11, the semiconductor device includes a one-time programmable (OTP) device disposed in the HV region 14, an MV device disposed in the MV region 16, an I / O device disposed in the I / O region 16, a core device disposed in the core region 20, and an OTP capacitor disposed in the OTP capacitor region 22. Preferably, the OTP capacitor comprises at least one fin-shaped structure 26 on the substrate 12, a doped region 50 disposed in the fin-shaped structure 26, at least one insulating layer such as the interfacial layer 78 and / or the low resistance dielectric layer 82 on the fin-shaped structure 26, and metal such as the work function metal layer 84 and the high k metal layer 86 on the dielectric layer 82, wherein the fin-shaped structure 26 with the heavily doped region 50 preferably serves as a bottom electrode for the OTP capacitor, the dielectric material such as the interfacial layer 78 and / or the high k dielectric layer 82 serves as a dielectric layer for the OTP capacitor, and the work function metal layer 84 and the low resistance metal layer 86 together serve as an upper electrode for the OTP capacitor.Referring to FIG. 12, FIG. 12 shows an overall layout of the semiconductor device according to an embodiment of the present invention. As shown in FIG. 12, the semiconductor device includes an OTP cell array, a row decoder, a column decoder, sense amplifiers, control logic, and an analog block, and MV devices. Preferably, the OTP cell array comprises OTP capacitors in the OTP capacitor region 22 as disclosed in the aforementioned embodiment, and row and column decoders are arranged around the OTP cell array. Moreover, a one-time programmable (OTP) block is disposed between the OTP cell array and the MV devices, the MV devices disposed immediately adjacent to the one-time programmable (OTP) block preferably comprising circuitry for performing read and write operations on the OTP capacitors within the OTP cell array.Overall, the present invention discloses an approach for integrating HV device, MV device, I / O device, core device, and OTP capacitor. Preferably, the HV devices and MV devices are fabricated according to planar MOS transistor fabrication processes, while the I / O devices, core devices, and OTP capacitors are fabricated according to non-planar or, in particular, FinFET fabrication processes. In order to allow better compatibility between the MV devices and the surrounding devices, an additional photo-etching process is performed prior to the RMG process in the context of the present invention to pattern the gate dielectric layer 40 of the MV device such that the gate layer 40 is formed into an inverted T-shape. In order to improve the read and write capability of the OTP capacitor, it would also be desirable to remove the gate dielectric layers 52 in the core region and the OTP capacitor region after the removal of the polysilicon gate material layers 56 during the RMG process and then form an interfacial layer 78 of silicon oxide on the surface of the substrate 12 in the core region 20 and the OTP capacitor region 22. Although the interfacial layer 78 in the core region 20 and the OTP capacitor region 22 and the gate dielectric layer 52 in the I / O region 18 are both made of silicon oxide, the thickness of the interfacial layer 78 is less than the thickness of the gate dielectric layer 52.

Claims

A semiconductor device comprising: a substrate (12) having a medium voltage, MV, region (16) and a one time programmable, OTP, capacitor region (22); an MV device in the MV region (16), the MV device comprising: a first gate dielectric layer (40) on the substrate (12); a first gate electrode (60) on the first gate dielectric layer (40); a spacer (62) adjacent the first gate electrode (60); and a shallow trench isolation, STI, (32) adjacent two sides of the first gate electrode (60), the first gate dielectric layer (40) comprising: a bottom portion (68) on the shallow trench isolation (32) and the substrate (12); and an upper portion (70) on the lower portion (68); and an OTP capacitor in the OTP capacitor region (22).The semiconductor device of claim 1, wherein the first gate dielectric layer (40) comprises an inverted T-shape.The semiconductor device according to claim 1, wherein the width of the upper portion (70) is less than the width of the lower portion (68).The semiconductor device of claim 1, wherein the sidewalls of the upper portion (70) and the spacer (62) are aligned.The semiconductor device of claim 1, wherein the OTP capacitor comprises: a fin-shaped structure (26) on the substrate (12); a doped region (50) in the fin-shaped structure (26); an interfacial layer (78) on the doped region (50); and an upper electrode on the interfacial layer (78).The semiconductor device of claim 5, wherein the top surface of the first gate dielectric layer (40) and the doped region (50) are coplanar.A semiconductor device comprising: a substrate (12) having a medium voltage, MV, region (16), a one time programmable, OTP, capacitor region (22), and a core region (20); an MV device in the MV region (16), the MV device comprising: a first gate dielectric layer (40) on the substrate (12); a first gate electrode (60) on the first gate dielectric layer (40); a spacer (62) adjacent the first gate electrode (60); and a shallow trench isolation, STI, (32) adjacent two sides of the first gate electrode (60); wherein the first gate dielectric layer (40) comprises: a bottom portion (68) on the shallow trench isolation (32) and the substrate (12); and a top portion (70) on the bottom portion (68); an OTP capacitor in the OTP capacitor region (22); and a metal oxide semiconductor, MOS, transistor in the core region (20).The semiconductor device of claim 7, wherein the first gate dielectric layer (40) comprises an inverted T-shape.The semiconductor device according to claim 7, wherein the width of the upper portion (70) is less than the width of the lower portion (68).The semiconductor device of claim 7, wherein the sidewalls of the upper portion (70) and the spacer (62) are aligned.The semiconductor device of claim 7, wherein the OTP capacitor comprises: a first fin-shaped structure (26) on the substrate (12); a doped region (50) in the first fin-shaped structure (26); a first interface layer (78) on the doped region (50); and a top electrode on the first interface layer (78).The semiconductor device of claim 11, wherein the top surface of the first gate dielectric layer (40) and the doped region (50) are coplanar.The semiconductor device of claim 11, wherein the MOS transistor comprises: a second fin-shaped structure (26) on the substrate (12); a second interface layer (78) on the second fin-shaped structure (26); a second gate electrode (60) on the second interface layer (78); and a source / drain region (72) adjoining two sides of the second gate electrode (60).

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