Method for manufacturing a power semiconductor device with a plurality of fins and a power semiconductor device manufactured therefrom

Abstract

Method (100) for fabricating a power semiconductor device with a plurality of fins, comprising the steps of (110) producing a plurality of mesas from a front face of a semiconductor substrate to a drift layer of the semiconductor substrate by etching, wherein each mesa has a top surface corresponding to a region of the front face of the semiconductor substrate, and each mesa is arranged between a first trench and a second trench, wherein the first trench has a first trench bottom surface and the second trench has a second trench bottom surface, wherein each mesa has a first side surface and a second side surface, wherein the first side surface corresponds to a first trench side surface of the first trench and the second side surface corresponds to a second trench side surface of the second trench, wherein each mesa has a width greater than 500 nm, and (120) applying a mask layer to the top surface.the first side face, the second side face, the first trench bottom surface and the second trench bottom surface, generating (130) a structured mask by area-wise removal of the mask layer so that an exposed surface is produced, wherein the exposed surface comprises the first side face, area-wise the top surface and the first trench bottom surface, generating (140) fins by machining the exposed surface, removing (150) the structured mask, and completing (160) the power semiconductor device.

Description

[0001] The invention relates to a method for producing a power semiconductor component having a plurality of fins and a power semiconductor component having a plurality of fins. State of the art

[0002] Power semiconductor components with a fin structure comprising a wide-bandgap substrate provide high channel density and minimal on-resistance in power electronics. The fins have a narrow width of less than 500 nm. The fins are manufactured by narrowing mesas on both sides.

[0003] The disadvantage here is that the surface quality of the fin sidewalls is negatively affected. In the case of a SiC substrate, carbon clusters can form on the fin sidewalls, leading to a reduction in channel mobility, as charge carriers exhibit increased scattering at these defects.

[0004] Another disadvantage is that the transconductance is very steep, which can lead to problems during dynamic operation of the power semiconductor component. For example, parasitic switching on of a transistor in a half-bridge configuration can occur.

[0005] The object of the invention is to overcome these disadvantages. Disclosure of the invention

[0006] The inventive method for producing a power semiconductor component with a plurality of fins comprises generating a plurality of mesas starting from a front side of a semiconductor substrate into a drift layer of the semiconductor substrate by means of etching, wherein each mesa has a top side corresponding to a region of the front side of the semiconductor substrate, and each mesa is arranged between a first trench and a second trench, wherein the first trench has a first trench bottom surface and the second trench has a second trench bottom surface, wherein each mesa has a first side surface and a second side surface, wherein the first side surface corresponds to a first trench side surface of the first trench and the second side surface corresponds to a second trench side surface of the second trench, wherein each mesa has a width greater than 500 nm, and applying a mask layer to the top side,the first side surface, the second side surface, the first trench bottom surface, and the second trench bottom surface. The method further comprises creating a structured mask by removing the mask layer in certain regions to create an exposed surface, the exposed surface comprising the first side surface, the top surface in certain regions, and the first trench bottom surface, and creating fins by machining the exposed surfaces. Furthermore, the method comprises removing the structured mask and completing the power semiconductor component.

[0007] The advantage here is that the fins are only narrowed on one side. This means that the first side of the fin has a different interface structure than the second side, resulting in high channel density and flat transconductance.

[0008] In a further development, the semiconductor substrate comprises SiC.

[0009] In a further embodiment, the mask layer comprises SiN.

[0010] The advantage here is that SiN has a high resistance to oxidation processes and can therefore be used as a mask to prevent the thermal growth of an oxide layer on a part of the semiconductor surface.

[0011] In a further development, the fins are produced by thermal oxidation.

[0012] In a further embodiment, the semiconductor substrate comprises GaN.

[0013] In a further development, the mask layer comprises Ti or TiO2.

[0014] In a further embodiment, the fins are produced using TMAH.

[0015] The power semiconductor component according to the invention with a plurality of fins is manufactured by means of the method according to the invention.

[0016] In one embodiment, the power semiconductor component is a FinFET.

[0017] In a further embodiment, the power semiconductor component is a FinMOSFET.

[0018] Further advantages arise from the following description of embodiments and the dependent patent claims. Short description of the drawings

[0019] The present invention is explained below with reference to preferred embodiments and the accompanying drawings. They show: Fig. 1 the inventive method for producing a power semiconductor component with a plurality of fins, Fig. 2a a starting product of the process according to the invention, Fig. 2b - 2e Intermediate products of the individual process steps of the process according to the invention, and Fig. 3 a power semiconductor component manufactured according to the invention.

[0020] Fig. 1 shows the inventive method 100 for producing a power semiconductor component with a plurality of fins. The method 100 starts with a step 110 in which a plurality of mesas are created by etching, starting from a front side of a semiconductor substrate and extending into a drift layer of the semiconductor substrate. The term mesa in this context refers to an elevation with a flat surface and steep flanks. Each mesa has an upper side that corresponds to a region of the front side of the semiconductor substrate or coincides with the front side. Each mesa is arranged between a first trench and a second trench, wherein the first trench has a first trench bottom surface and the second trench has a second trench bottom surface.Each mesa has a first side surface and a second side surface, wherein the first side surface corresponds to a first trench side surface of the first trench and the second side surface corresponds to a second trench side surface of the second trench. Each mesa has a width greater than 500 nm. In a subsequent step 120, a mask layer is applied to the top surface, the first side surface, the second side surface, the first trench bottom surface, and the second trench bottom surface. In a subsequent step 130, a structured mask is created by removing the mask layer in certain regions. This creates an exposed surface that includes the first side surface, the top surface in certain regions, and the first trench bottom surface. In a subsequent step 140, fins are created by machining the exposed surface.In a subsequent step 150, the patterned mask is removed, and the power semiconductor component is subsequently completed in a step 160. Step 160 comprises several prior art process steps. In other words, the mesas are narrowed on one side, creating fins with different interface structures on the sidewalls.

[0021] The semiconductor substrate comprises, for example, SiC or GaN. If the semiconductor substrate is SiC, SiN is used as the mask layer, for example. In step 140, thermal oxidation is then used, for example, to create the fins. In the case of GaN, Ti or TiO2 is used as the mask layer. In step 140, TMAH is then used, for example, to create the fins.

[0022] Fig. 2a shows the starting product 200 of the inventive method 100 from Fig. 1. The power semiconductor component manufactured based on the starting product is a FinMOSFET. The starting product 200 comprises a semiconductor substrate 201, in particular an n-type conductive layer. A drift layer 202 is arranged on the semiconductor substrate 201. A channel region 204, in particular a p-type channel, is arranged on the drift layer 202. A source region layer 205 is arranged on the channel region 204. The semiconductor substrate 201 comprises, for example, SiC or GaN.

[0023] Fig. 2b shows the intermediate product 210 of process step 110 from Fig. 1. It should be noted that like reference numerals describe like features. Fig. Figure 2b shows two mesa structures 203 separated by a second trench 207. The first trenches 206 can be seen in the edge region.

[0024] Fig. 2c shows the intermediate product 230 of process step 130 from Fig. 1. In addition to the Fig. 2a and Fig. 2b, a structured mask 211 is shown. The structured mask 211 partially covers a top surface of the mesas 203 and a second trench bottom surface of the second trench 207, as well as second side surfaces of the mesas. In other words, first side surfaces, regions of the top surface, and first trench bottom surfaces are exposed and form an exposed surface.

[0025] Fig. 2d shows the intermediate product 240 of process step 140 from Fig. 1. The mesa structures 203 are narrowed to form fins 212. In each case, one side wall of the fin 212, i.e., the second side surface, is protected by the structured mask 211. This means that to produce the fins 212, the final width of the fins 212 is generated via only one side surface of the mesas 203. In the example shown here, the narrowing occurs from the left for the left fin 212 and from the right for the right fin 212. In other words, the inner side walls of the fins 212 remain unchanged during the narrowing process. Due to the fact that the narrowing processes are not selective, the trench floor surfaces adjacent to the fins are also affected. This means that the first trenches 206 can be deeper than the second trenches 207. In a further embodiment not shown, the same side wall of the individual mesas can also be protected by the structured mask, ie always the left side of the mesas.In another embodiment (not shown), an entire mesa can be protected from narrowing by the structured mask. This allows, for example, different fin widths to be realized.

[0026] Fig. 2e shows the intermediate product 250 of process step 150 after removal of the structured mask.

[0027] Fig. 3 shows the power semiconductor component 300 manufactured according to the invention. The power semiconductor component 300 shows a FinMOSFET. The FinMOSFET comprises a drain electrode 309. A semiconductor substrate 301, for example SiC or GaN, is arranged on the drain electrode 309. A drift layer 302 is arranged on the semiconductor substrate 301. A preferably p-doped channel region 304 is arranged on the drift layer 302. A source region 305 is arranged on the channel region 304. A source electrode 308 is arranged on the source region 305. The fins 312 extend from the drift layer 302 to the source electrode 308. A gate electrode 307 is electrically separated from the fins 312 by a gate dielectric 313.

[0028] In a further embodiment, the manufactured power semiconductor component can be a FinFET. In this case, the FinFET lacks the Fig. 3 shown channel area 304.

[0029] The FinMOSFET or FinFET produced according to the invention is used, for example, in the electric drive train of an electric or hybrid vehicle, as well as in inverters for household appliances.

Claims

[1] A method (100) for producing a power semiconductor device having a plurality of fins, comprising the steps of: • Creating (110) a plurality of mesas starting from a front side of a semiconductor substrate into a drift layer of the semiconductor substrate by means of etching, wherein each mesa has a top side corresponding to a region of the front side of the semiconductor substrate, and each mesa is arranged between a first trench and a second trench, wherein the first trench has a first trench bottom surface and the second trench has a second trench bottom surface, wherein each mesa has a first side surface and a second side surface, wherein the first side surface corresponds to a first trench side surface of the first trench and the second side surface corresponds to a second trench side surface of the second trench, wherein each mesa has a width greater than 500 nm, • Applying (120) a mask layer to the top surface, the first side surface, the second side surface, the first trench bottom surface and the second trench bottom surface, • Creating (130) a structured mask by removing the mask layer in regions, so that an exposed surface is created, wherein the exposed surface comprises the first side surface, the top surface in regions and the first trench bottom surface, • Creating (140) fins by machining the exposed surface, • Remove (150) the structured mask, and • Completion (160) of the power semiconductor component. [2] Method (100) according to claim 1, characterized by that the semiconductor substrate comprises SiC. [3] Method (100) according to one of claims 1 or 2, characterized by that the mask layer comprises SiN. [4] Method (100) according to one of the preceding claims, characterized bythat the fins are produced by thermal oxidation. [5] Method (100) according to claim 1, characterized by that the semiconductor substrate comprises GaN. [6] Method (100) according to one of claims 1 or 5, characterized by that the mask layer comprises Ti or TiO2. [7] Method (100) according to one of claims 1 or 5 and 6, characterized by that the fins are produced using TMAH. [8] Power semiconductor component (200, 300) having a plurality of fins, which is manufactured by a method according to one of the preceding claims. [9] The power semiconductor device (200) of claim 8, wherein the power semiconductor device is a FinFET. [10] Power semiconductor component (200, 300) according to claim 8, characterized by that the power semiconductor component is a FinMOSFET.

Images