Hybrid analog-to-digital converter

Abstract

A system can include a hybrid analog-to-digital converter (ADC), consisting of a flash ADC in one mode and a delta-sigma ADC in a second mode. The flash ADC can provide output resulting from a coarse analog-to-digital conversion. This output can then be used to configure the delta-sigma ADC to perform a fine analog-to-digital conversion.

Description

BACKGROUND

[0001] This document generally concerns systems with analog-to-digital converters (ADCs) and in particular ADCs in image sensors or imaging systems.

[0002] Image sensors are commonly used in electronic systems or devices to generate image data. In a typical configuration, an image sensor comprises an image sensor array containing active image sensor pixels. Based on control signals received along control paths, the active image sensor pixels generate image signals in response to incident light. The generated image signals are read out along readout paths and are used to produce one or more frames that can be used within the electronic system.

[0003] The pixel-generated image signals are analog signals that are converted into digital data by ADCs during readout processes. It may be desirable to provide an ADC with high conversion speeds and reduced power consumption while delivering a high bit-resolution output. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a representation of an illustrative system comprising one or more image sensors according to some embodiments. Fig. Figure 2 is a representation of an illustrative image sensor circuit arrangement comprising an image sensor pixel array and a control and readout circuit arrangement for the pixel array according to some embodiments. Fig. Figure 3 is a representation of a hybrid analog-to-digital converter circuit arrangement according to some embodiments. Fig. Figure 4 is a diagram illustrating signal level ranges based on the light intensity of the corresponding pixel signal according to some embodiments. Fig. Figure 5 is a representation of an illustrative calibration circuit, configured according to some embodiments to store range information. Fig. Figure 6 is a circuit diagram of an illustrative delta-sigma analog-to-digital converter configured to operate in a flash operating mode according to some embodiments. Fig. Figure 7 is a circuit diagram of the delta-sigma analog-to-digital converter from Fig. 6, which is configured to operate in a flash operating mode according to some embodiments. DETAILED DESCRIPTION

[0004] Electronic systems and / or devices can include one or more image sensors that collect incoming light to capture images. The image sensor can include one or more arrays of image sensor pixels. The pixels in the image sensor can include light-sensitive elements, such as photodiodes, that convert the incoming light into image signals. Image sensors can have any number of pixels (e.g., hundreds, thousands, or more). A typical image sensor, for example, might have hundreds of thousands or millions of pixels (e.g., megapixels). Image sensors can include a control circuit arrangement, such as a circuit arrangement for operating the image pixels, and a readout circuit arrangement for reading out image signals corresponding to the electrical charge generated by the light-sensitive elements.

[0005] Fig. Figure 1 is a functional block diagram of an illustrative imaging system, such as an electronic device that uses an image sensor to capture images. Imaging system 10 of Fig. 1 can be a portable electronic device such as a camera, mobile phone, tablet computer, webcam, video camera, video surveillance system, automotive imaging system, video game system with imaging capabilities, augmented reality and / or virtual reality system, unmanned aerial vehicle system such as a drone, industrial system or any other desired imaging system or device that captures image data.

[0006] A camera module 12, sometimes referred to as an imaging module, can be used to convert incoming light into digital image data. The camera module 12 can include one or more macro lenses 14 and one or more image sensors 16. When capturing images, light from a scene can be focused by one or more macro lenses 14 onto each image sensor 16. The image sensor 16 can include a circuit arrangement for converting analog pixel image signals into corresponding digital image data, which is provided to the storage and processing circuit arrangement 18.

[0007] A storage and processing circuit arrangement 18 can include one or more integrated circuits, each providing data storage and / or data calculation or processing functions. Examples include image processing circuits such as digital signal processors, application-specific integrated circuits, general-purpose processors, microprocessors, microcontrollers, storage devices such as random-access memory and non-volatile memory, and / or other types of integrated circuits that include processors and / or memory.

[0008] The storage and processing circuit arrangement 18 can be implemented using components separate from the camera module and / or components that form part of the camera module. For example, the storage and processing circuit arrangement 18 can be implemented using circuits that form part of an integrated circuit that includes an image sensor 16 or an integrated circuit within the camera module 12. If the storage and processing circuit arrangement 18 is enclosed on integrated circuits other than those of the image sensors 16, the integrated circuits with the circuit arrangement 18 can be vertically stacked or packed with respect to the integrated circuits with the image sensors 16.

[0009] Image data acquired by the camera module 12 can be processed and stored using the processing circuit 18. For example, an image processing engine, an imaging mode selection engine, and / or other types of processing engines on the processing circuit 18 can process the image data acquired by the camera module 12. The processing circuit assembly 18 can, if desired, provide processed image data to external devices such as a computer, an external display, or other devices using wired and / or wireless communication paths.

[0010] As in Fig. As shown in Figure 2, the image sensor 16 can include a pixel array, such as the pixel array 20, containing image sensor pixels 22, which are sometimes referred to herein as image pixels or simply pixels, arranged in rows and columns. A row of pixels or a column of pixels may sometimes be referred to herein generally as a line of pixels. The image sensor 16 can include a control and processing circuit arrangement 24, sometimes referred to herein as the control circuit arrangement 24, which controls the operation of the pixel array 20. The pixel array 20 can, for example, contain hundreds or thousands of rows and columns of image sensor pixels 22. The pixel array 20 can be provided with a filter array having multiple visible color or invisible filter elements, each corresponding to a specific pixel, thus enabling a single image sensor to sample light of different colors or sets of wavelengths.

[0011] The image sensor pixels 22 can be formed in a semiconductor substrate using a technology that utilizes a complementary metal-oxide-semiconductor (CMOS), or a technology that utilizes a charge-coupled device (CCD), or using any other suitable technology that utilizes light-sensitive devices. The image sensor pixels 22 can be front-illuminated (FSI) or back-illuminated (BSI) image sensor pixels.

[0012] The control circuit arrangement 24 can be coupled to a pixel control circuit such as the row control circuit arrangement 26, which includes row drivers that provide control signals to the pixel array 20, and can be coupled to the pixel readout circuit arrangement such as a column readout and control circuit arrangement 28, which reads signals from the pixel array 20.

[0013] The line control circuit arrangement 26 can receive line addresses and / or signals specifying line addresses from the control circuit arrangement 24 and supply corresponding line control signals, such as reset, anti-blooming, line selection, charge transfer, dual conversion gain, and readout control signals, to the pixels 22 via conductive lines or paths 30, such as pixel line control paths. In particular, each pixel line can receive different control signals via a corresponding number of control paths, so that each pixel line is coupled to multiple conductive paths 30. One or more conductive lines or paths 32, such as pixel column readout paths, can be coupled to each column of pixels 22. The conductive paths 32 can be used to read image signals from the pixels 22 and to supply bias signals, such as bias currents or bias voltages, to the pixels 22.As an example, when performing a pixel readout operation, a pixel row in the pixel array 20 can be selected using the row control circuit arrangement 26, and image signals generated by the selected image pixels 22 in that pixel row can be read out along the conductive paths 32.

[0014] The column readout circuit arrangement 28 can receive image signals, such as analog pixel values ​​generated by the pixels 22, via the conductive paths 32. The column readout circuit arrangement 28 can be a storage or buffer circuit arrangement for temporarily storing calibration signals, such as...The column readout circuitry 28 may include an amplifier circuit arrangement or a multiplier circuit, an analog-to-digital converter (ADC) circuit arrangement, a bias circuit arrangement, a signal storage circuit arrangement for selectively enabling or disabling sections of the column readout circuitry 28, or another circuit arrangement coupled to one or more columns of pixels in the array 20 for operating the pixels 22 and / or reading image signals from the pixels 22. The ADC circuit arrangement in the readout circuitry 28 can convert analog pixel values ​​received from the array 20 into corresponding digital pixel values, sometimes referred to as digital image data or digital pixel data.The column readout circuit arrangement 28 can read the digital pixel data from the pixels 22 in one or more pixel columns of the control and processing circuit arrangement 24 and / or the processor 18 (. Fig. 1) for further processing and / or storage.

[0015] Fig. Figure 3 shows an illustrative analog-to-digital converter circuit arrangement, such as an analog-to-digital converter 40, which can be operated in both a flash ADC mode 42 and a delta-sigma ADC mode 44. The ADC 40 can be coupled to one or more conductive paths 32 for one or more corresponding columns of pixels 22. The ADC 40 can receive pixel-generated analog signals, such as reset level signals and image level signals, as an ADC input and convert these analog signals into corresponding digital data as an ADC output. A pixel readout circuit arrangement, such as the column readout circuit arrangement 28 in Figure 3, is also shown. Fig. 2 can include any suitable number of ADCs 40 that process the read-out analog signals for different pixel columns in parallel.

[0016] The ADC 40 can include a delta-sigma modulator with delta-sigma circuits 46, a comparator 48 (sometimes called a 1-bit ADC), and a digital-to-analog converter (DAC) 50. The ADC 40 can also include a digital filter 74 and an arithmetic circuit 76. The delta-sigma circuits 46 can include any suitable combination of delta circuits, such as differential amplifiers, and / or sigma circuits, such as integrators or integrator amplifiers. For example, the delta-sigma circuits 46 can form a first-order delta-sigma modulator, a second-order delta-sigma modulator, or any other higher-order delta-sigma modulator. The downstream output of delta-sigma circuits 46, such as... B. the most downstream integrator can be coupled to an input of comparator 48.The DAC 50 can be coupled via a feedback path between an output of the comparator 48 and the delta-sigma circuits 46. Based on the output of the comparator 48, the DAC 50 can provide high and low reference voltages for the delta-sigma circuits 46. The digital filter 74 can include a decimation filter that receives the output of the comparator. The arithmetic circuit 76, such as an adder and / or multiplier, can provide selective scaling for the output of the digital filter 74 to generate the ADC output for the ADC 40.

[0017] These components of the ADC 40 are for illustrative purposes only. If desired, the ADC 40 can include any suitable additional components. Since the actual (high-resolution) analog-to-digital conversion is performed in Delta-Sigma-ADC mode 44, the ADC 40 is sometimes referred to herein as the Delta-Sigma-ADC 40.

[0018] Some of the components of the ADC 40, such as the comparator 48 and the differential amplifier(s) and / or the integrating amplifier(s) in delta-sigma circuits 46, can be shared between the Flash ADC mode 42 and the Delta-Sigma ADC mode 44. In other words, if the ADC 40 is configured to form a Flash ADC in mode 42, one or more of the comparator 48 and amplifier(s) in delta-sigma circuits 46 can form the Flash ADC. If the ADC 40 is configured to form a Delta-Sigma ADC in mode 44, the same components (e.g., one or more of the comparator 48 and the amplifier(s) in delta-sigma circuits 46) can form the Delta-Sigma ADC.In this way, the additional functionalities provided by the Delta-Sigma-ADC 40, which serves as a Flash-ADC, can be provided without having to include at least some sections of a dedicated Flash-ADC, thereby desirably reducing the implementation scope of the ADC 40.

[0019] By first operating the ADC 40 as a Flash ADC in mode 42, the ADC 40 can perform a rough analog-to-digital conversion operation on an analog input signal. The results of the rough conversion operation can be a Flash ADC mode output 52. The output 52 can include one, two, three, four, five, or any other suitable number of bits resulting from the rough analog-to-digital conversion of the analog input signal. This one or more bits can help to characterize the light intensity region in which the analog input signal lies, thus helping to perform the fine or actual analog-to-digital conversion of the analog input signal more efficiently.

[0020] Following operation as a flash ADC, the ADC 40 can operate as a delta-sigma ADC in mode 44. As a delta-sigma ADC, the ADC 40 can perform analog-to-digital fine-conversion on the same analog input signal. The results of this fine-conversion can be the ADC output, which corresponds to the analog input signal. The ADC output can include any number of bits, such as 8 bits, 10 bits, 12 bits, or any other bit resolution. The bit resolution (number of bits) of the digital data output by the fine-conversion process for the analog input signal is greater than the bit resolution (number of bits) of the digital data output by the coarse-conversion process for the analog input signal.

[0021] As in Fig. As shown in Figure 3, the operation of ADC 40 as a delta-sigma ADC in mode 44 can be based on the output 52 of the coarse conversion operation. Specifically, ADC 40, operating as a delta-sigma ADC in mode 44, can receive input 54 based on the flash-mode output 52. Input 54 can include one or more control signals, one or more control bits, and / or one or more control data received at one or more components of ADC 40. In this way, input 54 can adjust the parameters of ADC 40 when operating in delta-sigma ADC mode 44 to optimize conversion speed, power consumption, high bit resolution, and other operating characteristics that depend on the characteristics of the analog input signal obtained during the fast initial coarse conversion.

[0022] In the arrangements described herein as an illustrative example, the ADC 40, when operating in Flash ADC mode, can generate 42 bits of information that specify the light intensity of the analog input signal, or more generally, the region on the photon transfer curve, as output 52. The bit information can specify different ranges for different regions of light intensity and the corresponding dominance of the shot noise in these ranges or regions.

[0023] Fig. Figure 4 is a diagram illustrating how these regions or areas can be defined based on the signal level of pixel-generated signals. In the example of Fig. Figure 4 shows line 56, illustrating how the signal level of pixel-generated signals increases as the image light intensity increases until the pixel-generated signal is saturated. Line 58 shows the noise level of the photon shot noise, which increases with the square root of the pixel-generated signal level. The level of the photon shot noise also increases with the signal level of the pixel-generated signal until saturation. The ratio between the signal level and the total noise level defines the signal-to-noise ratio (SNR). In regions of the curve where shot noise is the dominant noise, the SNR can be appropriately approximated as the ratio between the signal level and the noise level of the shot noise.

[0024] It may be desirable to classify any given pixel-generated signal into different regions corresponding to different ranges of light intensities and associated with varying degrees of shot noise. These regions are sometimes referred to herein as ranges and are represented in the example of Fig. 4 are shown as areas AREA1, AREA2, AREA3 and AREA4.

[0025] In an illustrative configuration, sometimes described herein as an example, the ADC 40 ( Fig. 3), operating in Flash ADC mode 42, generates a set of bits indicating the corresponding range to which the ADC input signal belongs as Flash mode output 52. For example, the result of coarse conversions with pixel-generated signals corresponding to light intensities in RANGE1 can be the binary value (bit value) "000", the result of coarse conversions with pixel-generated signals corresponding to light intensities in RANGE2 can be the binary value (bit value) "001", the result of coarse conversions with pixel-generated signals corresponding to light intensities in RANGE3 can be the binary value (bit value) "011", and the result of coarse conversions with pixel-generated signals corresponding to light intensities in RANGE4 can be the binary value (bit value) "111".

[0026] Since the ADC 40, operating in Flash ADC mode 42, helps to identify the region or range to which the ADC input signal belongs (rather than the specific digital ADC output with the desired ADC output bit resolution), this initial classification process, which is a Flash ADC conversion process, can sometimes be referred to as the analog-to-digital coarse conversion process. Based on the coarse conversion output, the ADC 40 can adjust its operating parameters to operate in Delta-Sigma ADC mode 44 and perform the fine conversion process in mode 44.

[0027] Since the ADC 40 sets the operating parameters for the Delta-Sigma-ADC mode 44 based on the range to which the ADC input signal belongs, the operating parameters can help to achieve a high (fine) conversion speed, reduced power consumption, high ADC output bit resolution and / or other properties as desired.

[0028] As an illustrative example, when the ADC 40 operates on an input signal in a region or area dominated by shot noise, such as in RANGE2, RANGE3 and RANGE4, the high and low reference voltages of the DAC (e.g., those supplied by the DAC 50 to the Delta-Sigma circuits 46 in Fig. 3 applied reference voltages), change the delta-sigma modulator clock frequency, and / or change the integrator amplifier bias current compared to operating on an input signal in a region or range that is not shot-noise dominated, such as RANGE1. In fact, these parameters (e.g., DAC reference voltages, delta-sigma modulator clock frequency, and / or integrator amplifier bias current) can be different or scaled across the shot-noise-dominated RANGE2, RANGE3, and RANGE4, as desired.

[0029] By scaling the DAC reference voltages based on the range to which the ADC input signal belongs, the quantization step of the ADC 40, operating in delta-sigma ADC mode, can be modified to reduce the number of conversion cycles required to achieve the same bit output resolution across the different ranges. This DAC reference voltage scaling for each range is described in Fig. 4 is represented by line 60, which indicates the corresponding different quantization noise levels for the different ranges displayed by ADC 40. In some of the illustrative configurations described herein, the quantization noise levels may be adjustable by setting the oversampling rate (e.g., the clock frequency) of the delta-sigma modulator and / or the integrator amplifier bias current.

[0030] By scaling the delta-sigma modulator clock frequency and / or the integrator amplifier bias current (e.g. operating parameters of delta-sigma circuits 46) ADC 40 can operate with reduced power consumption.

[0031] Since quantization steps differ across the ranges, the ADC 40 can compensate for these differences by scaling the output of the digital filter (e.g., decimator) of the Delta-Sigma-ADC 40. In particular, to gather range information that facilitates appropriate scaling for the digital filter output, the ADC 40 can be calibrated before performing the coarse and fine conversion operations. As described in Fig. As shown in Figure 5, the ADC 40 can be configured to receive a calibration input and generate a corresponding calibration output. The calibration output can be processed and / or stored in the calibration circuit 62 or, more precisely, in the memory circuit 64.

[0032] In particular, the calibration input can sample or traverse the ADC input voltage to detect range transitions such as transitions between range 1 and range 2, between range 2 and range 3, and between range 3 and range 4 ( Fig. 4) to mark. In the example of Fig. 4. There can be three transitions to be marked, and a ramp signal can go from a voltage starting at the first transition to a voltage after the third transition.

[0033] In an illustrative arrangement, the calibration circuit 62 can include a counter-based DAC that generates the ramp signal provided by the delta-sigma analog-to-digital converter 40 as a calibration input. As an example, each range can span a voltage range of 250 millivolts (mV), the ramp signal can start 100 mV before the first transition, and the ramp signal can end 100 mV after the last transition. Accordingly, the ramp signal can sample a total of 100 mV + 250 mV + 250 mV + 100 mV = 700 mV with a ramp resolution of 0.2 mV (e.g., 1 least significant bit). The ADC 40 can convert the swept voltages every 0.2 mV between the swept 700 mV in the flash ADC to obtain the appropriate range information, in this example with 3500 ADC conversions. The memory circuit 64 can store the appropriate range information corresponding to the range transitions.The storage circuit 64 can be formed from line buffers.

[0034] As in connection with Fig. As described in section 4, the result of coarse conversions assigned to the area AREA1 can be the binary value "000", the result of coarse conversions assigned to the area AREA2 can be the binary value "001", the result of coarse conversions assigned to the area AREA3 can be the binary value "011", and the result of coarse conversions assigned to the area AREA4 can be the binary value "111".

[0035] While the sweep voltages of the calibration input ramp signal are being converted, when the calibration output resulting from the conversion change changes from the binary value "000" to the binary value "001", the immediately preceding ADC conversion calibration output can be stored as the end of the range RANGE1, and the current ADC conversion calibration output can be stored as the offset or start of the range RANGE2, thus marking the range transition between the ranges RANGE1 and RANGE2.As the sweep continues and additional voltages of the calibration input ramp signal are converted, when the calibration output resulting from the conversion changes from the binary value "001" to the binary value "011", the immediately preceding ADC conversion calibration output can be stored as the end of range 2, and the current ADC conversion calibration output can be stored as the offset or start of range 3, thus marking the range transition between ranges 2 and 3.As the sweep continues and additional voltages of the calibration input ramp signal are converted, when the calibration output resulting from the conversion changes from the binary value "011" to the binary value "111", the immediately preceding ADC conversion calibration output can be stored as the end of range 3, and the current ADC conversion calibration output can be stored as the offset or start of range 4, thus marking the range transition between ranges 3 and 4.

[0036] In particular, the ADC 40 can store from the above calibration process (e.g. in the memory circuit 64) the ADC conversion calibration output for the end of range 1 (i.e., range 1 end), the ADC conversion calibration output for the offset (or start) of range 2 (i.e., range 2 offset), the ADC conversion calibration output for the end of range 2 (i.e., range 2 end), the ADC conversion calibration output for the offset (or start) of range 3 (i.e., range 3 offset), the ADC conversion calibration output for the end of range 3 (i.e., range 3 end), and the ADC conversion calibration output for the offset (or start) of range 4 (i.e., range 4 offset).

[0037] By obtaining these range transition values, the ADC 40 can appropriately scale the output from the digital filter in the ADC 40 to produce the suitable ADC output while taking the quantization step into account.

[0038] As a first example, if the pixel-generated signal and the corresponding output of the digital filter (i.e., DOUT) are within the range RANGE1, no scaling factor is needed, and the output of the digital filter can be passed on as the ADC output (i.e., ADCOUT). In other words: ADCOUT = DOUT.

[0039] As a second example, if the pixel-generated signal and the corresponding output of the digital filter (i.e., DOUT) are in the range RANGE2, the ADC 40 can calculate the ADC output (i.e., ADCOUT) based on the following equation: ADCOUT = RANGE1-End ((DOUT - RANGE2-Offset) *2), where 2 is an illustrative scaling factor for the range RANGE2.

[0040] As a third example, if the pixel-generated signal and the corresponding output of the digital filter (i.e., DOUT) are in the range RANGE3, the ADC 40 can calculate the ADC output (i.e., ADCOUT) based on the following equation: ADCOUT = RANGE1-End ((RANGE2-End - RANGE2-Offset) *2) ((DOUT - RANGE3-Offset) *4), where 2 is an illustrative scaling factor for the range RANGE2 and 4 is an illustrative scaling factor for the range RANGE3.

[0041] As a fourth example, if the pixel-generated signal and the corresponding output of the digital filter (i.e., DOUT) are in the range 4, the ADC 40 can calculate the ADC output (i.e., ADCOUT) based on the following equation: DCOUT = RANGE1-End + ((RANGE2-End - RANGE2-Offset) * 2) + ((RANGE3-End - RANGE3-Offset) * 4) + ((DOUT - RANGE4-Offset) * 8)), where 2 is an illustrative scaling factor for the range 2, 4 is an illustrative scaling factor for the range 3, and 8 is an illustrative scaling factor for the range 4.

[0042] The ADC 40 can select sections of the digital filter output in each of the areas based on the information associated with Fig. 5. In other words, the ADC 40 can obtain the range information, such as the corresponding digital output associated with the end of range RANGE1, the start of range RANGE2, the end of range RANGE2, the start of range RANGE3, the end of range RANGE3, and the start of range 44, from the memory circuit 64 in order to perform the aforementioned scaling calculations.

[0043] Fig. Figure 6 is a circuit diagram of an illustrative configuration of the ADC 40. In the example of Fig. 6 The ADC 40 includes a first integrator 70 or a sigma circuit 70, a second integrator 72 or a sigma circuit 72, a comparator 48, a DAC 50, a digital filter 74, and an arithmetic circuit 76. The integrators 70 and 72 and the switches coupled to the integrators 70 and 72, which can be operated based on different phases, can form the delta-sigma circuit 46 ( Fig. 3).

[0044] The integrator 70 can include the operational amplifier 82 with a first (non-inverting) input terminal coupled to a reference voltage terminal and configured to receive the reference voltage V1. The amplifier 82 has a second (inverting) input terminal coupled to the input terminal of the ADC 40 and configured to receive the ADC input analog signal along an input path. Switch 86, capacitor 94, and switch 96 can be coupled between the second input terminal and the input terminal of the ADC 40 along the input path. Switch 84, in combination with switch 86, can couple the second input terminal of the amplifier 82 to a reference voltage terminal.

[0045] Amplifier 82 has an output terminal that is coupled to integrator 72. Reset switch 88 can be coupled between the second input terminal of amplifier 82 and the output terminal of amplifier 82 along a first path. Capacitor 90 can be coupled between the second input terminal of amplifier 82 and the output terminal of amplifier 82 along a second path in parallel to the first path.

[0046] The integrator 72 can include the operational amplifier 102 with a first (non-inverting) input terminal coupled to a reference voltage terminal and configured to receive the reference voltage V2. The amplifier 102 has a second (inverting) input terminal coupled to the output terminal of the amplifier 82 and configured to receive the output signal of the amplifier 82 along an input path. The switch 106, the capacitor 114, and the switch 92 can be coupled between the second input terminal of the amplifier 102 and the output terminal of the amplifier 82 along the input path. The switch 104, in combination with the switch 106, can couple the second input terminal of the amplifier 102 (and a first terminal of the capacitor 114) to a reference voltage terminal.Switch 116 can couple an opposite second terminal of capacitor 114 to a reference voltage terminal.

[0047] Amplifier 102 has an output terminal that is coupled to comparator 48. Reset switch 108 can be coupled between the second input terminal of amplifier 102 and the output terminal of amplifier 102 along a first path. Capacitor 110 can be coupled between the second input terminal of amplifier 102 and the output terminal of amplifier 102 along a second path in parallel to the first path.

[0048] The comparator 48 can be formed from an operational amplifier having a first (non-inverting) input terminal coupled to a reference voltage terminal and configured to receive the reference voltage V3. The amplifier forming the comparator 48 can have a second (inverting) input terminal coupled to the output terminal of the amplifier 102 and configured to receive the output signal of the amplifier 102 along an input path. The switch 112 and the capacitor 122 can be coupled between the second input terminal of the amplifier of the comparator 48 and the output terminal of the amplifier 102 along the input path. The switch 120 can couple the second input terminal of the amplifier of the comparator 48 (and a first terminal of the capacitor 122) to a reference voltage terminal.The switch 118 can couple an opposite second terminal of the capacitor 122 with a reference voltage terminal.

[0049] Capacitor 124 can be connected along a first path between the second input terminal of comparator 48's amplifier and the output terminal of amplifier 82 (between switch 92 and capacitor 114). Capacitor 126 and switch 128 can be connected along a second path between comparator 48's second input terminal and ADC 40's input terminal. Switch 130 can connect the second path (between capacitor 126 and switch 128) to a reference voltage terminal.

[0050] The states of switches 84 and 104 can be controlled by the control signal p1. The states of switches 92, 96, 112, and 128 can be controlled by the control signal p1d (e.g., a delayed version of the control signal p1). The states of switches 86, 116, 118, and 120 can be controlled by the control signal p2 (e.g., an inverted version of the control signal p1). The states of switches 98, 106, and 130 can be controlled by the control signal p2d (e.g., a delayed version of the control signal p2). The control signals p1 and p2 can be non-overlapping clock signals (e.g., setting the clock signals is non-overlapping). A control circuit arrangement (e.g. a microcontroller, a processor, etc.) can feed these control signals to switches to operate the ADC 40 in two phases, the p1 / p1d phase and the p2 / p2d phase.

[0051] The comparator 48, or more specifically the amplifier forming the comparator 48, can have an output terminal coupled to the digital filter 74. The digital filter 74 can include a decimation filter and / or other types of digital filters. The comparator output signal COMP OUT can be generated at the output terminal and supplied to the digital filter 74. Additionally, the comparator output signal COMP OUT can be supplied to the DAC 50 as a control signal.

[0052] As in Fig. As shown in Figure 6, the DAC 50 can be coupled to the ADC 40 via the ADC input terminal and the second input terminal of the amplifier 82. Specifically, the DAC 50 can be coupled to the input path (between the capacitor 94 and the switch 96) via the switch 98. The DAC 50 can include two switches 78 configured to provide high and low reference voltages for the input path (e.g., for the second input terminal of the amplifier 82). In other words, a first switch 78 can provide a high reference voltage, while a second switch 78 can provide a low reference voltage. The comparator output signal COMP OUT can be supplied to the switch 78 as a control signal.The COMP OUT signal can selectively provide one of the high reference voltages (via the first switch 78) or the low reference voltages (via the second switch 78) for the input path and the second input terminal of the amplifier 82 via the capacitor 94.

[0053] The DAC 50 can include a variety of reference voltage connections, each supplying different voltages, and can include a corresponding number of switches (80) that provide one of the reference voltages as the high reference voltage of the DAC 50 and another of the reference voltages as the low reference voltage of the DAC 50. Although in the example of Fig. Figure 6 shows five illustrative reference voltage terminals and five corresponding switches 80; however, this is for illustrative purposes only. In configurations where ranges (e.g., RANGE1, RANGE2, RANGE3, and RANGE4) are provided, it may be desirable to provide eight reference voltage terminals, each providing eight different voltages vref1, vref2, vref3, vref4, and vref5 (as shown in Figure 80). Fig. 6 shown) and vref6, vref7 and vref8 (not explicitly in Fig. (shown in 6) and provide eight corresponding switches 80. In particular, a different pair of different voltages can be provided for each range as the high and low reference voltage of the DAC 50.

[0054] For example, for range 1, the voltage vref1 (e.g., 2.0 volts (V)) can be used as the high reference voltage of the DAC 50, and the voltage vref2 (e.g., 1.8 V) can be used as the low reference voltage of the DAC 50. As another example, for range 2, the voltage vref3 (e.g., 1.85 V) can be used as the high reference voltage of the DAC 50, and the voltage vref4 (e.g., 1.5 V) can be used as the low reference voltage of the DAC 50 in a first mode.

[0055] The coarse conversion of the flash ADC can produce the output (e.g., a set of bits such as "000", "001", "011" and "111" in the example of Fig. 4, specifying the ranges). The coarse conversion output of the ADC input can be used as input to configure the states of switches 80, thereby selecting the two suitable reference voltages to be used as the high and low reference voltages of the DAC 50.

[0056] As in connection with Fig. As described in section 4, the voltage levels of the high and low reference voltages of the DAC 50 can define a quantization step of the delta-sigma circuits. Accordingly, by adjusting the high and low reference voltages (e.g., selecting the desired high and low reference voltages) and thus the quantization step, the number of cycles required to convert the ADC input signal to an output with a specific bit resolution can be reduced.

[0057] In addition to selecting the appropriate pair of high and low reference voltages for the DAC 50, the ADC 40 can also be configured to adjust (e.g., scale) the delta-sigma modulator clock frequency (sometimes called oversampling rate) and / or to adjust (e.g., scale) the integrator amplifier bias current. Some illustrative configurations shown herein as examples (e.g., the ADC 40 configuration in Fig. 6) described, the clock frequency of the signals p1, pld, p2 and / or p2d ( Fig. 6) The delta-sigma modulator clock frequency can be specified or scaled accordingly, and the internal bias current of integrators 70 and / or 72 can be scaled accordingly to match the integrator amplifier bias current. Scaling one or more of these two parameters (e.g., the delta-sigma modulator clock frequency and / or the integrator amplifier bias current) can also scale the quantization noise floor (e.g., the steps of line 60 in Fig. 4), which reduces power consumption. For example, for range 1, the delta-sigma modulator clock frequency can be f Hertz (Hz), and the integrator-comparator bias current can be I milliamperes (mA). As another example, for range 2, the delta-sigma modulator clock frequency can be f / x Hz, and the integrator-comparator bias current can be I / x mA, where x is a scaling factor for range 2 greater than 1. As yet another example, for range 3, the delta-sigma modulator clock frequency can be f / y Hz, and the integrator-comparator bias current can be I / y mA, where y is a scaling factor for range 3 greater than x.

[0058] The digital filter 74 can be coupled with the arithmetic circuit 76, which receives the output of the digital filter 74 based on the range information derived from the data associated with Fig. The calibration process described in section 5 was obtained and is stored in the memory circuit 64. The arithmetic circuit 76 can include multiplier circuits and / or adder circuits that selectively multiply sections of the digital filter output by appropriate scaling factors and combine the corresponding scaled sections of the digital filter output in the same manner as described above in conjunction with Fig. As described in section 5, this scaling can help to linearize the (output) response obtained through the digital filter 74.

[0059] If desired, the arithmetic circuit 76 can be omitted, and the output response of the digital filter 74 can be left unlinearized. Accordingly, by not applying the corresponding scaling factor, the dynamic range of the digital filter's response can be extended, and the ADC 40 can operate with a wider dynamic range.

[0060] While Fig. Figure 6 shows some sections of the ADC 40 that form a Delta-Sigma-ADC in mode 44. Fig. Seven other sections of the ADC 40, forming a Flash ADC in mode 42. In the example of Fig. 7 can be used with the amplifier 82 (e.g. for the integrator 70 in Fig. 6), the amplifier 102 (e.g. for the integrator 72 in Fig. 6) and the amplifier for comparator 48 (also in Fig. 6) for the Flash ADC in addition to the formation elements of the Delta-Sigma ADC in Fig. 6 can be used.

[0061] In particular, the first (non-inverting) input terminal of amplifier 82 can be configured to receive a reference voltage V1 that is equal to or different from the reference voltage V1 in the delta-sigma mode configuration of Fig. The second (inverting) input can be connected to the ADC input of the ADC 40 via switch 132. The output of amplifier 82 can be connected to a signal memory 138.

[0062] The first (non-inverting) input terminal of amplifier 102 can be configured to receive a reference voltage V2 that is equal to or different from the reference voltage V2 in the delta-sigma mode configuration of Fig. The second (inverting) input can be connected to the ADC input of the ADC 40 via switch 132. The output of amplifier 102 can be connected to signal storage 148.

[0063] The first (non-inverting) input terminal of the amplifier for comparator 48 can be configured to receive a reference voltage V3 that is equal to or different from the reference voltage V3 in the delta-sigma mode configuration of Fig. The second (inverting) input can be connected to the ADC input of the ADC 40 via switch 132. The output of the amplifier for the comparator 48 can be connected to the signal memory 158.

[0064] Amplifiers 82, 102, and 48 can each be configured to provide a corresponding bit to signal memories 138, 148, and 158 (e.g., StrongARM signal memory) based on comparing the same analog input voltage with different reference voltages V1, V2, and V3. In other words, amplifiers 82, 102, and 48 can form three corresponding comparators or 1-bit ADCs for the Flash ADC configuration of ADC 40. Binary converter 160 can convert the three stored bits in signal memories 138, 148, and 158 into a corresponding binary value as the Flash ADC mode conversion output. The Flash ADC mode conversion output can be used to transmit the state of switches 80 to DAC 50 ( Fig. 6) to control when selecting the appropriate high and low reference voltage for the DAC 50.

[0065] Although various elements of the ADC 40 are in Fig. 6 and Fig. 7 is described separately; however, this is merely for illustrative purposes and is done to avoid unnecessarily obscuring the various aspects of the ADC 40. The aspects related to Fig. 6 and Fig. The seven described elements of ADC 40 can be implemented in a single ADC 40. For example, ADC 40, as described in Fig. Figure 6 shows, in addition to the switch 132, the signal storage devices 138, 148 and 158, the converter 160 and the paths coupled to each of these elements, as shown in Fig. 7 shown.

[0066] Several embodiments have been described that illustrate a hybrid ADC which can be operated as a Flash ADC and as a Delta-Sigma ADC.

[0067] As a first example, an image sensor can include an array of image sensor pixels and a pixel readout circuitry coupled to the array of image sensor pixels. The pixel readout circuitry can include an analog-to-digital converter (ADC) configured to operate as a flash ADC in a first mode and as a delta-sigma ADC in a second mode. Specifically, the ADC can be configured to perform a coarse conversion operation on a pixel signal when operating as the flash ADC and can be configured to perform a fine conversion operation on the pixel signal when operating as the delta-sigma ADC. The coarse conversion operation produces initial digital data with fewer bits than the subsequent digital data produced by the fine conversion operation.The analog-to-digital converter can be configured to perform the fine conversion process on the pixel signal based on an output of the coarse conversion process on the pixel signal.

[0068] If desired, the analog-to-digital converter (ADC) can include an amplifier that forms part of the flash ADC in the first mode and part of the delta-sigma ADC in the second mode. The amplifier can be configured to act as a comparator for the flash ADC in the first mode and as an integrator or comparator for the delta-sigma ADC in the second mode. Optionally, the ADC can include a first and a second additional amplifier, which form part of the flash ADC in the first mode and part of the delta-sigma ADC in the second mode.The analog-to-digital converter can include a digital-to-analog converter coupled to the amplifier, a digital filter coupled to the amplifier, and an arithmetic circuit coupled to the digital filter. The digital-to-analog converter can be coupled between an output terminal of the amplifier and an input terminal of the first additional amplifier. An output terminal of the first additional amplifier can be coupled to an input terminal of the second additional amplifier. An output terminal of the second additional amplifier can be coupled to an input terminal of the amplifier. The digital filter can be coupled to the output terminal of the amplifier. The arithmetic circuit can be coupled to the output terminal of the digital filter.

[0069] As a second example, an analog-to-digital converter (ADC) can be configured to receive an analog input signal. The ADC can include a delta-sigma circuit, a comparator coupled to the delta-sigma circuit with an output terminal, a digital filter coupled to the comparator's output terminal, and a digital-to-analog converter (DAC) coupled between the comparator's output terminal and the delta-sigma circuit. This DAC is configured to supply high and low reference voltages to the delta-sigma circuit based on a signal at the comparator's output terminal. The DAC can be configured to select the high reference voltage from a range of voltages and to select the low reference voltage from a range of voltages.If desired, the delta-sigma circuit and the comparator can be configured to perform at least part of a first analog-to-digital conversion on the analog input signal. The digital-to-analog converter can be configured to select the high reference voltage from several voltages based on the first analog-to-digital conversion, and the low reference voltage can also be selected from several voltages based on the first analog-to-digital conversion. The digital-to-analog converter can be configured to perform at least part of a second analog-to-digital conversion on the analog input signal using the selected high and low reference voltages.The analog-to-digital converter can include an arithmetic circuit that is coupled to and configured with an output terminal of the digital filter to obtain calibration information from a memory circuit and to selectively scale an output at the output terminal of the digital filter based on the calibration information.

[0070] As a third example, a delta-sigma analog-to-digital converter can be configured to receive an analog input signal. The delta-sigma analog-to-digital converter can include a delta-sigma circuit, a digital-to-analog converter coupled to the delta-sigma circuit, a comparator coupled to the delta-sigma circuit, and a digital filter coupled to the comparator. The delta-sigma circuit can include an amplifier. The amplifier and comparator can be configured to form a section of a flash analog-to-digital converter.

[0071] The flash analog-to-digital converter can be configured to provide a range specification for the analog input signal, where the range corresponds to a range of image light intensities. The delta-sigma analog-to-digital converter can be configured to perform analog-to-digital conversion of the input analog signals based on the specified range. In particular, the digital-to-analog converter can be configured to select high and low reference voltages based on the specified range. The delta-sigma circuit, the comparator, and the digital-to-analog converter can form, at least partially, a delta-sigma modulator. The clock frequency of the delta-sigma modulator can be adjusted based on the specified range. The bias current of an amplifier of the delta-sigma modulator can also be adjusted based on the specified range.

[0072] Those skilled in the art will recognize that the present embodiments can also be implemented in practice without some or all of these specific details. In other cases, already known processes have not been described in detail in order to avoid making the present embodiments unnecessarily opaque.

[0073] The foregoing is merely illustrative, and numerous modifications can be made to the described embodiments. The preceding embodiments can be implemented individually or in any combination.

Claims

[1] Image sensor comprising: an array of image sensor pixels; and pixel readout circuitry coupled to the array of image sensor pixels, the pixel readout circuitry comprising an analog-to-digital converter configured to operate as a flash analog-to-digital converter in a first mode and as a delta-sigma analog-to-digital converter in a second mode. [2] The image sensor of claim 1, wherein the analog-to-digital converter is configured to perform a coarse conversion operation on a pixel signal when operating as a flash analog-to-digital converter, and wherein the analog-to-digital converter is configured to perform a fine conversion operation on the pixel signal when operating as a delta-sigma analog-to-digital converter. [3] The image sensor of claim 2, wherein the coarse conversion process generates first digital data having fewer bits than second digital data generated by the fine conversion process. [4] The image sensor according to claim 2, wherein the analog-to-digital converter is configured to perform the fine conversion process on the pixel signal based on an output of the coarse conversion process on the pixel signal. [5] The image sensor of claim 1, wherein the analog-to-digital converter comprises an amplifier that is part of the flash analog-to-digital converter in the first mode and part of the delta-sigma analog-to-digital converter in the second mode. [6] The image sensor of claim 5, wherein the amplifier is configured to operate as a comparator for the flash analog-to-digital converter in the first mode and is configured to form an integrator for the delta-sigma analog-to-digital converter in the second mode. [7] The image sensor of claim 5, wherein the amplifier is configured to operate as a comparator for the flash analog-to-digital converter in the first mode and is configured to operate as a comparator for the delta-sigma analog-to-digital converter in the second mode. [8] The image sensor of claim 7, wherein the analog-to-digital converter comprises first and second additional amplifiers that are part of the flash analog-to-digital converter in the first mode and part of the delta-sigma analog-to-digital converter in the second mode. [9] The image sensor of claim 8, wherein the analog-to-digital converter comprises a digital-to-analog converter coupled to the amplifier, a digital filter coupled to the amplifier, and an arithmetic circuit coupled to the digital filter. [10] The image sensor of claim 9, wherein the digital-to-analog converter is coupled between an output terminal of the amplifier and an input terminal of the first additional amplifier, wherein an output terminal of the first additional amplifier is coupled to an input terminal of the second additional amplifier, wherein an output terminal of the second additional amplifier is coupled to an input terminal of the amplifier, wherein the digital filter is coupled to the output terminal of the amplifier, and wherein the arithmetic circuit is coupled to an output terminal of the digital filter. [11] An analog-to-digital converter configured to receive an analog input signal, the analog-to-digital converter comprising: a delta-sigma circuit; a comparator coupled to the delta-sigma circuit and having an output terminal; a digital filter coupled to the output terminal of the comparator; and a digital-to-analog converter coupled between the output terminal of the comparator and the delta-sigma circuit and configured to supply high and low reference voltages to the delta-sigma circuit based on a signal at the output terminal of the comparator, the digital-to-analog converter being configured to select the high reference voltage from a plurality of voltages and to select the low reference voltage from a plurality of voltages. [12] The analog-to-digital converter of claim 11, wherein the delta-sigma circuit and the comparator are configured to perform at least a portion of a first analog-to-digital conversion for the analog input signal, and wherein the digital-to-analog converter is configured to select the high reference voltage from a plurality of voltages based on the first analog-to-digital conversion and to select the low reference voltage from a plurality of voltages based on the first analog-to-digital conversion. [13] The analog-to-digital converter of claim 12, wherein the digital-to-analog converter is configured to perform at least a portion of a second analog-to-digital conversion for the analog input signal using the selected high and low reference voltages. [14] The analog-to-digital converter of claim 11, further comprising: an arithmetic circuit coupled to an output terminal of the digital filter and configured to selectively scale an output at the output terminal of the digital filter. [15] The analog-to-digital converter of claim 14, wherein the arithmetic circuit is configured to obtain calibration information from a memory circuit and to selectively scale the output at the output terminal of the digital filter based on the calibration information. [16] A delta-sigma analog-to-digital converter configured to receive an analog input signal, the delta-sigma analog-to-digital converter comprising: a delta-sigma circuit; a digital-to-analog converter coupled to the delta-sigma circuit; a comparator coupled to the delta-sigma circuit; and a digital filter coupled to the comparator, wherein the delta-sigma circuit comprises an amplifier, and wherein the amplifier and the comparator are configured to operate as a portion of a flash analog-to-digital converter. [17] The delta-sigma analog-to-digital converter of claim 16, wherein the flash analog-to-digital converter is configured to provide an indication of a range to which the analog input signal belongs, the range being associated with a range of image light intensities. [18] The delta-sigma analog-to-digital converter of claim 17, wherein the delta-sigma analog-to-digital converter is configured to perform analog-to-digital conversion of the analog input signal based on the indication of the range. [19] The delta-sigma analog-to-digital converter of claim 17, wherein the digital-to-analog converter is configured to select high and low reference voltages based on the range indication. [20] The delta-sigma analog-to-digital converter of claim 17, wherein the delta-sigma circuit, the comparator, and the digital-to-analog converter are configured to operate as at least a portion of a delta-sigma modulator, wherein a clock frequency of the delta-sigma modulator is adjusted based on the indication of the range, and wherein a bias current of an amplifier of the delta-sigma modulator is adjusted based on the indication of the range.

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