METHOD AND SWITCHING LOGIC FOR REDUCING THE AMPLIFICATION OF THE HARMONIC CONVERSION OF A MIXER AND THE BASIC AND HARMONIC CONDITIONING OF THE LOCAL OSCILLATOR

Abstract

Mixer switching logic can include a first transistor pair coupled to a first end node and configured to receive a local oscillator signal, a second transistor pair coupled to a second end node and configured to receive the local oscillator signal, a first digital-to-analog converter (DAC), a second DAC coupled between the first DAC and the first transistor pair, and a third DAC coupled between the first DAC and the second transistor pair. During a first phase, control switching logic can traverse the first DAC to match a first and / or another odd-order local oscillator pass. During a second phase, the control switching logic can traverse the second DAC to match a second and / or another even-order local oscillator pass.During a third phase, the control switching logic can traverse the second and third DACs to reject signals associated with a second harmonic conversion amplification of the mixer switching logic.

Description

[0001] This application claims priority to U.S. Patent Application No. 18 / 336,786, filed June 16, 2023, which is hereby incorporated by reference in its entirety. AREA

[0002] This disclosure relates generally to electronic devices, and more particularly to electronic devices having circuitry for wireless communication. STATE OF THE ART

[0003] Electronic devices are often provided with wireless communication capabilities. An electronic device with wireless communication capabilities includes wireless communication circuitry with one or more antennas used to transmit and receive radio-frequency signals.

[0004] The wireless communication circuitry may include a transceiver with one or more mixers. A mixer in the transmit path may be used to modulate signals from a baseband frequency to a radio frequency, while a mixer in the receive path may be used to demodulate signals from the radio frequency to the baseband frequency. Mixers receive clock signals generated by local oscillator circuitry. Designing satisfactory mixers and local oscillator circuitry for an electronic device can be challenging. SUMMARY

[0005] An electronic device may include wireless switching logic. The wireless switching logic may include one or more mixers that receive an oscillating signal. An oscillator may generate the oscillating signal, and oscillator driver logic may be used to transmit the oscillating signal to one or more mixers.

[0006] One aspect of the disclosure provides mixer circuitry including a first mixer transistor configured to receive a first oscillating signal and coupled to a first end node, a second mixer transistor configured to receive a second oscillating signal and coupled to the first end node, a first digital-to-analog converter (DAC), and a second digital-to-analog converter (DAC) coupled between the first DAC and the first mixer transistor. The second DAC may include a first output coupled to a gate terminal of the first mixer transistor and a second output coupled to a gate terminal of the second mixer transistor.The mixer circuitry may further include a third mixer transistor configured to receive the first oscillating signal and coupled to a second end node, a fourth mixer transistor configured to receive the second oscillating signal and coupled to the second end node, and a third digital-to-analog converter (DAC) coupled between the first DAC and the third mixer transistor. The first DAC may include a first output coupled to the second DAC and a second output coupled to the third DAC. The third DAC may include a first output coupled to a gate terminal of the third mixer transistor and a second output coupled to a gate terminal of the fourth mixer transistor.The mixer circuitry may further include control circuitry configured to adjust the first DAC during a first calibration phase, adjust the second DAC during a second calibration phase following the first calibration phase, and adjust the second and third DACs during a third calibration phase following the second calibration phase.

[0007] One aspect of the disclosure provides mixer circuitry including a first transistor pair coupled to a first end node and having first gate terminals configured to receive a local oscillator signal, a second transistor pair coupled to a second end node and having second gate terminals configured to receive the local oscillator signal, a first digital-to-analog converter (DAC), a second digital-to-analog converter (DAC) coupled between the first DAC and the first gate terminals of the first transistor pair, and a third digital-to-analog converter (DAC) coupled between the first DAC and the second gate terminals of the second transistor pair.The mixer circuitry may include control circuitry configured to adjust a direct current (DC) mismatch between the first end node and the second end node by adjusting the first DAC, adjust an impedance at the first end node by adjusting the second DAC, and adjust a DC level of the local oscillator signal by adjusting the second DAC together with the third DAC.

[0008] One aspect of the disclosure provides a method of operating mixer circuitry, including receiving a first oscillating signal at a gate terminal of a first mixer transistor, receiving a second oscillating signal at a gate terminal of a second mixer transistor, the first and second mixer transistors being coupled to a first end node, and using a second digital-to-analog converter (DAC) to receive a bias voltage from a first digital-to-analog converter (DAC), output a first bias voltage to the gate terminal of the first mixer transistor, and output a second bias voltage to the gate terminal of the second mixer transistor.The method may further include receiving the first oscillating signal at a gate terminal of a third mixer transistor, receiving the second oscillating signal at a gate terminal of a fourth mixer transistor, the third and fourth mixer transistors being coupled to a second end node, and using a third digital-to-analog converter (DAC) to receive a further bias voltage from the first digital-to-analog converter (DAC), output a third bias voltage to the gate terminal of the third mixer transistor, and output a fourth bias voltage to the gate terminal of the fourth mixer transistor.

[0009] The method may further include adjusting an offset of the first DAC during a first phase, adjusting an offset of the second DAC with respect to an offset of the third DAC during a second phase, and adjusting the offset of the second DAC together with the offset of the third DAC during a third phase. During the first phase, a DC mismatch between the first and second end nodes may be adjusted. During the second phase, the impedance at the first node may be adjusted relative to the impedance at the second end node. During the third phase, the DC level of the first oscillating signal may be adjusted relative to the DC level of the second oscillating signal. During the first phase, the first DAC may be passed through to adjust a first-order LO passthrough.During the second phase, the second DAC can be passed through to adjust a second-order LO passthrough. During the third phase, the second and third DACs can be passed through to reject signals associated with the second harmonic conversion gain of the mixer circuitry. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram of an illustrative electronic device with wireless circuitry according to some embodiments. Fig. 2 is a diagram of illustrative wireless circuitry including transceiver circuitry according to some embodiments. Fig. 3A is a diagram of an illustrative mixer in a receive path according to some embodiments. Fig. 3B is a diagram illustrating how a radio frequency blocker may downconvert to an intermediate frequency of interest through a second harmonic conversion gain of a receive mixer, according to some embodiments. Fig. 4A is a diagram of an illustrative mixer in a receive path according to some embodiments. Fig. 4B is a diagram illustrating, according to some embodiments, how a blocker signal at an intermediate frequency may be upconverted to a high frequency range of interest by the second harmonic conversion gain of a transmit mixer caused by a second harmonic component of the local oscillator circuitry feeding the transmit mixer. Fig. 5 is a diagram of illustrative mixer circuitry including a harmonic balancing circuit and a power reuse input transformer, according to some embodiments. Fig. 6 is a diagram of illustrative mixer circuitry including a harmonic trimming circuit and an active input transformer, according to some embodiments. Fig. 7 is a diagram of illustrative mixer circuitry including a harmonic balance circuit and a passive input, according to some embodiments. Fig. 8 is a circuit diagram illustrating an implementation of a differential bias digital-to-analog converter (DAC) according to some embodiments. Fig. 9 is a circuit diagram illustrating another implementation of a differential bias digital-to-analog converter (DAC) according to some embodiments. Fig. 10 is a flowchart illustrating steps for operating mixer circuitry of the Fig. 5 to 7 according to some embodiments. Fig. 11 is a diagram of illustrative mixer circuitry including a harmonic balance circuit with four single-ended bias DACs, according to some embodiments. Fig. 12 is a flowchart illustrating steps for operating mixer circuitry of the Fig. 11 according to some embodiments. DETAILED DESCRIPTION

[0010] An electronic device, such as the electronic device 10 of Fig. 1, can be provided with wireless circuitry. The wireless circuitry may include one or more mixers, such as a mixer in the transmit path for upconverting (modulating) signals from lower frequencies to higher frequencies and a mixer in the receive path for downconverting (demodulating) signals from higher frequencies to lower frequencies. A mixer may receive an oscillating (clock) signal from local oscillator circuitry. The local oscillator (LO) circuitry may have nonlinearities that generate a second harmonic component. The second harmonic component of the LO circuitry may mix with a block signal to interfere with the in-band signals of interest at the mixer's output. This effect is sometimes collectively referred to as the mixer's second harmonic conversion gain.

[0011] A mixer may include four mixer transistors configured to receive LO signals. The first and second mixer transistors may have gates configured to receive a positive local oscillator signal LO+. The third and fourth mixer transistors may have gates configured to receive a negative local oscillator signal LO-. The four mixer transistors may have gates coupled to a group of at least three differential bias DACs such as DAC1, DAC2, and DAC3. DAC1 may have a first (+) output coupled to an input of DAC2 and a second (-) output coupled to an input of DAC3. DAC2 may have a first (+) output coupled to the gate of the first mixer transistor and a second (-) output coupled to the gate of the third mixer transistor.DAC3 may have a first (+) output coupled to the gate of the second mixer transistor and a second (-) output coupled to the gate of the fourth mixer transistor.

[0012] The three DACs can be calibrated to reduce unwanted noise emissions from the mixer circuitry. The calibrating procedures can include: (1) Calibrating an offset of DAC1 to adjust for a DC mismatch between a first end node at the source terminals of the first and third mixer transistors and a second end node at the source terminals of the second and fourth mixer transistors; (2) Calibrating an offset of DAC2 with respect to the offset of DAC3 to adjust an impedance at the first end node relative to the impedance at the second end node at the fundamental and / or LO harmonic frequencies; and (3) Calibrating an offset of DAC2 together with DAC3 to differentially adjust LO+ relative to LO-. Operating the mixer circuitry in this manner may be technically advantageous and useful due to at least the following results. Step (1) minimizes first-order LO conduction. Step (2) minimizes second-order LO conduction.Step (3) minimizes a (2LO-IF) blocker generated as a result of the mixer's second harmonic conversion gain. In other words, unwanted in-band interference or spectral emissions can be suppressed.

[0013] The electronic device 10 of Fig. 1 may include a computing device such as a laptop computer, a desktop computer, a computer monitor containing an embedded computer, a tablet computer, a mobile phone, a media player, or other handheld or portable electronic device, a smaller device such as a wristwatch device, a pendant device, a headphone or earphone device, a device embedded in eyeglasses or other equipment worn on a user's head, or other wearable or miniature device, a television, a computer display not containing an embedded computer, a gaming device, a navigation device, an embedded system such as a system in which electronic equipment with a display is mounted in a kiosk system or automobile, a voice-activated speaker wirelessly connected to the Internet,a home entertainment device, a remote control device, a gaming controller, a peripheral user input device, a wireless base station or access point, equipment that implements the functionality of two or more of these devices, or other electronic equipment.

[0014] As shown in the functional block diagram of Fig. 1, a device 10 may include components located on or within a housing of an electronic device, such as a case 12. The case 12, which may sometimes be referred to as an enclosure, may be formed from plastic, glass, ceramic, fiber composites, metal (e.g., stainless steel, aluminum, metal alloys, etc.), other suitable materials, or a combination of these materials. In some embodiments, parts or all of the case 12 may be formed from dielectric or other low-conductivity material (e.g., glass, ceramic, plastic, sapphire, etc.). In other embodiments, the case 12, or at least some of the structures comprising the case 12, may be formed from metal elements.

[0015] Device 10 may include control circuitry 14. Control circuitry 14 may include storage elements, such as storage circuitry 16. Storage circuitry 16 may include hard disk drive storage, non-volatile memory (e.g., flash memory or other electrically programmable read-only memory configured to form a solid-state drive), volatile memory (e.g., static or dynamic random access memory), etc. Storage circuitry 16 may include data storage integrated with device 10 and / or removable storage media.

[0016] Control circuitry 14 may include processing circuitry, such as processing circuitry 18. Processing circuitry 18 may be used to control the operation of device 10. Processing circuitry 18 may include one or more microprocessors, microcontrollers, digital signal processors, host processors, baseband processor integrated circuits, application-specific integrated circuits, central processing units (CPUs), etc. Control circuitry 14 may be configured to perform operations in device 10 using hardware (e.g., dedicated hardware or circuitry), firmware, and / or software. Software code for performing operations in device 10 may be stored on storage circuitry 16 (e.g., storage circuitry 16 may include non-transitory (tangible) computer-readable storage media storing the software code).The software code may sometimes be referred to as program instructions, software, data, instructions, or code. Software code stored on storage circuitry 16 may be executed by processing circuitry 18.

[0017] The control circuitry 14 can be used to execute software on the device 10, such as satellite navigation applications, internet browsing applications, Voice over Internet Protocol (VOIP) phone call applications, email applications, media playback applications, operating system functions, etc. To support interactions with external devices, the control circuitry 14 can be used in implementing communication protocols. Communication protocols that can be implemented using the control circuitry 14 include internet protocols, wireless local area network (WLAN) protocols (e.g., IEEE 802.11 protocols—sometimes referred to as Wi-Fi®), protocols for other short-range wireless communication links such as the Bluetooth® protocol or other wireless personal area network (WPAN) protocols, IEEE 802.11ad protocols (e.g., ultra-wideband protocols), cellular phone protocols (e.g.,3G protocols, 4G protocols (LTE protocols), 5G protocols, etc.), antenna diversity protocols, satellite navigation system protocols (e.g., Global Positioning System (GPS) protocols, Global Navigation Satellite System (GLONASS) protocols, etc.), antenna-based spatial ranging protocols (e.g., Radio Detection and Ranging (RADAR) protocols or other desired ranging protocols for signals transmitted at millimeter and centimeter wave frequencies), or any other desired communication protocols. Each communication protocol can be associated with a corresponding Radio Access Technology (RAT), which specifies a physical connection methodology used in implementing the protocol.

[0018] Device 10 may include input / output circuitry 20. Input / output circuitry 20 may include input / output devices 22. Input / output devices 22 may be used to provide data to device 10 and to provide data from device 10 to devices external to device 10. Input / output devices 22 may include user interface devices, data port devices, and other input / output components. For example, input / output devices 22 may include touch sensors, displays (e.g., touch-sensitive and / or force-sensitive displays), light-emitting components, such as displays without touch-sensing capabilities, buttons (mechanical, capacitive, optical, etc.).), scroll wheels, touchpads, keypads, keyboards, microphones, cameras, buttons, speakers, status indicators, audio jacks and other audio port components, digital data port devices, motion sensors (accelerometers, gyroscopes, and / or compasses that detect motion), capacitance sensors, proximity sensors, magnetic sensors, force sensors (e.g., force sensors coupled to a display to detect pressure applied to the display), etc. In some configurations, keyboards, headphones, displays, pointing devices such as trackpads, mice, and joysticks, and other input / output devices may be coupled to device 10 using wired or wireless connections (e.g., some of input / output devices 22 may be peripherals coupled to a main processing unit or another portion of device 10 via a wired or wireless connection).

[0019] Input / output circuitry 20 may include wireless circuitry 24 for supporting wireless communications. Wireless circuitry 24 (sometimes referred to herein as wireless communications circuitry 24) may include one or more antennas. Wireless circuitry 24 may also include baseband processor circuitry, transceiver circuitry, amplifier circuitry, filter circuitry, switching circuitry, radio frequency transmission lines, and / or other circuitry for transmitting and / or receiving radio frequency signals using the antenna(s).

[0020] The wireless circuitry 24 may transmit and / or receive radio frequency signals within a corresponding frequency band at radio frequencies (sometimes referred to herein as a communications band or simply a “band”). The frequency bands processed by the wireless circuitry 24 may be wireless local area network (WLAN) frequency bands (e.g., Wi-Fi® (IEEE 802.11) or other WLAN communication bands), such as a 2.4 GHz WLAN band (e.g., from 2400 to 2480 MHz), a 5 GHz WLAN band (e.g., from 5180 to 5825 MHz), a Wi-Fi® 6E band (e.g., from 5925-7125 MHz), and / or other Wi-Fi® bands (e.g., from 1875-5160 MHz), wireless personal area network (WPAN) frequency bands, such as the 2.4 GHz Bluetooth® band or other WPAN communication bands, cellular phone frequency bands (e.g.,Bands from about 600 MHz to about 5 GHz, 3G bands, 4G LTE bands, 5G New Radio-Frequency Range 1 bands (5G New Radio-FR1 bands) below 10 GHz, 5G New Radio-Frequency Range 2 bands (5G New Radio-FR2 bands) between 20 and 60 GHz, etc.), other centimeter or millimeter wave frequency bands between 10-300 GHz, near-field communication frequency bands (e.g., at 13.56 MHz), satellite navigation frequency bands (e.g., a GPS band from 1565 to 1610 MHz, a Global Navigation Satellite System (GLONASS) band, a BeiDou Navigation Satellite System (BDS) band, etc.), ultra-wideband (UWB) frequency bands registered under the IEEE 802.15.4 protocol and / or other ultra-wideband communication protocols, communication bands under the 3GPP family of wireless communication standards, communication bands under the IEEE 802.XX family of standards, and / or any other desired frequency bands of interest.

[0021] Fig. 2 is a diagram showing illustrative components within the wireless circuit logic 24. As shown in Fig. 2, the wireless circuitry 24 may include a processor, such as processor 26, radio frequency (RF) transceiver circuitry, such as radio frequency transceiver 28, radio frequency front-end circuitry, such as radio frequency front-end module (FEM) 40, and antenna(s) 42. The processor 26 may be one or more processors, such as a baseband processor, an application processor, a digital signal processor, a microcontroller, a microprocessor, a central processing unit (CPU), a programmable device, a combination of these circuits, and / or one or more processors within the circuitry 18. The processor 26 may be configured to generate digital (transmit or baseband) signals. The processor 26 may be coupled to the transceiver 28 via path 34 (sometimes referred to as the baseband path). Transceiver 28 may be coupled to antenna 42 via radio frequency transmission line path 36.The radio frequency front-end module 40 can be inserted into the radio frequency transmission line 36 between the transceiver 28 and the antenna 42.

[0022] The wireless circuitry 24 may include one or more antennas, such as antenna 42. The antenna 42 may be formed using any desired antenna structure. For example, the antenna 42 may be an antenna with a resonant element formed from loop antenna structures, patch antenna structures, inverted-F antenna structures, slot antenna structures, planar inverted-F antenna structures, helical antenna structures, monopole antennas, dipoles, hybrids of these designs, etc. Two or more antennas 42 may be arranged in one or more phased antenna arrays (e.g., for transmitting radio-frequency signals at millimeter wave frequencies). Parasitic elements may be included in the antenna 42 to adjust the antenna performance. The antenna 42 may be provided with a conductive cavity that supports the antenna resonating element of the antenna 42 (e.g.the antenna 42 may be a cavity-based antenna, such as a cavity-based slot antenna).

[0023] In the example of Fig. 2, the wireless circuitry 24 is illustrated for clarity as including only a single processor 26, a single transceiver 28, a single front-end module 40, and a single antenna 42. In general, the wireless circuitry 24 may include any number of processors 26, any number of transceivers 28, any number of front-end modules 40, and any number of antennas 42. Each processor 26 may be coupled to one or more transceivers 28 via respective paths 34. Each transceiver 28 may include transmit circuitry configured to output uplink signals to antenna 42, may include receiver circuitry configured to receive downlink signals from antenna 42, and may be coupled to one or more antennas 42 via respective radio frequency transmission line paths 36.Each radio-frequency transmission line path 36 may have a respective front-end module 40 disposed thereon. If desired, two or more front-end modules 40 may be disposed on the same radio-frequency transmission line path 36. If desired, one or more of the radio-frequency transmission line paths 36 may be implemented in wireless circuitry 24 without an intervening front-end module.

[0024] Front-end module (FEM) 40 may include radio frequency front-end circuitry that operates on the radio frequency signals transmitted (sent and / or received) over the radio frequency transmission line path 36. The front-end module may, for example, include front-end module (FEM) components such as high-frequency filter circuits 44 (e.g., low-pass filters, high-pass filters, notch filters, band-pass filters, multiplexer circuits, duplexer circuits, diplexer circuits, triplexer circuits, etc.), switching logic 46 (e.g., one or more high-frequency switches), high-frequency amplifier circuits 48 (e.g., one or more power amplifiers and one or more low-noise amplifiers), impedance matching circuits (e.g., switching logic that helps match the impedance of the antenna 42 to the impedance of the high-frequency transmission line 36), antenna tuning circuits (e.g.,Networks of capacitors, resistors, inductors, and / or switches that adjust the frequency response of antenna 42), radio-frequency coupler circuits, charge pump circuits, power supply circuits, digital control and interface circuits, and / or any other desired circuitry that affects the radio-frequency signals transmitted and / or received by antenna 42. Each of the front-end module components can be mounted on a common (shared) substrate, such as a rigid printed circuit board substrate or a flexible printed circuit board substrate. If desired, the various front-end module components can also be integrated into a single integrated circuit chip.

[0025] Filter circuits 44, switching logic 46, amplifier circuits 48, and other circuits may be integrated into the radio frequency transmission line 36, the FEM 40, and / or the antenna 42 (e.g., to support antenna tuning, to support operation in desired frequency bands, etc.). These components, sometimes referred to herein as antenna tuning components, can be adjusted (e.g., using the control circuitry 14) to adapt the frequency response and wireless performance of the antenna 42 over time.

[0026] The radio frequency transmission line path 36 may be coupled to an antenna feed at the antenna 42. The antenna feed may include, for example, a positive antenna feed terminal and a ground antenna feed terminal.

[0027] The radio-frequency transmission line path 36 may include a positive transmission line signal path coupled to the positive antenna feed terminal on the antenna 42. The radio-frequency transmission line path 36 may include a ground transmission line signal path coupled to the ground antenna feed terminal on the antenna 42. This example is illustrative, and in general, the antennas 42 may be fed using any desired antenna feeding scheme. If desired, the antenna 42 may include multiple antenna feeds coupled to one or more radio-frequency transmission line paths 36.

[0028] The radio frequency transmission line path 36 may include transmission lines used to relay radio frequency antenna signals within the device 10 ( Fig. 1). Transmission lines in device 10 may include coaxial cables, microstrip transmission lines, stripline transmission lines, edge-coupled microstrip transmission lines, edge-coupled stripline transmission lines, transmission lines formed from combinations of transmission lines of these types, etc. Transmission lines in device 10, such as transmission lines in radio-frequency transmission line path 36, may be integrated into rigid and / or flexible printed circuit boards. In a suitable arrangement, radio-frequency transmission line paths such as radio-frequency transmission line path 36 may also include transmission line conductors integrated into multi-layer laminated structures (e.g., layers of a conductive material such as copper and a dielectric material such as a resin laminated together without intervening adhesive).The multilayer laminated structures may optionally be folded or bent in multiple dimensions (e.g., two or three dimensions) and may retain a bent or folded shape after bending (e.g., the multilayer laminated structures may be folded into a specific three-dimensional shape to guide them around other components of the device and may be rigid enough to retain their shape after folding without being held in place by stiffeners or other structures). All of the multiple layers of the laminated structures may be laminated together in stacks (e.g., in a single pressing process) without adhesive (e.g., as opposed to performing multiple pressing processes to laminate multiple layers together with adhesive).

[0029] The transceiver circuitry 28 may include transceiver circuitry for wireless local area networks that process WLAN communication bands (e.g., Wi-Fi® (IEEE 802.11) or other WLAN communication bands) such as a 2.4 GHz WLAN band (e.g., from 2400 to 2480 MHz), a 5 GHz WLAN band (e.g., from 5180 to 5825 MHz), a Wi-Fi® 6E band (e.g., from 5925-7125 MHz), and / or other Wi-Fi® bands (e.g., from 1875-5160 MHz), transceiver circuitry for wireless personal networks that process the 2.4 GHz Bluetooth® band or other WPAN communication bands, cellular phone transceiver circuitry that process cellular bands (e.g., bands of about 600 MHz to about 5 GHz, 3G bands, 4G LTE bands, bands in the 5G New Radio Frequency Range 1 (FR1) below 10 GHz, bands in the 5G New Radio Frequency Range 2 (FR2) between 20 and 60 GHz, etc.), transceiver circuitry for near-field communication (NFC) that uses near-field communication bands (e.g.at 13.56 MHz), satellite navigation receiver circuitry that processes satellite navigation bands (e.g., a GPS band from 1565 to 1610 MHz, a Global Navigation Satellite System (GLONASS) band, a BeiDou Navigation Satellite System band, etc.), ultra-wideband (UWB) transceiver circuitry that processes communications using the IEEE 802.15.4 protocol and / or other ultra-wideband communication protocols, and / or any other desired radio frequency transceiver circuitry for covering any other desired communication bands of interest.

[0030] When performing a wireless transmission, processor 26 may provide digital signals to transceiver 28 via path 34. Transceiver 28 may further include circuitry for converting the baseband signals received by processor 26 into corresponding intermediate frequency or radio frequency signals. For example, transceiver circuitry 28 may include mixer circuitry 50 for upconverting (or modulating) the baseband signals to intermediate frequencies or radio frequencies prior to transmission via antenna 42. Transceiver circuitry 28 may also include digital-to-analog converter (DAC) and / or analog-to-digital converter (ADC) circuitry for converting signals between digital and analog domains. Transceiver 28 may include a transmit component for transmitting the radio frequency signals via antenna 42, radio frequency transmission line path 36, and front-end module 40.The antenna 42 can transmit the radio frequency signals to external wireless equipment by emitting the radio frequency signals into free space.

[0031] When performing wireless reception, antenna 42 may receive radio-frequency signals from external wireless devices. The received radio-frequency signals may be transmitted to transceiver 28 via radio-frequency transmission line path 36 and front-end module 40. Transceiver 28 may include circuitry for converting the received radio-frequency signals into corresponding intermediate-frequency or baseband signals. For example, transceiver 28 may use mixer circuitry 50 to downconvert (or demodulate) the received radio-frequency signals to baseband frequencies before transmitting the received signals to baseband processor 26 via baseband path 34. Mixer circuitry 50 may include local oscillator circuitry, such as local oscillator (LO) circuitry 52.The local oscillator circuitry 52 may generate oscillator signals that the mixer circuitry 50 uses to modulate transmitted signals from baseband frequencies to radio frequencies and / or to demodulate the received signals from radio frequencies to baseband frequencies.

[0032] Fig. Figure 3A is a diagram of an illustrative mixer in a receive path (RX path) of the wireless circuitry. As shown in Fig. 3A, antenna 42 can transmit received radio frequency signals to mixer 51. The mixer 51 in the receive path (downlink path) can be referred to as a receive mixer. The mixer 51 can comprise one or more receive mixers in the Fig. 2. Mixer 51 may have a first input configured to receive a radio frequency signal from antenna 42, a second input configured to receive an oscillating signal LO, and an output at which a demodulated signal is generated that is downconverted to an intermediate frequency (IF) domain (as an example). One or more components, such as a radio frequency coupler, filter circuitry, antenna fine-tuning element(s), matching network(s), switching logic, amplifier circuitry, other radio frequency front-end components, other transceiver components, and / or other wireless components, may be disposed in the receive path between antenna 42 and mixer 51. Receive mixer 51, which receives a radio frequency signal, may be referred to as a radio frequency mixer.

[0033] Fig. Figure 3B is a diagram illustrating how a second harmonic conversion gain of mixer 51 can produce unwanted in-band emissions at the mixer output if care is not taken. As shown in Fig. 3B, the high-frequency signal received at the first input of the mixer 51 can be adjusted to frequency f RF adjacent channels or an in-band blocker may affect f RFB the LO signal received at the second input of the mixer 51 can be at the frequency f LO and the demodulated signal generated at the output of the mixer 51 can be set to intermediate frequency f IF In practice, the local oscillator circuitry feeding the second input of the mixer 51 may exhibit non-linear behavior resulting in the generation of a second harmonic component at frequency 2*f LOSuch a second harmonic component can combine with the RF signal of an adjacent channel or an in-band blocker on f RFB mix and a down-converted blocker signal on frequency f B generate, where blocker frequency f B equals 2*f LO minus f RFB (see, for example, arrows 60). This phenomenon is sometimes attributed to the second harmonic conversion gain of mixer 51.

[0034] The placement of the blocker frequency f B can be problematic if the selection of the high frequency f RF and the local oscillator frequency f LO to a corresponding f B which lies within or near the affected intermediate frequency (IF) range. For example, consider a scenario in which frequency f RF 37 GHz, frequency f RFB 38 GHz and frequency f LO 25 GHz. The intermediate frequency fIF is 12 GHz (e.g. f RF - f LO = 37 - 25 = 12 GHz). In this example, the down-converted blocker frequency f B also equal to 12 GHz (e.g. 2* f LO - f RFB = 2*25 - 38 = 12 GHz). In other words, the blocker signal can be reduced to f B the down-converted signal of interest to intermediate frequency f IF at the output of the mixer 51, which can lead to self-decoupling and a deterioration of the overall signal-to-noise ratio of the receive path.

[0035] Fig. Figure 4A is a diagram of an illustrative mixer in a transmit (TX) path of the wireless circuit logic. As shown in Fig. As shown in Figure 4A, mixer 51 can output radio-frequency signals that are ultimately radiated by antenna 42. Mixer 51 in the transmit path (uplink path) can be referred to as a transmit mixer.

[0036] Mixer 51 can control one or more transmit mixers in the Fig. 2. Transmit mixer 51 may have a first input configured to receive a signal in the intermediate frequency (IF) range, a second input configured to receive an oscillating signal LO, and an output at which a modulated signal is generated that is upconverted to a radio frequency (RF) range (as an example). One or more components, such as a radio frequency coupler, filter circuitry, antenna fine-tuning element(s), matching network(s), switching logic, amplifier circuitry, other radio frequency front-end components, other transceiver components, and / or other wireless components, may be disposed in the receive path between transmit mixer 42 and antenna 51. Transmit mixer 51, which outputs a radio frequency signal, may be referred to as a radio frequency mixer.

[0037] Fig. Figure 4B is a diagram illustrating how a second harmonic conversion gain of a transmit mixer 51 can produce unwanted in-band emissions at the mixer output if care is not taken. As shown in Fig. As shown in Figure 4B, the intermediate frequency signal received at the first input of the mixer 51 can be adjusted to frequency f IF the LO signal received at the second input of the mixer 51 can be at the frequency f LO and the modulated signal generated at the output of the mixer 51 can be set to high frequency f RF In practice, the local oscillator circuitry feeding the second input of the transmit mixer 51 may exhibit non-linear behavior, resulting in the generation of a second harmonic component at frequency 2*f LO Such a second harmonic component can interact with an adjacent channel signal or an in-band intermediate frequency blocker on f Bmix and generate an up-converted interference signal 63, which may fall into the high frequency range of interest (see, for example, arrows 62 pointing to frequency f RFB land, where f RFB equals 2*f LO minus f B This phenomenon is sometimes attributed to the second harmonic conversion gain of mixer 51.

[0038] The frequency f RFB of the interference signal 63 can be problematic if the selection of the high frequency f RF and the local oscillator frequency f LO results in the interference signal being within or close to the relevant high frequency (RF) range. Consider, for example, the scenario above, where frequency f RF 37 GHz and frequency f LO 25 GHz. The intermediate frequency f IF is 12 GHz (e.g. f RF - f LO = 37 - 25 = 12 GHz). In this example, an in-band blocker on frequency f Bequal to 13 GHz even with 2*f LO mixed to produce an up-converted interference signal 63 at frequency f RFB also to restore to 37 GHz (e.g. 2*f LO - f B = 2*25 - 13 = 37 GHz). In other words, signal 63 can represent the high-frequency signal of interest at f RF at the output of the transmit mixer 51, which may cause the transmit path to violate the performance criteria.

[0039] According to one embodiment, the mixer circuitry 50 is provided which includes a harmonic balancing circuit configured to reduce the various unwanted noise emissions associated with Fig. 3B and Fig. 4B. Fig. 5 is a circuit diagram of illustrative mixer circuitry 50 including harmonic balancing circuitry such as harmonic balancing circuitry 98. Mixer circuitry 50 may represent a transmit mixer (e.g., a mixer in a transmit path) or a receive mixer (e.g., a mixer in a receive path).

[0040] As in Fig. 5, mixer circuitry 50 may include a first input transistor 80-1 and a second input transistor 80-2 coupled to an input transformer such as transformer 82. Transformer 82 may include a primary coil (winding) Lp and a secondary coil (winding) Ls. Primary coil Lp may have a center tap shorted to the center tap of secondary coil Ls. By connecting the center tap terminals of coils Lp and Ls in this manner, current may be shared or reused between the two coils. Transformer 82 configured in this manner is therefore sometimes referred to as a "current reuse" transformer.

[0041] Input transistors 80-1 and 80-2 may be n-channel devices, such as n-type metal-oxide-semiconductor (NMOS) transistors. Input transistor 80-1 may have a drain terminal coupled to a first terminal of inductor Lp, a source terminal coupled to a ground power supply line 68 (e.g., a ground line on which a ground voltage is provided), and a gate terminal configured to receive the input voltage Vin+. Input transistor 80-2 may have a drain terminal coupled to a second terminal of inductor Lp, a source terminal coupled to ground line 68, and a gate terminal configured to receive the input voltage Vin-. The delta of the voltages Vin+ and Vin- may represent the differential high-frequency input voltage of mixer circuitry 50.The terms "source" and "drain" terminals, used to refer to current-carrying terminals in a transistor, can be used interchangeably and are sometimes referred to as "source-drain" terminals. Thus, the drain terminal of transistor 80-1 may sometimes be referred to as the first source-drain terminal, and the source terminal of transistor 80-1 may be referred to as the second source-drain terminal (or vice versa).

[0042] Transformer 82 may be coupled to mixer subcircuits 53-1 and 53-2. Mixer subcircuit 53-1 may include a first pair of mixer transistors 76-1a and 76-1b (e.g., a first transistor pair). Mixer transistor 76-1a may include a source terminal coupled to secondary coil Ls, a gate terminal configured to receive the LO+ signal, and a drain terminal coupled to a first output terminal o1. Mixer transistor 76-1b may include a source terminal also coupled to secondary coil Ls, a gate terminal configured to receive the LO- signal, and a drain terminal coupled to a second output terminal o2. The source terminals of the mixer transistors 76-1a and 76-1b may be coupled to a first terminal node Tp.Signals LO+ and LO- represent the positive and negative polarities of a differential signal and may collectively be referred to as a local oscillator signal or oscillating signal. The gate terminals of mixer transistors 76-1a and 76-1b together form a differential input terminal for receiving the oscillating signal. Output terminals o1 and o2 together form the differential output terminal OUT of mixer circuitry 50. An output inductor Lout may be coupled across the differential output port of mixer circuitry 50. In particular, output inductor Lout may have a first terminal coupled to output terminal o1, a second terminal coupled to output terminal o2, and a center tap terminal coupled to a positive power supply line 78 (e.g., a positive power supply terminal to which the positive power supply voltage Vdd is provided).

[0043] The mixer subcircuit 53-2 may include a second pair of mixer transistors 76-2a and 76-2b (e.g., a second transistor pair). The mixer transistor 76-2a may have a source terminal coupled to the secondary coil Ls, a gate terminal configured to receive the LO+ signal, and a drain terminal coupled to the second output terminal o2. The mixer transistor 76-2b may have a source terminal also coupled to the secondary coil Ls, a gate terminal configured to receive the LO- signal, and a drain terminal coupled to the first output terminal o1. The source terminals of the mixer transistors 76-2a and 76-2b may be coupled to a second terminal node Tm. The gate terminals of the mixer transistors 76-2a and 76-2b together form a differential input for receiving the oscillating signal.

[0044] To reduce the unwanted noise associated with the operation of the mixer circuitry 50, the four mixer transistors (e.g., transistors 76-1a, 76-1b, 76-2a, and 76-2b) may be configured to receive bias voltages from the harmonic balance circuit 98. The harmonic balance circuit 98 may include a plurality of differential direct current (DC) biased digital-to-analog converters, such as a first DAC 100-1, a second DAC 100-2, and a third DAC 100-3. The first DAC 100-1 may have a first (positive) output coupled to the second DAC 100-2 and may have a second (negative) output coupled to the third DAC 100-3.The second DAC 100-2 may have a first (positive) output coupled to the gate terminal of the mixer transistor 76-1a via resistor 102 and a second (negative) output coupled to the gate terminal of the mixer transistor 76-1b via resistor 104. The third DAC 100-3 may have a first (positive) output coupled to the gate terminal of the mixer transistor 76-2a via resistor 108 and a second (negative) output coupled to the gate terminal of the mixer transistor 76-2b via resistor 106. These three DACs 100-1, 100-2, and 100-3 can be configured (calibrated or trimmed) to provide appropriate bias voltages to the gate terminals of the mixer transistors for optimal LO pass-through reduction and harmonic gain rejection.

[0045] The embodiment of Fig. 5, in which the input portion of the mixer circuitry 50 is implemented using a current reuse transformer 82, is exemplary. Fig. 6 shows another embodiment of the mixer circuitry 50 with an input section implemented using an active transformer 82'. As in Fig. 6, transformer 82' includes a primary coil Lp having a center tap coupled to a power supply line, such as positive power supply line 78. Transformer 82' also includes a secondary coil Ls having a center tap coupled to a power supply line, such as ground line 68. This example, where the center tap of coil Lp is coupled to power supply line 78 and the center tap of coil Ls is coupled to ground line 68, is for illustrative purposes. As another example, the center tap of coil Lp may be coupled to ground line 68, while the center tap of coil Ls may be coupled to power supply line 78. As another example, the center tap of coils Lp and Ls may be coupled to different voltage lines.As another example, the center tap of the coils Lp and Ls can be coupled to the same or different power supply lines.

[0046] The embodiment of Fig. 6, in which the input portion of the mixer circuitry 50 is implemented using an active transformer 82', is exemplary. Fig. Figure 7 shows another embodiment of the mixer circuitry 50 with an input section implemented using passive components. As shown in Fig. 7, the input portion of the mixer circuitry 50 may include passive electrical components, such as passive components 90-1, 90-2, 92-1, and 92-2. Component 90-1 (e.g., a first input coupling capacitor) may have a first terminal configured to receive the input voltage Vin+ and a second terminal coupled to the first end node Tp of the mixer subcircuit 53-1. Component 90-2 (e.g., a second input coupling capacitor) may have a first terminal configured to receive the input voltage Vin- and a second terminal coupled to the second end node Tm of the mixer subcircuit 53-2. Component 92-1 (e.g., a resistor, capacitor, inductor, or other passive load) may be coupled between capacitor 90-1 and ground line 68. Similarly, component 92-2 (e.g.A resistor, capacitor, inductor, or other passive load may be coupled between capacitor 90-2 and ground line 68. The embodiment of . Fig. 7 without active input transistors (see e.g. input transistors 80-1 and 80-2 in Fig. 5 and Fig. 6, sometimes collectively referred to as a transconductance or “Gm” stage) is sometimes referred to as mixer circuit logic 50 with a passive input stage. The embodiments of the Fig. Figures 5 through 7, which show mixer circuitry 50 with various types of input stages, are exemplary. If desired, mixer circuitry 50 can also be implemented in other ways.

[0047] The differential DC bias DACs 100 (e.g. DACS 100-1, 100-2 and 100-3) can be implemented in different ways. Fig. 8 is a circuit diagram showing an implementation of a DAC circuit 100. As in Fig. 8, DAC 100 may include a differential buffer, such as buffer 110, resistors R1 and R2, and current sources I1 and I2. Buffer 110 may have a first (positive) input configured to receive an input bias voltage Vbias_in, a second (negative) input, and an output shorted to the second input via a feedback path 112. The input bias voltage Vbias_in may be fixed (static) or adjustable (tunable). Buffer 110 configured in this manner is sometimes referred to as a "unity gain buffer" and may have a gain of unity. The output of buffer 110 is coupled to node 116. Bias voltage Vbias may be generated at node 116 and may have a voltage level equal to Vbias_in.

[0048] Resistor R1 may have a first terminal coupled to node 116 and a second terminal coupled to node 114. Current source I1 may have a first terminal coupled to the positive power supply line 78 and a second terminal coupled to node 114. Current source I1 may be an adjustable current source (e.g., a current source with an adjustable amount of current, such as a current source DAC). Resistor R2 may have a first terminal coupled to node 116 and a second terminal coupled to node 118. Resistors R1 and R2 may optionally have an adjustable resistance. Current source I2 has a first terminal coupled to node 118 and a second terminal coupled to ground line 68. Current source I2 may be an adjustable current sink (e.g.,a current sink with an adjustable amount of current, such as a current sink DAC). In such a configuration, a first bias voltage equal to (Vbias + I1*R1) can be generated at the first (positive) output node 114, while a second bias voltage equal to (Vbias - I2*R2) can be generated at the second (negative) output node 118. The voltage level at output nodes 114 and 118 can be adjusted by fine-tuning Vbias (e.g., by adjusting the input bias voltage Vbias_in, by adjusting the current I1 or I2, and / or by adjusting the resistance of R1 and R2).

[0049] Fig. 9 is a circuit diagram showing another implementation of a DAC circuit 100. As in Fig. As shown in Figure 9, DAC 100 may include a differential buffer, such as buffer 120, resistors R1 and R2, and current sources I1 and I2. Buffer 120 may have a first (negative) input configured to receive an input bias voltage Vbias_in, a second (positive) input coupled to node 116, and an output for controlling current source I2. The input bias voltage Vbias_in may be fixed (static) or adjustable (tunable). Bias voltage Vbias may be generated at node 116 and may have a voltage level equal to Vbias_in.

[0050] Resistor R1 may have a first terminal coupled to node 116 and a second terminal coupled to node 114. Current source I1 may have a first terminal coupled to the positive power supply line 78 and a second terminal coupled to node 114. Current source I1 may be an adjustable current source (e.g., a current source with an adjustable amount of current, such as a current source DAC). Resistor R2 may have a first terminal coupled to node 116 and a second terminal coupled to node 118. Resistors R1 and R2 may optionally have an adjustable resistance. Current source I2 has a first terminal coupled to node 118 and a second terminal coupled to ground line 68. Current source I2 may be an adjustable current sink (e.g.,a current sink with an adjustable amount of current, such as a current sink DAC). In such a configuration, a first bias voltage equal to (Vbias + I1*R1) may be generated at the first (positive) output node 114, while a second bias voltage equal to (Vbias - I2*R2) may be generated at the second (negative) output node 118. The voltage level at output nodes 114 and 118 may be adjusted by fine-tuning Vbias (e.g., by adjusting the input bias voltage Vbias_in, by adjusting the current I1 or I2, and / or by adjusting the resistance of R1 and R2). The embodiments of . Fig. 8 and Fig. 9 are exemplary. In general, the mixer circuitry may be provided with differential bias DACs having any suitable DAC architecture.

[0051] Fig. 10 is a flowchart illustrating steps for operating mixer circuitry 50 of the Fig. 5 to 7, according to some embodiments. During the operations of block 200, the first DAC 100-1 (sometimes referred to and defined herein as "DAC1") may be passed through to adjust or minimize the DC mismatch between the end nodes Tp and Tm. The DAC1 may be adjusted by adjusting the current sources I1 and I2 (see, e.g., Fig. 8 and Fig. 9) so that the voltages at the two output nodes are adjusted over their tuning range. DAC1 calibrates the DC current flowing into the end nodes Tp and Tm, which is approximately 1:1 related to first- and third-order LO conduction (and generally to other higher-order odd-order LO conduction). Tuning DAC1 in this way can provide a DC offset for DAC1 (referred to and defined below as "OS1") that calibrates or minimizes first-order and other higher-odd-order LO conduction. Block 200 is sometimes referred to as the first calibration phase.

[0052] During the operations in block 202, the second DAC 100-2 (sometimes referred to and defined herein as "DAC2") may be passed through to match the LO impedance at the end node Tp with respect to the impedance at the end node Tm at the LO frequency. The signal at the LO frequency is upconverted to the second harmonic frequency in differential mode by the mixer's fundamental gain, so the DAC2 matching can be used to match the second harmonic passthrough ("2LO"). However, the DAC2 matching does not affect the amount of DC current flowing to the end node Tp and therefore has no effect on the LO passthrough matching of block 202. Thus, the operations of block 202 can be said to be orthogonal, or independent, to the operations of block 200.Adjusting DAC2 in this manner can establish a delta between the DC offset of DAC2 (referred to and defined herein as "OS2") and the DC offset of DAC3 (referred to and defined herein as "OS3"), which calibrates or minimizes 2LO passthrough. Block 202 is sometimes referred to as the second calibration phase.

[0053] During the operations of block 204, DAC2 and the third DAC 100-3 (sometimes referred to and defined herein as "DAC3") may be swept together (i.e., in parallel in the same direction) while maintaining the DC offset delta established by block 202 to shift the DC level of the LO+ signal relative to the DC level of the LO- signal. By sampling DAC2 and DAC3 in parallel, OS2 and the DC offset of DAC3 (hereinafter referred to and defined as "OS3") may be moved in the same direction, which may help minimize IF (intermediate frequency) passthrough and also any blocker signal component at (2LO - IF). However, swept DAC2+DAC3 together does not affect the DC offset delta established during block 204. Thus, it can be said that the operations of block 204 are orthogonal to the operations of block 202.Balancing DAC2 and DAC3 in this manner to minimize the (2LO - IF) blocker signal can therefore be viewed as calibrating or minimizing the mixer's second harmonic conversion gain. DAC1, DAC2, and DAC3 are therefore sometimes collectively referred to as harmonic suppression circuit 98. These various DACs can be controlled using control circuitry 14 (see . Fig. 1), the processing circuitry 18, the logic, or another controller. Block 204 is sometimes referred to as the third calibration phase.

[0054] The events of Fig. 10 are illustrative. In some embodiments, DAC2 may be set equal to DAC3, and the two may be adjusted together to individually adjust the (2LO - IF) component. In other embodiments, DAC3 may be set to zero and DAC2 adjusted alone to minimize the 2LO pass-through component. If desired, the operations of block 202 may be performed before block 200. If desired, the operations of block 204 may be performed before block 202 or before block 200. In some embodiments, one or more of the described operations may be modified, replaced, or omitted. In some embodiments, one or more of the described operations may be performed in parallel. In some embodiments, additional processes may be added or inserted between the described operations.If desired, the order of certain operations can be reversed or changed and / or the timing of the described operations can be adjusted so that they occur at slightly different times.

[0055] The embodiments of Fig. 5 to 7, in which the mixer circuitry 50 is provided with a harmonic suppression circuit 98 including three DACs, are exemplary. Fig. Figure 11 shows another embodiment of the mixer circuitry 50 that includes a harmonic suppression circuit 98 with four single-ended DC bias DACs. As shown in Fig. 11, the harmonic suppression circuit 98 may include a first DAC 101-1 (sometimes referred to herein as "DACa"), a second DAC 101-2 (sometimes referred to herein as "DACb"), a third DAC 101-3 (sometimes referred to herein as "DACc"), and a fourth DAC 101-4 (sometimes referred to herein as "DACd"). The first DACa may have an output coupled to the gate terminal of the mixer transistor 76-1a via resistor 102. The second DACb may have an output coupled to the gate terminal of the mixer transistor 76-1b via resistor 104. The third DACc may have an output coupled to the gate terminal of the mixer transistor 76-2a via resistor 108. The fourth DACd may have an output coupled to the gate terminal of the mixer transistor 76-2b via resistor 106.These four DACs can be configured (adjusted or calibrated) to provide appropriate bias voltages to the gate terminals of the mixer transistors for optimal harmonic gain rejection. The offset associated with DACa can be referred to as "OSa"; the offset associated with DACb can be referred to as "OSb"; the offset associated with DACc can be referred to as "OSc"; and the offset associated with DACd can be referred to as "OSd".

[0056] The mixer switching logic 50 of Fig. 11 includes a power reuse transformer 82. This is exemplary. As another example, the mixer circuitry 50 of Fig. 11 use an active transformer 82' (see, for example, the active input transformer 82' of Fig. 6). As another example, the mixer circuit logic 50 of Fig. 11 use a passive input stage (see e.g. the passive mixer input stage of Fig. 7). In general, a mixer circuit 50 can be used with any type of input stage.

[0057] Fig. 12 is a flowchart illustrating steps for operating the mixer circuit logic 50 of the Fig. 11. During the operations of block 210, DACa and DACb may be swept together (e.g., OSa and OSb may be swept in the same direction) to adjust or minimize the DC mismatches between the end nodes Tp and Tm. By sampling DACa and DACb in parallel while simultaneously fixing DACc and DACd, OSa and OSb may be tuned relative to OSc and OSd to calibrate or minimize first-order and other higher odd-order LO sweeps.

[0058] During the operations in block 212, DACa and DACb may be swept in opposite directions while maintaining the same mean code from block 212 to sample the LO impedance at the end node Tp at the LO frequency. The signal at the LO frequency is upconverted to the second harmonic frequency in differential mode by the mixer's fundamental gain, so that balancing DACa and DACb can be used to balance second harmonic ("2LO") passthrough. By balancing DACa and DACb in opposite directions, the delta of (OSa relative to OSb) and (OSc relative to OSd) can be tuned in this way to calibrate or minimize 2LO passthrough. The operations of block 212 can be said to be orthogonal, or independent, to the operations of block 210.

[0059] During the operations of block 214, DACa and DACc may be swept in a first direction while DACb and DACd may be swept in a second (opposite) direction, maintaining the same offset delta established by block 212 to shift the DC level of the LO+ signal relative to the DC level of the LO- signal. This can help minimize the IF (intermediate frequency) passthrough in a transmit mixer where the input signal is in the IF band, the RF passthrough in a receive mixer where the input signal is in the RF band, and also any blocker signal component at (2LO - IF). The operations of block 214 can be said to be orthogonal to the operations of block 212. Tuning the DACs in this way to minimize the (2LO - IF) blocker signal can therefore be seen as calibrating or minimizing the mixer's second harmonic conversion gain.These various DACs can be controlled using the control logic 14 (see . Fig. 1), the processing circuitry 18, the logic or any other control system.

[0060] The events of Fig. 12 are illustrative. In some embodiments, DAC1 may be set equal to DAC3, while DAC2 may be set equal to DAC4, and these DACs may be balanced to minimize the (2LO - IF) component. In other embodiments, DAC3 may be set equal to DAC4, while DAC1 may be passed in opposite direction to DAC2 to balance the 2LO pass-through component. If desired, the operations of block 212 may be performed before block 210. If desired, the operations of block 214 may be performed before block 212 or before block 210. In some embodiments, one or more of the described operations may be modified, replaced, or omitted. In some embodiments, one or more of the described operations may be performed in parallel. In some embodiments, additional processes may be added or inserted between the described operations.If desired, the order of certain operations can be reversed or changed and / or the timing of the described operations can be adjusted so that they occur at slightly different times.

[0061] The above in connection with Fig. 1 to 12 may be performed by the components of device 10 using software, firmware, and / or hardware (e.g., dedicated circuitry or hardware). Software code for performing these operations may be stored on non-transitory, computer-readable storage media (e.g., tangible computer-readable storage media) embodied on one or more of the components of device 10 (e.g., storage circuitry 16 and / or wireless communication circuitry 24 of Fig. 1). The software code may sometimes be referred to as software, data, instructions, program instructions, or code. The non-transitory computer-readable storage media may include disk drives, non-volatile memory such as non-volatile random access memory (NVRAM), removable flash drives or other removable media, other types of random access memory, etc. The software stored on the non-transitory computer-readable storage media may be executed by the processing circuitry of one or more components of the device 10 (e.g., by the processing circuitry in the wireless circuitry 24, the processing circuitry 18 of Fig. 1, etc.). Circuitry may include microprocessors, application processors, digital signal processors, central processing units (CPUs), application-specific integrated circuits with circuitry, or other circuitry.

[0062] According to one embodiment, mixer circuitry is provided including a first mixer transistor configured to receive a first oscillating signal and coupled to a first end node, a second mixer transistor configured to receive a second oscillating signal and coupled to the first end node, a first digital-to-analog converter (DAC), and a second digital-to-analog converter (DAC) coupled between the first DAC and the first mixer transistor.

[0063] According to another embodiment, the second DAC includes a first output coupled to a gate terminal of the first mixer transistor and a second output coupled to a gate terminal of the second mixer transistor.

[0064] According to another embodiment, the mixer circuitry includes a first resistor coupled between the first output of the second DAC and the gate terminal of the first mixer transistor, and a second resistor coupled between the second output of the second DAC and the gate terminal of the second mixer transistor.

[0065] According to another embodiment, the mixer circuit includes a third mixer transistor configured to receive the first oscillating signal and coupled to a second end node, a fourth mixer transistor configured to receive the second oscillating signal and coupled to the second end node, and a third digital-to-analog converter (DAC) coupled between the first DAC and the third mixer transistor.

[0066] According to another embodiment, the first DAC includes a first output coupled to the second DAC and a second output coupled to the third DAC.

[0067] According to another embodiment, the third DAC includes a first output coupled to a gate terminal of the third mixer transistor and a second output coupled to a gate terminal of the fourth mixer transistor.

[0068] According to another embodiment, the mixer circuitry includes a first resistor coupled between the first output of the third DAC and the gate terminal of the third mixer transistor, and a second resistor coupled between the second output of the third DAC and the gate terminal of the fourth mixer transistor.

[0069] According to another embodiment, the mixer circuitry includes a transformer coupled to the first and second end nodes.

[0070] According to another embodiment, the first mixer transistor has a drain terminal coupled to a first mixer output, the second mixer transistor has a drain terminal coupled to a second mixer output, the third mixer transistor has a drain terminal coupled to the first mixer output, and the fourth mixer transistor has a drain terminal coupled to the second mixer output.

[0071] According to another embodiment, the mixer circuitry includes control circuitry configured to adjust the first DAC during a first calibration phase, adjust the second DAC during a second calibration phase following the first calibration phase, and adjust the second and third DACs during a third calibration phase following the second calibration phase.

[0072] According to one embodiment, mixer circuitry is provided including a first transistor pair coupled to a first end node and having first gate terminals configured to receive a local oscillator signal, a second transistor pair coupled to a second end node and having second gate terminals configured to receive the local oscillator signal, a first digital-to-analog converter (DAC), a second digital-to-analog converter (DAC) coupled between the first DAC and the first gate terminals of the first transistor pair, and a third digital-to-analog converter (DAC) coupled between the first DAC and the second gate terminals of the second transistor pair.

[0073] According to another embodiment, the mixer circuitry includes an inductor having a first terminal coupled to the first end node and a second terminal coupled to the second end node.

[0074] According to another embodiment, the first DAC includes a first output coupled to the second DAC and a second output coupled to the third DAC.

[0075] According to another embodiment, the mixer circuitry includes control circuitry configured to adjust the first DAC during a first calibration phase, adjust the second DAC during a second calibration phase following the first calibration phase, and adjust the second and third DACs during a third calibration phase following the second calibration phase.

[0076] According to another embodiment, the mixer circuitry includes control circuitry configured to adjust a direct current (DC) mismatch between the first end node and the second end node by adjusting the first DAC, adjust an impedance at the first end node by adjusting the second DAC, and adjust a DC level of the local oscillator signal by adjusting the second DAC together with the third DAC.

[0077] According to one embodiment, a method of operating mixer circuitry is provided, including receiving a first oscillating signal at a gate terminal of a first mixer transistor, receiving a second oscillating signal at a gate terminal of a second mixer transistor, the first and second mixer transistors being coupled to a first end node and to a second digital-to-analog converter (DAC), receiving a bias voltage from a first digital-to-analog converter (DAC), outputting a first bias voltage to the gate terminal of the first mixer transistor, and outputting a second bias voltage to the gate terminal of the second mixer transistor.

[0078] According to another embodiment, the method includes receiving the first oscillating signal at a gate terminal of a third mixer transistor, receiving the second oscillating signal at a gate terminal of a fourth mixer transistor, the third and fourth mixer transistors being coupled to a second end node, and to a third digital-to-analog converter (DAC), receiving a further bias voltage from the first digital-to-analog converter (DAC), outputting a third bias voltage to the gate terminal of the third mixer transistor, and outputting a fourth bias voltage to the gate terminal of the fourth mixer transistor.

[0079] According to another embodiment, the method includes, during a first phase, adjusting an offset of the first DAC, during a second phase different from the first phase, adjusting an offset of the second DAC relative to an offset of the third DAC, and during a third phase different from the second phase, adjusting the offset of the second DAC together with the offset of the third DAC.

[0080] According to another embodiment, the method includes, during a first phase, adjusting a direct current (DC) mismatch between the first end node and the second end node, during a second phase different from the first phase, adjusting an impedance at the first end node relative to an impedance at the second end node, and during a third phase different from the second phase, adjusting a DC level of the first oscillating signal relative to a DC level of the second oscillating signal.

[0081] According to another embodiment, the method includes, during a first phase, sampling the first DAC to adjust a first-order local oscillator passthrough, during a second phase different from the first phase, sampling the second DAC to adjust a second-order local oscillator passthrough, and during a third phase different from the second phase, sampling the second and third DACs to reject signals associated with a second harmonic gain of the mixer circuitry.

[0082] The foregoing is illustrative, and various modifications may be made to the described embodiments. The foregoing embodiments may be implemented individually or in any combination. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 18 / 336,786

[0001]

Claims

[1] Mixer switching logic, comprising: a first mixer transistor configured to receive a first oscillating signal and coupled to a first end node; a second mixer transistor configured to receive a second oscillating signal and coupled to the first end node; a first digital-to-analog converter (DAC); and a second digital-to-analog converter (DAC) coupled between the first DAC and the first mixer transistor. [2] The mixer circuitry of claim 1, wherein the second DAC comprises: a first output coupled to a gate terminal of the first mixer transistor; and a second output coupled to a gate terminal of the second mixer transistor. [3] Mixer circuit logic according to claim 2, further comprising: a first resistor coupled between the first output of the second DAC and the gate terminal of the first mixer transistor; and a second resistor coupled between the second output of the second DAC and the gate terminal of the second mixer transistor. [4] Mixer circuit logic according to claim 1, further comprising: a third mixer transistor configured to receive the first oscillating signal and coupled to a second end node; a fourth mixer transistor configured to receive the second oscillating signal and coupled to the second end node; and a third digital-to-analog converter (DAC) coupled between the first DAC and the third mixer transistor. [5] Mixer circuitry according to claim 4, wherein the oscillator comprises: a first output coupled to the second DAC; and a second output coupled to the third DAC. [6] Mixer circuitry according to claim 4, wherein the third DAC comprises: a first output coupled to a gate terminal of the third mixer transistor; and a second output coupled to a gate terminal of the fourth mixer transistor. [7] Mixer circuit logic according to claim 6, further comprising: a first resistor coupled between the first output of the third DAC and the gate terminal of the third mixer transistor; and a second resistor coupled between the second output of the third DAC and the gate terminal of the fourth mixer transistor. [8] Mixer circuit logic according to claim 4, further comprising: a transformer coupled to the first and second end nodes. [9] Mixer circuit logic according to claim 4, wherein: the first mixer transistor has a drain terminal coupled to a first mixer output; the second mixer transistor has a drain terminal coupled to a second mixer output; the third mixer transistor has a drain terminal coupled to the first mixer output; and the fourth mixer transistor has a drain terminal coupled to the second mixer output. [10] The mixer circuitry of claim 4, further comprising control circuitry configured to: Adjusting the first DAC during an initial calibration phase; Adjusting the second DAC during a second calibration phase following the first calibration phase; and Aligning the second and third DACs during a third calibration phase following the second calibration phase. [11] A method of operating a mixer circuit logic, comprising: Receiving a first oscillating signal at a gate terminal of a first mixer transistor; Receiving a second oscillating signal at a gate terminal of a second mixer transistor, wherein the first and second mixer transistors are coupled to a first end node; and with a second digital-to-analog converter (DAC) receiving a bias voltage from a first digital-to-analog converter (DAC), outputting a first bias voltage to the gate terminal of the first mixer transistor, and outputs a second bias voltage to the gate terminal of the second mixer transistor. [12] The method of claim 11, further comprising: Receiving the first oscillating signal at a gate terminal of a third mixer transistor; Receiving the second oscillating signal at a gate terminal of a fourth mixer transistor, wherein the third and fourth mixer transistors are coupled to a second end node; and with a third digital-to-analog converter (DAC) receiving a further bias voltage from the first digital-to-analog converter (DAC), outputting a third bias voltage to the gate terminal of the third mixer transistor, and outputting a fourth bias voltage to the gate terminal of the fourth mixer transistor. [13] The method of claim 12, further comprising: during a first phase, adjusting an offset of the first DAC; during a second phase different from the first phase, adjusting an offset of the second DAC relative to an offset of the third DAC; and during a third phase different from the second phase, adjusting the offset of the second DAC together with the offset of the third DAC. [14] The method of claim 12, further comprising: during a first phase, adjusting a direct current (DC) mismatch between the first end node and the second end node; during a second phase different from the first phase, adjusting an impedance at the first end node relative to an impedance at the second end node; and during a third phase different from the second phase, adjusting a DC level of the first oscillating signal relative to a DC level of the second oscillating signal. [15] The method of claim 12, further comprising: during a first phase, sampling the first DAC to adjust a first-order local oscillator pass-through; during a second phase different from the first phase, sampling the second DAC to adjust a second second-order local oscillator pass-through; and during a third phase different from the second phase, sampling the second and third DACs to reject signals associated with a second harmonic gain of the mixer circuitry.

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