V-GROOVE-FABRICATION

Abstract

A device comprising a silicon substrate and a waveguide on the silicon substrate. The substrate contains a groove, the groove having an inclined back wall adjacent to the waveguide. The substrate also contains a trench extending along a second direction, typically orthogonal to the first direction, across the inclined back wall, the trench having a vertical wall at its intersection with the inclined back wall. An optical fiber is located in the groove, with one end of the optical fiber resting against the vertical wall.

Description

BACKGROUND

[0001] Today's consumer electronics market often requires complex functions that require highly complex circuitry. Scaling down to ever smaller basic building blocks, such as transistors, has allowed each successive generation to integrate even more complicated circuits onto a single chip. Semiconductor packages are used to protect an integrated circuit (IC) chip or die and provide the die with an electrical interface to external circuitry. With the increasing demand for smaller electronic devices, semiconductor packages are becoming even more compact and must support greater circuit density.

[0002] For example, one trend in semiconductor packaging is to place optical interconnects inside the package to connect directly to a logic chip to achieve higher data transfer speeds when transmitted by light. An optical interconnect might include a photonic integrated circuit (PIC) connected to a processor or memory, which is connected to external components via an optical fiber array and appropriate optical connectors or ferrules. One challenge is that optical interconnect packages require sub-µm accuracy to align the optical fibers with the on-chip photonic waveguide. A V-groove array is a passive alignment structure that has become a standard method for aligning optical fibers with photonic integrated circuits.However, the question arises as to how to ensure that the ends of the optical fibers are in the optimal position relative to the optical input / output facet or the waveguide of the PIC. Optical fiber arrays must be assembled simultaneously to achieve high-volume assembly, making meeting alignment accuracy requirements a significant yield challenge. BRIEF DESCRIPTION OF THE DRAWINGS The Fig. 1A to 1E illustrate an example of a silicon V-groove structure for integrating an optical interconnect or optical fiber connector into an optical semiconductor package. The Fig. 2 and Fig. 3 illustrate a groove alignment structure including a groove with an X-stop for integrating an optical interconnect or fiber connector into an optical interconnect package according to the described embodiments. Fig. 4 also illustrates a wafer-level sorting trench along the second direction above the set of grooves. The Fig. 5A to 5D are cross-sectional diagrams illustrating an exemplary process flow for manufacturing a groove alignment structure according to the stated embodiments. The Fig. 6A and Fig. 6B illustrate a wafer and one or more dies with integrated circuit (IC) structures formed on the surface of the wafer. Fig. 7 illustrates a block diagram of an electronic system according to an embodiment of the present disclosure. Fig. 8 is a cross-sectional side view of an integrated circuit (IC) package that may include one or more groove alignment structures in accordance with one or more embodiments disclosed herein. Fig. 9 shows a computing device according to an implementation of the disclosure. DESCRIPTION OF THE EMBODIMENTS

[0003] Groove alignment structures and manufacturing methods for Z-direction alignment of optical fibers on a photonic integrated circuit are described. In the following description, numerous specific details, such as specific material and tooling systems, are set forth in order to provide a thorough understanding of embodiments of the present disclosure. It will be understood by one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as single or dual damascene processing, are not described in detail so as not to unnecessarily obscure embodiments of the present disclosure. Additionally, it is to be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.In some cases, various operations are again described as multiple discrete operations in a manner that is most helpful for understanding the present disclosure. However, the order of description should not be construed to mean that these operations are necessarily order-dependent. In particular, these operations need not be performed in the order presented.

[0004] Certain terminology may also be used in the following description for reference purposes only and is therefore not intended to be limiting. For example, terms such as "upper," "lower," "above," "below," "below," "below," and "top" refer to directions in the drawings to which reference is made. Terms such as "front," "rear," "back," and "side" describe the orientation and / or placement of parts of the component within a consistent but arbitrary frame of reference, which will be made clear by reference to the text and accompanying drawings describing the component being discussed. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

[0005] There is an increasing need for techniques for integrating optical fiber connectors into a flip-chip package. One or more embodiments described herein are directed to groove alignment structures and fabrication methods for Z-aligning optical fibers on a photonic integrated circuit.

[0006] To illustrate the context, the Fig. 1A to 1C show an example of a V-groove architecture for integrating an optical fiber connector into a semiconductor package with optical interconnect. Fig. 1A shows a top view of the optical interconnect package 100, which may include a logic die 104 mounted on a polymer substrate 102. A PIC 106 is mounted on the polymer substrate 102 and connected to the logic die 104 via the polymer substrate 102. The PIC 106 is connected to external components via an optical fiber array 108 and a corresponding optical connector 110, also referred to as a ferrule. The optical interconnect package 100 requires an alignment accuracy of less than 1 µm to align the optical fibers comprising the fiber array 108 with the PIC 106.

[0007] For example, in one embodiment, the PIC 106 may provide a terabits / s optical physical layer to support high-bandwidth, low-latency connectivity. In one embodiment, the PIC 106 refers to a single die. In another embodiment, the PIC 106 may be included in a photonic multi-chip package with laser and electronic control chips. The PIC 106 may be mounted to the substrate 102 via microbumps or other contacts and connected to the logic die 104 via interconnects within the substrate 102. In one embodiment, the PIC 106 may have a body including a silicon substrate and a photonic device layer formed on the silicon substrate.In some embodiments, the PIC 106 may include a silicon-on-insulator (SOI) substrate with a silicon substrate, a thick oxide layer on the substrate, and a silicon layer with photonic devices on the oxide layer. In one example, the PIC 106 may have a thickness of about 75 μm.

[0008] Fig. Figure 1B shows a detailed front view of an edge of the PIC 106, demonstrating that existing solutions use a V-groove array 112 to guide and align the fiber array 108 into the PIC 106. The V-groove array 112 can be fabricated by anisotropic wet etching of the silicon substrate of the PIC 106. Each groove or V-groove can have a U-shaped, square, or V-shaped cross-section.

[0009] Fig. Figure 1C shows a front view of one of the V-grooves, showing that the corresponding optical fibers in the fiber array 108 are inserted into the corresponding V-grooves 112A. The sidewalls of each V-groove 112A are etched at a specific angle to a depth of approximately 80 μm, and each V-groove 112A can have a width approximately equal to the diameter of the optical fibers. After an optical fiber 108A is inserted, a compressor plate (not shown) then presses on the top surface of the optical fiber 108A to force the fiber into the V-groove 112A so that the center of the optical fiber 108A is aligned with the waveguide that outputs light from the PIC (PIC facet) 106 side. In this example, each optical fiber 108A in the fiber array 108 may have a diameter of about 125 µm, and there may be a gap (e.g., ~17.5 µm) between the optical fiber 108A and the bottom of the V-groove 112A.

[0010] The Fig. 1D and Fig. 1E are plan views and cross-sectional views of the V-groove 112A, respectively. The optical fiber 108A is in Fig. 1D is shown transparently, so that the bottom of the V-groove 112A is visible. Since the anisotropic etching process for forming the V-grooves <111> of the silicon substrate 106A of the PIC 106 is used as an etch stop, each V-groove 112A is formed with two sloped sidewalls 114A, a sloped backwall 114B adjacent to the waveguide 116, and a bottom 114C. The optical fiber 108A is inserted into the V-groove 112A and is shown directed toward a waveguide 116 on the PIC 106 at or near the top of the backwall 114B. The waveguide 116 is a channel that guides light emitted from an end surface of the waveguide called a facet. The waveguide 116 can be made from a variety of materials, including silicon, silicon nitride, and indium phosphide.

[0011] Due to the inclined back wall, as in Fig. As shown in Figure 1E, once the optical fiber 108A is inserted and pushed in the X direction (along the optical fiber axis) toward the waveguide 116, the optical fiber 108A hits the inclined back wall 114B and stops. The distance between the facet of the PIC 106 and the inserted optical fiber 108A is approximately 60 µm. Unfortunately, at this distance, light is lost from the facet into the optical fiber 108A. To avoid light loss, the optical fiber 108A should be located at a distance of 20 µm from the waveguide.

[0012] Although V-grooves are known to provide sufficient XY alignment of the optical fiber, an improved groove alignment structure is required to ensure accurate X-direction positioning of the optical fibers in close proximity to the waveguide. Such a groove alignment structure should also reduce the risk of the optical fiber colliding with the PIC facet, damaging both the optical fiber and the PIC facet.

[0013] According to the disclosed embodiments, improved groove alignment structures and manufacturing methods for X-direction alignment of optical fibers on a waveguide of a PIC are described. Embodiments disclose groove alignment structures with a novel X-stop incorporated into the groove that effectively controls the X-alignment of optical fibers on a PIC. In embodiments, an X-stop is formed by creating a fiber stop trench across the sloped backwall of a groove. The fiber stop trench forms a vertical wall at an intersection with the sloped backwall in close proximity to the waveguide, defining the X-stop. An optical fiber inserted into the groove alignment structure abuts the X-stop and not the backwall. The use of the X-stop ensures that the optical fiber is spaced 10 to 20 µm from the waveguide.In addition, the fiber stop prevents the optical fiber from being pushed forward so far that it touches the waveguide. This prevents potential damage to the waveguide and improves the yield of the PIC 106.

[0014] The Fig. 2 and Fig. 3 show an example of a groove alignment structure including a groove with an X-stop for integrating an optical connection or fiber connector into an optical interconnect package such as an optical interconnect package 100. The groove 212 is representative of the grooves containing a groove array that includes the V-groove array 112 of Fig. 1B should be replaced. Fig. Figure 2 shows a cross-sectional view of the groove 212 containing an inserted optical fiber 208.

[0015] According to the disclosed embodiments, a device such as the groove alignment structure 200 similar to that shown in Fig. 1A and Fig. 1B, a substrate 206 (e.g., silicon) of a PIC. A waveguide 216 is located on the substrate 206. A groove 212 runs along a first direction, and the groove includes an inclined backwall 214B adjacent to the waveguide 216. A trench 220 is located in the substrate 206 along a second direction generally orthogonal (+- 10%) to the first direction across the inclined backwall 214B. The trench 220 forms a vertical wall at an intersection with the respective inclined backwall to create an X-stop 222. An optical fiber 208 is located in the groove 212, with one end of the optical fiber 208 abutting the vertical wall.

[0016] The groove 212 is part of a groove array, and an adhesive material (not shown) may be located at the bottom of the groove 212. Optical fibers 208 may comprise a portion of an optical fiber array located in the set of grooves above the adhesive material, and a portion of each of the optical fibers extends over or rises above the substrate 206.

[0017] In embodiments, the X-stop 222 is designed to contact the cladding and not the optical core of the optical fiber 208. This ensures that the optical fiber 208 can be repeatedly inserted in a specified x-direction from the waveguide 216 without striking or damaging the fiber core of the optical fiber 208.

[0018] The X-stop 222 also ensures that the longest fiber in an optical fiber array is always less than 60 µm from the facet of the waveguide 216. As shown in Fig. As shown in Figure 2, the vertical wall defining the X-stop 222 is spaced between 10 and 20 µm from the waveguide 216. Consequently, a distance of 10 to 20 µm exists between the optical fiber 208 and the waveguide 216, and a distance is maintained between the optical fiber 208 and the waveguide 216.

[0019] In one embodiment, the fiber stop trench 220 forming the X-stop 222 may comprise a single continuous fiber stop trench extending across each groove 212 of a plurality of grooves. In an alternative embodiment, the fiber stop trench 220 may be discontinuous, such that each groove 212 of a plurality of grooves includes a corresponding fiber stop trench 220.

[0020] According to disclosed embodiments, the X-stop 222 provides effective X-direction alignment of optical fibers to the waveguide 216 on the substrate 206. Even if it is absolutely necessary during mechanical assembly to push the optical fiber 208 closer to the waveguide 216 than normal, the X-stop 222 protects the facet of the waveguide 216 from scratches or destruction due to contact with the optical fiber 208. This also ensures that the optical quality of the optical fiber and the PIC facet is not compromised.

[0021] Fig. Figure 3 illustrates a cross-sectional view of the groove 212 without the optical fiber 208, showing the groove 212 with the fiber stop trench and an optional wafer-level sort trench 402 in the substrate 206 adjacent to the fiber stop trench 220. A wafer-level sort trench is a trench etched into the substrate to define the boundaries of individual dies (e.g., PIC) and facilitate die separation from the wafer after wafer-level testing. In one embodiment, the wafer-level sort trench 402 is a single continuous trench spanning multiple grooves.

[0022] The fiber stop trench 220 and the wafer-level sorting trench 402 may be formed simultaneously after the groove is formed through a single dry etching process. In one embodiment, the wafer-level sorting trench 402 is etched to a deeper depth than the fiber stop trench 220. For example, in one embodiment, the fiber stop trench 220 may be between about 150 and 200 µm deep, while the wafer-level sorting trench 402 may have a depth of 180 to 260 µm, with the regions of the wafer-level sorting trench 402 between the grooves being shallower than the regions of the wafer-level sorting trench 402 etched into the bottom of the grooves 212.

[0023] Fig. Figure 4 shows an oblique side view of the PIC 206 and a groove array comprising a set of grooves 404 adjacent to a waveguide 216. Fig. Figure 4 also shows an enlarged view of the groove 212 in the set of grooves 404.

[0024] The PIC 206 includes a substrate, and the set of grooves 404 extends along a first direction on top of the substrate aligned with the waveguide 216. As shown in the enlarged view, each groove 212 has two sloped sidewalls 414A and 414B and a sloped backwall 214B adjacent to the waveguide 216. A set of one or more fiber stop trenches 220 extends along a second direction generally orthogonal to the first direction and extends across the sloped backwalls 214B of the grooves 212. As described above, one or more fiber stop trenches 220 each form a vertical wall at an intersection with the sloped backwalls 214B of the grooves 212 to create corresponding X-stops. As a corresponding optical fiber (not shown) is inserted into each groove 212, one end of the respective optical fiber rests against the vertical wall (X-stop) of the groove 212.The vertical wall defines a distance of 10 to 20 µm between the optical fiber and the waveguide 216.

[0025] Fig. 4 also shows a wafer-level sorting trench 402 along the second direction across the set of grooves 404. In this embodiment, the fiber stop trench 220 is discontinuous, such that the grooves in the set of grooves 404 include a respective fiber stop trench. The wafer-level sorting trench 402 is shown as continuous and extends across the set of grooves 404. The wafer-level sorting trench 402 is located such that a gap exists between the wafer-level sorting trench 402 and the vertical wall. In one embodiment, the wafer-level sorting trench 402 may be spaced approximately 50 to 60 µm from the fiber stop trench 220. The wafer-level sorting trench 402 effectively splits the groove 212 into two parts to form a first groove 212A and a second groove 212B. In one embodiment, the second groove 12B may be about 800 µm long.

[0026] In one embodiment, the optical fibers may have a diameter of approximately 80 to 125 µm and a pitch of approximately 125 to 250 µm. The set of grooves 404 may each have a width approximately equal to the diameter of the optical fibers.

[0027] The Fig. 5A to 5D are cross-sectional diagrams illustrating an exemplary process flow for manufacturing a groove alignment structure according to the stated embodiments. Fig. 5A shows that the process may begin by performing a first etch through a dielectric stack (not shown) of the PIC 506 with a waveguide 516 to expose the substrate 506A of the PIC 506, where grooves are formed. In one embodiment, the substrate 506A comprises silicon (Si), but may comprise other materials, including, but not limited to, silicon germanium (SiGe), silicon-on-insulator (SOI), and Group III-V semiconductors.

[0028] In embodiments, the first etching process may be performed by a dry etch (e.g., a reactive ion etch) or by a laser etch. Laser etching, if used, may also enable the creation of grooves after the PIC has been attached to a package (e.g., package 100), thereby reducing the risk of cracking the PIC. Any type of dry etching that etches directionally or anisotropically may be used. Optionally, a wet etch may be used instead of a dry etch. The etching process is performed after an etch mask has been formed using known photolithographic techniques. In certain embodiments, the etch mask may be a hard mask made of silicon dioxide or silicon nitride; and in other embodiments, the etch mask is made of known photoresist materials.

[0029] Fig. 5B shows that a second etching process is performed through the etch mask to form openings in the substrate 506A that define the positions, widths, and lengths of a plurality of grooves along a first direction (e.g., along an axis of the waveguide) of the substrate. The second etching process may be performed such that each groove 512 of the plurality of grooves has sloped sidewalls, a bottom, and a sloped backwall 514. The second etching process defines the X and Y alignment for an optical fiber array. After insertion into the grooves, the optical fibers travel within a plane (X) of the substrate 206A (see Fig. 1D).

[0030] In embodiments, the second etching process may be performed by crystallographic silicon wet etching using a tetramethylammonium hydroxide (TMAH) or KOH etching process. Substrate 506A is wet etched over a period of time to form the grooves to a desired depth, e.g., 80 µm.

[0031] Fig. Figure 5C shows that after the second etch to form the grooves 512, a third etch process is performed to create a fiber stop trench 520 across the back wall 514 of the grooves adjacent to the waveguide 516. The fiber stop trench 520 forms a vertical wall at an intersection with the sloped back wall 514 to create an X-stop 522. The vertical wall or X-stop 522 of the fiber stop trench formed in the back wall 514 defines the distance between the end of the waveguide 516 and the end of an optical fiber inserted into the corresponding groove. In embodiments, the third etch process can be performed by a dry etching process (e.g., a reactive ion etching process) or by a laser etching process. In embodiments, the third etch process used to create the fiber stop trench 520 can also be used to create the wafer-level sorting trench used in Fig. 4 is shown.

[0032] Fig. 5D shows that after the third etching process, an adhesive 526 is optionally applied to the bottom of each of the grooves 512, and an optical fiber 508 of an optical fiber array is inserted into corresponding grooves 512 on the adhesive material 526. Approximately half of the optical fiber 508 extends above the surface of the substrate 506A. The resulting groove alignment structure can then be covered by a polymer lid (not shown).

[0033] With reference to the Fig. 6A and Fig. 6B, a wafer 600 may be made of semiconductor material and include one or more dies 602 with integrated circuit (IC) structures formed on the surface of the wafer 600. Each of the dies 602 may be a repeating unit of a semiconductor product including a suitable IC (e.g., ICs having a substrate with V-grooves and corresponding fiber stop trenches forming X-stops as described above). After fabrication of the semiconductor product is complete, the wafer 600 may undergo a singulation process in which each of the dies 602 is separated from the others to provide discrete "chips" of the semiconductor product. In particular, structures including embedded non-volatile memory structures having a substrate with V-grooves and corresponding fiber stop trenches forming X-stops as described herein may take the shape of the wafer 600 (e.g., undivided) or the shape of the die 602 (e.g., singulated).Die 602 may include one or more integrated non-volatile memory structures and / or supporting circuitry for routing electrical signals, as well as other integrated circuit components. In some embodiments, wafer 600 or die 602 may include an additional memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple devices may be combined on a single semiconductor chip 602. For example, a memory array formed from multiple memory devices may be formed on the same chip 602 as a processing device or other logic configured to store information in the memory devices or execute instructions stored in the memory array.

[0034] Embodiments disclosed herein may be used to fabricate a variety of different types of integrated circuits and / or microelectronic devices. Examples of such integrated circuits include processors, chipset components, graphics processors, digital signal processors, microcontrollers, and the like. In other embodiments, semiconductor memory may be fabricated. Furthermore, integrated circuits or other microelectronic devices may be used in a variety of electronic devices known in the art. For example, in computer systems (e.g., desktop, laptop, server), mobile phones, personal electronics, etc. The integrated circuits may be coupled to a bus and other components in the systems. For example, a processor may be coupled to memory, a chipset, etc., through one or more buses.Each processor, memory, and chipset may potentially be manufactured using the approaches described herein.

[0035] Fig. 7 illustrates a block diagram of an electronic system 700 according to an embodiment of the present disclosure. The electronic system 700 may, for example, correspond to a portable system, a computer system, a process control system, or any other system that utilizes a processor and associated memory. The electronic system 700 may include a microprocessor 702 (including a processor 704 and a controller 706), a storage device 708, and an input / output device 710 (it is understood that in various embodiments, the electronic system 700 may include multiple processors, controllers, storage devices, and / or input / output devices).In one embodiment, electronic system 700 includes a set of instructions that define operations to be performed on data by processor 704, as well as other transactions between processor 704, storage device 708, and input / output device 710. Controller 706 coordinates the operations of processor 704, storage device 708, and input / output device 710 by cycling through a set of operations that cause instructions to be retrieved from storage device 708 and executed. Storage device 708 may include a non-volatile memory cell, as described herein. In one embodiment, storage device 708 is embedded within microprocessor 702, as shown in FIG. Fig. 7. In one embodiment, the processor 704 or other component of the electronic system 700 includes a substrate having V-grooves and corresponding fiber stop trenches forming X-stops, such as those described herein.

[0036] Fig. 8 is a cross-sectional view of an IC device assembly that may include a substrate having V-grooves and corresponding fiber stop trenches forming X-stops, in accordance with one or more embodiments described herein.

[0037] With reference to Fig. 8, an IC device assembly 800 includes components having one or more integrated circuit structures described herein. The IC device assembly 800 includes a number of components disposed on a circuit board 802 (which may be, for example, a motherboard). The IC device assembly 800 includes components disposed on a first surface 840 of the circuit board 802 and on an opposite second surface 842 of the circuit board 802. Generally, components may be disposed on one or both surfaces 840 and 842. In particular, any suitable components of the IC device assembly 800 may include a series of multilayer high-k gate dielectrics, as described in this specification.

[0038] In some embodiments, circuit board 802 may be a printed circuit board (PCB) including multiple metal layers separated by layers of dielectric material and interconnected by electrically conductive vias. One or more of the metal layers may be formed in a desired circuit pattern to conduct electrical signals (optionally in conjunction with other metal layers) between components coupled to circuit board 802. In other embodiments, circuit board 802 may be a non-PCB substrate.

[0039] The Fig. The IC device assembly 800 illustrated in Figure 8 includes a package-on-interposer structure 836 coupled to the first surface 840 of the circuit board 802 by coupling components 816. The coupling components 816 may electrically and mechanically couple the package-on-interposer structure 836 to the circuit board 802 and may include solder balls (as shown in Fig. 8), plug and socket parts of a socket, an adhesive, an underfill material, and / or any other suitable electrical and / or mechanical coupling structure.

[0040] The package-on-interposer structure 836 may include an IC package 820 coupled to an interposer 804 by coupling components 818. The coupling components 818 may take any form suitable for the application, such as the forms discussed above with reference to the coupling components 816. Although a single IC package 820 in Fig. 8, multiple IC packages may be coupled to the interposer 804. It is understood that additional interposers may be coupled to the interposer 804. The interposer 804 may provide an intermediate substrate that bridges the circuit board 802 and the IC package 820. The IC package 820 may, for example, include a die (die 602 of Fig. 6B) or any other suitable component. In general, the interposer 804 may spread a connection to a larger pitch or reroute a connection to another connection. For example, the interposer 804 may couple the IC package 820 (e.g., a die) to a ball grid array (BGA) of coupling components 816 for coupling the circuit board 802. In the Fig. In the embodiment illustrated in Figure 8, the IC package 820 and the circuit board 802 are mounted on opposite sides of the interposer 804. In other embodiments, the IC package 820 and the circuit board 802 may be mounted on the same side of the interposer 804. In some embodiments, three or more components may be interconnected via the interposer 804.

[0041] The interposer 804 may be formed from an epoxy resin, a glass-fiber reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer 804 may be formed from alternative rigid or flexible materials, which may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other Group III-V and Group IV materials. The interposer 804 may include metal interconnects 810 and vias 808, including, but not limited to, through-silicon vias (TSVs) 806. The interposer 804 may further include embedded devices, including both passive and active devices.Such devices may include, among others, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical system (MEMS) devices may also be formed on the interposer 804. The package-on-interposer structure 836 may take the form of any package-on-interposer structure known in the art.

[0042] The IC device assembly 800 may include an IC package 824 coupled to the first surface 840 of the circuit board 802 by coupling components 822. The coupling components 822 may take the form of any of the embodiments described above with respect to the coupling components 816, and the IC package 824 may take the form of any of the embodiments described above with respect to the IC package 820.

[0043] The Fig. The IC device assembly 800 illustrated in Figure 8 includes a package-to-package structure 834 coupled to the second surface 842 of the circuit board 802 by coupling components 828. The package-to-package structure 834 may include an IC package 826 and an IC package 832 coupled together by coupling components 830 such that the IC package 826 is disposed between the circuit board 802 and the IC package 832. The coupling components 828 and 830 may take the form of any of the embodiments of the coupling components 816 discussed above, and the IC packages 826 and 832 may take the form of any of the embodiments of the IC package 820 discussed above. The package-on-package structure 834 may be configured according to any of the package-on-package structures known in the art.

[0044] Fig.9 shows a computing device 900 according to one implementation of the disclosure. Computing device 900 includes a circuit board 902. Circuit board 902 may include a number of components, including, but not limited to, a processor 904 and at least one communication chip 906. Processor 904 is physically and electrically coupled to circuit board 902. In some implementations, at least one communication chip 906 is also physically and electrically coupled to circuit board 902. In further implementations, communication chip 906 is part of processor 904.

[0045] Depending on the application, computing device 900 may or may not include other components that are physically and electrically coupled to circuit board 902. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a cryptoprocessor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a GPS device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (e.g., hard drive, CD, digital versatile disk (DVD), etc.).

[0046] The communication chip 906 enables wireless communication for transferring data to and from the computing device 900. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can transfer data through modulated electromagnetic radiation over a non-solid medium. The term does not imply that the associated devices do not include wires, although they may not be present in some embodiments. The communication chip 906 can implement a variety of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), and IEEE 802.20, Long Term Evolution (LTE), EV-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocols referred to as 3G, 4G, 5G, and beyond. Computing device 900 may include multiple communication chips 906. For example, a first communication chip 906 may be dedicated to shorter-range wireless communication such as Wi-Fi and Bluetooth, and a second communication chip 906 may be dedicated to longer-range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, and others.

[0047] The processor 904 of the computing device 900 includes an integrated circuit die included within the processor 904. In some implementations of the disclosure, the integrated circuit die of the processor includes a substrate having V-grooves and corresponding fiber stop trenches forming X-stops, according to implementations of embodiments of the disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to convert that electronic data into other electronic data that can be stored in registers and / or memory.

[0048] The communication chip 906 also includes an integrated circuit die integrated into the communication chip 906. According to another embodiment of the disclosure, the integrated circuit die of the communication chip 906 includes a substrate with V-grooves and corresponding fiber stop trenches forming X-stops, according to embodiments of the disclosure.

[0049] In further implementations, another component housed in the computing device 900 may include an integrated circuit die including a substrate with V-grooves and corresponding fiber stop trenches forming X-stops, according to implementations of embodiments of the disclosure.

[0050] In various implementations, computing device 900 may be a notebook, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultramobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment controller, a digital camera, a portable music player, or a digital video recorder. In further implementations, computing device 900 may be any other device that processes data.

[0051] Therefore, the embodiments described herein include a V-groove fiber stop.

[0052] The above description of illustrated implementations of embodiments of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Although specific implementations of the disclosure and examples thereof have been described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as one skilled in the art will recognize.

[0053] These changes may be made to the disclosure in light of the foregoing detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and claims. Rather, the scope of the disclosure is to be determined solely by the following claims, which are to be interpreted in accordance with established doctrines of claim interpretation.

[0054] Example embodiment 1: A device comprising a silicon substrate and a waveguide on the silicon substrate. A groove is provided in the substrate, the groove having a sloped backwall adjacent to the waveguide. A trench is provided in the substrate, the trench extending along a second direction generally orthogonal to the first direction across the sloped backwall, the trench having a vertical wall at an intersection with the sloped backwall. An optical fiber is provided in the groove, one end of the optical fiber being in contact with the vertical wall.

[0055] Example embodiment 2: Device according to embodiment 1, wherein the vertical wall is spaced between 10 and 20 µm from the waveguide.

[0056] Example Embodiment 3: The device of Embodiment 1 or 2, further comprising a plurality of grooves in the substrate, and wherein the trench comprises a single continuous trench extending across the plurality of grooves.

[0057] Example Embodiment 4: The device of Embodiment 1, 2 or 3, further comprising a plurality of grooves in the substrate, wherein the trench is not continuous across each groove of the plurality of grooves.

[0058] Example design 5: Device according to design 1, 2, 3 or 4, wherein the fiber stop trench is between 150 and 200 µm deep.

[0059] Example Embodiment 6: The device of Embodiment 1, 2, 3, 4, or 5, wherein the trench comprises a first trench, the device further comprising a second trench in the substrate adjacent to the first trench.

[0060] Example Embodiment 7: The device of Embodiment 1, 2, 3, 4, 5, or 6, wherein a depth of the second trench ranges from 180 to 260 µm.

[0061] Example embodiment 8: Device of embodiment 1, 2, 3, 4, 5, 6 or 7, wherein the groove has a U-shaped, square or V-shaped cross-section.

[0062] Example embodiment 9: Device of embodiment 1, 2, 3, 4, 5, 6, 7 or 8, wherein the groove is about 80 µm deep.

[0063] Example Embodiment 10: A device includes a photonic integrated circuit (PIC) having a substrate. A set of grooves is located in the substrate, the grooves in the set of grooves having two sloped sidewalls and a sloped backwall. A set of one or more trenches extends along a second direction generally orthogonal to the first direction across the sloped backwall of the grooves, the one or more trenches having a vertical wall at an intersection with the sloped backwall of the grooves. A corresponding optical fiber is located in the grooves, one end of the respective optical fiber abutting the vertical wall of the grooves.

[0064] Example Embodiment 11: The device of Embodiment 10, wherein the trench comprises a first trench, the device further comprising a second trench along the second direction across the set of grooves.

[0065] Example embodiment 12: Device according to embodiment 11, wherein there is a gap between the second trench and the vertical wall.

[0066] Example embodiment 13: The device according to embodiment 11 or 12, wherein the second trench is spaced approximately 50 to 60 µm from the first trench.

[0067] Example Embodiment 14: The device of embodiment 10, 11, 12 or 13, further comprising a waveguide on the substrate, wherein the vertical wall is spaced between 10 and 20 µm from the waveguide.

[0068] Example Embodiment 15: The device of Embodiment 10, 11, 12, 13, or 14, wherein the trench comprises a single continuous fiber trench extending across the set of grooves.

[0069] Example embodiment 16: The device of embodiment 10, 11, 12, 13, 14, or 15, wherein the trench is not continuous so that the grooves in the set of grooves comprise a respective trench.

[0070] Example Embodiment 17: A method of fabricating a device includes performing a first etching process through a dielectric stack to expose a substrate in which grooves are formed. A second etching process is performed to form a plurality of grooves along a first direction of the substrate such that an individual groove of the plurality of grooves has sloped sidewalls, a bottom, and a sloped backwall. A third etching process is performed to create a trench across the sloped backwall of the grooves, forming a vertical wall at an intersection with the sloped backwall. An adhesive material is applied to a bottom of the grooves, and an optical fiber of an optical fiber array is inserted into the corresponding grooves.

[0071] Embodiment 18: The method of Embodiment 17, further comprising: performing the first etching process with a dry etch.

[0072] Example Embodiment 19: The method of Embodiment 17 or 18, further comprising: performing the second etching process with a wet etching method using a tetramethylammonium hydroxide (TMAH) or a KOH etching method.

[0073] Example Embodiment 20: The method of Embodiment 17, 18 or 19, further comprising: performing the third etching process with a dry etching method.

Claims

[1] Device comprising: a silicon substrate, a waveguide on the silicon substrate; a groove in the substrate, the groove having an inclined back wall adjacent the waveguide; a trench in the substrate, the trench extending along a second direction generally orthogonal to the first direction across the inclined back wall, the trench having a vertical wall at an intersection with the inclined back wall; and an optical fiber in the groove, with one end of the optical fiber resting against the vertical wall. [2] The device of claim 1, wherein the vertical wall is spaced between 10 and 20 µm from the waveguide. [3] The device of claim 1 or 2, further comprising a plurality of grooves in the substrate, wherein the trench comprises a single continuous trench extending across the plurality of grooves. [4] The device of claim 1, 2 or 3, further comprising a plurality of grooves in the substrate, wherein the trench is discontinuous across each groove of the plurality of grooves. [5] The device of claim 1, 2, 3 or 4, wherein the trench is between 150 and 200 µm deep. [6] The device of claim 1, 2, 3, 4 or 5, wherein the trench comprises a first trench, the device further comprising a second trench in the substrate adjacent to the first trench. [7] The device according to claim 6, wherein a depth of the second trench ranges from 180 to 260 µm. [8] Device according to claim 1, 2, 3, 4, 5, 6 or 7, wherein the groove has a U-shaped, square or V-shaped cross-section. [9] The device of claim 1, 2, 3, 4, 5, 6, 7 or 8, wherein the groove is about 80 µm deep. [10] Device comprising: a photonic integrated circuit (PIC) with a substrate, a set of grooves in the substrate, the grooves in the set of grooves having two inclined side walls and an inclined rear wall; one or more trenches along a second direction generally orthogonal to the first direction across the inclined back wall of the grooves, the one or more trenches having a vertical wall at an intersection with the inclined back wall of the grooves; and a respective optical fiber in the grooves, one end of the respective optical fiber resting against the vertical wall of the grooves. [11] The device of claim 10, wherein the trench comprises a first trench, the device further comprising a second trench along the second direction across the set of grooves. [12] The device of claim 11, wherein there is a gap between the second trench and the vertical wall. [13] The device of claim 11 or 12, wherein the second trench is spaced approximately 50 to 60 µm from the first trench. [14] The device of claim 10, 11, 12 or 13, further comprising a waveguide on the substrate, wherein the vertical wall is spaced between 10 and 20 µm from the waveguide. [15] The device of claim 10, 11, 12, 13 or 14, wherein the trench comprises a single continuous trench extending across the set of grooves. [16] The device of claim 10, 11, 12, 13, 14 or 15, wherein the trench is discontinuous so that the grooves in the set of grooves comprise a respective trench. [17] A method of manufacturing a device comprising: Performing a first etching process through a dielectric stack to expose a substrate in which grooves are formed; performing a second etching process to form a plurality of grooves along a first direction such that one of the grooves in the plurality of grooves has inclined sidewalls, a bottom, and an inclined backwall; performing a third etching process to create a trench across the inclined back wall of the grooves forming a vertical wall at an intersection with the inclined back wall; Applying an adhesive to a bottom of the plurality of grooves; and Inserting an optical fiber of an optical fiber array into the corresponding grooves. [18] The method of claim 17, further comprising: performing the first etching process with a dry etch. [19] The method of claim 17 or 18, further comprising: performing the second etching process with a wet etching method using a tetramethylammonium hydroxide (TMAH) or a KOH etching method. [20] The method of claim 17, 18 or 19, further comprising: performing the third etching process with a dry etching method.

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