CHIP MODULE AND METHOD FOR MANUFACTURING A CHIP MODULE

Abstract

A chip module (101) is provided. The chip module (101) has a contact surface (102) for contact-based communication with a reader, wherein the contact surface (102) is made of a metal, and the contact surface (102) is coated with a double layer (104) consisting of a lower layer (104u) of an organic silicon compound and / or a carbon compound and an upper layer (104o) of silicon oxide, wherein the double layer (104) has a thickness that provides an electrical surface contact resistance of at most 500 mΩ according to ISO 7810 when measured according to ISO 10373-1.

Description

TECHNICAL AREA

[0001] The present disclosure relates to a chip module and a method for manufacturing a chip module. BACKGROUND

[0002] Due to steadily rising precious metal prices, it is commercially desirable to minimize the thickness of the final gold (Au) plating layer on chip card modules. However, the protective effect of Au plating layers decreases with their thickness. Therefore, it is currently not possible to use thin Au plating layers (for example, with a thickness of less than 0.02 µm) for applications in the field of bank and identity (ID) cards, which must meet the requirements for salt spray testing according to ISO / IEC 7810 and chemical resistance according to ISO / IEC 10373-1.

[0003] Furthermore, the electroplated gold in thin layers (for example, with a thickness of less than 0.02 µm) loses its golden color, and the underlying grayish nickel layer becomes visible. The module's surface appears yellowish-silver and no longer exhibits the pronounced golden color valued by customers. This reduces market acceptance.

[0004] For these reasons, currently either the higher costs for the thicker Au coating must be accepted or a lower quality in terms of appearance and corrosion resistance must be accepted.

[0005] DE 10 2016 115 338 A1 discloses a semiconductor device comprising a substrate, a metallization layer arranged in and / or above the substrate, and a protective layer at least partially placed over the metallization layer, wherein the metallization layer contains at least one of the following: copper, aluminum, gold, silver, and wherein the protective layer contains a nitride material containing at least one of the following: copper, aluminum, gold, silver.

[0006] US 4,495,254 A discloses a method of protecting the surface of a metal object exposed to the atmosphere and abrasion during normal use from scratches and / or corrosion by means of a thin, transparent, abrasion-resistant film of an inert non-metallic material such as SiO2, SiC, Si3N4, TiO2, MgO, Al2O3, Ta2O5, Nb2O5, GeO2, spinel and selected colorless glass compositions. SHORT DESCRIPTION

[0007] A chip module according to claim 1 and a method for manufacturing a chip module according to claim 8 are provided. Further embodiments are described in the dependent claims.

[0008] A chip module is provided. The chip module has a contact surface for contact-based communication with a reader, wherein the contact surface is made of metal and coated with a double layer consisting of a lower layer of an organic silicon compound and / or a carbon compound and an upper layer of silicon oxide, wherein the upper layer has a thickness in the range of 75 nm to 85 nm and wherein the double layer has a thickness in the range of 90 nm to 200 nm.

[0009] The person skilled in the art will recognize further features and advantages of the invention when reading the following detailed description and when looking at the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The present disclosure is illustrated by way of example and is not limited to the depictions in the accompanying drawings, in which the same reference numerals refer to similar or identical elements. The elements in the drawings are not necessarily shown to scale. The features of the various examples shown can be combined, provided they are not mutually exclusive. Fig. Figure 1 shows a schematic cross-sectional view of a chip module (as an overview integrated into a chip card and as a close-up) according to various embodiments during contact-based operation; Fig. Figure 2 shows photographs for comparing contact surfaces of the chip module according to different embodiments and contact surfaces of chip modules according to the prior art; and Fig. Figure 3 shows a flowchart of a process for manufacturing a chip module according to various embodiments. DETAILED DESCRIPTION

[0011] A current Infineon solution is a gold layer (Au layer) with a thickness greater than 0.03 µm combined with an organic coating. The organic coating is a so-called self-assembled monolayer (SAM), in which the sulfur head group of a surfactant molecule bonds to the Au surface. It was chosen to ensure optimal protection in salt spray tests, gas tests, and an in-house test simulating the internal wallet. This combination resulted in superior corrosion resistance performance compared to competitors, as demonstrated by specification tests and practical experience. Competitors such as Linxens and Agencomm have developed similar combinations in recent years. As the Au thickness of the electroplated layer decreases, so does the protective effect of this coating, since the more porous gold layer offers fewer bonding partners for the coating molecules.

[0012] The embodiments described here enable the application of thin Au layers (< 0.02 µm) to chip card modules, while retaining both the excellent corrosion protection and the valuable golden color exhibited by standard Au layers (with a thickness of more than 0.03 µm).

[0013] In various embodiments, this is achieved by applying a double protective layer over the Au coating. The double protective layer consists of two different coatings that complement each other in their corrosion protection performance. The uppermost layer is a plasma-deposited SiO2 coating (Si oxide + short-chain aliphatics, approximately 80 nm thick) applied to an organic self-assembled monolayer (SAM).

[0014] As a second effect, in addition to the protective function, the SiO2 layer produces a yellow-gold interference color, which gives the surface a light golden appearance.

[0015] This is in Fig. 2 shown. Even though the grayscale representation of the originally colored photographs cannot reproduce the golden sheen, it is also evident from the grayscale representation that the appearance of the chip module 101 shown in the middle according to various embodiments (or several chip modules 101) is similar to that of the chip module 201 shown on the left according to the prior art, which has a final gold layer with a thickness of 30 nm or more.

[0016] In contrast, the appearance of the comparison example of a 220 chip module on the right, in which the gold layer has a thickness of less than 20 nm and in which no silicon oxide layer is applied over the SAM layer, appears darker and more matte, even in the grayscale representation.

[0017] Fig. Figure 1 shows a schematic cross-sectional view of a chip card 100 with a chip module 101 integrated into a chip card body 114 according to various embodiments, which has a contact surface 102 for contact-based operation (which in turn can have a plurality of contact surface areas that can be isolated from one another, for example, for providing an operating voltage with different polarities, different signals, etc.). The illustration shows the chip card 100 or the chip module 101 during contact-based operation, i.e., while part of a reader 106 contacts the contact surface.

[0018] The chip card 100 can be designed as a purely contact-based chip card, or, for example, as a dual-interface chip card that is set up for both contact-based and contactless operation.

[0019] In Fig. Figure 1 below shows a close-up of the upper illustration (chip 110 is omitted below for clarity), which in particular shows in detail an embodiment of the contact surface 102 and its coating.

[0020] The chip module 101 can include a chip 110, for example a semiconductor chip, e.g. a chip 110, which is set up for a typical chip card application, e.g. payment transactions, identification / authentication, or similar.

[0021] The chip 110 can be coupled, for example in a manner essentially known to those skilled in the art, to the contact surface 102, which has a metal component. The metal can, for example, be a base metal, as this can optimize cost savings through the protective layer. However, in various embodiments, precious metals can also be advantageously provided with the coating, as this can, for example, make it possible to form a thinner precious metal layer.

[0022] The contact surface 102 can be formed from a single metal, a stack of layers of different metals, or a metal alloy. The metal of the electrically conductive area can, for example, be a copper-tin-zinc alloy, gold, palladium, copper, nickel, copper-nickel, or an alloy of the aforementioned metals. The top metal layer can be gold or consist of gold.

[0023] In Fig. Figure 1 shows that the contact surface 102 is formed, for example, from a stack of three metal layers: a (copper) support layer 102a, which can have a thickness in the range of approximately 13 µm to approximately 35 µm; on the support layer 102a, a (nickel) intermediate layer 102b, which can have a thickness of approximately 1 µm to approximately 2 µm; and on the intermediate layer 102b, a top layer 102c, which can have, for example, gold, palladium, or a copper-tin-zinc alloy. The top layer 102c can, for example, have a thickness in the range of approximately 8 nm to approximately 300 nm.

[0024] According to various embodiments, the top layer 102c can have a thickness of less than 20 nm, for example in a range of about 8 nm to less than 20 nm.

[0025] The contact surface 102 can be formed on a support material 112 in various embodiments, for example, a support tape typically used in the manufacture of chip modules, which can be made of polyimide, polyethylene terephthalate (PET), or an epoxy material. A typical thickness of the support material 112 can range from approximately 25 µm to approximately 200 µm.

[0026] The chip module 101 can further have a coating of the contact surface 102 with a lower layer 104u made of at least one organic silicon compound and / or a carbon compound and with an upper layer 104o made of silicon oxide (SiO2) arranged thereon.

[0027] The lower layer 104u and the upper layer 104o can be referred to together as double layer 104 or simply layer 104.

[0028] The double layer 104 can have a thickness that exhibits an electrical surface contact resistance of not more than 500 mΩ according to ISO 7810 (when measured according to ISO 10373-1).

[0029] This means that when arranging the double layer 104, two inherently dielectric materials (namely the material of the lower layer 104u, provided it is the dielectric organic silicon compound, and the silicon oxide of the upper layer 104o) are applied so thinly, e.g., with a layer thickness in the range of approximately 10 nm to approximately 200 nm, e.g., between approximately 20 nm and approximately 100 nm, e.g., between approximately 20 nm and approximately 50 nm, that the surface contact resistance is nevertheless low enough to enable contact-based communication via the electrically conductive region 102. In particular, the electrical surface contact resistance can be at most 500 mΩ.

[0030] According to the invention, the thickness of the upper layer 104o can be selected in a range between about 75 nm and about 85 nm, for example about or exactly 80 nm, because this makes it possible to exploit a property of silicon oxide: Due to differences in refractive index between the silicon dioxide and air, the top layer produces interference colors depending on its thickness. With an applied layer thickness of approximately 80 nm (+ / - 5 nm), the layer exhibits a yellowish-gold interference color, making the surface appear light gold, similar to the appearance of a thicker gold layer.

[0031] According to various embodiments, in which the upper layer 104o has the described layer thickness of approximately 80 nm (+ / -5 nm) or a layer thickness different therefrom, the chip module 101 can exhibit higher corrosion resistance according to various embodiments.

[0032] The SAM, which can be used for the lower layer 104u, is a monomolecular layer of surfactant molecules with a sulfur-containing head group and has a typical thickness of a few angstroms. The sulfur can bind coordinatively to the Au atoms but has a low affinity for oxides. The sulfur can provide good protection against the conditions of the SM test (ISO / IEC 7810); however, its effectiveness may decrease slightly in thinner Au layers 102c, as the Au layer 102c can become porous and oxides of an underlying metal (e.g., nickel) may appear on the surface.

[0033] The upper layer 104o (the SiO2 layer), which is deposited on the lower layer 104u (for example, directly on it, so that the upper layer 104o and the lower layer 104u form a common interface), can effectively bond to the oxides on the surface (and also to the side chains of the SAM) and exhibit excellent resistance to corrosive chemicals such as SO2, H2S, NO x and Cl2 formation, however, is impaired in the salt spray test.

[0034] Under the conditions of the SM test, the upper layer 104o acts as a sacrificial layer, delaying the attack of the chemicals. The underlying lower layer 104u (SAM coating), on the other hand, demonstrates good performance in the salt spray test. The combination of both coatings is superior to either one alone.

[0035] The at least one electrically conductive area can, in various embodiments, have an Rz surface roughness in a range of approximately 0.1 to approximately 6 µm, e.g., between approximately 0.5 µm and 3 µm. As shown in Fig. As illustrated in Figure 1, this can, for example, lead to the thickness of layer 104 being slightly uneven, so that an electrical resistance between the reader and the electrically conductive area 104 is reduced, for example in the area of ​​a “mountain”.

[0036] "Organic silicon compound," also known as organosilicon compound or organosilicon compound, is a collective term for compounds that either exhibit direct silicon-carbon bonds (Si-C) or in which the carbon is linked to the silicon via oxygen, nitrogen, or sulfur atoms. Organosilicon compounds can be described by the general formula RnSiX4-n (with n ranging from 1 to 4), where R represents various organic groups, such as aliphatics, aromatics, and heterocycles, and X represents various groups, such as OH, Si-O, Si-N, Si-C, Cl, H, etc.

[0037] Examples of organic silicon compounds that can be used for layer 104 are organosilane, organosilanol, organochlorosilane, siloxane, silicon, polysilizane and carbosilane. Fig. Figure 3 shows a flowchart 300 of a method for manufacturing a chip module according to various embodiments.

[0038] The method comprises coating a contact surface for contact-based communication with a reader, which has a metal, with a lower layer of an organic silicon compound and / or a carbon compound (310), and coating the lower layer with an upper layer of silicon oxide, wherein the double layer of the lower and upper layers has a thickness that gives an electrical surface contact resistance of not more than 500 mΩ according to ISO 7810 when measured according to ISO 10373-1 (320).

[0039] The coating of the contact surface with the lower layer can be carried out in various embodiments by means of wet chemical coating by immersion, free jet plasma coating, chemical vapor deposition, hot wire activated vapor deposition or physical vapor deposition.

[0040] The coating of the lower layer with the upper layer can be carried out in various embodiments by means of wet chemical coating or plasma coating.

[0041] The following is a summary of some examples.

[0042] Exemplary embodiment 1 is a chip module. The chip module has a contact surface for contact-based communication with a reader, wherein the contact surface comprises a metal, and a coating of the contact surface with a double layer consisting of a lower layer of an organic silicon compound and / or a carbon compound and an upper layer of silicon oxide, wherein the double layer has a thickness that provides an electrical surface contact resistance of at most 500 mΩ according to ISO 7810 when measured according to ISO 10373-1.

[0043] Exemplary embodiment 2 is a chip module according to exemplary embodiment 1, wherein the contact surface has a gold layer as the uppermost metal layer, which forms a common interface with the lower layer.

[0044] Exemplary embodiment 3 is a chip module according to exemplary embodiment 2, wherein the gold layer has a layer thickness in a range of less than 20 nm, for example in a range of approximately 10 nm to less than 20 nm.

[0045] Exemplary embodiment 4 is a chip module according to one of the exemplary embodiments 1 to 3, wherein the upper layer has a layer thickness in a range of about 75 nm to about 85 nm, for example about 80 nm.

[0046] Exemplary embodiment 5 is a chip module according to one of the exemplary embodiments 1 to 4, wherein the upper layer is manufactured by plasma coating.

[0047] Exemplary embodiment 6 is a chip module according to one of the exemplary embodiments 1 to 5, wherein the double layer has a layer thickness in a range of approximately 90 nm to approximately 200 nm.

[0048] Exemplary embodiment 7 is a chip module according to one of the exemplary embodiments 1 to 6, wherein the lower layer is manufactured by means of a coating process from a group of coating processes, wherein the group comprises: wet chemical coating by immersion, free jet plasma coating, chemical vapor deposition, hot wire activated vapor deposition and physical vapor deposition.

[0049] Embodiment 8 is a chip module according to one of embodiments 1 to 7, wherein the at least one organic silicon compound comprises at least one compound selected from a group consisting of: Si-O, Si-N, Si-C, Si-OH and Si-H.

[0050] Embodiment 9 is a chip module according to any one of embodiments 1 to 8, wherein the at least one organic silicon compound comprises at least one compound selected from the group consisting of: organosilane, organosilanol, organochlorosilane, siloxane, silicon, polysilizae and carbosilane, and / or wherein the at least one carbon compound comprises at least one compound selected from the group consisting of: amorphous carbon, diamond, graphene and graphite.

[0051] Exemplary embodiment 10 is a method for manufacturing a chip module. The method comprises coating a contact surface for contact-based communication with a reader, which has a metal base, with a lower layer of an organic silicon compound and / or a carbon compound, and coating the lower layer with an upper layer of silicon oxide, wherein the double layer of the lower and upper layers has a thickness that exhibits an electrical surface contact resistance of at most 500 mΩ according to ISO 7810 when measured according to ISO 10373-1.

[0052] Embodiment 11 is a method according to embodiment 10, wherein the contact surface has a gold layer as the uppermost metal layer, which forms a common interface with the lower layer.

[0053] Embodiment 12 is a method according to embodiment 11, wherein the gold layer has a layer thickness in a range of less than 20 nm, for example in a range of approximately 10 nm to less than 20 nm.

[0054] Embodiment 13 is a method according to one of embodiments 10 to 12, wherein the upper layer has a layer thickness in a range of about 75 nm to about 85 nm, for example about 80 nm.

[0055] Embodiment 14 is a method according to one of embodiments 10 to 13, wherein the upper layer is manufactured by plasma coating.

[0056] Embodiment 15 is a method according to one of embodiments 10 to 14, wherein the double layer has a layer thickness in a range of approximately 90 nm to approximately 200 nm.

[0057] Exemplary embodiment 13 is a method according to one of the exemplary embodiments 10 to 15, wherein the lower layer is manufactured by means of a coating method from a group of coating methods, wherein the group comprises: wet chemical coating by immersion, free jet plasma coating, chemical vapor deposition, hot wire activated vapor deposition and physical vapor deposition.

[0058] Embodiment 13 is a method according to one of embodiments 10 to 16, wherein the at least one organic silicon compound comprises at least one compound selected from a group consisting of: Si-O, Si-N, Si-C, Si-OH and Si-H.

[0059] Embodiment 13 is a method according to any of embodiments 10 to 17, wherein the at least one organic silicon compound comprises at least one compound selected from the group consisting of: organosilane, organosilanol, organochlorosilane, siloxane, silicon, polysilizae and carbosilane, and / or wherein the at least one carbon compound comprises at least one compound selected from the group consisting of: amorphous carbon, diamond, graphene and graphite.

[0060] It should be noted that the description and drawings merely illustrate the principles of the proposed methods and devices. A person skilled in the art will be able to implement various arrangements which, although not explicitly described or shown here, embody the principles of the invention and are included within its scope. Furthermore, all examples and embodiments outlined in this document are, in principle and expressly, intended only for explanatory purposes to help the reader understand the principles of the proposed methods and devices. Moreover, all statements in this document that describe principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to include their equivalents.

Claims

[1] Chip module (101), comprising: • a contact surface (102) for contact-based communication with a reader; wherein the contact surface (102) comprises a metal; and • a coating of the contact surface (102) with a double layer (104) consisting of a lower layer (104u) of an organic silicon compound and / or a carbon compound and an upper layer (104o) of silicon oxide (SiO2), • wherein the upper layer (104o) has a layer thickness in the range of 75 nm to 85 nm; and • wherein the double layer (104) has a layer thickness in the range of 90 nm to 200 nm. [2] Chip module (101) according to claim 1, wherein the contact surface (102) has a gold layer as the uppermost metal layer which forms a common interface with the lower layer. [3] Chip module (101) according to claim 2, wherein the gold layer has a layer thickness in a range of less than 20 nm, for example in a range of approximately 10 nm to less than 20 nm. [4] Chip module (101) according to any one of claims 1 to 3, wherein the upper layer (104o) is manufactured by plasma coating. [5] Chip module (101) according to any one of claims 1 to 4, wherein the lower layer (104u) is manufactured by a coating method from a group of coating methods, the group comprising: • wet chemical coating by immersion; • Free-jet plasma coating; • chemical vapor deposition; • Hot-wire activated vapor deposition; and • Physical gas phase separation. [6] Chip module (101) according to any one of claims 1 to 5, wherein the at least one organic silicon compound comprises at least one compound selected from a group consisting of: • Si-O, • Si-N, • Si-C, • Si-OH, and • Si-H. [7] Chip module (101) according to any one of claims 1 to 6, wherein the at least one organic silicon compound comprises at least one compound selected from a group consisting of: • Organosilane, • Organosilanol, • Organochlorosilane, • Siloxane, • Silicone, • Polysilica, and • Carbosilane; and / or wherein the at least one carbon compound comprises at least one compound selected from a group consisting of: • amorphous carbon, • Diamond, • Graphs, and • Graphite. [8] Method for manufacturing a chip module comprising the method: • Coating a contact surface for contact-based communication with a reader, which has a metal, with a bottom layer of an organic silicon compound and / or a carbon compound (310); and • Coating the lower layer with an upper layer of silicon oxide, • wherein the upper layer (104o) has a layer thickness in the range of 75 nm to 85 nm; and • wherein the double layer (104) has a layer thickness in the range of 90 nm to 200 nm. [9] Method according to claim 8, wherein the contact surface has a gold layer as the uppermost metal layer which forms a common interface with the lower layer. [10] Method according to claim 9, wherein the gold layer has a layer thickness in a range of less than 20 nm, for example in a range of approximately 10 nm to less than 20 nm. [11] Method according to any one of claims 8 to 10, wherein the upper layer is manufactured by plasma coating. [12] Method according to any one of claims 8 to 11, wherein the lower layer is produced by a coating method from a group of coating methods, the group comprising: • wet chemical coating by immersion; • Free-jet plasma coating; • chemical vapor deposition; • Hot-wire activated vapor deposition; and • Physical gas phase separation. [13] Method according to any one of claims 8 to 12, wherein the at least one organic silicon compound comprises at least one compound selected from a group consisting of: • Si-O, • Si-N, • Si-C, • Si-OH, and • Si-H. [14] Method according to any one of claims 8 to 13, wherein the at least one organic silicon compound comprises at least one compound selected from a group consisting of: • Organosilane, • Organosilanol, • Organochlorosilane, • Siloxane, • Silicone, • Polysilica, and • Carbosilane; and / or wherein the at least one carbon compound comprises at least one compound selected from a group consisting of: • amorphous carbon, • Diamond, • Graphs, and • Graphite.

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