POWER SEMICONDUCTOR ARRANGEMENT WITH AN EMBEDDED POWER SEMICONDUCTOR DIE AND METHOD FOR MANUFACTURING THE SAME

Abstract

A power semiconductor arrangement comprising: a first power semiconductor chip comprising a first side and an opposite second side, a first metal substrate comprising a first side and an opposite second side, wherein the first side comprises a recess, and wherein the first power semiconductor chip is arranged in the recess such that the second side of the first power semiconductor chip faces a bottom side of the recess, a circuit board comprising a first side and an opposite second side, wherein the first power semiconductor chip and the first metal substrate are embedded in the circuit board between the first and second sides of the circuit board, a power electronics substrate arranged under the second side of the circuit board and coupled to a metal layer on the second side of the circuit board via a first solder connection, and a dielectric material layer,which is arranged between the second side of the printed circuit board and the power electronics substrate and is arranged laterally next to the first solder connection, wherein the dielectric material layer couples the printed circuit board to the power electronics substrate via a fusion connection.

Description

TECHNICAL FIELD

[0001] This disclosure generally relates to a power semiconductor device having an embedded power semiconductor die and a method for manufacturing a power semiconductor device. BACKGROUND

[0002] In many power electronics applications, such as traction inverters, there may be specific requirements that must be met by the application's components. Such requirements may include, for example, one or more of low thermal resistance, low stray inductance, and low development and manufacturing costs. Chip embedding may be a technology that can help meet these requirements. However, properly electrically isolating an embedded chip from a heat sink can be challenging (for example, there may be unresolved issues regarding how to fabricate a ceramic substrate suitable for embedding or how to properly embed a ceramic substrate into a laminate).Improved power semiconductor devices and improved methods for manufacturing a power semiconductor device can help solve these and other problems. SUMMARY

[0003] Various aspects relate to a power semiconductor arrangement, comprising: a first power semiconductor chip comprising a first side and an opposite second side, a first metal substrate comprising a first side and an opposite second side, wherein the first side comprises a recess, and wherein the first power semiconductor chip is arranged in the recess such that the second side of the first power semiconductor chip faces a bottom side of the recess, a printed circuit board comprising a first side and an opposite second side, wherein the first power semiconductor chip and the first metal substrate are embedded in the printed circuit board between the first and second sides of the printed circuit board, a power electronics substrate arranged under the second side of the printed circuit board and coupled to a metal layer on the second side of the printed circuit board via a first solder connection,and a dielectric material layer disposed between the second side of the circuit board and the power electronics substrate and disposed laterally adjacent to the first solder connection, wherein the dielectric material layer couples the circuit board to the power electronics substrate via a fusion bond.

[0004] Various aspects relate to a method for manufacturing a power semiconductor device, the method comprising: providing an embedding part comprising: a first power semiconductor chip comprising a first side and an opposite second side, a first metal substrate comprising a first side and an opposite second side, wherein the first side comprises a recess, and wherein the first power semiconductor chip is arranged in the recess such that the second side of the first power semiconductor chip faces a bottom side of the recess, and a circuit board comprising a first side and an opposite second side, wherein the first power semiconductor chip and the first metal substrate are embedded in the circuit board between the first and second sides of the circuit board; arranging a power electronics substrate under the second side of the circuit board;Disposing a dielectric material layer between the second side of the circuit board and the power electronics substrate; coupling the power electronics substrate to a metal layer on the second side of the circuit board via a first solder connection; and coupling the power electronics substrate to the circuit board via a fused connection formed using the dielectric material layer, wherein the dielectric material layer is arranged laterally adjacent to the first solder connection. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The accompanying drawings illustrate examples and, together with the description, serve to explain principles of the disclosure. Other examples and many of the intended advantages of the disclosure will become readily apparent in view of the following detailed description. The elements of the drawings are not necessarily to scale relative to one another. Like reference numerals designate corresponding similar parts. Fig. 1 shows a schematic sectional view of a power semiconductor arrangement with a power semiconductor die embedded in a circuit board and a power electronics substrate arranged on a bottom side of the circuit board. Fig. 2 shows a schematic sectional view of another power semiconductor arrangement, wherein two power semiconductor dies are embedded in the circuit board and electrically connected to each other, and wherein portions of a metal layer of the power electronics substrate under the two dies are electrically insulated from each other by a dielectric material layer. The Fig. 3A to Fig. 3D show the power semiconductor arrangement of Fig. 2 in various stages of manufacture according to an exemplary method for manufacturing a power semiconductor device. Fig. 4 shows a further power semiconductor device, wherein the dielectric material layer is provided in the form of a molded body. Fig. 5 shows another power semiconductor device configured for double-sided cooling. Fig. 6 is a flow diagram of an exemplary method for manufacturing a power semiconductor device. DETAILED DESCRIPTION

[0006] In the following detailed description, well-known structures and elements are shown in schematic form to facilitate the description of one or more aspects of the disclosure. In this regard, directional terminology such as "top," "bottom," "left," "right," "upper," "lower," etc., is used with reference to the orientation of the described figure(s). Because components of the disclosure can be positioned in a variety of orientations, the directional terminology is used for illustrative purposes only. It is understood that other examples may be used and structural or logical changes may be made.

[0007] Furthermore, although a particular feature or aspect of an example may be disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for a given or particular application, unless expressly stated otherwise or technically limited. Furthermore, to the extent the terms "including," "having," "with," or other variations thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprising." The terms "coupled" and "connected" may be used together with derivatives thereof.It is understood that these terms can be used to indicate that two elements cooperate or interact with each other, whether or not they are in direct physical or electrical contact; intervening elements or layers may be provided between the "bonded," "attached," or "connected" elements. However, it is also possible for the "bonded," "attached," or "connected" elements to be in direct contact with each other. Furthermore, the term "exemplary" is intended merely as an example and not as the best or optimal.

[0008] In several examples, layers or layer stacks are applied to one another, or materials are applied or deposited onto layers. It is understood that any such terms as "applied" or "deposited" are intended to cover literally all types and techniques of applying layers to one another. In particular, they are intended to cover techniques in which layers are applied all at once, such as lamination techniques, as well as techniques in which layers are deposited in a sequential manner, such as molding.

[0009] An efficient power semiconductor device and an efficient method for manufacturing a power semiconductor device can, for example, reduce material consumption, ohmic losses, chemical waste, etc., thus enabling energy and / or resource savings. Improved power semiconductor devices and improved methods for manufacturing a power semiconductor device, as specified in this description, can thus at least indirectly contribute to green technology solutions, i.e., climate-friendly solutions that mitigate energy and / or resource use.

[0010] Fig. 1 shows a sectional view of a power semiconductor device 100 including a first power semiconductor die 110, a first metal substrate 120, a printed circuit board (PCB) 130, a power electronics substrate 140, and a dielectric material layer 150.

[0011] The power semiconductor device 100 may be configured to operate (e.g., switch) with a high electrical current, e.g., a current of 1 A or more, or 10 A or more, or 100 A or more, and / or to operate with a high voltage, e.g., a voltage of 500 V or more, or 1 kV or more, or 1.2 kV or more, or 2 kV or more.

[0012] The power semiconductor device 100 may comprise or be part of any suitable electrical circuit, for example, a converter circuit, an inverter circuit, a half-bridge circuit, a full-bridge circuit, etc. The power semiconductor device 100 may, for example, be configured for use in automotive applications. The power semiconductor device 100 may, for example, be configured for use in a traction inverter.

[0013] The first power semiconductor die 110 comprises a first side 111 and an opposite second side 112. The first power semiconductor die 110 may, for example, comprise a first power electrode on the first side 111 and a second power electrode on the second side 112. According to one example, the first power electrode is a source electrode or an emitter electrode, and the second power electrode is a drain electrode or a collector electrode. According to another example, it is the other way around. The first power semiconductor die 110 may further comprise a gate electrode, which may, for example, be arranged on the first side.

[0014] According to one example, the power semiconductor arrangement 100 comprises exclusively the first power semiconductor die 110. According to another example, the power semiconductor arrangement comprises a plurality of (power) semiconductor dies. The semiconductor dies may all be of the same die type or of different die types.

[0015] In the case where the power semiconductor device 100 comprises a plurality of semiconductor dies, each of the semiconductor dies may be arranged on a separate metal substrate. However, it is also possible for at least some of the semiconductor dies to be arranged on a common metal substrate.

[0016] The first metal substrate 120 comprises a first side 121 and an opposite second side 122. The first side 121 comprises a recess 123 and the first power semiconductor chip 110 is arranged in the recess 123 such that the second side 112 of the first power semiconductor chip 110 faces a bottom side of the recess 123.

[0017] The first metal substrate 120 may, for example, be a metal block. The first metal substrate 120 may, for example, be a part that has been singulated from a metal sheet, e.g., by punching, cutting, etching, or milling. The first metal substrate 120 may comprise or consist of any suitable metal or metal alloy. The first metal substrate 120 may, for example, comprise or consist of Al or Cu.

[0018] The first metal substrate 120 may have any suitable dimensions. For example, the first metal substrate 120 may have a length and / or a width (where the length and width are measured parallel to the first and second sides 121, 122) in the range of about 5 mm to about 10 cm. The lower limit of this range may also be about 10 mm or about 15 mm or about 2 cm or about 3 cm or about 4 cm or about 5 cm, and the upper limit may also be about 9 cm or about 8 cm or about 7 cm or about 6 cm. For example, the first metal substrate 120 may have a thickness (where the thickness is measured perpendicular to the first and second sides 121, 122) in the range of about 500 μm to about 10 mm. The lower limit of this range may also be about 800 µm or about 1 mm or about 1.27 mm or about 1.5 mm or about 2 mm or about 3 mm or about 4 mm and the upper limit may also be about 9 mm or about 8 mm or about 7 mm or about 6 mm or about 5 mm.

[0019] The recess 123 can be formed, for example, by one or more of punching, milling, and etching the first side 121 of the first metal substrate 120. The recess 123 can, for example, have a length and / or a width in the range of about 2 mm to about 5 cm. The lower limit of this range can also be about 3 mm or about 4 mm or about 5 mm or about 6 mm or about 8 mm or about 10 mm or about 15 mm, and the upper limit can also be about 4 cm or about 3 cm or about 2 cm. The recess 123 can, for example, have a depth in the range of about 50 µm to about 1 mm. The lower limit of this range may also be about 80 µm or about 100 µm or about 137 µm or about 150 µm or about 200 µm or about 300 µm and the upper limit may also be about 800 µm or about 600 µm or about 400 µm.

[0020] According to one example, the first metal substrate 120 is configured to act as a heat spreader for distributing heat generated by the first power semiconductor chip 110 during operation. Additionally or alternatively, the first metal substrate 120 may be electrically connected to the first power semiconductor chip 110 (in particular, to the second power electrode on the second side 112 of the power semiconductor chip 110), and the first metal substrate 120 may be configured to connect the power semiconductor chip 110 to other parts of the power semiconductor device 100 (e.g., to a redistribution layer). The first power semiconductor chip 110 may, for example, be soldered, sintered, or glued to the bottom side of the recess 123 with conductive adhesive.

[0021] The PCB 130 includes a first side 131 and an opposite second side 132, with the first power semiconductor chip 110 and the first metal substrate 120 embedded within the PCB 130 between the first and second sides 131, 132. The power semiconductor chip 110 and the first metal substrate 120 may be embedded into the PCB 130 such that no part of the power semiconductor chip 110, and possibly no part of the first metal substrate 120, is exposed from the PCB 130.

[0022] The PCB 130 may comprise any suitable dielectric material, for example, a laminate material such as FR-4. The PCB 130 may additionally comprise any suitable number of metal layers disposed on and / or within the dielectric material. Such metal layer(s) may comprise or consist of, for example, Al or Cu. Such metal layer(s) may be configured as electrical redistribution layer(s) and / or may be configured for heat dissipation.

[0023] In the Fig. In the example shown in Figure 1, a plurality of embedded redistribution layers 133 are shown. The redistribution layers 133 may be arranged between the first and second sides 131, 132 of the circuit board 130. The redistribution layers 133 may, for example, be electrically connected to the first power electrode on the first side 111 of the power semiconductor chip 110 and / or to the first metal substrate 120.

[0024] The PCB 130 may have any suitable dimensions. For example, the PCB 130 may have a length and / or width (where the length and width are measured parallel to the first and second sides 131, 132) in the range of about 1 cm to about 20 cm. The lower limit of this range may also be about 2 cm, or about 4 cm, or about 6 cm, or about 8 cm, and the upper limit may also be about 18 cm, or about 16 cm, or about 14 cm, or about 12 cm, or about 10 cm. For example, the PCB 130 may have a thickness (where the thickness is measured between the first and second sides 131, 132) in the range of 2 mm to 5 cm. The lower limit of this range may also be about 4 mm, or about 6 mm, or about 8 mm, or about 1 cm, and the upper limit may also be about 4 cm, or about 3 cm, or about 2 cm, or about 1.5 cm.

[0025] The power electronics substrate 140 is disposed beneath the second side 132 of the circuit board 130. The power electronics substrate 140 is coupled to a metal layer 134 on the second side 132 of the circuit board 130 via a first solder joint 160. According to another example, a sintered joint is used instead of a solder joint.

[0026] The power electronics substrate 140 may, for example, include a first metal layer 141, a second metal layer 142, and an insulating layer 143 (e.g., a ceramic layer) disposed between the metal layers 141, 142. The power electronics substrate 140 may, for example, be a direct copper bonded (DCB), direct aluminum bonded (DAB), active metal brazed (AMB), or insulated metal substrate (IMS) type substrate.

[0027] For example, the power electronics substrate 140 may cover the entire second side 132 of the circuit board 130 or the power electronics substrate 140 may cover only a portion of the second side 132 (the latter case is shown in Fig. 1). The power electronics substrate 140 may, for example, cover 20% or more, or 30% or more, or 50% or more, or 70% or more, or 90% or more of the second side 132.

[0028] The power electronics substrate 140 may be configured to be coupled to a heat sink such that the second metal layer 142 faces the heat sink. The power electronics substrate 140 may be configured to electrically isolate the heat sink from the first power semiconductor chip 110 and the first metal substrate 120. This may be necessary, for example, because the first metal substrate 120 may be electrically connected to the metal layer 134 on the second side of the circuit board 130 through one or more electrical connectors such as vias.

[0029] The dielectric material layer 150 is disposed between the second side 132 of the circuit board 130 and the power electronics substrate 140. The dielectric material layer 150 is further disposed laterally adjacent to the first solder connection 160. The dielectric material layer 150 couples the circuit board 130 to the power electronics substrate 140 via a fused connection.

[0030] The fused bond may be formed, for example, by heating the dielectric material layer 150 such that the dielectric material layer 150 at least partially liquefies, pressing the at least partially liquefied dielectric material against the second side 132 of the circuit board 130, and allowing the at least partially liquefied dielectric material to solidify.

[0031] As in the example of Fig. As shown in Figure 1, the dielectric material layer 150 may be in direct contact with dielectric material of the circuit board 130 (e.g., a laminate material such as FR-4 or a solder mask). However, according to another example, it is also possible for the dielectric material layer 150 to be in direct contact with the metal layer 134 of the circuit board 130.

[0032] The dielectric material of the dielectric material layer 150 may be required to meet one or more or all of the following requirements: electrically insulating; reliably adhering to the first metal layer 141 or the dielectric (e.g., ceramic) layer 143 of the power electronics substrate 140 and to the metal layer 134 or the dielectric material of the circuit board 130; long-term stability for temperatures up to about 150°C or even about 175°C; short-term elasticity for temperatures up to about 200°C.

[0033] The dielectric material layer 150 may, for example, comprise or consist of a thermoplastic material. The dielectric material layer 150 may, for example, comprise or consist of one or more of an adhesive, a tape, silicone, and paste. The adhesive, silicone, or tape may be cured during a soldering process that provides the first solder connection 160.

[0034] Fig. 2 shows another power semiconductor device 200, which may be similar or identical to the power semiconductor device 100, except for the differences described below.

[0035] In particular, the power semiconductor device 200 may include all components described with respect to the power semiconductor device 100, and the power semiconductor device 200 additionally includes a second power semiconductor chip 210 and a second metal substrate 220.

[0036] The second power semiconductor chip 210 comprises a first side 211 and an opposite second side 212. The second metal substrate 220 comprises a first side 221 and an opposite second side 222, wherein the first side 221 comprises a recess 223, and wherein the second power semiconductor chip 210 is arranged in the recess 223 such that the second side 212 of the second power semiconductor chip 210 faces a bottom side of the recess 223. Furthermore, the second power semiconductor chip 210 and the second metal substrate 220 are embedded in the circuit board 130 laterally next to the first metal substrate 120.

[0037] The first and second power semiconductor chips 110, 210 may be connected via one or more redistribution layers 133 of the circuit board 130 (and possibly via the second metal substrate 220, see Fig. 2) be electrically connected. The connected semiconductor dies 110, 210 can, for example, provide a half-bridge circuit.

[0038] The first metal layer 141 of the power electronics substrate 140 includes a first portion 141_1 disposed vertically below the first metal substrate 120 and a second portion 141_2 disposed vertically below the second metal substrate 220. The second portion 141_2 may be coupled to the metal layer 134 on the second side 132 of the circuit board 130 by a second solder joint 230.

[0039] A gap between the first portion 141_1 and the second portion 141_2 is filled by the dielectric material layer 150. In this way, the dielectric material layer 150 can electrically insulate the first and second portions 141_1, 141_2 from each other. A strength of electrical insulation provided by the dielectric material layer 150 filling the gap can be, for example, 500 V or more, or 800 V or more, or 1 kV or more, or 1.2 kV or more, or 2 kV or more.

[0040] The power electronics substrate 140 and the dielectric material layer 150 can provide a reliable, yet comparatively cost-effective way to electrically isolate the second power electrodes arranged on the second sides 112, 212 of the first and second power semiconductor chips 110, 210, both from each other and from a heat sink. In other words, there is no need to provide an insulating layer between the first sides 121, 221 and the second sides 122, 222 of the first and second metal substrates 120, 220, since the required electrical insulation is provided by the power electronics substrate 140 and the dielectric material layer 150 outside the circuit board 130.

[0041] The Fig. 3A to Fig. 3D show the power semiconductor device 200 in various stages of manufacture according to an exemplary method for manufacturing a power semiconductor device.

[0042] As in Fig. 3A, the power electronics substrate 140 is provided. The upper part of Fig. 3A shows a top view and the lower part shows a sectional view of the power electronics substrate 140. In the Fig. In the example shown in Figure 3A, the first metal layer 141 of the power electronics substrate 140 comprises two sections 141_1 and 141_2. However, the first metal layer 141 may comprise any suitable number of sections (the number, arrangement, and dimensions of these sections may correspond to the number, arrangement, and dimensions of metal substrates in the circuit board 130).

[0043] As in Fig. As shown in Figure 3B, solder material 300 is deposited on the first metal layer 141 of the power electronics substrate 140. The solder material 300 can be deposited, for example, in liquid form or as a paste.

[0044] As in Fig. As shown in Figure 3C, the dielectric material of the dielectric material layer 150 is deposited on the power electronics substrate 140. For example, the dielectric material may be deposited in the form of a frame configured to surround the first and second portions 141_1, 141_2 of the first metal layer 141. According to another example, the dielectric material is deposited in liquid form.

[0045] A width w of the gap between the first and second sections 141_1, 141_2 of the first metal layer 141 can, for example, range from approximately 0.5 mm to approximately 5 mm. The lower limit of this range can also be approximately 1 mm, or approximately 1.5 mm, or approximately 2 mm, and the upper limit can also be approximately 4 mm or approximately 3 mm. A height z of the dielectric material layer 150 can, for example, range from approximately 50 µm to approximately 200 µm. The lower limit of this range can also be approximately 100 µm, and the upper limit can also be approximately 150 µm.

[0046] As in Fig. As shown in Figure 3D, the circuit board 130 is provided with the power semiconductor dies 110, 210 and the metal substrates 120, 220. Heat and possibly also pressure are applied to form the solder connections 160, 230 using the solder material 300 and to form the fused connection using the dielectric material of the dielectric material layer 150, as described above.

[0047] Fig. 4 shows another power semiconductor device 400, which may be similar or identical to the power semiconductor devices 100 and 200, except for the differences described below.

[0048] In particular, in the power semiconductor device, the dielectric material layer 150 is provided in the form of a molded body. The molded body can be manufactured, for example, using a process such as compression molding, injection molding, or transfer molding. According to one example, the molded body partially or completely covers the second side 132 of the circuit board 130, and the molded body can also partially or completely cover the first side 131 and / or lateral sides connecting the first and second sides 131, 132 of the circuit board 130.

[0049] Fig. 5 shows another power semiconductor device 500, which may be similar or identical to the power semiconductor devices 100 to 400, except for the differences described below.

[0050] In particular, the power semiconductor device 500 is configured for double-sided cooling (DSC), meaning that a first heat sink may be arranged over the first side 131 of the circuit board 130 and a second heat sink may be arranged over the second side 132 of the circuit board 130. To couple to both heat sinks, the power semiconductor device 500 may include the power electronics substrate 140 arranged on the second side 132 and another power electronics substrate 510 arranged on the first side 131.

[0051] The further power electronics substrate 510 may be mechanically coupled to the circuit board 130 via a further fuse link formed using a further dielectric material layer 150, in a similar manner as described with respect to the power electronics substrate 140. Furthermore, the circuit board 130 of the power semiconductor device 500 may comprise a further metal layer 134 exposed from the first side 131 of the circuit board, and the further power electronics substrate 510 may be soldered to this further metal layer 134. The further dielectric material layer 150 may, of course, also be configured to electrically insulate portions of a metal layer of the further power electronics substrate 510 from one another, as described above with respect to the dielectric material layer 150.

[0052] According to one example, a molding process is used to form the dielectric material layers 150 between the power electronics substrates 140, 510 and the circuit board 130, as described with respect to the power semiconductor device 400. According to another example, the dielectric material layers 150 are formed as described with respect to the power semiconductor device 100.

[0053] Fig. 6 is a flowchart of a method 600 for manufacturing a power semiconductor device. The method 600 can be used, for example, to manufacture power semiconductor devices 100 to 500.

[0054] The method 600 includes, at 601, a process of providing an embedding part, wherein the embedding part comprises: a first power semiconductor chip comprising a first side and an opposite second side; a first metal substrate comprising a first side and an opposite second side, wherein the first side comprises a recess, and wherein the first power semiconductor chip is arranged in the recess such that the second side of the first power semiconductor chip faces a bottom side of the recess; and a circuit board comprising a first side and an opposite second side, wherein the first power semiconductor chip and the first metal substrate are embedded in the circuit board between the first and second sides of the circuit board; the method 600 includes, at 602, a process of arranging a power electronics substrate under the second side of the circuit board;at 603, a process of disposing a dielectric material layer between the second side of the circuit board and the power electronics substrate; at 604, a process of coupling the power electronics substrate to a metal layer on the second side of the circuit board via a first solder joint; and at 605, a process of coupling the power electronics substrate to the circuit board via a fused joint formed using the dielectric material layer, wherein the dielectric material layer is disposed laterally adjacent to the first solder joint. EXAMPLES

[0055] In the following, the power semiconductor device and the method for manufacturing a power semiconductor device are explained in more detail using specific examples. Example 1 is a power semiconductor arrangement comprising: a first power semiconductor chip comprising a first side and an opposite second side, a first metal substrate comprising a first side and an opposite second side, wherein the first side comprises a recess, and wherein the first power semiconductor chip is arranged in the recess such that the second side of the first power semiconductor chip faces a bottom side of the recess, a circuit board comprising a first side and an opposite second side, wherein the first power semiconductor chip and the first metal substrate are embedded in the circuit board between the first and second sides of the circuit board, a power electronics substrate arranged below the second side of the circuit board and coupled to a metal layer on the second side of the circuit board via a first solder connection, and a dielectric material layer,which is arranged between the second side of the printed circuit board and the power electronics substrate and is arranged laterally next to the first solder connection, wherein the dielectric material layer couples the printed circuit board to the power electronics substrate via a fusion connection. Example 2 is the power semiconductor device according to Example 1, wherein the power electronics substrate comprises an electrically insulating layer arranged between a first and a second metal layer, wherein the first metal layer faces the circuit board. Example 3 is the power semiconductor device of Example 2, wherein the second metal layer of the power electronics substrate is configured to be coupled to a heat sink. Example 4 is the power semiconductor device according to one of the preceding examples, wherein the power electronics substrate is a substrate of the type direct copper bonded, direct aluminum bonded, active metal brazed or insulated metal substrate. Example 5 is the power semiconductor device according to any one of the preceding examples, wherein the first power semiconductor chip comprises a first power electrode on the first side and a second power electrode on the second side, and wherein the second power electrode is electrically connected to the first metal substrate. Example 6 is the power semiconductor device of Example 5, wherein the circuit board comprises one or more embedded redistribution layers disposed between the first and second sides, wherein the one or more redistribution layers are electrically connected to the first power electrode and / or to the first metal substrate. Example 7 is the power semiconductor device according to any one of the preceding examples, wherein the dielectric material of the dielectric material layer comprises or consists of a thermoplastic material. Example 8 is the power semiconductor device according to any one of Examples 1 to 6, wherein the dielectric material of the dielectric material layer comprises or consists of a molding material. Example 9 is the power semiconductor arrangement according to any one of the preceding examples, further comprising: a second power semiconductor chip comprising a first side and an opposite second side, a second metal substrate comprising a first side and an opposite second side, wherein the first side comprises a recess, and wherein the second power semiconductor chip is arranged in the recess such that the second side of the second power semiconductor chip faces a bottom side of the recess, wherein the second power semiconductor chip and the second metal substrate are embedded in the circuit board between the first and the second side of the circuit board and laterally next to the first metal substrate, wherein a first metal layer of the power electronics substrate has a first portion arranged vertically below the first metal substrate, and a second portion,which is arranged vertically below the second metal substrate, and wherein the dielectric material layer fills a gap between the first portion and the second portion., Example 10 is the power semiconductor device of Example 9, wherein the first portion is coupled to the metal layer on the second side of the circuit board by the first solder joint and the second portion is coupled to the metal layer on the second side of the circuit board by a second solder joint. Example 11 is the power semiconductor device according to one of examples 9 or 10, wherein a width of the gap is in the range of 0.5 mm to 5 mm, in particular in the range of 1 mm to 3 mm, wherein the width is measured parallel to the second side of the circuit board. Example 12 is the power semiconductor device of any one of Examples 9 to 11, wherein the dielectric material layer filling the gap provides electrical insulation between the first and second portions of the first metal layer of the power electronics substrate of 1.2 kV or more. Example 13 is the power semiconductor module according to any one of Examples 9 to 12, wherein the first power semiconductor chip and the second power semiconductor chip are electrically connected to each other via the circuit board to form a half-bridge circuit. Example 14 is a method of manufacturing a power semiconductor device, the method comprising: providing an embedding part comprising: a first power semiconductor chip comprising a first side and an opposite second side, a first metal substrate comprising a first side and an opposite second side, wherein the first side comprises a recess, and wherein the first power semiconductor chip is arranged in the recess such that the second side of the first power semiconductor chip faces a bottom side of the recess, and a circuit board comprising a first side and an opposite second side, wherein the first power semiconductor chip and the first metal substrate are embedded in the circuit board between the first and second sides of the circuit board; arranging a power electronics substrate under the second side of the circuit board;Disposing a dielectric material layer between the second side of the circuit board and the power electronics substrate; coupling the power electronics substrate to a metal layer on the second side of the circuit board via a first solder connection; and coupling the power electronics substrate to the circuit board via a fused connection formed using the dielectric material layer, wherein the dielectric material layer is arranged laterally adjacent to the first solder connection. Example 15 is the method of Example 14, wherein disposing the dielectric material layer between the second side of the circuit board and the power electronics substrate comprises depositing a thermoplastic material on the power electronics substrate prior to disposing the power electronics substrate beneath the second side of the circuit board. Example 16 is the method of Example 14 or 15, wherein the first solder joint and the fused joint are formed during the same heating process. Example 17 is an apparatus comprising means for performing the method of any one of Examples 14 to 16.

[0056] Although the disclosure has been illustrated and described with respect to one or more implementations, changes and / or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular, with respect to the various functions performed by the above-described components or structures (assemblies, devices, circuits, systems, etc.), unless otherwise indicated, the terms (including any reference to a "means") used to describe such components are intended to correspond to any component or structure that performs the specified function of the described component (e.g., that is functionally equivalent), even if it is not structurally equivalent to the disclosed structure that performs the function in the example implementations of the disclosure illustrated herein.

Claims

[1] Power semiconductor device (100), comprising: a first power semiconductor chip (110) comprising a first side (111) and an opposite second side (112), a first metal substrate (120) comprising a first side (121) and an opposite second side (122), wherein the first side (121) comprises a recess (123) and wherein the first power semiconductor chip (110) is arranged in the recess (123) such that the second side (112) of the first power semiconductor chip (110) faces a bottom side of the recess (123), a circuit board (130) comprising a first side (131) and an opposite second side (132), wherein the first power semiconductor chip (110) and the first metal substrate (120) are embedded in the circuit board (130) between the first and second sides (131, 132) of the circuit board (130), a power electronics substrate (140) disposed beneath the second side (132) of the circuit board (130) and coupled to a metal layer (134) on the second side (132) of the circuit board (130) via a first solder connection (160), and a dielectric material layer (150) disposed between the second side (132) of the circuit board (130) and the power electronics substrate (140) and disposed laterally adjacent to the first solder connection (160), wherein the dielectric material layer (150) couples the circuit board (130) to the power electronics substrate (140) via a fused connection. [2] Power semiconductor device (100) according to claim 1, wherein the power electronics substrate (140) comprises an electrically insulating layer (143) arranged between a first and a second metal layer (141, 142), the first metal layer (141) facing the circuit board (130). [3] The power semiconductor device (100) of claim 2, wherein the second metal layer (142) of the power electronics substrate (140) is configured to be coupled to a heat sink. [4] Power semiconductor arrangement (100) according to one of the preceding claims, wherein the power electronics substrate (140) is a substrate of the type direct copper bonded, direct aluminum bonded, active metal brazed or insulated metal substrate. [5] Power semiconductor device (100) according to one of the preceding claims, wherein the first power semiconductor chip (110) comprises a first power electrode on the first side (111) and a second power electrode on the second side (112), and wherein the second power electrode is electrically connected to the first metal substrate (120). [6] The power semiconductor device (100) of claim 5, wherein the circuit board (130) comprises one or more embedded redistribution layers (133) disposed between the first and second sides (131, 132), the one or more redistribution layers (133) being electrically connected to the first power electrode and / or to the first metal substrate (120). [7] Power semiconductor device (100) according to one of the preceding claims, wherein the dielectric material of the dielectric material layer (150) comprises or consists of a thermoplastic material. [8] Power semiconductor device (100) according to one of claims 1 to 6, wherein the dielectric material of the dielectric material layer (1510) comprises or consists of a molding material. [9] Power semiconductor device (200) according to one of the preceding claims, further comprising: a second power semiconductor chip (210) comprising a first side (211) and an opposite second side (212), a second metal substrate (220) comprising a first side (221) and an opposite second side (222), wherein the first side (221) comprises a recess (223) and wherein the second power semiconductor chip (210) is arranged in the recess (223) such that the second side (212) of the second power semiconductor chip (210) faces a bottom side of the recess (223), wherein the second power semiconductor chip (210) and the second metal substrate (220) are embedded in the circuit board (130) between the first and second sides (131, 132) of the circuit board (130) and laterally adjacent to the first metal substrate (120), wherein a first metal layer (141) of the power electronics substrate (140) comprises a first portion (141_1) arranged vertically below the first metal substrate (120) and a second portion (141_2) arranged vertically below the second metal substrate (140), and wherein the dielectric material layer (150) fills a gap between the first portion (141_1) and the second portion (141_2). [10] The power semiconductor device (200) of claim 9, wherein the first portion (141_1) is coupled to the metal layer (134) on the second side (132) of the circuit board (130) by the first solder joint (160) and the second portion (141_2) is coupled to the metal layer (134) on the second side (132) of the circuit board (130) by a second solder joint (230). [11] Power semiconductor arrangement (200) according to one of claims 9 or 10, wherein a width of the gap is in the range of 0.5 mm to 5 mm, in particular in the range of 1 mm to 3 mm, wherein the width is measured parallel to the second side (132) of the printed circuit board (130). [12] The power semiconductor device (200) according to any one of claims 9 to 11, wherein the dielectric material layer (150) filling the gap provides electrical insulation between the first and second portions (141_1, 141_2) of the first metal layer (141) of the power electronics substrate (140) of 1.2 kV or more. [13] The power semiconductor module (200) according to any one of claims 9 to 12, wherein the first power semiconductor chip (110) and the second power semiconductor chip (210) are electrically connected to each other via the circuit board (130) to form a half-bridge circuit. [14] A method (600) for manufacturing a power semiconductor device, the method comprising: Providing (601) an embedding part comprising: a first power semiconductor chip comprising a first side and an opposite second side, a first metal substrate comprising a first side and an opposite second side, wherein the first side comprises a recess and wherein the first power semiconductor chip is arranged in the recess such that the second side of the first power semiconductor chip faces a bottom side of the recess, and a circuit board comprising a first side and an opposite second side, wherein the first power semiconductor chip and the first metal substrate are embedded in the circuit board between the first and second sides of the circuit board; disposing (602) a power electronics substrate under the second side of the circuit board; disposing (603) a dielectric material layer between the second side of the circuit board and the power electronics substrate; coupling (604) the power electronics substrate via a first solder connection to a metal layer on the second side of the circuit board; and Coupling (605) the power electronics substrate to the circuit board via a fusion bond formed using the dielectric material layer, wherein the dielectric material layer is arranged laterally adjacent to the first solder bond. [15] The method (600) of claim 14, wherein disposing (603) the dielectric material layer between the second side of the circuit board and the power electronics substrate comprises depositing a thermoplastic material on the power electronics substrate prior to disposing the power electronics substrate under the second side of the circuit board. [16] The method (600) of claim 14 or 15, wherein the first solder joint and the fused joint are formed during the same heating process.

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