Semiconductor device comprising a multilayer dielectric high-k gate laminate structure and a method for manufacturing the same

Abstract

A semiconductor device (1) comprising a SiC body, comprising: a drift region (10) of a first conductivity type, a body region (20) of a second conductivity type and a source region (30) of the first conductivity type; a gate structure comprising a gate electrode (50) and a gate dielectric (40) isolating the gate electrode (50) from the SiC body, the gate structure being arranged adjacent to the source region (30), the body region (20) and the drift region (10); wherein the gate dielectric (40) comprises a multi-layer laminate structure including alternating layers of a first dielectric material (41, 43) and a second dielectric material (42, 44), wherein the first and second dielectric materials have a k-value of 4 or higher, the first dielectric material (41, 43) has a conduction band offset at least 0.3 eV higher and a valence band offset at least 0.3 eV lower than the second dielectric material (42, 44), or vice versa, wherein the offset is calculated to the silicon carbide valence and conduction bands, respectively.

Description

TECHNICAL FIELDThe present disclosure relates to semiconductor devices and a method for manufacturing the same. More particularly, this specification relates to semiconductor devices, e.g., those comprising a silicon carbide (SiC) body having high-k multilayer dielectric laminate structures.BACKGROUNDIn the manufacture of semiconductors, it is desirable to improve transistor performance even as the devices become smaller due to the current scaling. The reduced scaling with conventional gate dielectrics generally creates problems in the reliability of, among other things, MOS transistors due to, e.g., short channel formation effects. SiO 2- dielectric materials may be replaced with high-k dielectric materials to improve device performance, as the actual thickness of the dielectric may be reduced by providing a similar equivalent oxide thickness (EOT). However, significant electron tunnel effects are described due to the lower band offsets of high-k gate materials compared to SiO 2.Patent application CN 1 15 116 839 A describes a dielectric material for a gate oxide of a transistor based on an SiC substrate. More specifically, a dielectric material of multiple alternating HfO 2 and Al 2 O 3- layers is described therein.Patent application US 2013 / 0 313 576 A1 describes the production and application of monocrystalline SiC having the usual structures such as drift, body and source regions for a vertical transistor.Patent application DE 10 2018 105 953 A1 describes the production of semiconductor wafers having a structure with negative capacitance in which the dielectric layer comprises one or more HfO2layers alternately stacked on top of one another and one or more ZrO2layers.The patent DE 11 2004 002 608 B4 describes semiconductor components with dielectric materials having a higher dielectric constant (dielectrics having a high K) than silicon dioxide.In view of the foregoing, the present disclosure is intended to solve the foregoing problems and simultaneously improve performance of semiconductor devices, particularly those having a SiC body, to reduce the scale of these semiconductor devices.SUMMARYAccording to an embodiment, a semiconductor device may include a silicon carbide body, hereinafter SiC body, including a drift region of a first conductivity type, a body region of a second conductivity type, a source region of the first conductivity type, and a gate structure. The gate structure may include a gate electrode and a gate dielectric isolating the gate electrode from the SiC body, wherein the gate structure may be arranged adjacent to the source region, the body region and the drift region. The gate dielectric may comprise a multilayer laminate structure including alternating layers of a first dielectric material and a second dielectric material, wherein the first and second dielectric materials have a dielectric constant (k-value) of 4 or higher. According to an embodiment, the first dielectric material may have a conduction band offset higher by at least 0.3 eV and a valence band offset lower by at least 0.3 eV than the second dielectric material, or vice versa. In the context of the present disclosure, the valence band offset and the conduction band offset are calculated on the silicon carbide valence band and the silicon carbide conduction band, respectively, unless otherwise described.According to another embodiment, the first dielectric material may have a high conduction band offset but a low valence band offset and the second dielectric material may have a low conduction band offset but a high valence band offset, or vice versa. This specific arrangement of the multilayer laminate in the gate dielectric combines the ability to use high-k materials in the gate dielectric stack without excessive tunneling currents thereover.According to the terms "high" and "low", this means that the energy levels of the conduction bands or valence bands have an offset of at least 1.0 eV, in particular 1.5 eV or more, which is to be considered high enough to suppress carrier tunnelling through the gate dielectric. An offset is considered low if the energy level of the dielectric has a difference to the valence band of less than 1.0 eV, in particular of 0.7 eV or less.In another embodiment, a semiconductor device may include a SiC body including a drift region of a first conductivity type, a body region of a second conductivity type, a source region of the first conductivity type, and a gate structure. The gate structure may include a gate electrode and a gate dielectric isolating the gate electrode from the SiC body, the gate structure being disposed adjacent to the source region, the body region and the drift region. The gate dielectric according to this embodiment may comprise a multilayer laminate structure comprising alternating layers of a first dielectric material comprising or being silicon oxide and a second dielectric material having a dielectric constant (k-value) of 4 or higher, wherein the thickness of the layers of the first dielectric material is at most 5 nm and the gate dielectric comprises layers of the first dielectric material as the first and the last layer of the multilayer laminate structure. This multilayer laminate, in combination with a regular gate dielectric, e.g., silicon oxide, in the gate dielectric enables the use of materials having high-k values in the gate dielectric stack to reduce the thickness of the gate dielectric and simultaneously avoids excessive tunnel currents thereover due to the higher dielectric constant of the dielectric material used in the multilayer laminate structure.The disclosure further describes a method of manufacturing a semiconductor device comprising a silicon carbide (SiC) body, wherein the SiC body may comprise a drift region of a first conductivity type, a body region of a second conductivity type, and a source region of the first conductivity type. The SiC body may be provided with a gate structure comprising a gate electrode and a gate dielectric insulating the gate electrode from the SiC body, wherein the gate structure may be arranged adjacent to the source region, the body region and the drift region. In this embodiment, the gate dielectric may be deposited on portions of the SiC body in a multi-layered laminate structure including alternating layers of a first dielectric material and a second dielectric material, wherein the first and second dielectric materials have a dielectric constant (k-value) of 4 or higher. According to an embodiment, the first dielectric material may have a conduction band offset higher by at least 0.3 eV and a valence band offset lower by at least 0.3 eV than the second dielectric material, or vice versa. According to another embodiment, the first dielectric material has a high conduction band offset but a low valence band offset and the second dielectric material has a low conduction band offset but a high valence band offset or vice versa, wherein the offset is calculated on the silicon carbide valence bands. According to a further alternative, the first dielectric material comprises or is silicon oxide and the second dielectric material has a dielectric constant (k-value) of 4 or higher, wherein the thickness of the layers of the first dielectric material is at most 5 nm and the gate dielectric comprises layers of the first dielectric material as the first and the last layer of the multilayer laminate structure. The method of specifically stacking high-k materials in the gate dielectric stack enables the scaling of the obtained semiconductor devices and an interface work function technique to improve the reliability and performance of these semiconductor devices.Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and upon viewing the accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGSThe present disclosure is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like reference numerals refer to similar or identical elements. The elements of the drawings are not necessarily to scale relative to each other. The features of the various illustrated examples may be combined unless they are mutually exclusive. FIG. 1 illustrates a semiconductor device according to a first embodiment comprising a planar MOSFET concept with a gate dielectric in a multi-layered laminate structure. FIG. 2 illustrates a semiconductor device according to a second embodiment comprising a trench MOSFET concept with a gate dielectric in a multi-layered laminate structure. FIG. 3 illustrates a semiconductor device according to a third embodiment, including a planar MOSFET concept including a gate dielectric in a multi-layered laminate structure and an inter-layer dielectric source metal. FIG. 4 illustrates a semiconductor device according to a fourth embodiment including a trench MOSFET concept having a gate dielectric in a multi-layered laminate structure and a source metal having an interlayer dielectric. FIG. 5 illustrates a band diagram of a gate dielectric in a multi-layered laminate structure according to an embodiment of the application. FIG. 6 illustrates a band diagram of a gate dielectric in a multi-layered laminate structure according to another embodiment of the application. FIG. 7 illustrates a band diagram of a gate dielectric in a multi-layered laminate structure according to yet another embodiment of the application. FIG. 8 illustrates a band diagram of a gate dielectric in a multi-layered laminate structure according to another alternative embodiment of the application. FIG. 9 illustrates a band diagram of a gate dielectric in a multi-layered laminate structure according to another alternative embodiment of the application.DETAILED DESCRIPTIONIn a general aspect, the semiconductor devices described herein are based on wide band gap materials, particularly power semiconductor devices comprising, for example, SiC substrates. Examples of such semiconductor devices having specific gate dielectric structures include metal oxide semiconductor field effect transistors (MOSFETs), junction field effect transistors (JFETs), or insulated gate bipolar transistors (IGBTs). Any other semiconductor devices having a dielectric gate structure are included in the general concept of the present disclosure, although not mentioned literally herein. Wide bandgap semiconductor devices are generally capable of maintaining breakdown voltages higher than conventional silicon power devices. These semiconductor devices may include a SiC body having a drift region of a first conductivity type, a body region of a second conductivity type, a source region of the first conductivity type, and a gate structure including a gate electrode and a gate dielectric insulating the gate electrode from the SiC body, the gate structure being disposed adjacent to the source region, the body region, and the drift region. Although all examples are described with respect to semiconductor devices having a SiC body, the present concept may be implemented in other wide band gap semiconductor devices based on, for example, GaN, AIN, Ga 2 O 3 and so forth.A drift region of a first conductivity type may be formed by doping the respective region of the SiC body. In the same manner, the source region may be formed by doping the respective region of the SiC body. Depending on the type of the semiconductor device, a first conductivity type may mean a doping with negative charge carriers and a second conductivity type may mean a doping with positive charge carriers (holes), for example, or vice versa. For each embodiment, the general conductivity of the first or second type is intended to be the same, however, different charge carrier concentrations may be used within each conductivity type, also known as n +- or n - or p +- or p - doped substrates or active regions.The SiC body may include a well region having higher doping levels for increasing charge transfer through the conductivity channel. Further, the SiC body may include SiC epitaxial layers of the same conductivity type as the drift region of the SiC body. Moreover, a drain electrode may be provided adjacent to the drift region of the SiC body and / or the SiC epitaxial layers. In general, the dielectric structures described herein may be used in n-channel or p-channel transistors.Generally, planar-type semiconductor devices may include a gate structure that may extend between the source region and the drain region. The gate structure may be disposed on a portion of the source region and a portion of the drain region. In some examples, a first source region and a second source region may be provided within a pnp junction, as described herein. Then, the gate structure may be disposed on the SiC body and may be disposed on a portion of the first source region and on a portion of the second source region.In FIG. 1, a planar type MOSFET is shown as an example of a semiconductor device 1 described herein. In particular, a half-cell of such a transistor is shown, while further cell structures may be configured individually in the same or a different conventional technique. The semiconductor device 1 comprises a drift region 10 of a first conductivity type (e.g. n-doped SiC), a body region 20 of a second conductivity type (e.g. p-doped SiC), a source region 30 of the first conductivity type (e.g. n-doped SiC) and a gate structure having a gate dielectric 40 and a gate electrode 50. The gate dielectric 40 isolates the gate electrode 50 from the SiC body 20.A common gate dielectric used in the gate structure is a gate oxide, for example silicon oxide, in particular SiO 2. The gate dielectric is usually exposed to high electric fields in power semiconductor devices. When SiO 2 is used, the electric fields are high due to the low dielectric constant (k value of about 3.9) and the drain-source-on-resistance (RDSON) is limited simultaneously with the operating voltage. The semiconductor devices described herein may be provided with a specific gate dielectric structure, thereby dramatically improving the RDSON compared to SiO 2- gate oxides. In addition, the gate oxide must be protected from these fields in the off state of the transistor due to the high electric fields in the SiO 2 in order not to lead to a dielectric breakdown and to a destruction of the gate oxide. The gate structure may generally include a gate dielectric and a gate electrode. Exemplary gate electrodes may be poly-Si-type or a metal gate electrode or combination materials comprising a metal. Desired metal gate properties are achieved by specifically combining the gate dielectric with the respective metal gate electrode material.In the case of a SiC body, the use of a high-k dielectric becomes important because the breakdown field in SiC and SiO 2 is similar, SiO 2 as a gate oxide may be damaged when a high reverse voltage is applied to the semiconductor device such as a transistor. With a high-k gate dielectric, this problem can be avoided with SiO 2- gate oxide structures. Therefore, the high-k dielectric structures described herein may, for example, particularly improve the performance of power transistors. Of course, the dielectric gate structures described herein may be used in other semiconductor technologies and may result in the same or different advantages over common oxide gate structures.In some examples described herein, the gate dielectric 40 comprises a multilayer laminate structure including alternating layers of a first dielectric material 41, 43 and a second dielectric material 42, 44, wherein the first and second dielectric materials have a dielectric constant (also referred to as k-value or permittivity) of 4 or higher (see FIG. 1 ). Materials having a dielectric constant of more than 4 are usually known as high-k dielectrics, wherein particularly selected high-k dielectrics may have a k value of 9 or more, in particular 20 or more. Such high-k dielectrics may be used instead of SiO 2 in the gate dielectric or in addition to SiO 2- based dielectric layers to reduce the electric field in the gate dielectric of such semiconductor devices, and are suitable for achieving improvements in breakdown performance and RDSON performance. At the same time, the gate structure may be formed in a smaller size while providing similar or even better isolation properties compared to SiO 2- gate structures in the semiconductor devices having a dielectric multilayer structure as described herein.In the examples described herein, the high-k dielectric is intended to act as an insulator. Therefore, the high-k dielectric structure requires a band offset that is sufficiently high to minimize or avoid carrier and / or hole ingress into the SiC bands of the SiC body. According to the examples, the high-k dielectric structure includes a multi-layered laminate structure that is adapted to these requirements by selecting the first dielectric material to have a high conduction band offset but a low valence band offset and selecting the second dielectric material to have a low conduction band offset but a high valence band offset. In this regard, the offset to the silicon carbide valence bands is calculated. In particular, a low conduction or valence band offset means that it is 1.0 eV or less. This allows the use of materials with a limited band gap, e.g. materials with a band gap of less than 7.0 eV. Accordingly, either the first dielectric material or the second dielectric material provides a band offset at either the valence band or the conductive band location of the SiC body that is high enough to minimize or avoid carrier and / or hole ingress. Instead of blocking hole and carrier transfer by a material with a band offset to the valence and conduction bands simultaneously, blocking is performed by two different gate dielectric materials. Due to an alternating multilayer arrangement of these two different gate dielectric materials, sufficient suppression or blocking of hole and carrier transfer may be achieved.A band diagram of an example of such a multilayer dielectric structure is shown in FIG. 5. On the left side, the valence and conduction band energies of the SiC body are shown. The band gap is 3.26 eV. At the interface to SiC, the energy levels of the first dielectric material layer of the multilayer laminate, here an HfO 2- dielectric layer, are shown. The conduction band offset calculated on the conduction band of the SiC body is shown as 0.7 eV. This is considered a low band offset in the sense of the present disclosure. The valence band offset is indicated as 1.74 eV, which is considered a high band offset. A ZrO 2- dielectric layer is shown as the next layer in this example. The conduction band offset is calculated as 1.82 eV, which means a high band offset, and the valence band offset is calculated as 0.52 eV, which means a low band offset. In this example, the energy levels of two further alternating layers of HfO 2 and ZrO 2 are shown with the respective conduction and valence band energy levels, followed by the conduction band minimum of a metal gate. This drawing shows only an example of the gate dielectric multilayer structure, and various numbers of layers may be implemented according to the technical concept described herein. Two or five or six or even more alternating dielectric layers, in particular comprising a high-k dielectric material, may be included in the multilayer laminate as described herein. The gate dielectric multilayer structure may either begin and end with the first and second gate dielectric materials, or the first and last layers of the laminate may be made of the same dielectric material, meaning either the first or second dielectric material.In FIG. 6, a band diagram of another example of a semiconductor device is given. Here, the energy levels of an example having a similar general constitution of the semiconductor device are as shown in FIG. 5, except that ZrO 2 is used as the first dielectric material and HfO 2 is used as the second dielectric material. A similar effect with respect to charge tunneling can be achieved because alternating layers of a first high-k dielectric material having a high conduction band offset and a second high-k dielectric having a high valence band offset are combined as a multilayer laminate stack in this example.In some examples, the gate dielectric provided by a multilayer structure of first and second high-k materials, particularly when arranged alternately, is capable of providing a similar equivalent oxide thickness (EOT) as compared to larger scaled devices with conventional SiO 2- gate oxide structures. As described herein, since the overall gate dielectric may be formed in a thinner layer thickness using the multi-layer structure comprising high-k dielectric materials, it is possible to meet the reduced scaling requirement of semiconductor devices while maintaining or even improving the performance of the semiconductor devices.In another embodiment, the general structure of the semiconductor device is like the planar semiconductor devices described above, but is embodied as a trench semiconductor device. FIG. 2 shows a general structure of a semiconductor having a trench configuration (half cell). In general, any examples described with respect to the planar semiconductor devices in this specification may be implemented in the trench semiconductor devices, although these examples are not repeated again here. In contrast to a planar semiconductor device, a trench semiconductor device may have a gate structure including a gate trench disposed in the SiC body 20 and adjacent to the source region 30. The gate trench may have a depth that is greater than a depth of the body region 20 and that is less than a depth of the drift region 10, wherein the gate dielectric 40 in the gate trench is arranged on a sidewall of the gate trench and a bottom surface of the gate trench. On a sidewall of the gate trench, not only includes a sidewall, for example, the sidewall in the first half cell as shown in FIG. 2, but also includes any other sidewall, for example, the sidewall of the second half cell. The gate electrode 50 may be disposed on the gate dielectric 40. The gate dielectric is fabricated and patterned into a multilayer laminate structure including alternating layers of the first dielectric material 41 and the second dielectric material 42 as shown in FIG. 2, as in the planar semiconductor devices described herein. Like the planar systems described above, the gate dielectric may include more than the two layers 41, 42 shown herein, for example two or more layers of the first dielectric material in combination with two or more layers of the second dielectric material configured alternately in the multi-layer laminate structure. Further examples may include layers of a third or further dielectric material, which may include Si-based, Al-based, or high-k dielectric materials other than the first and second dielectric materials.Further examples of semiconductor devices having the above-described general planar and trench structures are shown in FIGS. 3 and 4. A half cell of a planar MOSFET is shown in FIG. 3. The cell structure of the MOSFET as semiconductor device 1 comprises a drift region 10 of a first conductivity type (e.g. n-doped SiC), a body region 20 of a second conductivity type (e.g. p-doped SiC), a source region 30 of the first conductivity type (e.g. n-doped SiC) and a gate structure having a gate dielectric 40 and a gate electrode 50. The gate dielectric 40 isolates the gate electrode 50 from the SiC body 20. In some examples described herein, the gate dielectric 40 comprises a multilayer laminate structure including alternating layers of a first dielectric material 41, 43 and a second dielectric material 42, 44, wherein the first and second dielectric materials have a dielectric constant (also referred to as k-value or permittivity) of 4 or higher (see FIG. 3 ). Materials having a dielectric constant of more than 4 are usually known as high-k dielectrics, wherein particularly selected high-k dielectrics may have a k value of 9 or more, in particular 20 or more. Such high-k dielectrics may be used instead of SiO 2 in the gate dielectric or in addition to SiO 2- based dielectric layers to reduce the electric field in the gate dielectric of such semiconductor devices, and are suitable for achieving improvements in breakdown performance and RDSON performance. At the same time, the gate structure may be formed in a smaller size while providing similar or even better isolation properties compared to SiO 2- gate structures in the semiconductor devices having a dielectric multilayer structure as described herein.FIG. 4 shows a general structure of a semiconductor device 1 having a trench configuration (half cell). In general, any examples described with respect to the planar semiconductor devices in this specification may be implemented in the trench semiconductor devices, although these examples are not repeated again here. In contrast to a planar semiconductor device, a trench semiconductor device 1 may have a gate structure comprising a gate trench arranged in the SiC body 20 and adjacent to the source region 30. The gate trench may have a depth that is greater than a depth of the body region 20 and that is less than a depth of the drift region 10, wherein the gate dielectric 40 in the gate trench is arranged on a sidewall of the gate trench and a bottom surface of the gate trench. The gate electrode 50 may be disposed on the gate dielectric 40. The gate dielectric is fabricated and patterned into a multilayer laminate structure including alternating layers of a first dielectric material 41 and a second dielectric material 42 as shown in FIG. 4, as in the planar semiconductor devices described herein.In the two alternative embodiments of the semiconductor device 1 shown in FIGS. 3 and 4, respectively, a source metal 60 may electrically contact the source region, wherein an interlayer dielectric 65 isolates the gate electrode 50 from the source metal 60. The gate electrode 50 may be made of or include polycrystalline silicon (poly-Si) in some examples. In this case, the interlayer dielectric 65 includes a multilayer laminate structure (not shown in FIGS. 3 and 4 ) including alternating layers of a first dielectric material and a second dielectric material, the first and second dielectric materials having a dielectric constant (k-value) of 4 or higher. The first dielectric material may have a conduction band offset higher by at least 0.3 eV and a valence band offset lower by at least 0.3 eV than the second dielectric material, or vice versa. Separately or in combination, the first dielectric material may have a high conduction band offset but a low valence band offset and the second dielectric material may have a low conduction band offset but a high valence band offset. The offset (e.g., valence band offset and conduction band offset) of the first dielectric material and the second dielectric material is calculated to the SiC valence and conduction bands (e.g., conduction band minimum) on the one hand and the Fermi level of the poly-Si on the other hand. The same high-k dielectric materials as used in the gate dielectric structure described above may be implemented in the interlayer dielectric. That is, the first dielectric material may have the same characteristics as the first dielectric material (or the second dielectric material), and the second dielectric material may have the same characteristics as the second dielectric material (or the first dielectric material, respectively).In another example, the semiconductor device 1 having an interlayer dielectric 65 includes a metal gate electrode 50, and the interlayer dielectric 65 includes a multilayer laminate structure including alternating layers of a first dielectric material and a second dielectric material, wherein the first and second dielectric materials have a dielectric constant (k-value) of 4 or higher. The first dielectric material may have a conduction band offset higher by at least 0.3 eV and a valence band offset lower by at least 0.3 eV than the second dielectric material, or vice versa. Separately or in combination, the first dielectric material may have a high conduction band offset but a low valence band offset and the second dielectric material may have a low conduction band offset but a high valence band offset, where the offset is calculated on the SiC valence and conduction bands (e.g., conduction band minimum) on the one side or Fermi level of the gate metal. The high-k dielectric materials may be selected from the same materials as in the gate dielectric structure described above.The present disclosure also includes planar or trench semiconductor devices including a common gate structure, for example based on SiO 2 as gate dielectric, and a source metal electrically contacting the source region, wherein an interlayer dielectric isolates the gate electrode from the source metal. The gate electrode may be made of or comprise polycrystalline silicon (poly-Si) in some examples. In this case, the interlayer dielectric may comprise a multilayer laminate structure including alternating layers of a first dielectric material and a second dielectric material, wherein the first and second dielectric materials have a dielectric constant (k-value) of 4 or higher. The first dielectric material may have a conduction band offset higher by at least 0.3 eV and a valence band offset lower by at least 0.3 eV than the second dielectric material, or vice versa. Separately or in combination, the first dielectric material may have a high conduction band offset but a low valence band offset and the second dielectric material may have a low conduction band offset but a high valence band offset, where the offset is calculated on the poly-Si valence bands. The same high-k dielectric materials as used in the gate dielectric structure described above may be implemented in the interlayer dielectric. If the gate electrode consists of or comprises a metal gate having a conduction band minimum, the offset to the conduction band minimum of either the metal gate or the source metal may be calculated.In another embodiment, the semiconductor device may further comprise a source metal electrically contacting the source region, wherein an interlayer dielectric isolates the gate electrode from the source metal, and wherein the interlayer dielectric comprises alternating layers of a first dielectric material comprising or being silicon oxide and a second dielectric material having a dielectric constant (k-value) of 4 or higher. In this embodiment, the thickness of the layers of the first dielectric material is at most 5 nm. Further, the interlayer dielectric may include layers of the first dielectric material as the first and last layers of the multilayer laminate structure, respectively. In this embodiment, the layer thickness of the interlayer dielectric stack (e.g., the multilayer laminate structure of the interlayer dielectric) may be reduced due to the second high-k dielectric material without excessive tunnel currents across the interlayer dielectric layer stack (e.g., the multilayer laminate structure of the interlayer dielectric). Even if a high-k dielectric can improve the capacitance between the source and the gate and slow switching, such an interlayer dielectric laminate structure of high-k dielectric materials can improve the overall performance of a semiconductor device. This may, for example, actually be desirable for power MOSFETs.In another example of the semiconductor device as described in any of the above embodiments, at least one of the interlayer dielectric and the gate dielectric comprises at least two of the layers with a first dielectric material and at least two of the layers with a second dielectric material. At least two means that two, three or more layers of the first dielectric material are arranged alternately with two, three or even more layers of a second dielectric material. Alternately, a dielectric layer stack may include a layer of a first dielectric material, a layer of a second dielectric material, a layer of a first dielectric material, and a layer of a second dielectric material in this order. Optionally, further first and second dielectric layers may follow this order of layers, wherein the last layer may be of a first or a second dielectric layer type. Alternatively, the alternating layer stack may begin with a second dielectric layer, followed by a first dielectric layer, a second dielectric layer and a further first dielectric layer, for example. Thus, the terms "first" and "second" do not identify which of these layers is the layer adjacent the gate or source electrode and the SiC substrate, respectively.A semiconductor device according to another example may include an interlayer dielectric further including an interfacial dielectric layer disposed between at least a portion of the source metal and the first layer of the multilayer laminate structure. Example interfacial dielectric layers may be based on silicon oxides and / or nitrides such as silicon oxide (SiO 2) or mixed nitrides and oxides of Si. In this case, the Si-based interfacial dielectric layer may be provided as thin as possible, for example, 5 nm or less. In some examples described herein, Al-based oxides are by definition excluded to be suitably used as the first and second high-k dielectric materials. However, in these examples, the Al-based oxides, nitrides, or mixed oxides and nitrides may be disposed as the interfacial dielectric layer.The gate dielectric of another example of the semiconductor device may further include an interfacial dielectric layer disposed between at least a portion of the SiC body and the first layer of the multilayer laminate structure. Exemplary interfacial dielectric layers may be based on Si oxides and / or nitrides such as SiO 2 or mixed nitrides and oxides of Si. In this case, the Si-based interfacial dielectric layer may be provided as thin as possible, for example, 5 nm or less. In some examples described herein, Al-based oxides are by definition excluded to be suitably used as the first and second high-k dielectric materials. However, in these examples, the Al-based oxides, nitrides, or mixed oxides and nitrides may be disposed as the interfacial dielectric layer.In some examples of the semiconductor devices described herein, the first and second dielectric materials may have a band gap of less than 7.0 eV. Exemplary high-k dielectric materials are AlN (about 6.2 eV), HfO 2(5,7 eV), ZrO 2(5,6 eV), Ta 2 O 5(4,4 eV), and La 2 O 5(5,45 eV). These small bandgap materials are said not to be sufficiently blocking for holes and electron carriers in Si- or SiC-based semiconductor gate dielectric systems. However, when used in the multi-layer laminate structure as defined herein, these high-k dielectric materials prove sufficient to meet all of the requirements of the gate dielectric material when arranged in a stack of alternating layers such that the first dielectric material has a high conduction band offset but a low valence band offset and the second dielectric material has a low conduction band offset but a high valence band offset. Thus, the first significance has been overcome by this particular arrangement of at least two of these materials in the multilayer laminate structure. The specific selection of the first and second dielectric materials according to the above general concept of the present disclosure makes it possible to suppress or block the current tunnel of the holes and the electron carriers from the substrate side (e.g., SiC) and / or from the gate electrode side at the same level. In this regard, it is important that either the first or second dielectric materials have a high band offset from the conduction band of the SiC and that the other dielectric material that does not have a high band offset from the conduction band has at least one high band offset from the valence band. When this is realized in the multilayer laminate of alternating dielectric material layers, it is possible to reduce the band gap of each of the high-k dielectric materials. Thus, higher permittivity (higher k-value) materials may be suitably implemented in the gate structure. The same general concept may be similarly applied with respect to the interlayer dielectric described herein to be disposed between, for example, at least a portion of the source material and the first layer of the multilayer laminate structure.In some examples, the first and / or second dielectric material in at least some of the layers of the multilayer laminate structure may comprise composite materials including two or more different high-k materials. Thus, the permittivity and the band offset of each of the layers of the layer stack in the multi-layer laminate structure may be varied specifically according to their requirements. For example, the composite materials may include mixtures of two oxides with different cations or mixtures of oxides and nitrides of one cation, while mixtures of other combinations of two or more high-k materials may also be used.In FIGS. 7 and 8, semiconductor devices are shown having similar dielectric multilayer laminate structures as described with respect to the band diagrams shown in FIGS. 5 and 6, except that an additional interfacial dielectric layer, here a thin SiO 2- layer (thickness about 5 nm), is provided as the interfacial layer between the SiC substrate and the first layer of the multilayer laminate stack. In FIG. 7, the first layer of the multilayer stack is HfO 2 and the second layer is ZrO 2, while the order of the high-k layers is ZrO 2 and HfO 2 in the multilayer laminate stack shown in FIG. 8.The multilayer laminate structure may include further layers within the alternating layers of the first and second dielectric materials, the further layers comprising a third or further dielectric material having a high-k different from the first and second dielectric materials, according to further examples. In this regard, any of the high-k materials identified herein may be used regardless of their band offsets if the stack includes layers of the first and second dielectric materials having a sufficient thickness and band offset characteristic to suppress or block current tunneling as well as possible. Exemplary high-k materials may be those having higher band offsets than described above, for example, Si or Al oxides or mixed oxides and nitrides.Exemplary high-k materials having a high conduction band offset compared to the SiC conduction band are those having a band offset of 1.0 eV or higher, for example between about 1.0-1.5 eV and 2.7 eV. Examples of high conduction band offset materials include Al 2 O 3(1,9 eV), AIN (1.3 eV), ZrO 2(1,82 eV). High-k materials with a high valence band offset compared to the SiC valence band are those that have a band offset of 1.0 eV or higher, for example between about 1.0-1.5 eV and 2.9 eV. Examples of materials with a high valence band offset include Al 2 O 3(1,84 eV), AIN (1.7 eV), HfO 2(1,74 eV), Ta 2 O 5(1,54 eV), La 2 O 3(1,2 eV). Taking these band offset values into account, therefore, exemplary alternating layer stacks may be based on combinations of ZrO 2 / AlN or ZrO 2 / HfO 2 or ZrO 2 / La 2 O 3 or ZrO 2 / Ta 2 O 5 or AlN / Ta 2 O5bas.In some examples, the first dielectric material has an offset to the conduction band of the SiC body material of at least 1.0 eV and the second dielectric material has an offset to the valence band of the SiC body material of at least 1.0 eV. In other examples, the first dielectric material has an offset to the valence band of the SiC body material of at least 1.0 eV and the second dielectric material has an offset to the conduction band of the SiC body material of at least 1.0 eV. At least 1.0 eV may comprise any value within the range between 1.0 eV and 2.5 and 2.7 eV, respectively, as described above.According to some embodiments, it may be advantageous that the conduction band offsets and the valence band offsets of the first and second dielectric materials are not identical or similar to each other, but may have a distinct difference. Therefore, the first dielectric material and the second dielectric material may have different conduction band values and valence band values, respectively. The difference is at least 0.3 eV on the side of the conduction band or of the valence band. This difference in band values facilitates improving blocking of hole or carrier tunnelling phenomena in the semiconductor devices in which the gate dielectric and / or the interlayer dielectric are made accordingly.The semiconductor device according to an alternative or the above-identified embodiments may further include a gate dielectric having a total k-value higher than silicon oxide (SiO 2) and including a multilayer laminate structure including alternating layers of a first dielectric material having a band gap lower than 7.0 eV and a second dielectric material having a band gap lower than 7.0 eV. In this embodiment, the first dielectric material may have an offset to the conduction band of the SiC body material of at least 1.0 eV and the second dielectric material may have an offset to the valence band of the SiC body material of at least 1.0 eV. If the dielectric material is adjacent to the gate material (e.g., poly-Si or metal), the offset is calculated to the Fermi level of the gate material. Suitable high-k dielectric materials may be selected from the high-k materials identified above. In this embodiment, Al 2 O 3 having a band gap of about 7.0 eV may not fall within the definition of the first and second embodiments. However, among other things, AIN, HfO 2, ZrO 2, Ta 2 O 5, La 2 O 3 would fall within the specifically selected high-k materials that would fall within the definition used for this embodiment. As is known to those skilled in the art, these examples have a higher k value than Al 2 O 3 and make it possible to reduce the size of the semiconductor devices even further.In particular, the thickness of the gate dielectric may be further reduced if selected nitrides or oxides from this list are used. As mentioned in the embodiments described herein above, the selected first dielectric material may have a high conduction band offset but a low valence band offset and the selected second dielectric material may have a high valence band offset and a low conduction band offset, the offset being calculated on the silicon carbide valence bands.When the semiconductor device is implemented with an interlayer dielectric in addition to the above-mentioned gate dielectric or with a conventional gate dielectric, the interlayer dielectric may have a total k value higher than silicon oxide (SiO 2) and may include a multilayer laminate structure including alternating layers of a first dielectric material having a band gap of less than 7.0 eV and a second dielectric material having a band gap of less than 7.0 eV. In these embodiments, the first dielectric material may have an offset to the conduction band of the SiC body material or the Fermi level of the source metal of at least 1.0 eV, and the second dielectric material may have an offset to the valence band of the SiC body material or the Fermi level of the source metal of at least 1.0 eV. The same first and second dielectric materials as described in the previous embodiment may be implemented. In particular, AIN, HfO 2, ZrO 2, Ta 2 O 5, La 2 O 3 among others would fall within the specifically selected high-k materials that would fall within the definition used for this embodiment. As is known to those skilled in the art, these examples have a higher k value than Al 2 O 3 and make it possible to reduce the size of the semiconductor devices even further. In particular, the thickness of the interlayer dielectric can be further reduced if selected nitrides or oxides from this list are used. In particular, the selected first dielectric material may have a high conduction band offset but a low valence band offset, and the selected second dielectric material may have a high valence band offset and a low conduction band offset, wherein the offset is calculated on the silicon carbide valence and conduction bands, respectively.In some examples of the semiconductor devices according to any of the above-described embodiments, the thickness of the layers in the multi-layer laminate structure may vary over the thickness of at least one of the gate dielectric or interlayer dielectric, if present in the device structure. For example, a thick layer of a first dielectric may be combined with a thick layer of a second dielectric. The thickness may be selected such that tunnelling of holes or charge carriers through the gate dielectric or interlayer dielectric may be reduced to a low value or even blocked. Depending on the permittivity of the first and second dielectric materials used in this laminate structure, two or more alternating layers may, of course, be arranged in the dielectric structure. In some examples, the use of two layers is sufficient. However, since the dielectric material may have either a low conduction band offset or a low valence band offset to the adjacent SiC or material of the gate electrode (e.g., poly-Si or a metal gate), it is possible to suppress either electron injection from the gate electrode (high valence band offset) or electron injection from SiC (high conduction band offset) during application of a positive gate voltage. In addition, the first dielectric device having a high valence band offset may suppress electron injection of SiC during application of a negative potential to the gate. If a material with a high conduction band offset is adjacent to the SiC substrate, suppressing hole injection from the gate during the application of a negative gate voltage may be observed or guaranteed in later applications of the semiconductor devices.According to further embodiments, the semiconductor device may include a gate electrode comprising a metal gate or doped metal gate. Using a metal gate instead of polycrystalline Si allows a band technique at the gate electrode. Thus, the Fermi level of the metal gate can be adjusted to be nearly at the center of the band gap height of the adjacent dielectric material. Exemplary metal gate materials are TiN or metal gates with La or Al doping. TiN has, for example, a lower Fermi level than for high n-doped poly-Si. For example, if the TiN is doped with La, the Fermi level can be increased to higher energies. In contrast, Al doping reduces the Fermi level compared to the undoped state. Therefore, it is possible to adjust the work function of the interface by La- and / or Al-based intermediate layers. Thus, the band offset between the gate and the high-k dielectric may be increased (higher or lower energy value setting depending on the high-k conduction and valence band energies). Due to this gate work function tuning at the gate electrode, electron tunneling into the gate dielectric can be suppressed.In another embodiment described herein, a semiconductor device comprising a silicon carbide (SiC) body is configured with a drift region of a first conductivity type, a body region of a second conductivity type, and a source region of the first conductivity type. The semiconductor device may include a gate structure including a gate electrode and a gate dielectric insulating the gate electrode from the SiC body, the gate structure being disposed adjacent to the source region, the body region, and the drift region. The general constitution is as described with respect to the other embodiments. However, the gate dielectric according to this embodiment comprises a multilayer laminate structure comprising alternating layers of a first dielectric material comprising or being silicon oxide and a second dielectric material having a dielectric constant (k-value) of 4 or higher, wherein the thickness of the layers of the first dielectric material is at most 5 nm and the gate dielectric comprises layers of the first dielectric material as the first and the last layer of the multilayer laminate structure. An exemplary band diagram of a gate dielectric according to this embodiment is shown in FIG. 9. A first thick layer of SiO 2 having a total band gap of 9.0 eV is shown in FIG. 9, which is adjacent to the SiC body having a band gap of 3.26 eV. Alternating layers of HfO 2( band gap of 5.7 eV) and thinner SiO 2- layers are provided in this dielectric structure. The respective offsets to the SiC valence and conduction bands are given in FIG. 9. Generally, the first dielectric may be silicon dioxide when the superlattice of alternating layers of at least first and second dielectric materials comprises a high-k dielectric material having sufficient thickness and permittivity. Although current tunnelling has been observed when the layer thickness of silicon oxide layers is too small in conventional semiconductor devices, the arrangement with one or more alternating layers of a second dielectric material suppresses the tunnelling phenomena. Thus, the layers of a second dielectric material may be arranged alternately with a first dielectric material comprising or being SiO 2. The layer thickness of the first dielectric material may be at most 5 nm, which is rather small compared to conventional semiconductor devices based on dielectric silicon oxide structures. The high band offsets of SiO 2 allow to suppress current tunneling along with the layers of high-k dielectric material provided in an alternating multilayer structure. Of course, the second layers of dielectric material may comprise the same high-k material or may be formed of different high-k materials, i.e. at least a second high-k dielectric material and a third or fourth high-k dielectric material, arranged in combination with each other in this multilayer laminate structure, also referred to as superlattice structure. Similar effects to the other embodiments described herein were observed.In an example of the above embodiment, the multilayer laminate structure may include a third or further dielectric material layer including a material selected from a Si-based, Al-based, or high-k dielectric material other than the first and second dielectric materials. Thus, a dielectric laminate structure having a thin SiO 2- layer, a layer of a first high-k dielectric material, and one or more layers of a second and further high-k materials may be combined and repeatedly stacked in this or any other order in the dielectric laminate structure. In order to achieve the effects described above, the first, second, third and further dielectric materials may be selected to have the respective band offsets to the valence and conduction bands of the SiC.In some examples, the semiconductor device of the foregoing embodiment may provide a gate structure including a gate trench disposed in the SiC body and adjacent to the source region, the gate trench having a depth that is greater than a depth of the body region and that is less than a depth of the drift region. The gate dielectric may be disposed in the gate trench on a sidewall of the gate trench and a bottom surface of the gate trench, wherein the gate electrode may be disposed on the gate dielectric. Therefore, all features described with respect to planar embodiments of the semiconductor devices described herein may be implemented in a so-called trench semiconductor device, for example a trench MOSFET or IGBT having a trench gate structure.According to other examples, the above-mentioned semiconductor devices may further comprise a source metal electrically contacting the source region, wherein an interlayer dielectric isolates the gate electrode from the source metal. In some examples, the interlayer dielectric may comprise a multilayer laminate structure including alternating layers of a first dielectric material and a second dielectric material, wherein the first and second dielectric materials have a dielectric constant (k-value) of 4 or higher, the first dielectric material has a high conduction band offset but a low valence band offset, and the second dielectric material has a low conduction band offset but a high valence band offset, the offset being calculated on the conduction band minimum of the source metal. Although this interlayer dielectric structure is described herein with respect to embodiments including a similarly composed gate dielectric structure, these interlayer dielectrics may be suitably used in conventional semiconductor devices having, for example, silicon oxide gate dielectric structures in the same manner.According to alternative examples of semiconductor devices having an interlayer dielectric insulating the gate electrode from the source metal as described above, the interlayer dielectric may comprise alternating layers of a first dielectric material being or comprising silicon oxide and a second dielectric material having a dielectric constant (k-value) of 4 or higher, wherein the thickness of the layers of the first dielectric material is at most 5 nm and the interlayer dielectric includes layers of the first dielectric material as the first and the last layer of the multilayer laminate structure. Such alternative dielectric layer structures comprising thin silicon oxide (SiO 2-) layers may also be suitably used in conventional semiconductor devices having, for example, silicon oxide dielectric gate structures.Moreover, the disclosure provides a method for manufacturing a semiconductor device, in particular a semiconductor device comprising a silicon carbide (SiC) body, wherein the SiC body comprises a drift region of a first conductivity type, a body region of a second conductivity type and a source region of the first conductivity type, and wherein the SiC body is provided with a gate structure comprising a gate electrode and a gate dielectric isolating the gate electrode from the SiC body, wherein the gate structure is arranged adjacent to the source region, the body region and the drift region. In this regard, planar or trench structures may be provided in the semiconductor device in the usual manner known to those skilled in the art. In these semiconductor devices, the gate dielectric is deposited on portions of the SiC body in a multi-layered laminate structure that includes alternating layers of a first dielectric material and a second dielectric material. In some examples, the method includes the act of providing the multilayer structure such that the first and second dielectric materials have a dielectric constant (k-value) of 4 or higher, the first dielectric material has a high conduction band offset but a low valence band offset, and the second dielectric material has a low conduction band offset but a high valence band offset, wherein the offset is calculated on the silicon carbide valence and conduction bands, respectively. In an alternative example of the method, the method comprises the operation of providing the multilayer structure such that the first dielectric material comprises or is silicon oxide and the second dielectric material has a dielectric constant (k-value) of 4 or higher, wherein the thickness of the layers of the first dielectric material is at most 5 nm and the interlayer dielectric includes layers of the first dielectric material as the first and last layers of the multilayer laminate structure.The use or selection of the specific dielectric materials is performed as described in the embodiments with respect to the alternative semiconductor devices based on the properties and parameters of the dielectric materials, such as the k-value, the band gap, the conduction or valence band offsets to SiC, or the conduction band minimum or Fermi levels of the metals used in the substrate, source or gate structures. In this regard, the method includes acts to specifically select the material combinations such that the respective band offsets or band gap values are adjusted or varied as described above. In some examples, the Fermi level of the gate electrode may be adjusted based on the valence and conduction band offsets of the dielectric material layer adjacent the gate electrode. Thus, this enables a Fermi level technique in the metal gate depending on the combination of the high-k materials and the respective band offsets in the dielectric multilayer laminate structures used in the respective embodiment described herein. This Fermi level technique may be used, for example, to tune the band gap offsets and to improve or optimize the conduction and / or valence band offset levels to the Fermi level of the gate electrode.Although specific examples have been illustrated and described herein, those skilled in the art will appreciate that a variety of alternative and / or equivalent implementations may replace the specific examples shown and described without departing from the scope of the present disclosure. This application is intended to cover any adaptations or variations of the specific examples discussed herein. Therefore, it is intended that this disclosure be limited only by the claims and their equivalents.It should be noted that the methods and apparatuses, including preferred embodiments thereof, as set forth herein may be used alone or in combination with the other methods and apparatuses disclosed herein. In addition, the features set forth in the context of a device are also applicable to a corresponding method and vice versa. Furthermore, all aspects of the methods and apparatuses set forth in the present document may be combined as desired. In particular, the features of the claims can be combined with one another in any desired manner.It should be noted that the description and drawings merely illustrate the principles of the proposed methods and systems. Those skilled in the art will be able to implement various arrangements which, although not explicitly described or shown herein, embody the principles of the disclosure and are included in the spirit and scope thereof. Furthermore, all examples and embodiments set forth in the present document are expressly intended for purposes of illustration only to aid the reader in understanding the principles of the proposed methods and systems. Furthermore, all statements herein are intended to provide principles, aspects, and embodiments of the disclosure, as well as specific examples thereof, including equivalents thereof.

Claims

A semiconductor device (1) comprising a SiC body, comprising: a drift region (10) of a first conductivity type, a body region (20) of a second conductivity type, and a source region (30) of the first conductivity type; a gate structure comprising a gate electrode (50) and a gate dielectric (40) insulating the gate electrode (50) from the SiC body, wherein the gate structure is arranged adjacent to the source region (30), the body region (20), and the drift region (10); wherein the gate dielectric (40) comprises a multilayer laminate structure including alternating layers of a first dielectric material (41, 43) and a second dielectric material (42, 44), wherein the first and second dielectric materials have a k value of 4 or higher, the first dielectric material (41, 43) has a conduction band offset higher by at least 0.3 eV and a valence band offset lower by at least 0.3 eV than the second dielectric material (42, 44), or vice versa, wherein the offset is calculated on the silicon carbide valence and conduction bands, respectively.The semiconductor device of claim 1, wherein the first dielectric material (41, 43) has a high conduction band offset but a low valence band offset and the second dielectric material (42, 44) has a low conduction band offset but a high valence band offset or vice versa, the offset being calculated on the silicon carbide valence bands.The semiconductor device of claim 1 or 2, wherein the gate structure comprises a gate trench disposed in the SiC body and adjacent to the source region (30), wherein the gate trench has a depth that is greater than a depth of the body region (20) and that is less than a depth of the drift region (10), wherein the gate dielectric (40) in the gate trench is disposed on a sidewall of the gate trench and a bottom surface of the gate trench, and wherein the gate electrode (50) is disposed on the gate dielectric (40).The semiconductor device of any preceding claim, further comprising a source metal (60) electrically contacting the source region (30), wherein an interlayer dielectric (65) isolates the gate electrode (50) from the source metal (60), wherein the gate electrode (50) is made of or comprises polycrystalline silicon, and wherein the interlayer dielectric (65) comprises a multilayer interlayer dielectric laminate structure including alternating layers of a first dielectric material (41, 43) and a second dielectric material (42, 44), wherein the first and second dielectric materials have a k-value of 4 or higher, wherein at least one condition is fulfilled by: the first dielectric material (41, 43) has a conduction band offset higher by at least 0.3 eV and a valence band offset lower by at least 0.3 eV than the second dielectric material (42, 44), or the first dielectric material (41, 41, 43) has a high conduction band offset but a low valence band offset and the second dielectric material (42, 44) has a low conduction band offset but a high valence band offset, the offset being calculated on the SiC valence bands of the source region (30) and the Fermi level of the polycrystalline silicon or gate electrode (50).The semiconductor device of any one of claims 1 to 3, further comprising a source metal (60) electrically contacting the source region (30), wherein an interlayer dielectric (65) isolates the gate electrode (50) from the source metal (60), wherein the gate electrode (50) is or comprises a metal gate electrode, and wherein the interlayer dielectric (65) comprises a multilayer interlayer dielectric laminate structure including alternating layers of a first dielectric material (41, 43) and a second dielectric material (42, 44), wherein the first and second dielectric materials have a k value of 4 or higher, the first dielectric material (41, 43) has a high conduction band offset, wherein at least one of the two conditions applies: the first dielectric material (41, 43), 43) has a conduction band offset higher by at least 0.3 eV and a valence band offset lower by at least 0.3 eV than the second dielectric material (42, 44) or else has a low valence band offset and the second dielectric material (42, 44) has a low conduction band offset but a high valence band offset, wherein the offset is calculated on the conduction band minimum of the source region (30) or on the Fermi level of either the gate or the source metal (60).The semiconductor device according to any one of claims 1 to 3, further comprising a source metal (60) electrically contacting the source region (30), wherein an interlayer dielectric (65) isolates the gate electrode (50) from the source metal (60), wherein the interlayer dielectric (65) comprises alternating layers of a first dielectric material (41, 43) comprising or being silicon oxide and a second dielectric material (42, 44) having a k value of 4 or higher, wherein the thickness of the layers of the first dielectric material (41, 43) is at most 5 nm, and the interlayer dielectric (65) includes layers of the first dielectric material (41, 43) as the first and the last layer of the multilayer laminate structure.The semiconductor device according to any of the preceding claims, wherein the gate dielectric (40) comprises at least two of the layers with the first dielectric material (41, 43) and at least two of the layers with the second dielectric material (42, 44).The semiconductor device according to any of the preceding claims, wherein the gate dielectric (40) or the interlayer dielectric (65) multilayer structure comprises a third or further dielectric material layer(s) comprising a material selected from a Si-based, Al-based or a high-k dielectric material different from the first and second dielectric material.The semiconductor device of any preceding claim, wherein the gate dielectric (40) further comprises an interfacial dielectric layer disposed between at least a portion of the SiC body and the first layer of the multilayer laminate structure.The semiconductor device of claim 9, wherein the interfacial dielectric layer comprises silicon oxide.The semiconductor device of any preceding claim, wherein the first and second dielectric materials (41, 43; 42, 44) have a band gap of less than 7.0 eV.The semiconductor device of any preceding claim, wherein the first dielectric material (41, 43) has an offset to the conduction band of the SiC body material of at least 1.0 eV and the second dielectric material (42, 44) has an offset to the valence band of the SiC body material of at least 1.0 eV or the first dielectric material (41, 43) has an offset to the valence band of the SiC body material of at least 1.0 eV and the second dielectric material (42, 44) has an offset to the conduction band of the SiC body material of at least 1.0 eV.The semiconductor device of any preceding claim, wherein at least one of the interlayer dielectric (65) and the gate dielectric (40) has a total k value that is higher than silicon oxide, and comprising a multilayer laminate structure including alternating layers of a first dielectric material (41, 43) having a band gap of less than 7.0 eV and a second dielectric material (42, 44) having a band gap of less than 7.0 eV, wherein the first dielectric material (41, 43) has an offset to the conduction band of the SiC body material or source metal of at least 0.8 eV and the second dielectric material (42, 44) has an offset to the valence band of the SiC body material or source metal of at least 0.8 eV.The semiconductor device of any preceding claim, wherein the thickness of the layers in the multilayer laminate structure varies across the thickness of at least one of the gate dielectric (40) or interlayer dielectric (65).A semiconductor device comprising a SiC body, comprising: a drift region (10) of a first conductivity type, a body region (20) of a second conductivity type, and a source region (30) of the first conductivity type; a gate structure comprising a gate electrode (50) and a gate dielectric (40) insulating the gate electrode (50) from the SiC body, wherein the gate structure is arranged adjacent to the source region (30), the body region (20), and the drift region (10); wherein the gate dielectric (40) comprises a multilayer laminate structure including alternating layers of a first dielectric material (41, 43) comprising or being silicon oxide and a second dielectric material (42, 44) having a k-value of 4 or higher, wherein the thickness of the layers of the first dielectric material (41, 43) is at most 5 nm and the gate dielectric (40) includes layers of the first dielectric material (41, 43) as the first and the last layer of the multilayer laminate structure.The semiconductor device of claim 15, wherein the multilayer laminate structure comprises a third or further dielectric material layer comprising a material selected from a Si-based, Al-based or a high-k dielectric material other than the first and second dielectric materials (41, 43; 42, 44).The semiconductor device of claim 15 or claim 16, wherein the gate structure comprises a gate trench disposed in the SiC body and adjacent to the source region (30), wherein the gate trench has a depth that is greater than a depth of the body region (20) and that is less than a depth of the drift region (10), wherein the gate dielectric (40) in the gate trench is disposed on a sidewall of the gate trench and a bottom surface of the gate trench, and wherein the gate electrode (50) is disposed on the gate dielectric (40).A method of manufacturing a semiconductor device comprising a SiC body, wherein the SiC body comprises a drift region (10) of a first conductivity type, a body region (20) of a second conductivity type and a source region (30) of the first conductivity type; and wherein the SiC body is provided with a gate structure comprising a gate electrode (50) and a gate dielectric (40) isolating the gate electrode (50) from the SiC body, wherein the gate structure is arranged adjacent to the source region (30), the body region (20) and the drift region (10); wherein the gate dielectric (40) is deposited on portions of the SiC body in a multi-layered laminate structure comprising alternating layers of a first dielectric material (41, 43) and a second dielectric material (42, 44), and wherein the first and second dielectric materials (41, 43; 42, 44) has a k-value of 4 or higher, the first dielectric material (41, 43) has a conduction band offset higher by at least 0.3 eV and a valence band offset lower by at least 0.3 eV than the second dielectric material (42, 44) or vice versa or wherein the first dielectric material (41, 43) comprises or is silicon oxide and the second dielectric material (42, 44) has a k-value of 4 or higher, wherein the thickness of the layers of the first dielectric material (41, 43) is at most 5 nm and the interlayer dielectric (65) includes layers of the first dielectric material (41, 43) as the first and the last layer of the multilayer laminate structure.The method for manufacturing a semiconductor device according to claim 18, wherein the Fermi level of the gate electrode (50) is adjusted based on the valence and conduction band offsets of the dielectric material layer adjacent to the gate electrode (50).

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