SEMICONDUCTOR CHIP AND METHOD FOR PRODUCING THE SAME

Abstract

The disclosure relates to a semiconductor chip (1) comprising a silicon carbide (SiC) semiconductor body (11); a passivation system (40) on a first side (11.1) of the SiC semiconductor body (11); a metallization (30) in which a load pad (31) is formed, on the first side (11.1); wherein the passivation system (40) covers a lateral edge (31.1) of the load pad (31) and has an opening (41) on the load pad (31) and comprises an inorganic passivation layer system (45) and an organic layer (41) on the inorganic passivation layer system (45), wherein a lateral edge (45.i) of the inorganic passivation layer system (45) is arranged on the SiC semiconductor body (11), wherein the inorganic passivation layer system (45) is laterally set back under the organic layer (41), wherein the lateral edge (45.i) of the inorganic passivation layer system (45) is covered by the organic layer (41).Next to the load pad (31), a channel (32, 33) is formed in the metallization (30), wherein the inorganic passivation layer system (45) is interrupted above the channel (32, 33).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor chip comprising a semiconductor body. BACKGROUND

[0002] In embodiments of this application, the semiconductor body is made of silicon carbide (SiC), which has a comparatively wide band gap, e.g., compared to silicon. This may be of interest, for example, for power semiconductor devices in high-voltage and / or high-current applications. A device structure with a load terminal or terminals can be formed in the semiconductor body, for example, a transistor structure with a source terminal and a drain terminal. A metallization layer can be formed on the semiconductor body for wiring and contacting the device structure.

[0003] A power device with a load pad is known from US 2022 / 0 310 822 A1.

[0004] From US 2017 / 0 271 305 A1 a semiconductor component for assembly via solder bumps is known. SUMMARY

[0005] It is an object of the invention to provide advantageous semiconductor chips. This object is achieved by the semiconductor chip according to claim 1, the semiconductor chip according to claim 2, the semiconductor chip according to claim 15, and the manufacturing method according to claim 20. The subclaims relate to advantageous embodiments.

[0006] The semiconductor chip according to claim 1 comprises a silicon carbide (SiC) semiconductor body, a passivation system on a first side of the SiC semiconductor body, and a metallization on the first side of the SiC semiconductor body, in which a load pad is formed. The passivation system covers a lateral edge of the load pad and has an opening on the load pad. The passivation system comprises an inorganic passivation layer system and an organic layer on the inorganic passivation layer system. A lateral edge of the inorganic passivation layer system is arranged on the SiC semiconductor body. The inorganic passivation layer system is laterally recessed beneath the organic layer, wherein the lateral edge of the inorganic passivation layer system is covered by the organic layer.The semiconductor chip according to claim 1 is characterized in that a runner is formed next to the load pad in the metallization, wherein the inorganic passivation layer system above the runner is uninterrupted.

[0007] In one embodiment, a semiconductor chip comprises a silicon carbide (SiC) semiconductor body and a passivation system on a first side of the SiC semiconductor body. The passivation system comprises an inorganic passivation layer system and an organic layer, wherein a lateral edge of the inorganic passivation layer system is arranged on the SiC semiconductor body. The organic layer can cover this lateral edge of the inorganic passivation layer system, e.g., extend laterally further than the inorganic passivation layer system. In other words, the lateral edge of the inorganic passivation layer system is laterally recessed beneath the organic layer.

[0008] Viewed in a sectional plane perpendicular to the lateral edge of the inorganic passivation layer system, the organic layer on the inorganic passivation layer system can extend on one side of the lateral edge and cover the lateral edge of the inorganic passivation layer system toward the other side, e.g., laterally outward (toward a lateral edge of the SiC semiconductor body). The organic layer covering the lateral edge of the inorganic passivation layer system can, for example, reduce or slow down silicon carbide oxidation, e.g., oxidation of the SiC semiconductor body adjacent to or below the inorganic passivation layer system.

[0009] Such oxidation could be triggered or driven by moisture, e.g., in combination with electric fields. For example, at the lateral edge of the inorganic passivation layer system lying on top of the SiC semiconductor body, SiC oxidation could introduce mechanical stress and create a risk of delamination. By extending the organic layer, e.g., the imide layer, over the lateral edge, SiC oxidation at this geometrically critical location can at least be delayed.

[0010] Further embodiments and features are provided in the claims and throughout the disclosure. The individual features are intended to be disclosed independently of a specific claim category; the disclosure relates to device and apparatus aspects, but also to method and use aspects. For example, if a chip fabricated in a specific manner is described, this is also a disclosure of a respective fabrication process, and vice versa. In general terms, embodiments of the present application aim to provide an organic layer with an overlap, e.g., laterally outwardly, at a lateral edge of an inorganic layer, i.e., to cover the lateral edge of the inorganic layer.

[0011] When reference is generally made to an arrangement of a layer or lateral edge of the layer “on” another layer or entity, e.g., on the SiC semiconductor body, this does not necessarily imply an arrangement directly adjacent to this layer or entity. In other words, an additional layer may be arranged between the inorganic passivation layer system and the first side of the SiC semiconductor body, e.g., an aluminum oxide layer. For example, only the aluminum oxide layer may be arranged between the inorganic passivation layer system and the first side of the SiC semiconductor body. The additional layer may, for example, serve as an adhesion promoter and / or etch stop layer. It may, for example, have a thickness of no more than 30 nm, 20 nm, or 15 nm, with possible lower limits being, for example, 3 nm or 5 nm. In summary, in other words, an arrangement “on” may mean a certain distance, e.g.,a comparatively small pitch of not more than 100 nm, 50 nm, 30 nm, 20 nm or 15 nm, or a “direct on” arrangement.

[0012] The lateral edge of the additional layer can be arranged on the SiC semiconductor body, e.g., where the lateral edge of the inorganic passivation layer system is arranged. Alternatively, the additional layer can extend further, e.g., laterally outward, than the inorganic passivation layer system. Irrespective of these details, the coverage, e.g., by the organic layer, can prevent or slow down moisture and / or ionic contamination. However, as an alternative to the subsequent additional layer, the inorganic passivation layer system, e.g., its lateral edge, can also be arranged directly on the SiC semiconductor body. Additionally or alternatively, the organic layer can be arranged directly on the first side of the semiconductor body, adjacent to the inorganic passivation layer system.

[0013] In general, the SiC semiconductor body may comprise a SiC semiconductor substrate, for example, in combination with one or a plurality of epitaxial SiC layers thereon. The side of an uppermost epitaxial SiC layer facing away from the SiC substrate may be the "first side" of the SiC semiconductor body. Conversely, the side of the SiC substrate facing away from the epitaxial SiC layer(s) may be the "second side" of the SiC semiconductor body.

[0014] In one embodiment, the inorganic passivation layer system is laterally recessed by at least 1 µm below the organic layer, with further lower limits being, for example, at least 2 µm or 2.5 µm. Possible upper limits can be, for example, at most 50 µm, 30 µm, or 20 µm. In detail, a respective distance can be taken in a sectional plane perpendicular to the lateral edge of the inorganic passivation layer system, i.e., the distance between the lateral edge of the inorganic passivation layer system and a lateral edge of the organic layer (at the lower end of the organic layer).

[0015] In one embodiment, the lateral edge of the inorganic passivation layer system is an outer lateral edge facing the lateral edge of the SiC semiconductor body (whereas an inner lateral edge may face the active region). Near the lateral edge of the SiC semiconductor body, an electric field may be present, for example, resulting from a backside potential that may extend from the backside (second side) to the frontside (first side) at the lateral edge of the SiC semiconductor body and that could trigger or drive oxidation processes. The outer lateral edge may, for example, be the outermost lateral edge of the inorganic passivation layer or of the inorganic passivation layer system, wherein, for example, no other element of the inorganic passivation layer system is arranged further outward.

[0016] In general, "outer" and "outermost" refer to the lateral position relative to the respective lateral edge of the SiC semiconductor body, i.e., closer or closest to that lateral edge. For example, the elements discussed in terms of their relative position are arranged on the same side of an active area of ​​the chip, i.e., at the same lateral edge of the SiC semiconductor body. Similar structures may be arranged at the other lateral edges of the SiC semiconductor body, but this is not mandatory.

[0017] The outer lateral edge of the inorganic passivation layer system may be offset inward from the lateral edge of the SiC semiconductor body, e.g., lie parallel to the lateral edge of the SiC semiconductor body, as viewed in a vertical plan view. Laterally outside the outer lateral edge of the inorganic passivation layer system, the SiC semiconductor body may be exposed without an additional layer, e.g., not covered by an inorganic layer, wherein the organic layer may provide coverage over at least a lateral portion.

[0018] The lateral edge, e.g., outer lateral edge, of the inorganic passivation layer system can be arranged between the lateral edge of the SiC semiconductor body and an active region. In other words, the lateral edge of the inorganic passivation layer system can be arranged in an edge termination region. In the active region, a device structure can be formed in the SiC semiconductor body, which device structure, for example, comprises a first load terminal arranged on the first side of the SiC semiconductor body. In addition, the device structure can comprise a second load terminal, e.g., on a vertically opposite second side of the SiC semiconductor body. The device structure can, for example, be an FET with a source terminal region and a drain terminal region in the SiC semiconductor body, e.g., the source region on the first side of the SiC semiconductor body and the drain region on the second side thereof.In other words, the load pad in the metallization may be a source pad connected to a source terminal of the device structure.

[0019] In addition to the source region and the drain region, the device may comprise a body region to which a gate electrode capacitively couples. Additionally, a drift region may be arranged between the body region and the drain region, e.g., of the same doping type but with a lower concentration than the drain region. The source region and the drain region, and, if present, the drift region, may consist of a first doping type; the body region may consist of a second doping type. In the illustrated embodiments, the first doping type is n-type and the second doping type is p-type.

[0020] In one embodiment, the semiconductor chip comprises an insulating layer on the first side of the SiC semiconductor body. The insulating layer can, for example, be arranged directly on the first side, namely adjacent to the SiC semiconductor body. It can serve as an interlayer dielectric, e.g., defining a contact structure between a metallization above and the semiconductor body below. The insulating layer can comprise an oxide layer, e.g., a borophosphosilicate glass (BPSG) layer. In other words, the insulating layer can comprise a doped oxide layer, e.g., in addition to an undoped oxide layer. The insulating layer can, for example, have a total thickness of at least 0.5 µm and / or at most 3 µm.

[0021] The insulating layer may have an outer lateral edge on the SiC semiconductor body, wherein the outer lateral edge of the insulating layer is offset inward from the lateral edge of the SiC semiconductor body. The outer lateral edge of the insulating layer may be covered by the inorganic passivation layer system, so that, in other words, the outer lateral edge of the inorganic passivation layer system is arranged at a lateral position between the lateral edge of the SiC semiconductor body and the outer lateral edge of the insulating layer.

[0022] In one embodiment, the outer lateral edge of the insulating layer is offset inward from the lateral edge of the inorganic passivation layer system by at least 1 µm, with further lower limits being, for example, at least 2 µm, 3 µm, or 4 µm. Possible upper limits can be, for example, at most 20 µm or 10 µm. In detail, a respective distance can be taken in a sectional plane perpendicular to the lateral edge of the inorganic passivation layer system, i.e., the minimum distance between the lateral edge of the inorganic passivation layer system and the outer lateral edge of the insulating layer.

[0023] In one embodiment, the semiconductor chip comprises a metallization on the first side of the SiC semiconductor body, with an insulating layer, as discussed above, being arranged, for example, between the SiC semiconductor body and the metallization. In the case of an FET formed in the semiconductor body, the load pad may, for example, be a source pad, see above in detail.

[0024] The passivation system can cover a lateral edge of the load pad, e.g., extending laterally and reaching onto the load pad. The passivation system can have an opening on the load pad, e.g., for later contacting in a housing or other mounting structure.

[0025] Viewed in a section plane perpendicular to the lateral edge of the load pad, the inorganic passivation layer system has an inner lateral end on the load pad. Generally, the organic layer may be flush with the inner lateral end of the inorganic passivation layer system on the load pad. However, in one embodiment, the organic layer extends further inward than the inorganic passivation layer system, i.e., it covers the inner lateral end of the inorganic passivation layer system laterally inward.

[0026] In one embodiment, the inorganic passivation layer system extends continuously, i.e., without an interruption, between the lateral edge of the load pad and the inner lateral end of the inorganic passivation layer system, viewed in a sectional plane perpendicular to the lateral edge of the load pad. Alternatively, the inorganic passivation layer system may be provided with an interruption on the load pad, e.g., at a lateral position between the lateral edge of the load pad and the inner lateral end of the inorganic passivation layer system. Regardless of whether the inorganic passivation layer system is provided with an interruption or not, the organic layer may extend continuously, i.e., without an interruption, between the opening on the load pad and the lateral edge of the load pad (and further outward toward the lateral edge of the SiC semiconductor body).

[0027] In one embodiment, the metallization in the region of the load pad is formed with a step. Laterally outside the step, e.g., closer to a lateral edge of the SiC semiconductor body or chip, the load pad has a first thickness t1. Laterally inside the step, e.g., at a greater distance from the lateral edge of the SiC semiconductor body or chip, the load pad has a second thickness t2. Here, t1 is smaller than t2. In other words, the load pad has a smaller thickness t1 in an edge portion of the load pad and a larger thickness in a central portion of the load pad. The latter may, for example, have advantages with regard to thermal management or assembly and bonding, wherein the smaller thickness in the edge portion may, for example, reduce a topology of the passivation system extending onto the load pad.

[0028] In one embodiment, an inner lateral position x2, to which the passivation system extends, is arranged laterally outside the step. In other words, the passivation system, viewed in the section plane, extends laterally onto the load pad, but ends in its edge region, where the load pad has a thickness t1. Viewed in a section plane, the passivation system covers the lateral edge of the load pad, but not the step.

[0029] In one embodiment, an inorganic layer or an inorganic layer stack covers a flank of the step in the load pad. The inorganic layer may be a silicon nitride layer and / or a silicon oxide layer, or the inorganic layer stack may comprise a silicon nitride layer and / or a silicon oxide layer. Regardless of a specific material, covering the flank may be advantageous, for example, with respect to migration or diffusion processes. Such processes may, for example, be driven by an electric field originating from a backside potential extending to the first side at the lateral edge of the semiconductor body (even if the electric field is reduced in an edge termination region or structure, a residual field strength may remain).

[0030] The flank covered by an inorganic layer or an inorganic layer stack is also intended to be disclosed independently of the overlapping organic layer. In other words, a semiconductor chip is intended to be disclosed, comprising: a semiconductor body; a metallization on a first side of the semiconductor body, in which a load pad is formed; wherein the metallization is formed with a step in the region of the load pad, wherein the load pad has a first thickness t1 laterally outside the step and a second thickness t2 laterally inside the step, wherein t1 is smaller than t2, wherein an inorganic layer or an inorganic layer stack covers a flank of the step. With regard to possible embodiments and additional features, reference is made to the disclosure as a whole.

[0031] In one embodiment, the metallization comprises a copper layer. The copper layer may be part of a copper layer system, which may, for example, comprise a sputter-deposited copper layer and one or a plurality of bath-deposited copper layers thereon. In one embodiment, the metallization comprises a first bath-deposited copper layer and a second bath-deposited copper layer deposited on the first bath-deposited copper layer, wherein the second bath-deposited copper layer may be patterned with respect to the first bath-deposited copper layer. In other words, the second bath-deposited copper layer may form the step in the load pad.

[0032] For patterning the second bath-deposited copper layer, a mask may be provided on the first bath-deposited copper layer prior to deposition of the second bath-deposited copper layer. The step in the load pad may be formed at a lateral edge of the second bath-deposited copper layer that is shifted inward with respect to a lateral edge of the first bath-deposited copper layer. Alternatively, however, a copper layer or layers may be sputter-deposited, regardless of whether a bath-deposited copper layer system is subsequently applied or not. In other words, a sputter-deposited copper layer or layers may be combined with a bath-deposited copper layer or layers, or the copper metallization as a whole may be sputter-deposited.Also in the case of sputter-deposited copper metallization, an upper copper layer may be patterned with respect to a copper layer below it to form a step.

[0033] Overall, regardless of whether sputter-deposited and / or bath-deposited, all copper layers of the metallization can have a thickness of at least 3 µm, for example, with further lower limits being, for example, 5 µm or 7 µm. Upper limits can be, for example, 25 µm or 20 µm. A barrier layer system of the metallization (e.g., comprising a Ti / TiN layer) can be arranged beneath the lowest copper layer, e.g., the sputter-deposited copper layer.

[0034] In one embodiment, the inorganic passivation layer system comprises a silicon nitride layer and a silicon oxide layer. The silicon nitride layer can be arranged below or on top of the silicon oxide layer. In one embodiment, the silicon oxide layer is arranged on a first silicon nitride layer, with a second silicon nitride layer arranged on the silicon oxide layer, for example, the silicon oxide layer being arranged directly on the first silicon nitride layer and / or the second silicon nitride layer being arranged directly on the silicon oxide layer. The first silicon nitride layer can, for example, be thinner than the silicon oxide layer and / or the second silicon nitride layer. Regardless of these geometric details, the silicon oxide layer can, for example, be an undoped silicon oxide layer, e.g., undoped silicon glass (USG).

[0035] In one embodiment, the semiconductor chip comprises a SiC semiconductor body, an insulating layer on a first side of the SiC semiconductor body, and a passivation system with an organic layer, e.g., an imide layer, on the insulating layer. The insulating layer may have an outer lateral edge on the SiC semiconductor body, e.g., directly on the SiC semiconductor body or with an additional layer in between (e.g., an aluminum oxide layer, see the above description of the "on" arrangement). Regardless of these details, the outer lateral edge of the insulating layer may be covered by the organic layer, i.e., the outer lateral edge of the insulating layer is laterally recessed below the organic layer.

[0036] As discussed above for the lateral edge of the inorganic passivation layer system covered by the organic layer, covering the outer lateral edge of the insulating layer can, for example, reduce the risk of delamination (by slowing or preventing SiC oxidation at the edge of or even beneath the insulating layer). For further details of the insulating layer, reference is made to the above description; it may, for example, comprise an oxide layer (e.g., BPSG layer) and have a total thickness of at least 0.5 µm and / or at most 3 µm.

[0037] In one embodiment, an outer lateral edge of the inorganic passivation layer system is arranged on the insulating layer, i.e., an outer portion of the insulating layer is not covered by the inorganic passivation layer system. Then, the organic layer, e.g., an imide layer, can cover both the outer lateral edge of the inorganic passivation layer system on the insulating layer and the outer lateral edge of the insulating layer on the SiC semiconductor body.

[0038] In one embodiment, the organic layer has a thickness of at least 1 µm, with further lower limits being, for example, at least 2 µm, 3 µm, 4 µm, or 5 µm. Possible upper limits may be, for example, no more than 50 µm, 40 µm, 30 µm, or 25 µm.

[0039] In one embodiment, the organic layer is an imide layer. The imide can be, for example, a photosensitive polyimide precursor.

[0040] In one embodiment, a method of manufacturing a semiconductor chip comprises: I) forming an inorganic passivation layer system on a first side of a SiC semiconductor body such that a lateral edge of the inorganic passivation layer system is arranged on the SiC semiconductor body (e.g. directly on or with an additional layer in between); II) Forming an organic layer on the inorganic passivation layer system covering the lateral edge of the inorganic passivation layer system.

[0041] For additional embodiments and features, reference is made to the disclosure as a whole.

[0042] In one embodiment, step I comprises: i) depositing the inorganic passivation layer system on the first side of the SiC semiconductor body; ii) locally etching away the inorganic passivation layer system to define the lateral edge of the inorganic passivation layer system.

[0043] For step ii), a mask may be deposited on the inorganic passivation layer system. The inorganic passivation layer system may be locally etched away where the mask has an opening, for example, at the lateral edge of the SiC semiconductor body and / or on a load pad formed in a metallization. Regardless of these details, the mask may be removed after the inorganic passivation layer system has been locally etched away, e.g., before forming the organic layer in step II).

[0044] Each of these methods or process steps discussed above can be used to manufacture a semiconductor chip discussed above. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The semiconductor chip and the manufacturing method are explained in more detail below using exemplary embodiments. The individual features may also be relevant in other combinations. Fig. 1 shows a cross-sectional view of a semiconductor chip comprising a SiC semiconductor body and a passivation system; Fig. Figure 2 shows a more detailed view of a passivation system on a SiC semiconductor body; Fig. 3 shows a schematic cross-section of a device formed in an active region of a semiconductor chip; Fig. 4a-e illustrate various steps for producing a semiconductor chip with a passivation system comprising an inorganic passivation layer system and an organic layer; Fig. 5 shows a detailed view of an embodiment of a passivation system on a SiC semiconductor body; Fig. 6 summarizes some manufacturing steps in a flow chart; Fig. 7 shows a cross-sectional view of a semiconductor chip comprising a SiC semiconductor body, an insulating layer and a passivation system. DETAILED DESCRIPTION

[0046] Fig. 1 shows a section of a semiconductor chip 1 in a vertical cross-section. The semiconductor chip 1 comprises a silicon carbide (SiC) semiconductor body 11. An insulating layer 90 is arranged on a first side 11.1 of the SiC semiconductor body 11. Furthermore, a metallization 30 comprising a barrier layer system 130 is formed on the SiC semiconductor body 11. A copper layer system 230 is arranged on the barrier layer system 130. In the example shown, this system comprises a sputter-deposited copper layer 231 and a bath-deposited copper layer system 235 with a first bath-deposited copper layer 235a and a second bath-deposited copper layer 235b.

[0047] In detail, the cross-sectional view of Fig. 1 at a lateral edge 1.1 of the chip 1, wherein an inactive region 1b is laterally between the lateral edge 1.1 of the chip 1 and a Fig. 1 is arranged in the active region 1a shown on the right. Transistor device cells can be arranged in the active region 1a (see in detail below). In the active region 1a, a load pad 31 can be formed in the metallization 30, for example, a source pad connected to a source terminal of the device or device cells. In the inactive region 1b, a gate runner 32 and / or a source runner 33, each extending along the active region 1a, can be formed in the metallization 30.

[0048] A passivation system 40 is arranged on the metallization 30, which in the example shown comprises an inorganic passivation layer system 45 and an organic layer 41, e.g., imide layer 42, on the inorganic passivation layer system 45. As described with respect to Fig. 4e, an additional adhesion promoter layer can be arranged in between (not shown here).

[0049] The shown inorganic passivation layer system 45 comprises a first silicon nitride layer 45.1, an undoped silicon oxide layer 45.2 directly on the first silicon nitride layer 45.1, and a second silicon nitride layer 45.3 directly on the undoped silicon oxide layer 45.2. The passivation system 40 covers the gate runner 32 and the source runner 33 and also covers the insulating layer 90 made of doped oxide (e.g., borophosphosilicate glass, BPSG). In the example shown, an aluminum oxide layer 340 (in Fig. 1 shown only as a line) under the inorganic passivation layer system 45, ie on the insulating layer 90 and also on the metallization 30.

[0050] The cutting plane of Fig. 1 is perpendicular to a lateral edge 31.1 of the load pad 31. The passivation system 40 extends between an outer lateral position x1 adjacent to the load pad and an inner lateral position x2, which lies on the load pad 31, ie, covers the lateral edge 31.1 of the load pad 31. In the embodiment shown, an interruption 60 is provided in at least one layer 41, 42, 45.1-45.3 of the passivation system 40; in this case, the interruption 60 completely intersects the inorganic passivation layer system 45. It is located at an interruption position x i arranged laterally between the lateral edge 31.1 of the load pad 31 and the inner lateral position x2.

[0051] Fig. 2 shows a more detailed view of a lateral edge 45.i of the inorganic passivation layer system 45 arranged on the SiC semiconductor body 11, wherein the section plane is perpendicular to this lateral edge 45.i. The lateral edge 45.i of the inorganic passivation layer system 45 is offset inward from a lateral edge 11.i of the SiC semiconductor body 11. The organic layer 41, e.g., imide layer 42 in the example shown, extends further outward and covers the lateral edge 45.i of the inorganic passivation layer system 45. Consequently, an outer lateral edge 41.i of the organic layer 41 is arranged further outward, i.e., closer to the lateral edge 11.i of the SiC semiconductor body 11, than the lateral edge 45.i of the inorganic passivation layer system 45.

[0052] In the example shown, the inorganic passivation layer system 45, i.e., the first silicon nitride layer 45.1, and the organic layer 41 are each arranged directly on the first side 11.1 of the SiC semiconductor body 11, namely the inorganic passivation layer system 45 laterally outside the insulating layer 90 and the organic layer 41 laterally outside the lateral edge 45.i of the inorganic passivation layer system. Alternatively, however, an additional layer may be arranged therebetween, e.g., an aluminum oxide layer (see Fig. 5 for illustration).

[0053] Fig. Figure 3 illustrates a possible device 200 and device structure 20 formed in the active area 1a of the chip 1, e.g., under the load pad 31 (see Fig. 1 for comparison). In the SiC semiconductor body 11, a load terminal 21 is formed on the first side 11.1, which in the example shown is a source region 22. A drain region 27 is arranged on the vertically opposite second side 11.2, with a body region 23 arranged below the source region 22 and a drift region 24 arranged between the body region 23 and the drain region 27.

[0054] A gate region 25, comprising a gate electrode 25.1 and a gate dielectric 25.2 that capacitively couples the gate electrode 25.1 to the body region 23, is arranged in a trench 26. A voltage applied to the gate electrode 25.1 can control channel formation in the body region 23 and, consequently, a current flow between the source region 22 and the drain region 25. The device 200 can comprise a plurality of device cells 201 connected in parallel.

[0055] Fig. 4a-e illustrate some steps for manufacturing a semiconductor chip with a semiconductor body and a metallization and passivation system. In Fig. 4a, the insulating layer 90 has already been deposited on the first side 11.1 of the semiconductor body 11, and the metallization 30 has been formed. The aluminum oxide layer 230 (shown only as a line) has been deposited on the metallization 30, and the silicon nitride layer 45.1 and the silicon oxide layer 45.2 have been deposited.

[0056] Before covering the silicon oxide layer 45.2 by the second silicon nitride layer 45.3, as in Fig. 4b, the silicon oxide layer 45.2 can be etched back (not shown in detail here). In Fig. 4b, the inorganic passivation layer system 45 has been deposited but not yet patterned. For this purpose, a mask 145 is provided on the inorganic passivation layer system 45. The mask 145 has an opening 160 that defines where the interruption in the inorganic passivation layer system 45 is to be etched. Furthermore, the mask 145 defines an inner and outer lateral end of the inorganic passivation layer system 45, i.e., where the inorganic passivation layer system 45 is to be opened on the load pad 31.

[0057] Fig. 4c illustrates the inorganic passivation layer system 45 after the etching step, ie, after the discontinuity 60 has been etched into the inorganic passivation layer system 45 and the lateral edge 45.i of the inorganic passivation layer system 45 has been defined. For example, applying an anisotropic etching step may leave inorganic layers 81.1, 81.2, e.g., a stack 80 of inorganic layers 81.1, 81.2, on the flank 71 of the step 70.

[0058] In a subsequent step, which is Fig. As illustrated in Figure 4d, the organic layer 41, e.g., imide layer 42 in the example shown, was deposited on the patterned inorganic passivation layer system 45. For patterning the organic layer 41, a mask 141 is formed on the organic layer 41. The mask 141 defines the lateral edge 41.i and the opening 140 in the organic layer 41, see Fig. 4e for illustration. In this process step, the organic layer 41 was etched back and the mask was removed from the organic layer 41.

[0059] Fig. 5 shows a detailed view of a lateral edge 11.i of the SiC semiconductor body 11. The Fig. The embodiment shown in Figure 5 differs from that shown in Fig. 2 in that the inorganic passivation layer system 45 and the organic layer 41, e.g., imide layer 42, are not arranged directly on the first side 11.1 of the SiC semiconductor body 11 laterally outside the insulating layer 90. Instead, an adhesion promoter or etch stop layer 290 is arranged therebetween, which in the example shown is an aluminum oxide layer.

[0060] Fig. 6 summarizes some manufacturing steps in a flowchart. Forming 600 an inorganic passivation layer system on a first side of a SiC semiconductor body may include depositing 601 the inorganic passivation layer system on the first side, wherein the inorganic passivation layer system is subsequently locally etched away 602 to define a lateral edge of the inorganic passivation layer system. Subsequently, the organic layer may be formed 610, e.g., by depositing 611 the organic layer and locally etching 612 it away to define an opening and a lateral edge.

[0061] Fig. Figure 7 shows an embodiment which differs partly from that described with respect to Fig. 1. Also in this case, an insulating layer 90, a metallization 30 and a passivation system 40 are arranged on the first side 11.1 of the SiC semiconductor body 11 (see the above description for further details). In contrast to Fig. 1, the outer lateral edge 45.i of the inorganic passivation layer system 45 is not arranged next to the insulating layer 90, but on the insulating layer 90. Consequently, a portion 90a of the insulating layer 90 next to the outer lateral edge 45.i of the inorganic passivation layer system 45, ie between the outer lateral edge 45.i of the inorganic passivation layer system 45 and the outer lateral edge 90.i of the insulating layer 90, is not covered by the inorganic passivation layer system 45.

[0062] The organic layer 41, e.g., imide layer 42, extends further outward, ie, toward the outer lateral edge 1.1 of the chip 1, than the inorganic passivation layer system 45 and the insulating layer 90. It covers the outer lateral edge 45.i of the inorganic passivation layer system 45 and also the outer lateral edge 90.i of the insulating layer 90.

Claims

[1] Semiconductor chip (1), comprising: a silicon carbide (SiC) semiconductor body (11); a passivation system (40) on a first side (11.1) of the SiC semiconductor body (11); a metallization (30) on the first side (11.1) of the SiC semiconductor body (11), in which a load pad (31) is formed; wherein the passivation system (40) covers a lateral edge (31.1) of the load pad (31) and has an opening on the load pad (31), wherein the passivation system (40) comprises an inorganic passivation layer system (45) and an organic layer (41) on the inorganic passivation layer system (45), wherein a lateral edge (45.i) of the inorganic passivation layer system (45) is arranged on the SiC semiconductor body (11), and wherein the inorganic passivation layer system (45) is laterally recessed under the organic layer (41), wherein the lateral edge (45.i) of the inorganic passivation layer system (45) is covered by the organic layer (41), characterized by , that a runner (32, 33) is formed next to the load pad (31) in the metallization (30), wherein the inorganic passivation layer system (45) above the runner (32, 33) is uninterrupted. [2] Semiconductor chip (1), comprising: a silicon carbide (SiC) semiconductor body (11); a passivation system (40) on a first side (11.1) of the SiC semiconductor body (11); a metallization (30) on the first side (11.1) of the SiC semiconductor body (11), in which a load pad (31) is formed; wherein the passivation system (40) covers a lateral edge (31.1) of the load pad (31) and has an opening on the load pad (31), wherein the passivation system (40) comprises an inorganic passivation layer system (45) and an organic layer (41) on the inorganic passivation layer system (45), wherein a lateral edge (45.i) of the inorganic passivation layer system (45) is arranged on the SiC semiconductor body (11), wherein the inorganic passivation layer system (45) is laterally recessed under the organic layer (41), wherein the lateral edge (45.i) of the inorganic passivation layer system (45) is covered by the organic layer (41), and wherein the metallization (30) is formed in the region of the load pad (31) with a step (70), wherein the load pad (31) has a first thickness t1 laterally outside the step (70) and a second thickness t2 laterally inside the step (70), wherein t1 is smaller than t2, characterized by , that an inorganic layer (81.1, 81.2) or a layer stack (80) covers a flank (71) of the step (70). [3] Semiconductor chip (1) according to claim 1 or 2, wherein the inorganic passivation layer system (45) is laterally recessed by at least 1 µm below the organic layer (41). [4] Semiconductor chip (1) according to one of the preceding claims, wherein the lateral edge (45.i) is an outer lateral edge of the inorganic passivation layer system (45) which is offset inwardly from a lateral edge (11.i) of the SiC semiconductor body (11). [5] Semiconductor chip (1) according to claim 4, wherein the lateral edge (45.i) of the inorganic passivation layer system (45) is arranged between the lateral edge (11.i) of the SiC semiconductor body (11) and an active region (1a) of the semiconductor chip (1). [6] Semiconductor chip (1) according to claim 4 or 5, comprising: an insulating layer (90) on the first side (11.1) of the SiC semiconductor body (11); wherein the insulating layer (90) has an outer lateral edge (90.i) on the SiC semiconductor body (11), wherein the outer lateral edge (90.i) of the insulating layer (90) is offset inwardly from the lateral edge (45.i) of the inorganic passivation layer system (45). [7] Semiconductor chip (1) according to claim 6, wherein the outer lateral edge (90.i) of the insulating layer (90) is offset inwardly from the lateral edge (45.i) of the inorganic passivation layer system (45) by at least 1 µm. [8] Semiconductor chip (1) according to one of the preceding claims, wherein the inorganic passivation layer system (45), viewed in a sectional plane perpendicular to the lateral edge (31.1) of the load pad (31), has an inner lateral end (45.ii) on the load pad (31), wherein the organic layer (41) extends further inward than the inorganic passivation layer system (45) and covers the inner lateral end (45.ii) of the inorganic passivation layer system (45). [9] Semiconductor chip (1) according to claim 4 or 5, wherein the inorganic passivation layer system (45), viewed in a sectional plane perpendicular to the lateral edge (31.1) of the load pad (31), has an inner lateral end (45.ii) on the load pad (31), wherein the inorganic passivation layer system (45), viewed in a sectional plane perpendicular to the lateral edge (31.1) of the load pad (31), extends uninterruptedly between the inner lateral end (45.ii) of the inorganic passivation layer system (45) and the lateral edge (31.1) of the load pad (31). [10] Semiconductor chip (1) according to claim 9, as far as dependent on claim 2, wherein a runner (32, 33) is formed next to the load pad (31) in the metallization (30), wherein the inorganic passivation layer system (45) above the runner (32, 33) is uninterrupted. [11] Semiconductor chip (1) according to one of claims 3 to 9, as far as dependent on claim 1, wherein the metallization (30) in the region of the load pad (31) is formed with a step (70), wherein the load pad (31) has a first thickness t1 laterally outside the step (70) and a second thickness t2 laterally inside the step (70), wherein t1 is smaller than t2. [12] Semiconductor chip (1) according to claim 11, wherein an inorganic layer (81.1, 81.2) or a layer stack (80) covers a flank (71) of the step (70). [13] Semiconductor chip (1) according to one of the preceding claims, wherein the metallization (30) comprises a copper layer. [14] Semiconductor chip (1) according to one of the preceding claims, wherein the inorganic passivation layer system (45) comprises a silicon nitride layer (45.1, 45.3) and a silicon oxide layer (45.2). [15] Semiconductor chip (1), comprising: a silicon carbide (SiC) semiconductor body (11); an insulating layer (90) on a first side (11.1) of the SiC semiconductor body (11); a passivation system (40) on the first side (11.1) of the SiC semiconductor body (11); a metallization (30) on the first side (11.1) of the SiC semiconductor body (11), in which a load pad (31) is formed; wherein the passivation system (40) covers a lateral edge (31.1) of the load pad (31) and has an opening on the load pad (31), wherein the insulating layer (90) has an outer lateral edge (90.i) on the SiC semiconductor body (11), wherein the passivation system (40) comprises an organic layer (41) on the insulating layer (90), and wherein the insulating layer (90) is laterally recessed under the organic layer (41), wherein the outer lateral edge (90.i) of the insulating layer (90) is covered by the organic layer (41), characterized by , that the metallization (30) is formed with a step (70) in the region of the load pad (31), wherein the load pad (31) has a first thickness t1 laterally outside the step (70) and a second thickness t2 laterally inside the step (70), wherein t1 is smaller than t2. [16] Semiconductor chip (1) according to claim 15, wherein an inorganic layer (81.1, 81.2) or a layer stack (80) covers a flank (71) of the step (70). [17] Semiconductor chip (1) according to claim 15 or 16, wherein the passivation system (40) comprises an inorganic passivation layer system (45), wherein an outer lateral edge (45.i) of the inorganic passivation layer system (45) is arranged on the insulating layer (90). [18] Semiconductor chip (1) according to one of the preceding claims, wherein the organic layer (41) has a thickness of at least 1 µm and / or at most 50 µm. [19] Semiconductor chip (1) according to one of the preceding claims, wherein the organic layer (41) is an imide layer (42). [20] Method for producing the semiconductor chip (1) according to one of the preceding claims, comprising the steps: I) forming (600) the inorganic passivation layer system (45) on the first side (11.1) of the silicon carbide (SiC) semiconductor body (11) such that a lateral edge (45.i) of the inorganic passivation layer system (45) is arranged on the SiC semiconductor body (11); II) forming (610) the organic layer (41) on the inorganic passivation layer system (45) covering the lateral edge (45.i) of the inorganic passivation layer system (45). [21] The method of claim 20, wherein step I) comprises: i) depositing (601) the inorganic passivation layer system (45) on the first side (11.1) of the SiC semiconductor body (11); ii) locally etching away (602) the inorganic passivation layer system (45) to define the lateral edge (45.i) of the inorganic passivation layer system (45). [22] The method of claim 21, wherein a mask (145) is applied for step ii), wherein the mask (145) is removed after the local etching away of the inorganic passivation layer system (45) and before the formation of the organic layer (41) in step II).

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