COMPARATOR CIRCUIT SELF-TEST

Abstract

A circuit arrangement (110) is presented. The circuit arrangement (110) comprises a comparator circuit (112). The comparator circuit (112) is configured to compare a voltage with a provided reference voltage. The circuit arrangement (110) further comprises a time evaluation circuit (114). The time evaluation circuit (114) is configured to determine a time interval between a start signal and a stop signal. The circuit arrangement (110) further comprises a voltage ramp generation circuit (116). The voltage ramp generation circuit (116) is configured to generate a voltage ramp beginning with the start signal. Furthermore, a method for performing a self-test of a comparator circuit (112) and a use of the circuit arrangement (110) and the method for performing a self-test are presented.

Description

TECHNICAL FIELDThe present disclosure relates to a circuit arrangement, a method for performing a self-test of a comparator circuit, and a use thereof.BACKGROUNDComparator circuits may be used for various purposes. For example, in safety-related applications, a comparator circuit may be used to compare an input to a threshold that should not be exceeded during fault-free operation. The threshold may relate, for example, to an overvoltage threshold, an overcurrent threshold or an overtemperature threshold and is typically provided in the form of a reference voltage in the comparator circuit. Thus, the comparator circuit typically compares the reference voltage with an input voltage. In the case of a malfunction, for example due to a deterioration of an element, safety measures typically have to be taken. As indicated, the comparator circuit may identify such a fault by comparing the input voltage to the reference voltage and may output a signal to initiate such a safety provision. For example, the comparator may output a low voltage as long as the input voltage is below the reference voltage, and output a high voltage as soon as the input voltage exceeds the reference voltage. The accuracy of the comparator circuit is typically decisive, in particular for safety-relevant applications. The comparator circuit must not only be functionally capable of switching between outputs, but also the reference voltage must typically be precise and remain stable. Thus, there is a need to improve the reliability of comparator circuits and, in particular, to control the accuracy of the reference voltages used.Document KR 10 2023 0 063 710 A discloses an electronic circuit for performing an analog integrated self test and an operating method thereof. According to an embodiment, the electronic circuit comprises: a ramp signal generator for generating a first ramp signal; an oscillator for generating a clock signal; a first monitoring circuit that operates in a first mode for monitoring an external output voltage or in a second mode for performing ABIST based on the first ramp signal and generates a comparator output; and a logic controller for controlling the first monitoring circuit to operate in the first or second mode. When the first monitoring circuit is operating in the second mode, the logic controller counts the clock signal and generates an ABIST output that indicates whether the first monitoring circuit is operating normally based on a count value and the comparator output.Document KR 10 2021 0 072 526 A discloses a test circuit for testing a monitoring circuit, comprising: a ramp generator configured to generate a ramp signal in response to an activated first control signal; a counter configured to count pulses of a clock signal in response to the activated first control signal; at least one register configured to store an output value of the counter based on a change in at least one output signal generated by the monitoring circuit in response to the ramp signal in a test mode; and a controller configured to generate the first control signal and verify the monitoring circuit based on a ratio of a value stored in the at least one register to a duration during which the first control signal is activated.The document DE 196 34 049 A1 discloses a method for measuring values on electronic, analog circuits having at least one measuring point, in particular safety-relevant circuits for occupant protection systems in motor vehicles. According to the invention, the electrical voltages generated at the measurement points as measured variables are each compared with a gradually increasing ramp voltage, wherein the number of steps required until the voltage value of the measured variable of the respective measurement point is reached is present as a measurement unit proportional to the measured variable.The comparison of all measured variables with the ramp voltage can thus be carried out simultaneously, wherein the ramp voltage is designed such that it extends over the entire measurement range.Document US 2019 / 0 072 589 A1 discloses a digital voltmeter in which a number of clock pulses for a first ramp voltage is determined to achieve an input voltage. Next, a number of clock pulses for a second ramp voltage to reach the input voltage is determined. One of the first and second ramp voltages is determined which requires the least number of clock pulses to reach the input voltage. A number of clock pulses is determined for the particular one of the first and second ramp voltages that reaches a reference voltage. Based on the determined number of clock pulses for reaching the reference voltage and the determined lowest number of clock pulses for reaching the input voltage, a digital code is generated for the input voltage.SUMMARYIn a first aspect, a circuit arrangement is presented. The circuit arrangement comprises a comparator circuit. The comparator circuit is configured to compare a voltage with a reference voltage provided. The circuit arrangement further comprises a time evaluation circuit. The time evaluation circuit is configured to determine a time interval between a start signal and a stop signal. The circuit arrangement further comprises a voltage ramp generation circuit. The voltage ramp generation circuit is configured to generate a voltage ramp beginning with the start signal. In a normal operating mode, the circuit arrangement is configured to compare an input voltage with the reference voltage using the comparator circuit. In a self-test mode for performing a self-test of the comparator circuit, the circuit arrangement is configured to generate a voltage ramp using the voltage ramp generation circuit, to continuously compare the generated voltage ramp with the reference voltage using the comparator circuit and to determine a time interval using the time evaluation circuit in which the generated voltage ramp reaches the reference voltage.In another aspect, a method for performing a self-test of a comparator circuit is presented. The method comprises: a) generating a voltage ramp using a voltage ramp generation circuit; b) continuously comparing the generated voltage ramp with a provided reference voltage using the comparator circuit; and c) determining a time interval using a time evaluation circuit in which the generated voltage ramp reaches the reference voltage.In a further aspect, a use of the circuit arrangement or of the method for an automobile application is presented.Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and upon viewing the accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGSThe present disclosure is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like reference numerals refer to similar or identical elements. The elements of the drawings are not necessarily to scale relative to each other. The features of the various illustrated examples may be combined unless they are mutually exclusive. FIG. 1 schematically illustrates an example of a circuit arrangement according to the present disclosure; FIG. 2 schematically illustrates a signal profile in the circuit arrangement over time; and FIG. 3 illustrates a flowchart of an example of a method for performing a self-test of a comparator circuit according to the present disclosure.DETAILED DESCRIPTIONThe examples described herein provide significant advantages. In particular, they can improve the reliability of comparator circuits, which can be important in particular for safety-relevant applications. In particular, they may control a provided reference voltage in the comparator circuits and adjust it if necessary. Thus, a precise and stable reference voltage can be ensured, which can be used, for example, as a threshold for identifying a malfunction. The accuracy of the reference voltage may be ensured, in particular, by implementing a self-test mechanism that may be performed without requiring a plurality of additional components. Since a comparator circuit is typically part of a superordinate circuit, in particular a superordinate integrated circuit, which typically comprises different components for different purposes, these components can additionally be used for carrying out the addressed self-test. Thus, with the approach provided, the reliability of the comparator circuit may be improved in a robust manner and at low cost, for example in terms of system complexity or in terms of the area consumed on a semiconductor die in an integrated circuit.FIG. 1 schematically illustrates an example of a circuit arrangement 110. The circuit arrangement 110 may be a superordinate circuit comprising a plurality of subordinate circuits. The subordinate circuits may be at least partially connected to each other, such as by using wires or conductive traces. A circuit may generally comprise at least one electronic component, for example a transistor, a resistor, a capacitor or an inductance. In particular, the circuit can comprise a multiplicity of electronic components which are likewise at least partially connected to one another. In particular, the circuit arrangement 110 may be an integrated circuit or may comprise an integrated circuit or may be part of an integrated circuit. Thus, the circuit arrangement 110 may be arranged on a semiconductor die. As an example, silicon, silicon carbide or gallium nitride may be used as the semiconductor material of the semiconductor die. Other options are of course also conceivable.The circuit arrangement 110 comprises a comparator circuit 112. The comparator circuit 112 is configured to compare a voltage with a reference voltage provided. The comparator circuit 112 may be any circuit configured to compare at least two voltages. Thus, an output of the comparator circuit 112 may indicate which input voltage is higher. Various embodiments of a comparator circuit are well known to those skilled in the art and may be used to implement the comparator circuit 112, in particular to implement internal circuitry of the comparator circuit 112. As indicated, the comparator circuit 112 may compare two voltages, one of which may be, in particular, a reference voltage. The reference voltage is indicated by the abbreviation V ref in the figures. The reference voltage may be predetermined. Thus, the reference voltage may be set to a predetermined value, for example, a threshold for identifying a fault case. For example, the reference voltage may be an overvoltage threshold. Additionally or alternatively, the reference voltage may be, for example, a predetermined voltage value that relates to an overcurrent threshold or an overtemperature threshold. However, the reference voltage may be variable. The reference voltage may be unstable over time, for example due to instability of a voltage source. This can impair the detection of a malfunction. Thus, in order to ensure reliable detection of the malfunction and further protection of a corresponding device, the variation should be identified and possibly also compensated, for example by recalibration or readjustment of the reference voltage to an original value.The circuit arrangement 110 further comprises a time evaluation circuit 114. The time evaluation circuit 114 is configured to determine a time interval between a start signal and a stop signal. The start signal and / or the stop signal can be provided to a plurality of components of the circuit arrangement 110, in particular the time evaluation circuit 114 and / or a voltage ramp generation circuit 116, which is described in more detail below. As the name already implies, the start signal may indicate a start or a start of a process and the end signal may indicate a stop or an end of the process. The process can relate in particular to a plurality of components of the circuit arrangement 110, in particular the comparator circuit 112, the time evaluation circuit 114 and the voltage ramp generation circuit 116. As will also be described in more detail below, the process may in particular be a self-test of the comparator circuit 112. Thus, the time evaluation circuit 114 may be configured to record a time period of the self test.Again, various embodiments of a time evaluation circuit are well known to those skilled in the art and may be used to implement the time evaluation circuit 114. In particular, the time evaluation circuit 114 may be or comprise a counter, for example a 7-bit counter. The counter may be configured to start counting with the start signal and stop counting with the stop signal. The time evaluation circuit 114, in particular the counter, can furthermore comprise a clock input. Thus, the time evaluation circuit 114, in particular the counter, may be configured to count clock periods. The clock may be, for example, an oscillator or comprise an oscillator, such as a 75 MHz oscillator. Thus, the counter may count oscillator periods, for example 75 MHz oscillator periods. Such clocks, or in particular oscillators, are typically already part of an integrated circuit in many applications. Thus, no further time evaluation circuit besides that already existing may be required for carrying out the self-test under consideration. This may generally reduce system complexity and in an integrated circuit this may in particular save area on the semiconductor die that may be used elsewhere, for example. Obviously, to perform the self test to improve the accuracy of the reference voltage, the time evaluation circuit 114 should be as precise as possible. However, this is again typically already fulfilled for clocks, or in particular for oscillators, in an integrated circuit which have a variation in the range of typically only 1%.As already stated, the circuit arrangement 110 further comprises the voltage ramp generation circuit 116. The voltage ramp generation circuit 116 is configured to generate a voltage ramp beginning with the start signal. Thus, as said, the start signal may be provided in particular to both the voltage ramp generation circuit 116 and the time evaluation circuit 114, which may be coupled in this sense. Again, various embodiments of a voltage ramp generation circuit are well known to those skilled in the art and may be used to implement the time voltage ramp generation circuit 116. In particular, the voltage ramp generation circuit 116 may include a capacitor 118. The capacitor 118 may be configured to generate the voltage ramp and apply the voltage ramp to the comparator circuit 112 by accumulating electrical charges. As is well known, the voltage generated by capacitors increases linearly with increasing electrical charge stored therein, such that over time a voltage ramp is generated as they are charged.The voltage ramp generation circuit 116 may further include a current source 120. The current source 120 may be configured to supply the capacitor 118 with the electrical charges. Thus, the current source 120 may be connected to the capacitor 118. The current source 120 can be, in particular, a constant current source. Thus, the current source 120 may charge the capacitor 118 constantly over time, in particular. The current source 120 may be supplied by a supply voltage V 1. Thus, a current from the current source 120 may charge the capacitor 118, which may result in a continuous, and in particular linearly increasing voltage generated by the capacitor 118. The current source 120 can furthermore be, in particular, a trimmable current source. During manufacture, capacitances of capacitor 118 may vary from device to device, which may result in different voltage ramps being generated. Such a variation can be compensated for in particular by appropriate trimming of the current source 120 at the end of the production. This may ensure high precision of the voltage ramp generation circuit 116, which may in turn be advantageous to improve the accuracy of the reference voltage.The voltage ramp generation circuit 116 may further include a discharge switch 122. The discharge switch 122 may be, for example, a transistor. The discharge switch 122 may be configured to discharge the capacitor 118 with the start signal. The discharge switch 122 may thus be connected to the capacitor 118 and to ground, for example. When performing the self-test and receiving the start signal, i.e. at the beginning of the self-test, the discharge switch 122 can then discharge the capacitor 118 to ground, so that the capacitor 118 can in turn be charged by the current source 120 for generating the voltage ramp. Thus, when performing the self-test and when not receiving the start signal, i.e. during the course of the self-test, the discharge switch 122 can be opened again, so that it cannot discharge the capacitor 118 directly.The circuit arrangement 110 or in particular the comparator circuit 112 can have two operating modes: a normal operating mode and a self-test mode. In the normal operating mode, the circuit arrangement 110 is configured to compare an input voltage with the reference voltage using the comparator circuit 112. The input voltage may be any voltage of interest. The input voltage may be provided from an external voltage supply. Depending on the application, the input voltage can be, for example, a supply voltage for a device. Thus, in the normal operating mode, the comparator circuit 112 may monitor whether the input voltage is within an acceptable range or whether the input voltage exceeds a threshold indicative of a fault. In FIG. 1, the input voltage is indicated by the abbreviation V in. The input voltage may be applied directly or indirectly to the comparator circuit 112 to compare the input voltage with the reference voltage. In particular, the input voltage may be adjusted using a voltage divider 124 before being applied to the comparator circuit 112, for example due to a limited compatible voltage range of the comparator circuit 112. As an example, the voltage divider 124 may include a resistor 126 and a resistor 128.In the self-test mode, the circuit arrangement 110 is configured to generate a voltage ramp using the voltage ramp generation circuit 116, to continuously compare the generated voltage ramp with the reference voltage using the comparator circuit 112 and to determine the time interval using the time evaluation circuit 114 in which the generated voltage ramp reaches the reference voltage. The circuit arrangement 110 or in particular its components may switch from the normal operating mode to the self-test mode in order to control the accuracy of the comparator circuit 112 using a self-test enable signal. Thus, upon receiving the self-test mode enable signal, each component may transition operation to the self-test mode accordingly. Upon receiving the self-test enable signal and the start signal, the time evaluation circuit 114 may be reset. Thus, the counter may start re-counting up from 0, for example. Further, upon receiving the self-test enable signal and the start signal, the voltage ramp generation circuit 116 may start generating the voltage ramp, such as by discharging the capacitor 118 and thereafter continuously recharging, as described above.The comparator circuit 112 may continuously compare the generated voltage ramp or, in other words, the current voltage value of the generated voltage ramp with the reference value. Thus, once the generated voltage ramp reaches or exceeds the reference voltage, this may be indicated by the comparator circuit 112, such as by changing from a low voltage output to a high voltage output. In FIG. 1, the output voltage of the comparator circuit 112 is indicated by V out. The output voltage of the comparator circuit 112 can also be fed as a stop signal into the time evaluation circuit 114. Thus, upon receiving the self-test enable signal and the stop signal, which may relate to a high voltage output of the comparator circuit 112, for example, the time evaluation circuit 114 may stop recording the time. In other words, the comparator circuit 112 may be further configured to provide the stop signal to the time evaluation circuit 114 when the generated voltage ramp reaches the reference voltage during the self-test of the comparator circuit 112. Thus, the self-test mode may be started with the start signal and stopped with the stop signal, and in the self-test mode, the time evaluation circuit 114 may track or record the time interval between the start signal and the stop signal.The circuit arrangement 110 may further comprise multiplexers 130 and 132 configured to multiplex the reference voltage, the input voltage and the generated voltage ramp. In particular, the first multiplexer 130 may be configured to multiplex the reference voltage and the input voltage at a first comparator input 134. In particular, the first multiplexer 130 can be configured to apply the input voltage to the first comparator input 134 in the normal operating mode and to apply the reference voltage to the first comparator input 134 in the self-test mode. The second multiplexer 132 may be configured to multiplex the reference voltage and the generated voltage ramp at a second comparator input 136. In particular, the second multiplexer 132 can be configured to apply the reference voltage to the second comparator input 136 in the normal operating mode and to apply the generated voltage ramp to the second comparator input 136 in the self-test mode. The transition between the normal operation mode and the self-test mode can be achieved again for the multiplexers 130 and 132 using the above-mentioned self-test enable signal. Thus, in summary, in the normal operating mode, the comparator circuit 112 can compare the input voltage at the first comparator input 134 with the reference voltage at the second comparator input 136. In contrast, in the self-test mode, the comparator circuit 112 may compare the reference voltage at the first comparator input 134 with the generated voltage ramp at the second comparator input 136.FIG. 2 schematically illustrates a signal profile in the circuit arrangement 110 over time, in particular in the self-test mode. As described in greater detail above, the voltage ramp generation circuit 116 may begin generating a voltage ramp with a start signal. In FIG. 2, the voltage ramp is indicated by the abbreviation V ramp. At the same time, the time evaluation circuit 114 can start recording the time. In particular, as also stated in more detail above, the timing evaluation circuit 114 may be or may include a counter having a clock input and the counter may start counting clock signals beginning with the start signal. The comparator circuit 112 may compare the voltage ramp and the reference voltage continuously, as also described in more detail above. Once the voltage ramp reaches the reference voltage, the comparator circuit 112 may then indicate a stop signal to the time evaluation circuit 114. The time evaluation circuit 114 may then count a last clock period and may stop counting thereafter. Thus, a subsequent clock period received after the stop signal cannot be counted any longer. In particular, a rising edge of the subsequent clock period can no longer be taken into account. As already stated, a higher precision of the clock can improve the accuracy of a time interval determined by the time evaluation circuit 114 and thus of a ultimately determined overall reference voltage.The circuit arrangement 110 may be configured to further determine the reference voltage from the determined time interval. Thus, accuracy of the reference voltage or variations of the reference voltage may be monitored and not only a proper transition between a high voltage output and a low voltage output of the comparator circuit 112. As said, in practice, the reference voltage may be unstable over time. As an example, a voltage value of the reference voltage may drift over time, such as due to degradation of a component or due to changing environmental conditions. Thus, in normal operation, a potentially incorrect or at least inaccurate or inaccurate reference voltage can be applied, which can be disadvantageous in particular for safety-relevant applications. In the self-test presented, the actual reference voltage can be determined and the reference voltage can be reset again to the originally intended value. In particular, the reference voltage may be determined from the number of counted clock signals, such as using the following formula: wherein V Ref as said, refers to the reference voltage, n refers to the number of counted clock periods, T refers to a time interval of one clock period, C refers to a capacitance of the capacitor 118, and I refers to a current provided to the capacitor 118 from the current source 120 to generate the voltage ramp. For determining the reference voltage, the circuit arrangement 110 may comprise a further evaluation device, such as a microcontroller, in particular a microcontroller within the same integrated circuit, or at least have access thereto. However, to improve the accuracy of the comparator circuit 112, it may not necessarily be necessary to determine an actual value of the reference voltage. The circuitry 110 may instead perform the self-test repeatedly, for example, and determine a variation of the recorded time intervals that correlates with a variation of the reference voltage. Thus, the reference voltage can also be corrected by compensating for the variations. In any case, the circuit arrangement 110 may be configured to recalibration of the reference voltage. In other words, the circuit arrangement 110 may correct unintended variations of the reference voltage and, in particular, reset the reference voltage to the originally intended value.The circuit arrangement 110 and / or the self-test described can be used in particular in an automobile application, such as for controlling an engine of a vehicle or a vehicle light. In the automotive field, the Automotive Safety Integrity Level (ASIL) is a risk classification scheme defined by the ISO 26262 - Functional Safety for Road Vehicles - Standard. There are four ASILs identified by the standard: ASIL A, ASIL B, ASIL C, ASIL D. ASIL D dictates the highest security requirements and ASIL A the lowest. Hazards identified as QMs related to quality management do not dictate security requirements. The devices and methods illustrated in this disclosure can be used in particular for safety-relevant applications. Thus, in the automotive field, the devices and methods illustrated in this disclosure may be used particularly for ASIL applications.FIG. 3 illustrates a flowchart of an example of a method for performing the self-test. The method comprises the following steps. The method steps shown can be carried out in the sequence indicated. It should be noted, however, that a different order may be possible. The method may comprise further method steps which are not listed. Furthermore, one or more of the method steps can be carried out once or repeatedly. Furthermore, two or more of the method steps can be carried out simultaneously or in a temporally overlapping manner. For example, steps a) to c) may be performed in parallel and / or repeatedly. The method may be at least partially computer-implemented. Thus, one or more of the following method steps may be computer-implemented. a) (denoted by reference numeral 138) generating a voltage ramp using voltage ramp generation circuit 116; b) (denoted by reference numeral 140) continuously comparing the generated voltage ramp with a provided reference voltage using comparator circuit 112; and c) (denoted by reference numeral 142) determining a time interval, using time evaluation circuit 114, in which the generated voltage ramp reaches the reference voltage.As already indicated, step a) may comprise charging the capacitor 118, in particular using the current source 120, and step c) may comprise counting a number of clock periods. Steps a) to c) can be started in particular with a start signal and stopped with a stop signal. The stop signal may be provided to the time evaluation circuit 114 by the comparator circuit 112 when the generated voltage ramp reaches the reference voltage. The start signal may indicate a restart of the generated voltage ramp. The method may further comprise at least one of the following steps:d) (denoted by reference numeral 144) determining the reference voltage from the determined time interval, in particular from a number of counted clock periods;e) (denoted by reference numeral 146) repeatedly performing at least steps a) to c) and determining variation of the determined times.f) (designated 148) recalibrating the reference voltage;g) (denoted by reference numeral 150) comparing an input voltage with the reference voltage using the comparator circuit 112; andh) (denoted by reference numeral 152) multiplexing at least two of the reference voltage, the voltage ramp and the input voltage at at least one of the comparator inputs 134 and 136.In addition to the examples described above, the following examples are disclosed herein:Example 1: A Circuit Arrangement Comprising:• a comparator circuit configured to compare a voltage with a reference voltage provided;• a time evaluation circuit configured to determine a time interval between a start signal and a stop signal; and• a voltage ramp generation circuit configured to generate a voltage ramp starting from the start signal, wherein the circuit arrangement is configured to:• in a normal operating mode:comparing an input voltage with the reference voltage using the comparator circuit; and• in a self-test mode for performing a self-test of the comparator circuit:◯ generating a voltage ramp using the voltage ramp generation circuit; continuously comparing the generated voltage ramp with the reference voltage using the comparator circuit; and◯ determining a time interval, using the time evaluation circuit, in which the generated voltage ramp reaches the reference voltage.Example 2: The circuit arrangement according to the preceding example, wherein the circuit arrangement is further configured to determine the reference voltage from the time interval determined in the self-test of the comparator circuit.Example 3: The circuit arrangement according to any of the preceding examples, wherein the circuit arrangement is further configured to repeatedly perform a self-test of the comparator circuit.Example 4: The circuit arrangement according to the preceding example, wherein the circuit arrangement is further configured to determine a variation of the time intervals determined in the self-tests.Example 5: The circuit arrangement according to one of the preceding examples, wherein the self-test mode is started with the start signal and stopped with the stop signal.Example 6: The circuit arrangement of any of the preceding examples, wherein the circuit arrangement is further configured to re-calibrate the reference voltage.Example 7: The circuit arrangement according to any of the preceding examples, wherein the voltage ramp generation circuit comprises a capacitor, wherein the capacitor is configured to generate the voltage ramp and apply the voltage ramp to the comparator circuit by accumulating electrical charges.Example 8: The circuit arrangement according to the preceding example, wherein the voltage ramp generation circuit further comprises a current source, in particular a constant current source, which is configured to supply the capacitor with the electrical charges.Example 9: The circuit arrangement according to the preceding example, wherein the current source is a trimmable current source.Example 10: The circuit arrangement according to any of the three preceding examples, wherein the voltage ramp generation circuit further comprises a discharge switch configured to discharge the capacitor with the start signal.Example 11: The circuit arrangement according to one of the preceding examples, wherein the comparator circuit is further configured to provide the stop signal to the time evaluation circuit when the generated voltage ramp reaches the reference voltage during the self-test of the comparator circuit.Example 12: The circuit arrangement according to one of the preceding examples, wherein the time evaluation circuit comprises a counter which is configured to start counting with the start signal and to stop counting with the stop signal.Example 13: The circuit arrangement according to the preceding example, wherein the time evaluation circuit further comprises a clock input, wherein the counter is configured to count clock periods.Example 14: The circuit arrangement of any of the preceding examples, wherein the circuit arrangement further comprises at least one multiplexer configured to multiplex at least two of the reference voltage, the input voltage and the generated voltage ramp.Example 15: The circuit arrangement of the preceding example, wherein the circuit arrangement comprises a first multiplexer configured to multiplex the reference voltage and the input voltage at a first comparator input.Example 16: The circuit arrangement according to the preceding example, wherein the first multiplexer is configured to apply the input voltage to the first comparator input in the normal operating mode and to apply the reference voltage to the first comparator input in the self-test mode.Example 17: The circuit arrangement according to any of the three preceding examples, wherein the circuit arrangement comprises a second multiplexer configured to multiplex the reference voltage and the generated voltage ramp at a second comparator input.Example 18: The circuit arrangement according to the preceding example, wherein the second multiplexer is configured to apply the reference voltage to the second comparator input in the normal operating mode and to apply the generated voltage ramp to the second comparator input in the self-test mode.Example 19: The circuit arrangement of any of the preceding examples, wherein the circuit arrangement is an integrated circuit.Example 20: A method for performing a self-test of a comparator circuit, the method comprising: a) generating a voltage ramp using a voltage ramp generation circuit; b) continuously comparing the generated voltage ramp with a provided reference voltage using the comparator circuit; and c) determining a time interval using a time evaluation circuit in which the generated voltage ramp reaches the reference voltage.Example 21: The method of the preceding example, wherein the comparator circuit, the voltage ramp generation circuit, and the time evaluation circuit are comprised by a circuit arrangement according to any of the preceding examples, which relate to a circuit arrangement.Example 22: The method of any of the preceding method examples, wherein step a) comprises charging a capacitor comprised by the voltage ramp generation circuit using a current source comprised by the voltage ramp generation circuit.Example 23: The method of any of the preceding method examples, wherein step c) comprises counting a number of clock periods.Example 24: The method of any of the preceding method examples, further comprising:d) determining the reference voltage from the determined time interval, in particular from a number of counted clock periods.Example 25: The method of the preceding example, wherein the reference voltage is determined using the following formula: wherein V Ref refers to the reference voltage, n refers to the number of counted clock periods, T refers to a time interval of one clock period, C refers to a capacitance of a capacitor comprised by the voltage ramp generation circuit, I refers to a current provided to the capacitor using a current source comprised by the voltage ramp generation circuit.Example 26: The method of any of the preceding method examples, further comprising:e) repeatedly performing at least steps a) to c) and determining a variation of the determined times.Example 27: The method of any of the preceding method examples, further comprising:f) Recalibration of the reference voltage.Example 28: The method according to any of the preceding method examples, wherein steps a) to c) are carried out in parallel.Example 29: The method according to one of the preceding method examples, wherein steps a) to c) are started with a start signal and stopped with a stop signal.Example 30: The method according to the preceding example, wherein the stop signal is provided to the time evaluation circuit by the comparator circuit when the generated voltage ramp reaches the reference voltage.Example 31: The method according to one of the two preceding method examples, wherein the start signal initiates a restart of the generated voltage ramp.Example 32: The method of any of the preceding method examples, further comprising:g) comparing an input voltage with the reference voltage using the comparator circuit.Example 33: The method of the preceding example, wherein the input voltage is provided directly or indirectly from an external voltage supply.Example 34: The method according to one of the two preceding method examples, further comprising:h) multiplexing at least two of the reference voltage, the voltage ramp and the input voltage at at least one comparator input.Example 35: A use for an automobile application of at least one of a circuit arrangement according to any of the preceding examples, which relates to a circuit arrangement, and a method for performing a self-test according to any of the preceding method examples.Although specific examples have been illustrated and described herein, those skilled in the art will recognize that a variety of alternative and / or equivalent implementations may replace the specific examples shown and described without departing from the scope of the present disclosure. This application is intended to cover any adaptations or variations of the specific examples discussed herein. Therefore, it is intended that this disclosure be limited only by the claims and their equivalents.It should be noted that the methods and apparatus, including preferred embodiments thereof, as described herein may be used alone or in combination with the other methods and apparatus disclosed herein. In addition, the features described in connection with a device can also be applied to a corresponding method and vice versa.Moreover, all aspects of the methods and apparatus described herein may be combined as desired. In particular, the features of the claims can be combined with one another in any desired manner.It should be noted that the description and drawings merely illustrate the principles of the proposed methods and systems. Those skilled in the art will be able to implement various arrangements which, although not expressly described or shown herein, embody the principles of the disclosure and are included in the spirit and scope thereof. Moreover, all examples and embodiments described herein are intended to be expressly for illustrative purposes only in order to aid the reader in understanding the principles of the proposed methods and systems. Moreover, all statements herein providing principles, aspects, and embodiments of the disclosure, as well as specific examples thereof, are intended to encompass equivalents thereof.

Claims

A circuit arrangement (110) comprising: • a comparator circuit (112) configured to compare a voltage with a provided reference voltage; • a time evaluation circuit (114) configured to determine a time interval between a start signal and a stop signal; and • a voltage ramp generation circuit (116) configured to generate a voltage ramp starting from the start signal, wherein the circuit arrangement (110) is configured to: • in a normal operating mode: ◯ compare an input voltage with the reference voltage using the comparator circuit (112); and • in a self-test mode for performing a self-test of the comparator circuit (112): ◯ generate a voltage ramp using the voltage ramp generation circuit (116); ◯ continuously compare the generated voltage ramp with the reference voltage using the comparator circuit (112); ◯ determining a time interval using the time evaluation circuit (114) in which the generated voltage ramp reaches the reference voltage, wherein the circuit arrangement (110) comprises a first multiplexer (130) configured to multiplex the reference voltage and the input voltage at a first comparator input (134), wherein the first multiplexer (130) is configured to apply the input voltage to the first comparator input (134) in the normal operating mode and to apply the reference voltage to the first comparator input (134) in the self-test mode, wherein the circuit arrangement (110) comprises a second multiplexer (132) configured to multiplex the reference voltage and the generated voltage ramp at a second comparator input (136), wherein the second multiplexer (132) is configured to apply the reference voltage to the second comparator input (136) in the normal operating mode and to apply the generated voltage ramp to the second comparator input (136) in the self-test mode.The circuit arrangement (110) according to the preceding claim, wherein the circuit arrangement (110) is further configured to determine the reference voltage from the time interval determined in the self-test of the comparator circuit (112).The circuit arrangement (110) according to any one of the preceding claims, wherein the circuit arrangement (110) is further configured to repeatedly perform a self-test of the comparator circuit (112) and to determine a variation of the time intervals determined in the self-tests.The circuit arrangement (110) according to any of the preceding claims, wherein the circuit arrangement (110) is further configured to recalibration of the reference voltage.The circuit arrangement (110) according to any of the preceding claims, wherein the voltage ramp generation circuit (116) comprises a capacitor (118), wherein the capacitor (118) is configured to generate the voltage ramp and apply the voltage ramp to the comparator circuit (112) by accumulating electrical charges.The circuit arrangement (110) according to the preceding claim, wherein the voltage ramp generation circuit (116) further comprises a current source (120), in particular a constant current source, which is configured to supply the capacitor (118) with the electrical charges.The circuit arrangement (110) according to the preceding claim, wherein the current source (120) is a trimmable current source.The circuit arrangement (110) according to any of the three preceding claims, wherein the voltage ramp generation circuit (116) further comprises a discharge switch (122) configured to discharge the capacitor (118) with the start signal.The circuit arrangement (110) according to any one of the preceding claims, wherein the comparator circuit (112) is further configured to provide the stop signal to the time evaluation circuit (114) when the generated voltage ramp reaches the reference voltage during the self-test of the comparator circuit (112).The circuit arrangement (110) according to any one of the preceding claims, wherein the time evaluation circuit (114) comprises a counter configured to start counting with the start signal and to stop counting with the stop signal, wherein the time evaluation circuit (114) further comprises a clock input, wherein the counter is configured to count clock periods.The circuit arrangement (110) according to any of the preceding claims, wherein the circuit arrangement (110) further comprises at least one multiplexer (130, 132) configured to multiplex at least two of the reference voltage, the input voltage and the generated voltage ramp.The circuit arrangement (110) according to any of the preceding claims, wherein the circuit arrangement (110) is an integrated circuit.A method for performing a self-test of a comparator circuit (112) with a circuit arrangement (110) according to any of the preceding claims, which relates to a circuit arrangement (110), the method comprising: a) generating a voltage ramp using a voltage ramp generating circuit (116); b) continuously comparing the generated voltage ramp with a provided reference voltage using the comparator circuit (112); and c) determining a time interval using a time evaluation circuit (114), in which the generated voltage ramp reaches the reference voltage.The method according to the preceding claim, further comprising: d) determining the reference voltage from the determined time interval, in particular from a number of counted clock periods.The method of the preceding claim, wherein the reference voltage is determined using the formula: V Ref = I C ⋅ n ⋅ T, wherein V Ref relates to the reference voltage, n relates to the number of counted clock periods, T relates to a time interval of one clock period, C relates to a capacitance of a capacitor (118) comprised by the voltage ramp generation circuit (116), I relates to a current provided to the capacitor (118) using a current source (120) comprised by the voltage ramp generation circuit (116).The method of any preceding method claim, further comprising: e) repeatedly performing at least steps a) to c) and determining a variation of the determined times.The method of any preceding method claim, further comprising: f) recalibration of the reference voltage.A use for an automotive application of at least one of a circuit arrangement (110) according to any of the preceding claims, relating to a circuit arrangement (110), and a method for performing a self-test according to any of the preceding method claims.

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