Circuit arrangement

Abstract

The invention relates to a circuit arrangement (1) which has a power module (3) and at least one capacitor (2), wherein the power module (3) has a plurality of power transistors on a first substrate, wherein the capacitor (2) and the power semiconductors are connected to one another via at least one first electrical connection and at least one second electrical connection, wherein the electrical connections are formed at least partially by a further substrate, wherein the further substrate is designed as a printed circuit board (5) or as an insulated metal substrate.

Description

[0001] The invention relates to a circuit arrangement comprising a power module and at least one capacitor.

[0002] Such a circuit arrangement is present, for example, in the traction network of an electric or hybrid vehicle, where the power module is an inverter, in particular a pulse-controlled inverter. The capacitor is then a so-called intermediate circuit capacitor. The capacitor and the inverter are then connected to one another via a first electrical connection and a further electrical connection, with the positive high-voltage potential DC+ being applied to the first electrical connection and the negative high-voltage potential DC- being applied to the second electrical connection. The switching losses in the inverter are strongly dependent on the commutation inductance, i.e., the electrical path to the intermediate circuit capacitor. Therefore, a low-inductance electrical connection is desired.

[0003] CN 1 17 412 485 B discloses a circuit arrangement with an intermediate circuit capacitor and power module integrated into a six-layer printed circuit board component. This very compact design is very complex to manufacture. Another problem is the poor heat dissipation of the power losses of the inverter's power transistors.

[0004] In most implementations, the power module therefore has its own substrate (e.g., Cu / ceramic / Cu) on which the power transistors are arranged. The ceramic allows for very effective power dissipation. The electrical connection to the separate DC link capacitor is then established via busbars. To keep the inductance low, these must be placed close together while remaining electrically isolated from each other. Therefore, it is common practice to laminate or overmold the busbars, although this again increases the spacing.

[0005] A circuit arrangement of this type is known from DE 10 2022 207 268 A1.

[0006] From DE 10 2015 115 271 A1, DE 10 2019 133 377 A1 and DE 10 2013 219 833 A1, further circuit arrangements are known, each comprising a power module and at least one capacitor, wherein the connection between the power module and the capacitor is made via a further substrate in the form of a printed circuit board.

[0007] The invention is therefore based on the technical problem of creating a generic circuit arrangement in which commutation inductance is reduced.

[0008] The solution to the technical problem is achieved by a circuit arrangement having the features of claim 1. Further advantageous embodiments of the invention emerge from the subclaims.

[0009] The circuit arrangement comprises a power module and at least one capacitor. The power module further comprises a plurality of power transistors on a first substrate. The capacitor and the power semiconductors are connected to one another via at least one first electrical connection and at least one second electrical connection. The electrical connections are at least partially formed by a further substrate, wherein the further substrate is designed as a printed circuit board. This makes it possible to achieve very tight (closely spaced) routing of the electrical connections, so that the inductance is low. In particular, use is made of the sophisticated insulation technology used in multilayer printed circuit boards. The substrate of the power module is preferably designed as a Cu-ceramic-Cu substrate.

[0010] The electrical connections are formed in different metallization levels of the circuit board. This allows almost the entire metallization level to be used as an electrical connection, which is advantageous in terms of resistance and current carrying capacity. The thickness of the metallization level is preferably between 140 - 210 µm (equivalent to 4 - 6 ounces per square foot). 2 ), with the metallization layer preferably being made of copper. Alternatively, the circuit board can also be manufactured using thick-copper technology, where layer thicknesses of up to 400 µm are achieved. With an IMS, thicknesses greater than 400 µm can be achieved.

[0011] Furthermore, the circuit board has at least four metallization levels, with the first electrical connection and the second electrical connection each having at least two metallization levels. This can improve the current-carrying capacity. The metallization levels of the first electrical connection and the second electrical connection are arranged alternately one above the other, so that the inductance is reduced to a non-alternating arrangement.

[0012] The power module is preferably designed as part of a pulse inverter.

[0013] In another embodiment, a top metallization layer and a bottom metallization layer are uncontacted or connected to a ground connection. The top and bottom metallization layers thus act as shields for the first and second electrical connections.

[0014] In a further embodiment, at least one metallization layer is formed with at least one contact tab. This simplifies direct contact between the circuit board and the power module, in particular with the power transistors.

[0015] In a further embodiment, at least one metallization level of the first electrical connections and at least one metallization level of the second electrical connection are structured with contact tabs, wherein the contact tabs are arranged alternately, which reduces the inductance.

[0016] In a further embodiment, the further substrate is directly connected to the power module, e.g. soldered, welded or sintered.

[0017] In an alternative embodiment, the additional substrate is connected to the power module via pins or leadframes. The connection can be made by soldering, welding, sintering, pressing, clamping, clinching, plugging, or gluing.

[0018] The invention is explained in more detail below using preferred embodiments. The figures show: Fig. 1 a schematic representation of a circuit arrangement in a first embodiment, Fig. 2 a schematic representation of a circuit arrangement in a second embodiment, Fig. 3 a schematic representation of a printed circuit board in a third embodiment not according to the claims, Fig. 4a shows a representation of metallization levels for a first electrical connection and a second electrical connection and Fig. 4b shows an illustration of metallization levels for a first electrical connection and a second electrical connection in an alternative embodiment.

[0019] In the Fig. Figure 1 shows a highly schematic representation of a first embodiment of a circuit arrangement 1. The circuit arrangement 1 comprises a capacitor 2 and a power module 3, wherein the power module 3 is designed as a pulse-controlled inverter 4. The power module 3 has a substrate on which the power transistors are arranged. The power transistors are the high-side and low-side switches of the pulse-controlled inverter, wherein the high-side switches are to be connected to the positive potential DC+ and the low-side switches to the negative potential DC-. To connect the capacitor 2 and the power module 3, a printed circuit board 5 is provided which has four metallization levels 6, between which insulation layers 7 are arranged. The capacitor 2 and the power module 3 are connected to the printed circuit board 5 via pins 8.A first electrical connection for the positive potential DC+ is formed by a pin 8 of the capacitor 2 and two metallization levels 6 as well as a pin 8 of the power module 3. The second electrical connection for the negative potential DC is formed accordingly. The metallization levels 6 for DC+ and DC- are arranged alternately. Recesses 9 are shown in the metallization levels 6, where the pins 8 can be passed through the metallization levels 6 without contacting them. The circuit board 5 can be designed as a multi-layer conventional circuit board or as a flexible circuit board. Preferably, the metallization level is as thick as possible. Therefore, the circuit board can also be manufactured using thick-film copper technology. The number of metallization levels 6 can also be greater than 4, e.g., 6, 8, or 12.Due to the fact that the insulation layers 7 are very thin, the resulting inductance is very small.

[0020] In the Fig. 2 shows an alternative embodiment of the circuit arrangement 1, the only difference to the embodiment according to Fig. 1 is that the pins 8 on the power module 3 are omitted and the circuit board 5 is connected directly to the power transistors, which will be explained in more detail later.

[0021] In the Fig. Figure 3 shows a further embodiment, wherein only the circuit board 5 is shown in cross-section without the cutouts 9. The difference is that the uppermost and lowermost metallization levels 6 are not used for the first and second electrical connections, but are connected to ground GND or are uncontacted, thus forming a shield.

[0022] In Fig. 4a and Fig. 4b shows two metallization levels 6, whereby the insulation layers 7 above, between and below are not shown (see Fig. 2). One metallization level 6 is used to connect DC+ and the other for DC-. The metallization levels 6 have the following Fig. 4a has alternating contact tabs 10, by means of which the power transistors are then directly contacted. In Fig. Figure 4b shows an alternative embodiment, in which the contact tabs 10 are formed by cutouts. For contacting, the insulation layers 7 in the area of ​​the contact tabs 10 are removed, leaving them exposed. The design of the contact tabs 10 depends crucially on the arrangement of the high-side and low-side switches on the substrate of the power module 3. List of reference symbols 1 Circuit arrangement 2 capacitors 3 Power module 4 pulse inverters 5 circuit board 6 Metallization level 7 Insulation layer 8-pin 9 Recess 10 contact tab DC+ positive potential DC- negative potential GND Ground

Claims

[1] Circuit arrangement (1) comprising a power module (3) and at least one capacitor (2), wherein the power module (3) comprises a plurality of power transistors on a first substrate, wherein the capacitor (2) and the power transistors are connected to one another via at least one first electrical connection and at least one second electrical connection, wherein the electrical connections are formed at least partially by a further substrate, wherein the further substrate is designed as a printed circuit board (5), wherein the electrical connections are formed in different metallization levels (6) of the printed circuit board (5), wherein the printed circuit board (5) has at least four metallization levels (6), wherein the first electrical connection and the second electrical connection each have at least two metallization levels (6), characterized bythat the metallization levels (6) of the first electrical connection and the second electrical connection are arranged alternately one above the other. [2] Circuit arrangement (1) according to claim 1, characterized by that the power module (3) is designed as part of a pulse inverter (4). [3] Circuit arrangement (1) according to claim 1 or 2, characterized by that a top metallization level (6) and a bottom metallization level (6) are uncontacted or connected to a ground (GND). [4] Circuit arrangement (1) according to one of claims 1 to 3, characterized by that at least one metallization level (6) is structured with at least one contact tab (10). [5] Circuit arrangement (1) according to claim 4, characterized bythat at least one metallization level (6) of the first electrical connection and at least one metallization level (6) of the second electrical connection are structured with contact tabs (10), wherein the contact tabs (10) are arranged alternately. [6] Circuit arrangement (1) according to one of the preceding claims, characterized by that the further substrate is directly connected to the power module (3). [7] Circuit arrangement (1) according to one of claims 1 to 5, characterized by that the further substrate is connected to the power module (3) via pins (8).

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