Phase-locked loop with monitored digital-to-time converter

Abstract

The present invention relates to a phase-locked loop (1) comprising a time-to-digital converter (2) for detecting a phase of a reference signal (100), wherein a feedback signal (200) formed from an output signal (300) of the phase-locked loop (1) is supplied to the time-to-digital converter (2), wherein the phase-locked loop (1) comprises a digital-to-time converter (3) configured for applying dithering to the feedback signal (200) or to the reference signal (100), wherein the digital-to-time converter (3) is part of a ring oscillator with a predefined oscillation frequency, and wherein the phase-locked loop (1) comprises an evaluation unit for detecting an actual frequency of the ring oscillator.

Description

State of the art

[0001] The present invention relates to a phase-locked loop. The phase-locked loop is supported by a digital-to-time converter and allows monitoring of the performance of the digital-to-time converter.

[0002] In phase-locked loops, it is common practice to employ digital-to-time converters (DTCs). This means that dithering is applied to a feedback signal or the reference signal of the phase-locked loop. Due to safety requirements, it may be necessary to monitor the DTC as part of a self-test. However, such monitoring can be very difficult, especially in highly complex digital phase-locked loops with DTCs. For example, directly measuring the DTC with a range of less than 100 ps and a maximum step size of 1 ps at an accuracy of < 0.3 LSB on a system-on-a-chip is extremely challenging. Disclosure of the invention

[0003] The phase-locked loop according to the invention allows for reliable performance monitoring of a digital-to-time converter used therein during a self-test, and thus for a reliable determination of the converter's health status. This determination is particularly time-efficient and reliable. The phase-locked loop therefore enables a reliable self-test, also known as a built-in self-test (BIST).

[0004] The phase-locked loop includes a time-to-digital converter for capturing the phase of a reference signal. The phase-locked loop is formed by feeding a feedback signal, derived from an output signal of the phase-locked loop, back to the time-to-digital converter.

[0005] Furthermore, the phase-locked loop includes a digital-to-time converter (DCT) designed to apply dithering to the feedback signal or the reference signal. Specifically in digital phase-locked loops, the DCT is used to apply dithering to the relatively coarse quantization steps of the phase measurement via the phase-locked loop's time-to-digital converter (TDC). Typically, the time steps of the DCT are significantly smaller than those of the TDC to suppress or avoid aliasing effects. These short time steps complicate monitoring by timing measurement or conversion to voltages or currents when high-precision monitoring is required.

[0006] It is therefore intended that the digital-to-time converter is part of a ring oscillator with a predefined oscillation frequency. This predefined oscillation frequency is specifically dependent on an input value of the digital-to-time converter, since a predefined delay is expected for each input value, and this delay is reflected in the predefined oscillation frequency. A frequency can also be measured with high precision and easily generated by the ring oscillator, making the frequency an optimal criterion for determining the health status of the digital-to-time converter.

[0007] The phase-locked loop includes an evaluation unit for capturing the actual frequency of the ring oscillator. This provides both the actual frequency of the ring oscillator, which can be determined easily and with high precision, and a target frequency for comparison. This allows for a reliable assessment of the digital-to-time converter's health status.

[0008] The dependent claims describe preferred embodiments of the invention.

[0009] The ring oscillator preferably includes a delay element with a fixed delay. This delay element allows the predefined oscillation frequency of the ring oscillator to be adjusted to the parameters of the evaluation unit. Furthermore, the delay element minimizes any negative influence of the ring oscillator on the digital-to-time converter. In particular, the delay element is adjustable to calibrate the delay, for example, to adapt it to process variations during the manufacturing of the phase-locked loop or to the phase-locked loop hardware.

[0010] A NAND module is preferably arranged between the delay element and an output of the digital-to-time converter. This module has as inputs the output of the digital-to-time converter and a test signal. When a test is to be performed, the output of the digital-to-time converter is fed to the delay element and, in particular, back to the input of the digital-to-time converter to form a ring required for the ring oscillator.

[0011] Preferably, a multiplexer is connected upstream of a reference clock input of the digital-to-time converter. Depending on the test execution signal, the multiplexer is configured to apply either a reference clock signal or the output of the delay element to the reference clock input. This again forms a ring oscillator when a test is to be performed. Outside of test times, the digital-to-time converter functions normally without any influence from the ring oscillator.

[0012] The evaluation unit preferably includes a counter. The counter is used to count the oscillation periods of the ring oscillator. This makes it possible to determine the actual frequency of the ring oscillator. Counting the oscillation periods is simple and highly precise. This allows for the acquisition of high-quality measurement results that can be used to determine the health status of the digital-to-time converter.

[0013] The counter is preferably a binary counter of size N, where N is a natural number. A digital implementation of the counter is particularly advantageous.

[0014] Furthermore, it is preferably provided that the evaluation unit includes a sampling module. The sampling module serves to sample an output of the counter with a predefined clock signal. This allows the frequency to be determined, since the sampling combines a time factor with the counter's result, thus enabling the determination of the number of oscillation periods per unit of time. This allows the actual oscillation frequency of the ring oscillator to be determined.

[0015] A particularly advantageous feature of the evaluation unit is its frequency estimation module. This module is designed to efficiently estimate the actual frequency of the ring oscillator based on the output of the sampling module. This enables, in particular, continuous and reliable determination of the ring oscillator's actual frequency.

[0016] In particular, the frequency estimation module is designed to estimate the actual frequency of the ring oscillator using the least squares method. This allows for a particularly fast frequency determination, i.e., the reliable determination of the frequency based on just a few oscillation periods of the ring oscillator, even with unavoidable noise superposition. The determined actual frequencies can then be analyzed to identify inconsistencies in the operation of the digital-to-time converter and thus monitor its overall health.

[0017] In an advantageous embodiment, the evaluation unit is designed to estimate an integral nonlinearity and / or a differential nonlinearity of the digital-to-time converter by comparing the actual frequency with the predefined oscillation frequency. Brief description of the drawings

[0018] Exemplary embodiments of the invention are described in detail below with reference to the accompanying drawings. The drawing shows: Fig. 1a a schematic view of a phase-locked loop according to an embodiment of the invention when using the digital-to-time converter in the feedback path, and Fig. 1b a schematic view of a phase-locked loop according to an embodiment of the invention when using the digital-to-time converter in the path of the reference signal, and Fig. 2 a schematic view of a ring oscillator with a digital-to-time converter of the phase-locked loop according to the embodiment of the invention. Embodiments of the invention

[0019] Preferably, all identical components, elements and / or units in all figures are provided with the same reference numerals.

[0020] Fig. Figure 1a schematically shows a phase-locked loop (PLL). Specifically, PLL is a digital phase-locked loop (DPLL) or an all-digital phase-locked loop (ADPLL). PLL is supported by a digital-to-time converter (DTC) in the feedback path.

[0021] The phase-locked loop 1 serves to adjust the phase of an oscillator according to the phase of a reference signal 100. In the illustrated embodiment, a digitally controlled oscillator 13, also called a DCO, is provided. To determine the phase, the reference signal 100 is first fed to a time-to-digital converter 2, the result of which passes through a loop filter 12 and reaches the oscillator 13. The loop filter 12 is, for example, a digital loop filter, also called a digital loop filter (DLF). The resulting output signal 300 is fed back to obtain a feedback signal 200, which is also fed back to the time-to-digital converter 2.

[0022] The feedback signal 200, for example, passes through a frequency divider 14, with one output 700 of the frequency divider 14 being fed to the digital-to-time converter 3 to apply dithering to the feedback signal 200. The digital-to-time converter 3 has, for example, a step size of 1 ps with a range of 63 ps. Therefore, the performance of the digital-to-time converter 3 cannot be directly measured. To nevertheless enable a self-test, the digital-to-time converter 3 is embedded in a ring oscillator 5, which is Fig. 2 is shown schematically. In this way, the possibility of a built-in self-test, also abbreviated BIST, is achieved.

[0023] Fig. Figure 1b shows an alternative implementation of the phase-controlled loop 1, wherein the phase-controlled loop 1 here has a phase detection unit 2, 3, which is used to detect a phase difference between a reference signal 100 and a feedback signal 200 and to output a measurement signal φ representing the phase difference. meas is trained.

[0024] The phase detection unit 2, 3 comprises a series circuit consisting of a digital-to-time converter 3 and a time-to-digital converter 2 for phase measurement. The digital-to-time converter 3 is connected upstream of the time-to-digital converter 2 and serves to apply a dither to the reference signal 100, which can be supplied to the digital-to-time converter 3. An output of the digital-to-time converter 3 can be supplied to the time-to-digital converter 2, with the applied dither advantageously compensating for the relatively coarse quantization steps of the time-to-digital converter 2. The feedback signal 200 can also be supplied to the time-to-digital converter 2.

[0025] In this embodiment, the phase-locked loop 1 also includes an optional modulator unit 15, wherein the modulation in the illustrated embodiment is a two-point modulation. For this purpose, an optional input unit 16, 17 is provided, which is configured to generate a target signal φ. tgt In the illustrated embodiment, the input unit 16, 17 has a ramp generator 16, which serves to generate a ramp signal. This is converted to the target signal φ via an integrator 17. tgt The ramp signal is also output to modulator unit 15.

[0026] A phase deviation detection unit 18 is designed to generate an error signal φ err from the measurement signal φ meas and the target signal φ tgt By taking the target signal φ into account tgt The aforementioned two-point modulation is achieved.

[0027] The phase-locked loop 1 has a loop filter 12 for filtering the error signal φ. err the output of the loop filter 12 can be fed to the modulator unit 15. The loop filter 12 is, for example, a digital loop filter, also called a digital loop filter (DLF). The loop filter 12 thus receives the modulated or, in an alternative configuration, the unmodulated result of the time-to-digital converter 2.

[0028] The modulator unit 15 serves to modulate the filtered error signal and to generate a tune signal 500. The oscillator 13 can be controlled by the tune signal 500, which in turn generates an output signal 300 from the tune signal 500. The feedback signal 200 supplied to the phase detection unit 2 is derived from the output signal 300 of the phase-locked loop 1.

[0029] Modulator unit 15 represents a second point of the two-point modulation. For example, modulator unit 15 is a delta-sigma modulator. If modulation is not desired, modulator unit 15, setpoint units 16 and 17, and phase deviation detection unit 18 can be omitted in an alternative configuration.

[0030] Fig.Figure 2 schematically shows a ring oscillator 5 of the phase-locked loop 1 according to the embodiment of the invention. The digital-to-time converter 3 is part of this ring oscillator 5, which has a predefined oscillation frequency. This predefined oscillation frequency is influenced by the digital-to-time converter 3, as it introduces a corresponding delay for a predetermined input value, resulting in the predefined oscillation frequency. Thus, the oscillation frequency of the ring oscillator 5 represents a measure of the functionality of the digital-to-time converter 3. By comparing the predefined oscillation frequency with a measured actual frequency of the ring oscillator 5, the health status of the digital-to-time converter 3 can be determined. The phase-locked loop 1 therefore includes an evaluation unit 4 for measuring the actual frequency of the ring oscillator 5.

[0031] A NAND module 7 is provided, which has as inputs the output 3a of the digital-to-time converter 3 and a test signal 400. The output of the NAND module 7 is fed to a delay element 6 with a fixed delay. A multiplexer 8 is connected upstream of a reference clock input 3b of the digital-to-time converter 3. Depending on the test signal 400, the multiplexer 8 is configured to apply either a reference clock signal 500 or the output of the delay element 6 to the reference clock input 3b. In this way, the ring oscillator 5 can be closed by the test signal 400 to test the digital-to-time converter 3.

[0032] The evaluation unit 4 includes a counter 9 for counting the oscillation periods of the ring oscillator 5. Counter 9 is a binary counter with size N, where N is a natural number. Evaluation unit 4 also includes a sampling module 10 for sampling an output of counter 9 with a predefined clock signal. The predefined clock signal is the reference clock signal 500.

[0033] Furthermore, the evaluation unit 4 includes a frequency estimation module 11. The frequency estimation module 11 is configured to estimate the actual frequency of the ring oscillator 5 based on the output of the sampling module 10. In this embodiment, this is done using the least squares method.

[0034] The described setup allows the health status of the digital-to-time converter to be determined based on the actual frequency of the ring oscillator 5. The frequency estimation module 11 reliably detects the actual frequency, requiring only a few oscillation periods of the ring oscillator 5. The fixed delay of the delay element 6 allows the oscillation frequency of the ring oscillator 5 to be adapted to the characteristics and boundary conditions of the counter 9 and the sampling module 10. Furthermore, production-related variations can be calibrated out.

[0035] For example, the fixed delay 6 is 200 ps. With an exemplary step size of 1 ps for the digital-to-time converter 3 and 64 steps [0..63], this results, for example, in a frequency of the ring oscillator 5 of [1.901; 1.908;...2.487; 2.5] GHz. In this case, the smallest frequency step is 7.25 MHz, since for one period of the ring oscillator 5, both the delay element 6 and the digital-to-time converter 3 are traversed twice.

[0036] Using a reference clock signal of 500 MHz from 100 MHz, the necessary size N of the counter 9 can be calculated according to the formula: N=ceil(log2(2.5GHz100MHz))=5 bit

[0037] The operation ceil(...) rounds up to the nearest natural number. Thus, a 5-bit counter 9 is used to count the oscillation periods of the ring oscillator 5 to reliably determine its actual frequency.

[0038] The required measurement accuracy is, for example, 1 / 10 LSB. This corresponds to a standard deviation of <725 kHz. Based on linear regression, this results in a requirement of 27 samples from counter 9. The total duration of a test cycle with 64 steps of the digital-to-time converter 3 can therefore be calculated according to the formula: TBIST=1100 MHz×64×27=17.28 μs

[0039] Thus, a highly accurate test of the digital-to-time converter 3 can be performed very quickly by determining the actual frequency of the ring oscillator 5. For example, the evaluation unit 4 is designed to estimate integral and / or differential nonlinearity of the digital-to-time converter 3 by comparing the actual frequency with the predefined oscillation frequency. This enables reliable self-testing.

Claims

[1] Phase-locked loop (1) comprising a time-to-digital converter (2) for detecting a phase of a reference signal (100), wherein a feedback signal (200) formed from an output signal (300) of the phase-locked loop (1) is supplied to the time-to-digital converter (2), - wherein the phase-locked loop (1) includes a digital-to-time converter (3) configured to apply dithering to the feedback signal (200) or to the reference signal (100), - wherein the digital-to-time converter (3) is part of a ring oscillator (5) with a predefined oscillation frequency, and - wherein the phase-locked loop (1) has an evaluation unit (4) for detecting an actual frequency of the ring oscillator (5). [2] Phase-controlled loop (1) according to claim 1, characterized by , that the ring oscillator (5) has a delay element (6) with a fixed delay. [3] Phase-controlled loop (1) according to claim 2, characterized by , that between the delay element (6) and an output (3a) of the digital-to-time converter (3) a NAND module (7) is arranged, which has as inputs the output (3a) of the digital-to-time converter (3) and a test execution signal (400). [4] Phase-controlled loop (1) according to claim 2 or 3, characterized by , that a multiplexer (8) is connected upstream of a reference clock input (3b) of the digital-to-time converter (3), wherein the multiplexer (8) is configured to apply either a reference clock signal (500) or the output of the delay element (6) to the reference clock input (3b) depending on the test execution signal (400). [5] Phase-controlled loop (1) according to any one of the preceding claims, characterized by , that the evaluation unit (4) has a counter (9) for counting the oscillation periods of the ring oscillator (5) in order to determine the actual frequency of the ring oscillator (5). [6] Phase-controlled loop (1) according to claim 5, characterized by , that the counter (9) is a binary counter of size N, where N is a natural number. [7] Phase-controlled loop (1) according to claim 5 or 6, characterized by , that the evaluation unit (4) has a sampling module (10) to sample an output of the counter (9) with a predefined clock signal. [8] Phase-controlled loop (1) according to claim 7, characterized by , that the evaluation unit (4) has a frequency estimation module (11) which is configured to estimate the actual frequency of the ring oscillator (5) based on the output of the sampling module (10). [9] Phase-controlled loop (1) according to claim 8, characterized by , that the frequency estimation module (11) is configured to estimate the actual frequency of the ring oscillator (5) using the least squares method. [10] Phase-controlled loop (1) according to any one of the preceding claims, characterized by, that the evaluation unit (4) is designed to estimate an integral nonlinearity and / or a differential nonlinearity of the digital-to-time converter (3) by comparing the actual frequency with the predefined oscillation frequency.

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