FORMATION OF CFETS THROUGH LOW-TEMPERATURE NEW GROWTH

Abstract

A method comprises forming a lower transistor and an upper transistor above the lower transistor. The lower transistor has a lower source / drain region above a semiconductor substrate, and the lower source / drain region has a bottom surface facing the semiconductor substrate. The upper transistor has an upper source / drain region positioned above the lower source / drain region. The method further comprises forming a contact opening to expose the bottom surface of the lower source / drain region, performing an epitaxial process to grow a semiconductor layer on the lower source / drain region, and forming a silicide layer that is electrically connected to the lower source / drain region through the semiconductor layer.The regrowth of low-temperature epitaxy semiconductor layers from the back side of the source / drain regions reduces the resistance of the lower source / drain regions and the corresponding contact resistance. Applying low-temperature epitaxy to form the source / drain regions further reduces the resistance of these regions and their corresponding contact connections.

Description

PRIORITY CLAIM AND CROSS-REFERENCE

[0001] This patent application claims priority from the following provisional US patent application: Application number 63 / 718,011, filed on November 8, 2024, entitled “Semiconductor Device and Method for Fabricating the Same”, which is incorporated by reference into the present application. BACKGROUND

[0002] Semiconductor devices are used in a wide variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers onto a semiconductor substrate and structuring the various material layers using lithography to create circuit components and elements on them.

[0003] By continuously reducing the minimum feature size, which allows more components to be integrated into a given area, the semiconductor industry is constantly improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). However, reducing the minimum feature size introduces additional problems that need to be addressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying figures. It should be noted that, in accordance with industry practice, various elements are not shown to scale. In fact, the dimensions of various features or elements may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 shows a perspective view of an exemplary complementary field-effect transistor (CFET) in accordance with some embodiments. The Fig. Figures 2-6, 7A, 7B and 8-16 are views of intermediate stages in the manufacture of CFETs in accordance with some embodiments. Fig. 17 presents a process flow for manufacturing the CFETs in Fig. 16 in accordance with some embodiments. The Fig. Figures 18-37 are views of intermediate stages in the manufacture of CFETs in accordance with some embodiments. Fig. 38 presents a process flow for manufacturing the CFETs in Fig. 37 in accordance with some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides numerous different embodiments, or examples, for implementing various features / elements of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not to be considered as limitations. For example, the formation of a first element above or on top of a second element in the following description may include embodiments in which the first and second elements are in direct contact with each other, but may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements are not in direct contact with each other.Furthermore, the present disclosure may repeat reference numerals and / or reference symbols in the various examples. This repetition serves the purpose of simplification and clarity and does not in itself prescribe a relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, terms of spatial relationships, such as "underlying," "below," "lower," "above," "upper," and the like, may be used herein for a simpler description of the relationship of one element or feature to another element(s) or feature(s) shown in the figures. These spatial relationship terms serve to encompass various other orientations of the device during its use or operation, in addition to the orientation depicted in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatial relationship terms used herein may be interpreted accordingly.

[0007] Complementary field-effect transistors (CFETs) and the methods for their fabrication are provided. In accordance with some embodiments, each CFET has a lower source / drain region and an upper source / drain region that overlaps the lower source / drain region. A backside regrowth process is performed from the back of the CFET. Germanium-containing epitaxial layers are formed from the back of the lower source / drain region. The epitaxial process can be performed at a low temperature to achieve a high activation rate in the lower source / drain region.

[0008] In accordance with the alternative embodiments, lower dummy source / drain regions and upper dummy source / drain regions are formed. The upper dummy source / drain regions are then removed from the front side of the wafer, and upper substitute source / drain regions are formed by low-temperature epitaxy. The lower dummy source / drain regions are removed from the back side of the wafer, and lower substitute source / drain regions are formed by low-temperature epitaxy. The dummy source / drain regions facilitate the self-alignment of the low-temperature epitaxy. The low-temperature epitaxy enhances the activation of the substitute source / drain regions.

[0009] Although all-around gate transistors (GAA transistors) (such as nanostructured FETs) are discussed as examples, it is understood that the concept of the present disclosure can also be applied to the formation of other types of transistors, such as planar transistors, fin field-effect transistors (FinFETs), or the like. Throughout this description, the terms "FET" and "transistor" are used synonymously.

[0010] Figure 1 shows an example of CFETs 10 (which incorporate the FETs (transistors) 10U and 10L) in accordance with some embodiments. Fig. Figure 1 is a three-dimensional view, with some elements of the CFETs omitted for the sake of clarity.

[0011] The CFETs feature multiple vertically stacked FETs. For example, a CFET can have a lower nanostructure FET 10L of a first device type (e.g., type n / type p) and an upper nanostructure FET 10U of a second device type (e.g., type p / type n), which is oriented opposite the first device type. The nanostructure FETs 10U and 10L feature semiconductor nanostructures 26' (which include lower semiconductor nanostructures 26'L and upper semiconductor nanostructures 26'U), with the semiconductor nanostructures 26' serving as the channel regions for the nanostructure FETs. The lower semiconductor nanostructures 26'L are configured for the lower nanostructure FET 10L, and the upper semiconductor nanostructures 26'U are configured for the upper nanostructure FET 10U.

[0012] Gate dielectrics 78 surround the respective semiconductor nanostructures 26'. Gate electrodes 80 (each comprising a lower gate electrode 80L and an upper gate electrode 80U) are arranged over the gate dielectrics 78. Source / drain regions 62 (equivalent to lower source / drain regions 62L and upper source / drain regions 62U) are arranged on opposite sides of the gate dielectrics 78 and the respective gate electrodes 80. Depending on the context, the term source / drain region may refer to a source and / or a drain individually or collectively. Insulating elements (not shown) may be formed to separate certain source / drain regions 62 and / or certain gate electrodes 80.

[0013] Fig. Figure 1 further represents reference cross-sections, which are used in later figures. Cross-section A - A is a vertical cross-section that runs parallel to a longitudinal axis of the semiconductor nanostructures 26' of a CFET and, for example, in the direction of current flow between the source / drain regions 62 of the CFET. Cross-section B - B' is a vertical cross-section that runs perpendicular to cross-section A - A' and along a longitudinal axis of a gate electrode 80 of the CFET. For clarity, the following figures refer to these reference cross-sections.

[0014] The Fig. Figures 2 to 17 show cross-sectional views of intermediate stages in the formation of CFETs (which are in Fig. 1 are shown schematically) in accordance with some embodiments. The corresponding processes are also shown in process flow 200, which is in Fig. Figure 17 is shown schematically. Unless otherwise stated, in the following discussion, figures with numbers followed by the letter “A” represent the vertical cross-sectional views along a cross-section similar to the vertical reference cross-section A - A’ in Figure 1. Figures with numbers followed by the letter “B” represent the cross-sectional views along a cross-section similar to the vertical reference cross-section B - B’ in Figure 1.

[0015] In Fig. A wafer 2, which has a substrate 20, is provided. The substrate 20 can be a semiconductor substrate, such as a basic semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which can be doped (for example, with a p-type or n-type dopant) or undoped. The SOI substrate can have a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide layer (BOX layer), a silicon oxide layer, or the like. The insulating layer is provided on a substrate, such as a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, can also be used.In some embodiments, the semiconductor material of substrate 20 may include silicon, germanium, carbon-doped silicon, a III-V compound semiconductor; or the like, or combinations thereof.

[0016] A multi-layered stack 22 is formed above the substrate 20. The process in question is in process sequence 200, which is in Fig. Figure 17 is shown as process 202. The multilayer stack 22 has alternating dummy semiconductor layers 24 (which have dummy semiconductor layers 24A and 24B) and semiconductor layers 26 (which have lower semiconductor layers 26L and upper semiconductor layers 26U). The lower semiconductor layers 26L and the upper semiconductor layers 26U serve to form a lower FET and an upper FET, respectively.

[0017] Corresponding wells (not shown) can be formed in the lower semiconductor layers 26L and the upper semiconductor layers 26U. The semiconductor layers 26L and 26U can, for example, be doped in situ (during epitaxial growth) and / or implanted to obtain the desired conductivity types.

[0018] In the illustrated example, the multilayer stack 22 has six dummy semiconductor layers 24 and six semiconductor layers 26. However, it is understood that the multilayer stack 22 can have any number of dummy semiconductor layers 24 and semiconductor layers 26. Each layer of the multilayer stack 22 can be grown by a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), or deposited by a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like.

[0019] The dummy semiconductor layers 24A are formed from a first semiconductor material, and the dummy semiconductor layer 24B is formed from a second semiconductor material that differs from the first. Both the first and second semiconductor materials can be selected from the available semiconductor materials of the substrate 20. The first and second semiconductor materials exhibit high etch selectivity with respect to each other. Therefore, the dummy semiconductor layer 24B can be removed at a higher rate in subsequent processes than the dummy semiconductor layers 24A.

[0020] The semiconductor layers 26 (comprising the lower semiconductor layers 26L and the upper semiconductor layers 26U) are formed from one or more semiconductor materials. The semiconductor material(s) can be selected from the available semiconductor materials of the substrate 20. The lower semiconductor layers 26L and the upper semiconductor layers 26U can be formed from the same semiconductor material or from different semiconductor materials.

[0021] In some embodiments, the dummy semiconductor layers 24A are formed of or contain silicon germanium, the semiconductor layers 26 are formed of silicon, and the dummy semiconductor layer 24B may be formed of germanium or silicon germanium, which has a higher atomic percentage of germanium than the semiconductor layer 24A.

[0022] In Fig. 3. The multilayer stack 22 and the substrate 20 are structured to form semiconductor strips 28. The process in question is in process sequence 200, which is in Fig. Figure 17 is shown as process 204. Each of the semiconductor strips 28 has a semiconductor strip 20' (the sections of the original substrate 20) and a multilayer stack 22', which is the remaining section of the multilayer stack 22. The remaining sections 22' of the multilayer stack 22 are hereby referred to as nanostructures, which are identified by the appropriate reference numeral followed by the symbol ",'". Accordingly, the multilayer stack 22' has dummy nanostructures 24'A, dummy nanostructures 24'B, lower semiconductor nanostructures 26'L, middle semiconductor nanostructures 26'M, and upper semiconductor nanostructures 26'U. Etching can be performed by any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. Etching can be anisotropic.The dummy nanostructures 24'A and the dummy nanostructures 24'B can also be referred to collectively as dummy nanostructures 24'. The lower semiconductor nanostructures 26'L and the upper semiconductor nanostructures 26'U can also be referred to collectively as the semiconductor nanostructures 26'.

[0023] The lower semiconductor nanostructures 26L serve as channel regions for the lower nanostructure FETs of the CFETs. The upper semiconductor nanostructures 26'U also serve as channel regions for the upper nanostructure FETs of the CFETs. The middle semiconductor nanostructures 26'M are those located directly above / below (for example, in contact with) the dummy nanostructures 24'B. The middle semiconductor nanostructures 26'M can be used for insulation and may or may not serve as channel regions for the CFETs. The dummy nanostructures 24'B are subsequently replaced by insulation structures. The insulation structures and the middle semiconductor nanostructures 26'M can define the boundaries of the lower and upper nanostructure FETs.

[0024] In Fig. 4 Insulation zones 32 are formed above the substrate 20 and between adjacent semiconductor strips 28. The process in question is in process sequence 200, which is in Fig. Figure 17 is shown as process 205. The insulation regions 32 may have a dielectric lining and a dielectric material over the dielectric lining. The insulation regions 32 are then recessed. Some upper sections of the semiconductor strips 28 (which have the multilayer stacks 22') extend beyond the remaining insulation regions 32 to form projecting fins 34.

[0025] Then a dielectric dummy layer 36 is formed on the protruding fins 34. The process in question is in process sequence 200, which is in Fig. Figure 17 is shown as process 206. The dielectric dummy layer 36 can, for example, be formed from or contain silicon oxide, silicon nitride, a combination thereof, or the like, and can be applied or thermally grown in accordance with suitable techniques.

[0026] A dummy gate layer 38 is formed over the dielectric dummy layer 36. The process in question is in process sequence 200, which is in Fig. Figure 17 is shown as process 208. The dummy gate layer 38 can be applied, for example, by physical vapor deposition (PVD), CVD, or other techniques and then planarized, for example, by a CMP process. The material of the dummy gate layer 38 can be conductive or non-conductive and can be selected from a group including amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), or the like. A mask layer 40 is formed over the planarized dummy gate layer 38 and can contain, for example, silicon nitride, silicon oxynitride, or the like.

[0027] Next, the mask layer 40 is structured by photolithography and etching processes to form a mask, which is then used to etch and structure the dummy gate layer 38 and, if necessary, the dielectric dummy layer 36. A resulting structure is shown in Fig. 5 shown. The remaining sections of the mask layer 40, the dummy gate layer 38 and the dielectric dummy layer 36 form the dummy gate stack 42.

[0028] In Fig. 5. Spacer elements 44 are formed above the multilayer stacks 22' and on exposed sidewalls of the dummy gate stacks 42. The gate spacer elements 44 can be formed by conformal formation of one or more dielectric layers and subsequent anisotropic etching of the dielectric layers. The usable dielectric materials can include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or the like, which can be formed by a deposition process such as CVD, ALD, or the like.

[0029] Then source / drain depressions 46 are formed in the semiconductor strips 28. The process in question is in process sequence 200, which is in Fig. Figure 17 is shown as process 210. The source / drain depressions 46 are formed by etching and can extend through the multilayer stacks 22' and into the semiconductor strips 20'. The lower surfaces of the source / drain depressions 46 can be arranged above, below, or on the same plane as the upper surfaces of the insulation regions 32 ( Fig. 4) In the etching processes, the spacer elements 44 and the dummy gate stacks 42 mask specific sections of the semiconductor strips 28. The etching can comprise a single or multiple etching processes. Timed etching processes can be used to stop the etching of the source / drain pits 46 once the source / drain pits 46 have reached a desired depth.

[0030] Then the dummy nanostructures 24'A are laterally recessed, and a dielectric material is filled into the corresponding recesses to form internal spacer elements 54, which are dielectric spacer elements. The resulting structure is in Fig. 6 shown. Dielectric insulating layers 56 are also formed to replace the dummy nanostructures 24'B.

[0031] Next, lower epitaxial source / drain regions 62L are formed in the lower sections of the source / drain depressions 46 ( Fig. 5) The process in question is in process flow 200, which is in Fig. Figure 17 is shown as process 212. The lower epitaxial source / drain regions 62L are in contact with the lower semiconductor nanostructures 26L, but not with the upper semiconductor nanostructures 26'U. Internal spacers 54 electrically isolate the lower epitaxial source / drain regions 62L from the dummy nanostructures 24'A, which are replaced by substitute gates in subsequent processes.

[0032] The lower epitaxial source / drain regions 62L are grown epitaxially and exhibit a conductivity type suitable for the device type (p-type or n-type) of the lower nanostructure FETs. If the lower epitaxial source / drain regions 62L are n-type, the corresponding material can contain silicon or carbon-doped silicon doped with an n-type dopant, such as phosphorus, arsenic, or the like. If the lower epitaxial source / drain regions 62L are p-type, the corresponding material can contain silicon or silicon-germanium doped with a p-type dopant, such as boron, indium, or the like. The lower epitaxial source / drain regions 62L can be doped in situ, implanted with the appropriate p- or n-type dopants, or not.

[0033] In accordance with some embodiments, the temperature for forming the lower epitaxial source / drain regions 62L can be a relatively high temperature, which may be in a range of approximately 550°C to approximately 800°C.

[0034] A first contact etch stop layer (CESL) 66 and a first ILD 68 are formed. The first CESL 66 can be formed from a dielectric material exhibiting high etch selectivity against the etching of the first ILD 68, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, which can be formed by any suitable deposition process, such as CVD, ALD, or the like. The first ILD 68 can be formed from a dielectric material that can be applied by any suitable process, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The applicable dielectric material of the first ILD 68 can include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), silicon oxide, or the like.

[0035] The formation processes can include the deposition of a conformal CESL layer, the deposition of material for the ILD 68 followed by a planarization process and a subsequent back-etching process. In some embodiments, the first ILD 68 is etched first, leaving the first CESL 66 unetched. An anisotropic etching process is then performed to remove the portions of the first CESL 66 that are higher than the recessed first ILD 68. After recession, the sidewalls of the upper semiconductor nanostructures 26'U are exposed.

[0036] Next, upper epitaxial source / drain regions 62U are formed in the upper sections of the source / drain depressions 46. The process in question is in process flow 200, which is in Fig. Figure 17 is shown as process 214. The materials of the upper epitaxial source / drain regions 62U can be selected from the same group of materials as those for forming the lower source / drain regions 62L, depending on the desired conductivity type of the upper epitaxial source / drain regions 62U.

[0037] The conductivity type of the upper epitaxial source / drain regions 62U can be opposite to that of the lower epitaxial source / drain regions 62L. In other words, the upper epitaxial source / drain regions 62U can be doped in the opposite way to the lower epitaxial source / drain regions 62L. The upper epitaxial source / drain regions 62U can be doped in situ, or they can be implanted with the appropriate n- or p-dopers, or not.

[0038] Next, a second CESL 70 and a second ILD 72 are formed. The materials and formation procedures can be the same as those for the first CESL 66 and the first ILD 68, respectively, and are not discussed in detail here. The formation process can include depositing the layers for the CESL 70 and the ILD 72 and performing a planarization process to remove the excess portion of the layers in question. After the planarization process, the top surfaces of the second ILD 72, the gate spacers 44, and the dummy gate stack 42 are coplanar (within process deviations). The planarization process can remove the masks 40 or leave the hard masks 40 in place.

[0039] The dummy gate stacks 42 are then removed in one or more etching processes in such a way that depressions ( Fig. 7A, filled by gate stacks 90 and dielectric hard masks 92). Each of the wells exposes and / or overlays sections of the multilayer stacks 22'. The process in question is in process sequence 200, which is in Fig. 17 is shown as process 216.

[0040] The remaining sections of the dummy nanostructures 24'A ( Fig. 6) are then removed by etching, so that the depressions extend between the semiconductor nanostructures 26'. The process in question is in process sequence 200, which is in Fig. Figure 17, also shown as process 216, illustrates this process. In the etching process, the dummy nanostructures 24'A are etched at a higher rate than the semiconductor nanostructures 26', the dielectric insulating layers 56, and the internal spacer elements 54. The etching can be isotropic. For example, if the dummy nanostructures 24'A are formed from silicon germanium and the semiconductor nanostructures 26' are formed from silicon, the etching process can involve wet etching using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like.

[0041] Replacement gate stacks 90 (which include gate stacks 90L and 90U) are formed in the corresponding recesses, as shown in Fig. 7A is shown. The process in question is in process flow 200, which is in Fig. Figure 17 is shown as process 218. The resulting gate stacks 90L have gate dielectrics 78 and gate electrodes 80L. The resulting gate stacks 90U have gate dielectrics 78 and gate electrodes 80U.

[0042] The gate dielectrics 78 are formed on the exposed surfaces of the exposed elements, which have the semiconductor nanostructures 26' and the spacer elements 44. The gate dielectrics 78 envelop all (for example, four) sides of the semiconductor nanostructures 26'. Each of the gate dielectrics 78 can have an interface layer which may contain an oxide, such as a silicon oxide. The interface layer can be formed by a thermal oxidation process and / or a deposition process. The gate dielectrics 78 can also have high k-value dielectric layers, which have a dielectric constant (a high k-value) of more than, for example, approximately 7.0. High k-value dielectric layers can be formed from or contain a metal oxide or silicate of a metal selected from the group comprising hafnium, zirconium, barium, titanium, lead, and combinations thereof.

[0043] Gate electrodes 80L and 80U are also formed. During the formation process, conductive layers are first formed on the high k-value dielectric layer, and the remaining sections of the cavities are filled. Each of the 80L and 80U gates can contain a metallic material, such as TiN, TaN, TiAl, TiAlC, cobalt, ruthenium, aluminum, tungsten, combinations thereof, and / or multiple layers thereof. The 80L and 80U gate electrodes can provide work functions suitable for the resulting 10L lower FETs (lower transistors). Fig. 16) and upper FETs (upper transistors) 10U ( Fig. 16) are suitable. The gate electrodes 80L and 80U can be common gates formed in the same formation process, or they can be electrically separated and formed in separate formation processes. Dielectric hard masks 92 are formed over the gate stacks 90U.

[0044] Fig. 7B shows a cross-sectional view of the in Fig. The structure shown in Figure 4 represents the cross-section. The cross-section shown can be cross-section 7B - 7B, as in Figure 4. Fig. 7A shown. As in Fig. As shown in Figure 7B, STI regions 32 are formed above the substrate 20. The semiconductor strips 20' are formed between the STI regions 32. Fin spacer elements 45 can be formed on the sidewalls of the upper sections of the semiconductor strips 20'. The lower source / drain regions 62L, the first CESL 66, the first ILD 68, the upper source / drain regions 62U, the second CESL 70, and the second ILD 72 are shown.

[0045] A dielectric isolation zone 110 is formed. The process in question is in process sequence 200, which is in Fig. Figure 17 is shown as process 220. The dielectric isolation region 110 penetrates the second ILD 72, the second CESL 70, the first ILD 68, and the first CESL 66. The formation process can involve performing one or more etching processes to form a trench and filling the trench with a dielectric material. The dielectric isolation region 110 can be used as a metal-cut gate region, which, for example, is used to cut long gate stacks into shorter sections, each of which is used as a gate stack for one of the CFETs.

[0046] In accordance with some embodiments, the material of the dielectric insulation area 110 may contain silicon nitride, a metal oxide of a metal such as Hf, Ti, Al, W, Nb, Re or the like, a metal nitride of a metal such as Hf, Ti, Al, W, Nb, Re or the like, or combinations thereof.

[0047] In some embodiments, no conductive element is formed within the dielectric isolation region 110. In alternative embodiments, the dielectric isolation region 110 is configured as a dielectric lining, and a conductive element 112, which is a conductive terminal, is formed within and surrounded by the dielectric isolation region 110. The conductive element 112 can be used to electrically connect the elements formed on the front side of the CFET to the back side of the CFET. The conductive element 112 is shown with a dashed line to indicate that it may or may not be formed.

[0048] Referring to Fig. In step 8, a contact etch stop layer 114 and a dielectric layer 116 are formed. The etch stop layer 114 can consist of AlN, AlO, SiOC, or the like, or multiple layers thereof. The dielectric layer 116 can contain silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or the like.

[0049] In a subsequent process, dielectric linings 118, silicide layers 120, and contact terminals 122 are formed. In accordance with some embodiments, the formation process includes etching the dielectric layer 116, the etch stop layer 114, the second ILD 72, the second CESL 70, the first ILD 68, and the first CESL 66 to form contact openings, thus exposing the upper source / drain regions 62U.

[0050] Then dielectric linings 118 are formed in the contact openings. The process in question is in process sequence 200, which is in Fig. Figure 17 is shown as process 222. The formation process can include the deposition of a conformal dielectric layer by a conformal deposition process and the execution of an anisotropic etching process to remove the horizontal sections of the conformal dielectric layer. The vertical sections of the conformal dielectric layer remain as the dielectric liners 118. The material of the dielectric liners 118 can contain silicon nitride, silicon oxynitride, silicon carbonitride, or the like.

[0051] Fig. Figure 8 further describes the formation of silicide layers 120 on the upper surfaces of the upper source / drain areas 62U. The process in question is in process flow 200, which is in Fig. Figure 17 is shown as process 224. The formation process can involve the application of a metal layer (not shown), for example, using a conformal deposition process such as a physical vapor deposition (PVD) process. The applied metal layer can contain titanium, cobalt, or the like. Subsequently, an annealing process is carried out to cause the metal layer to react with the silicon in the upper source / drain regions 62U to form silicide layers 120. The remaining metal layer can then be removed, for example, by performing an etching process.

[0052] Next, (front-side) contact connections 122 are formed. The relevant process is in process flow 200, which is in Fig. Figure 17 is shown as process 226. In accordance with some embodiments, the contact terminals 122 contain a metal, such as tungsten, molybdenum, ruthenium, iridium, or the like, or alloys thereof. In accordance with some embodiments, the contact terminals 122 have a single-layer structure, wherein the entire contact terminals 122 are formed from one of the aforementioned homogeneous materials.

[0053] In accordance with alternative embodiments, the formation of the contact terminals 122 may include the formation of a barrier layer, which may contain titanium, titanium nitride, tantalum, tantalum nitride, or the like. Next, a metallic material is deposited over and in contact with the barrier layer. The metallic material may contain tungsten, cobalt, copper, nickel, molybdenum, ruthenium, iridium, or the like, or a combination thereof. After the metallic material has been deposited, a planarization process, such as a CMP process or a mechanical grinding process, is performed to remove excess portions of the deposited material, leaving the contact terminals 122.

[0054] Referring to Fig. 9. Wafer 2 is now turned over. Next, substrate 20 is thinned, for example by a CMP process or a mechanical grinding process. The relevant process is in process sequence 200, which is in Fig. The structure shown in 17 is represented as process 228. The resulting structure is in Fig. Figure 10 shows that, in accordance with some embodiments, dilution can lead to the removal of the STI regions 32 and the base substrate 20. In accordance with alternative embodiments, the STI regions 32 can remain, as shown in Fig. 10 shown. As a result of the thinning process, the dielectric insulation area 110 (and the contact plug 112, if one has been formed) is also exposed.

[0055] In a subsequent process, as in Fig. As shown in Figure 11, a dielectric layer is applied. The process in question is described in process sequence 200, which is in Fig. Figure 17 is shown as process 230. The dielectric layer 126 can contain silicon oxide or other suitable dielectric materials.

[0056] As in Fig. As shown in Figure 12, (rear) contact openings 128 are formed by etching processes. The relevant process is in process sequence 200, which is in Fig. Figure 17 is shown as process 232. The etching is stopped at the rear surfaces of the lower source / drain regions 62L, thus exposing the lower source / drain regions 62L opposite the contact openings 128. The dielectric insulation region 110 (and the contact plug 112, if one has been formed) are also exposed.

[0057] In a subsequent process, dielectric linings 130 are formed. This formation process can involve depositing a conformal dielectric layer by a conformal deposition process and performing an anisotropic etching process to remove the horizontal sections of the conformal dielectric layer. The vertical sections of the conformal dielectric layer remain as the dielectric linings 130. The material of the dielectric linings 130 can include silicon nitride, silicon oxynitride, silicon carbonitride, or the like.

[0058] Fig. Figure 13 represents a first epitaxy process for the targeted formation of epitaxial semiconductor layers 132. The epitaxy process begins from the lower source / drain regions 62L, but not from exposed dielectric materials. The process in question is described in process sequence 200, which is in Fig. Figure 17 is shown as process 234. The epitaxial semiconductor layers 132 have the same conductivity type as the lower source / drain regions 62L. For example, if the lower source / drain regions 62L are p-type regions, then the epitaxial semiconductor layers 132 are also of type p and may contain boron, indium, or the like. If, on the other hand, the lower source / drain regions 62L are n-type regions, then the epitaxial semiconductor layers 132 are also of type p and may contain phosphorus, antimony, arsenic, and / or the like.

[0059] The concentration of the p-type dopant (such as boron) or the n-type dopant (such as phosphorus) in the epitaxial semiconductor layers 132 can be higher than in the lower source / drain regions 62L to achieve lower contact resistance and lower layer resistance. For example, the boron concentration in the epitaxial semiconductor layers 132 can be in the range of approximately 1 × 10²⁰ / cm². 3 and approximately 4E21 / cm 3 lie. In the following discussion, the epitaxial semiconductor layers 132 are discussed as p-regions by way of example, although they can also be n-regions if the lower source / drain regions 62L are n-regions.

[0060] In accordance with some embodiments, the epitaxial semiconductor layers 132 are formed by a low-temperature epitaxy process. The wafer temperature for forming the epitaxial semiconductor layers 132 is also lower than the wafer temperature for forming the lower source / drain regions 62L. For example, the wafer temperature for forming the epitaxial semiconductor layers 132 can be lower than approximately 400°C and can be in the range of approximately 300°C to approximately 400°C. Due to the low temperature, the surfaces of the epitaxial semiconductor layers 132 do not exhibit prominent facets. As in Fig. As shown in Figure 13, the epitaxial semiconductor layers 132 can, for example, have rounded surfaces.

[0061] In accordance with some embodiments, the epitaxial semiconductor layers 132 are higher than the exposed upper ends of the sidewall sections of the first CESL 66. Furthermore, the epitaxial semiconductor layers 132 can extend laterally beyond the exposed surfaces of the lower source / drain regions 62L. Dashed lines 131, for example, schematically show the surfaces of the respective epitaxial semiconductor layers 132 that may or may not be in contact with the upper surfaces of the sidewall sections of the first CESL 66 and with the upper exposed surfaces of the first ILD 68.

[0062] In accordance with some embodiments, the lower source / drain regions 62L contain SiGeB, and the germanium atom percentage can range from approximately 50 percent to approximately 75 percent. The epitaxial semiconductor layers 132 can also contain SiGeB, and the germanium atom percentage can also be in the same range as that of the lower source / drain regions 62L, for example, from approximately 50 percent to approximately 75 percent. The germanium atom percentage of the epitaxial semiconductor layers 132 can be equal to, higher than, or lower than the atom percentage of the lower source / drain regions 62L.

[0063] Fig. 14 represents the formation of epitaxial semiconductor layers 134, which are formed specifically from the epitaxial semiconductor layers 132, but not from exposed dielectric materials. The process in question is described in process sequence 200, which is in Fig. Figure 17 is shown as process 236. The epitaxial semiconductor layers 134 also exhibit the same conductivity type as the lower source / drain regions 62L. The concentration of the p-type dopant (such as boron) or the n-type dopant (such as phosphorus) can be in the range of approximately 8 x 10⁻²⁰ / cm². 3 and approximately 4E21 / cm 3 lie, and can be equal to, higher than or lower than the concentration of the dopant in the epitaxial semiconductor layers 132.

[0064] In accordance with some embodiments, the epitaxial semiconductor layers 134 are formed by a low-temperature epitaxy process, and the temperature can be the same as, higher than, or lower than the temperature used to form the epitaxial semiconductor layers 132. For example, the wafer temperature used to form the epitaxial semiconductor layers 134 can be lower than approximately 400°C and can be in the range of approximately 300°C to approximately 400°C. The epitaxial semiconductor layers 134 also have rounded surfaces.

[0065] In accordance with some embodiments, the epitaxial semiconductor layers 134 may extend laterally beyond the exposed surfaces of the lower source / drain regions 62L. The epitaxial semiconductor layers 134 may or may not be in contact with the upper surfaces of the sidewall sections of the first CESL 66, and may or may not be in contact with the exposed upper surface of the first ILD 68.

[0066] In accordance with some embodiments, the epitaxial semiconductor layers 134 have a higher germanium atom percentage than the epitaxial semiconductor layers 132 and may contain SiGeB or GeB (without silicon). The germanium atom percentage can range from approximately 85 percent to approximately 100 percent.

[0067] The epitaxial semiconductor layers 134 are applied to the back side of the substrate 20 without an additional wet etching process being performed on the back side of the substrate. Accordingly, the epitaxial semiconductor layers 134 can contain GeB to reduce the contact resistance, whereby the GeB is not adversely oxidized by the residues from the wet etching process.

[0068] Next, as in Fig. As shown in Figure 15, silicide layers 136 are formed. The process in question is in process sequence 200, which is in Fig. Figure 17 is shown as process 238. The formation process can include the deposition of a metal layer (not shown), for example, using a conformal deposition process such as a PVD process. The deposited metal layer can contain titanium, cobalt, or the like. Subsequently, an annealing process is carried out to cause the metal layer to react with the silicon in the upper epitaxial semiconductor layers 134 to form silicide layers 136. The remaining metal layer can then be removed, for example, by performing an etching process.

[0069] The silicide process can consume the upper portions of the epitaxial semiconductor layers 134, while leaving the lower portions of the epitaxial semiconductor layers 134 behind. The lower source / drain regions 62L, the epitaxial semiconductor layers 132, and the epitaxial semiconductor layers 134 together form lower composite source / drain regions, which are referred to below as lower source / drain regions 62L'.

[0070] It is desirable that the silicide process does not completely consume the epitaxial semiconductor layers 134, and that the remaining sections of the epitaxial semiconductor layers 134 are left behind to separate the silicide layers 136 from the epitaxial semiconductor layers 132. If, on the other hand, the silicide layers 136 are in direct contact with the epitaxial semiconductor layers 132, the contact resistance between the subsequently formed contact terminals 138 ( Fig. 16) and the lower source / drain regions 62L' increase, so that it would be higher than if certain sections of the epitaxial semiconductor layers 134 were left behind.

[0071] The thickness of the remaining sections of the epitaxial semiconductor layers 134 is controlled such that it is not too large and is less than approximately 2 nm. If, on the other hand, the epitaxial semiconductor layers 134 are too thick, the resistance of the resulting lower composite source / drain regions 62L' would also be high.

[0072] Since the silicide layers 136 are formed by silicifying the epitaxial semiconductor layers 134, the ratio of the atomic percent APSi / APGe in the silicide layers 136 can be the same as that in the epitaxial semiconductor layers 134, where the values ​​APSi indicate the atomic percent of silicon and the values ​​APGe indicate the atomic percent of germanium.

[0073] Referring to Fig. 16 Rear contact connections 138 are formed to fill the contact openings 128 and electrically connect them to the silicide layers 136. The process in question is in process sequence 200, which is in Fig. Figure 17 is shown as process 240.

[0074] In accordance with some embodiments, the formation of the rear contact terminals 138 may include the formation of a barrier layer, which may contain titanium nitride, tantalum nitride, or the like. Next, a metallic material is deposited over and in contact with the barrier layer. The metallic material may include tungsten, cobalt, or the like. Then, a planarization process, such as a CMP process or a mechanical grinding process, is performed to remove excess portions of the barrier layer and the metallic material, leaving the rear contact terminals 138. In accordance with alternative embodiments, the contact terminals 138 do not have a barrier and may contain tungsten, ruthenium, or the like.

[0075] The embodiments of the present disclosure exhibit several advantageous features. In accordance with some embodiments, the regrowth of epitaxial semiconductor layers by low-temperature epitaxy from the back side of the lower source / drain regions reduces the resistance of the lower source / drain regions and the corresponding contact resistance. The low-temperature regrowth also improves the activation rate of the newly grown epitaxial semiconductor layers. Furthermore, to reduce the strength of the Schottky barrier and achieve a lower contact resistance, a germanium-boron layer with a high germanium atom percentage (which may be free of or substantially free of silicon) is introduced at the silicide interface, resulting in a low work function and strong Fermi-level pinning.

[0076] The Fig. Figures 18 to 37 show cross-sectional views of intermediate stages in the formation of CFETs (which in Fig. (1 schematically depicted) in accordance with alternative embodiments. The corresponding processes are also shown in process flow 300, which is in Fig. Figure 38 is shown schematically. In accordance with these embodiments, lower dummy source / drain regions and upper dummy source / drain regions are formed and then replaced by (epitaxial) substitute source / drain regions.

[0077] The structures and initial processes in accordance with these embodiments can be essentially the same as those described in the Fig. 1 and Fig. 5 shown and discussed, and are also in process flow 200, which is in Fig. Figure 17 shows processes 202, 204, 205, 206, 208, and 210. These processes are part of process flow 300, which is shown in Fig. 38 is also shown as process 302. As in Fig. As shown in Figure 5, the structured multilayer stacks 22' have been formed. Dummy gate stacks 42 and spacer elements 44 have also been formed above the multilayer stacks 22'. Dummy nanostructures 24'B remain within the multilayer stacks 22', with the sidewalls of the dummy nanostructures 24'B exposed relative to the source / drain depressions 46.

[0078] Then the dummy nanostructures 24'A are laterally recessed, and a dielectric material is filled into the corresponding recesses to form internal spacer elements 54, which are dielectric spacers. The resulting structure is in Fig. 18 shown. Dielectric insulating layers 56 are also formed to replace the dummy nanostructures 24'B.

[0079] In a subsequent process, as in Fig. As shown in Figure 18, (lower) dummy source / drain areas 62L-D are formed. The processes in question are in process flow 300, which is in Fig. Figure 38, also depicted as process 304. In accordance with some embodiments, the material of the dummy source / drain regions 62L-D can contain an intrinsic semiconductor material, such as SiGe, Si, SiC, or the like, without any p-type or n-type dopants. If Si is used, other elements can be added such that, upon subsequent removal of the dummy source / drain regions 62U-D, the selectivity between the dummy source / drain regions 62L-D and the semiconductor nanostructures 26'U is high.

[0080] In accordance with alternative embodiments, the semiconductor material can be a p-type semiconductor containing a p-type dopant, such as boron. In accordance with further alternative embodiments, the semiconductor material can be an n-type semiconductor containing an n-type dopant, such as phosphorus.

[0081] In accordance with some embodiments, the dummy source / drain regions 62L-D have an epitaxial material with a crystalline structure. The wafer temperature for forming the dummy source / drain regions 62L-D can be relatively high, for example, in a range of approximately 550°C to approximately 800°C. Alternatively, the wafer temperature for forming the dummy source / drain regions 62L-D can be relatively low, for example, in a range of approximately 300°C to approximately 550°C.

[0082] In accordance with alternative embodiments, the dummy source / drain regions 62L-D have a polycrystalline or amorphous structure. The wafer temperature for forming the dummy source / drain regions 62L-D can be low, for example, lower than approximately 300°C. The upper surfaces of the dummy source / drain regions 62L-D are controlled such that they are higher than the uppermost of the lower semiconductor nanostructures 26'L.

[0083] Referring to Fig. 19, a first contact etch stop layer (CESL) 66 and a first ILD 68 are formed. The processes in question are in process flow 300, which is in Fig. Figure 38, also shown as process 306. The first CESL 66 can be formed from a dielectric material exhibiting high etch selectivity against the etching of the first ILD 68, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, which can be formed by any suitable deposition process, such as CVD, ALD, or the like. The first ILD 68 can be formed from a dielectric material that can be deposited by any suitable process, such as CVD, PECVD, or FCVD. The usable dielectric material of the first ILD 68 can include PSG, BSG, BPSG, USG, silicon oxide, or the like.

[0084] The formation processes can include the deposition of a conformal CESL layer, the deposition of material for the ILD 68 followed by a planarization process and a subsequent back-etching process. In some embodiments, the first ILD 68 is etched first, leaving the first CESL 66 unetched. An anisotropic etching process is then performed to remove the portions of the first CESL 66 that are higher than the recessed first ILD 68. After recession, the sidewalls of the upper semiconductor nanostructures 26'U are exposed.

[0085] In a subsequent process, as in Fig. As shown in Figure 20, dummy source / drain areas 62U-D are formed. The processes in question are in process flow 300, which is shown in Fig. Figure 38, also depicted as process 308. In accordance with some embodiments, the material of the dummy source / drain regions 62U-D can contain an intrinsic semiconductor material, such as SiGe, Si, SiC, or the like, provided that it is not doped with any p-type or n-type dopant. If Si is used, other elements can be added to increase its selectivity towards the semiconductor nanostructures 26'U upon subsequent removal of the dummy source / drain regions 62U-D.

[0086] In accordance with alternative embodiments, the semiconductor material of the dummy source / drain regions 62U-D can be a p-type semiconductor material containing a p-type dopant, such as boron. In accordance with further alternative embodiments, the semiconductor material can be an n-type semiconductor material containing an n-type dopant, such as phosphorus.

[0087] The material of the dummy source / drain regions 62U-D can be the same as or different from that of the dummy source / drain regions 62L-D. In accordance with some embodiments, the dummy source / drain regions 62U-D feature an epitaxial semiconductor material with a crystalline structure. The wafer temperature for forming the dummy source / drain regions 62U-D can be relatively high, for example, in a range of approximately 550°C to approximately 800°C. Alternatively, the wafer temperature for forming the dummy source / drain regions 62U-D can be relatively low, for example, in a range of approximately 300°C to approximately 550°C.

[0088] In accordance with alternative embodiments, the dummy source / drain regions 62U-D have a polycrystalline or amorphous structure. The wafer temperature for forming the dummy source / drain regions 62U-D can be low, for example, less than approximately 300°C. The upper surfaces of the dummy source / drain regions 62U-D are controlled such that they are higher than the uppermost of the upper semiconductor nanostructures 26'U.

[0089] If the dummy source / drain regions are 62U-D doped, the conductivity type (and dopant) of the dummy source / drain regions 62U-D may be opposite to, or the same as, the conductivity type (and dopant) of the lower epitaxial source / drain regions 62L-D. Alternatively, either the dummy source / drain regions 62U-D or the dummy source / drain regions 62L-D may be doped, while the others are intrinsic.

[0090] Referring to Fig. 21. A second CESL 70 and a second ILD 72 are formed. The process in question is in process flow 300, which is in Fig. Figure 38 is shown as process 310. The materials and formation procedures can be the same as those for the first CESL 66 and the first ILD 68, respectively, and are not discussed in detail here. The formation process can include depositing the layers for CESL 70 and ILD 72 and performing a planarization process to remove the excess portion of the layers in question. After the planarization process, the top surfaces of the second ILD 72, the gate spacers 44, and the dummy gate stack 42 are coplanar (within process deviations). The planarization process can remove the masks 40 or leave the hard masks 40 in place.

[0091] Then replacement gate stack 90 are formed, with the resulting structure in Fig. Figure 22 shows the relevant processes. These processes are included in process flow 300, which is shown in Fig. Figure 38 is also shown as process 312. To form the replacement dummy gates 90, the dummy gate stacks 42 are first removed in one or more etching processes such that depressions ( Fig. 22, filled by gate stack 90). Each of the depressions exposes and / or overlays sections of the multilayer stack 22'.

[0092] The remaining sections of the dummy nanostructures 24'A ( Fig. 21) are then removed by etching, so that the depressions extend between the semiconductor nanostructures 26'. In the etching process, the dummy nanostructures 24'A are etched at a higher rate than the semiconductor nanostructures 26', the dielectric insulating layers 56, and the internal spacer elements 54. The etching can be isotropic. For example, if the dummy nanostructures 24'A are formed from silicon germanium and the semiconductor nanostructures 26' are formed from silicon, the etching process can involve a wet etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like.

[0093] The formation of the replacement gate stacks 90 involves the formation of gate dielectrics 78, which are formed in the recesses and on the exposed semiconductor nanostructures 26'. The gate dielectrics 78 are formed on the exposed surfaces of the exposed elements, which include the semiconductor nanostructures 26' and the spacer elements 44. The gate dielectrics 78 envelop all (for example, four) sides of the semiconductor nanostructures 26'.

[0094] Each of the gate dielectrics 78 can have an interface layer which may contain an oxide, such as silicon oxide. The interface layer can be formed by a thermal oxidation process and / or a deposition process. The gate dielectrics 78 can also have high k-value dielectric layers, which have a dielectric constant (a high k-value) greater than, for example, approximately 7.0. High k-value dielectric layers can be formed from or contain a metal oxide or silicate of a metal selected from the group comprising hafnium, zirconium, barium, titanium, lead, and combinations thereof.

[0095] Gate electrodes 80L and 80U are also formed. During the formation process, conductive layers are first formed on the high k-value dielectric layer, and the remaining sections of the cavities are filled. Each of the 80L and 80U gates can contain a metallic material, such as TiN, TaN, TiAl, TiAlC, cobalt, ruthenium, aluminum, tungsten, combinations thereof, and / or multiple layers thereof. The 80L and 80U gate electrodes can provide work functions suitable for the resulting 10L lower FETs (lower transistors). Fig. 37) and upper FETs (upper transistors) 10U ( Fig. 37) are suitable. The gate electrodes 80L and 80U can be common gates formed in the same formation process, or they can be electrically separated and formed in separate formation processes.

[0096] The resulting gate stacks 90L have gate dielectrics 78 and gate electrodes 80L. The resulting gate stacks 90U have gate dielectrics 78 and gate electrodes 80U. Dielectric hard masks 92 are formed over the gate stacks 90U.

[0097] Further referring to Fig. In step 22, a contact etch stop layer 114 and a dielectric layer 116 are formed. The process in question is in process sequence 300, which is in Fig. Figure 38 is shown as process 314. The etch stop layer 114 can comprise AlN, AlO, SiOC, or the like, or multiple layers thereof. The dielectric layer 116 can contain silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or the like.

[0098] Next, as in Fig. As shown in Figure 23, structuring processes are carried out to etch the dielectric layer 116, the etch stop layer 114, and the second ILD 72 such that openings 141 are formed. The process in question is shown in process sequence 300, which is in Fig. Figure 38 is shown as process 316. In accordance with some embodiments, the lower sections of the second CESL 70 are etched. The etching can be anisotropic, so that the sidewall sections of the second CESL 70 remain as a dielectric insulating layer.

[0099] In accordance with alternative embodiments, the vertical sections of the second CESL 70 are also etched, instead of using these vertical sections of the second CESL 70 as the dielectric insulating layer. A conformal deposition process is then carried out, followed by an anisotropic etching process to form the dielectric insulating layer.

[0100] After etching the sidewall sections of the second CESL 70, the dummy source / drain areas 62U-D are also etched. Because the etching process can be anisotropic, certain sections of the dummy source / drain areas 62U-D may (or may not) remain directly beneath the vertical sections of the second CESL 70. After etching the dummy source / drain areas 62U-D, the first ILD 68 is exposed, and the etching process stops at the top surface of the first ILD 68.

[0101] Then an etching process is performed to remove any remaining sections (if any) of the dummy source / drain areas 62U-D. This process is part of process flow 300, which is in Fig. Figure 38 is shown as process 318. The resulting structure is in Fig. Figure 24 shows that the etching is isotropic, exposing the sidewalls of the semiconductor nanostructures 26'U. Due to the selection of materials for the dummy source / drain regions 62U-D, which differ from the materials of the semiconductor nanostructures 26'U, the semiconductor nanostructures 26'U remain essentially unetched.

[0102] Fig. Figure 25 represents the epitaxial regrowth process for forming the upper epitaxial source / drain regions 62U. The process in question is in process flow 300, which is in Fig. Figure 38 is shown as process 320. The upper epitaxial source / drain regions 62U are in contact with the upper semiconductor nanostructures 26'U, but not with the lower semiconductor nanostructures 26'L. In accordance with some embodiments, the upper epitaxial source / drain regions 62U, which are grown from adjacent upper semiconductor nanostructures 26'U, are spaced apart from one another. In the following discussion, the upper epitaxial source / drain regions 62U, which are grown from adjacent upper semiconductor nanostructures 26'U, are also referred to as the sections of an upper semiconductor nanostructure 26U.

[0103] The upper epitaxial source / drain regions 62U are epitaxially grown and exhibit a conductivity type suitable for the device type (p-type or n-type) of the upper nanostructure FETs. If the upper epitaxial source / drain regions 62U are n-type, the corresponding material can contain silicon or carbon-doped silicon doped with an n-type dopant, such as phosphorus, arsenic, or the like. If the upper epitaxial source / drain regions 62U are p-type, the corresponding material can contain silicon or silicon-germanium doped with a p-type dopant, such as boron, indium, or the like.

[0104] The temperature for the formation of the upper epitaxial source / drain regions 62U is controlled such that it is neither too high nor too low. In accordance with some embodiments, the temperature for the formation of the upper epitaxial source / drain regions 62U can be relatively low, less than approximately 400°C, and may range from approximately 300°C to approximately 400°C. If the temperature is too high, for example, more than approximately 400°C, this can negatively affect the reliability of the gate stack. If the temperature is too low, for example, less than approximately 300°C, the upper epitaxial source / drain regions 62U may exhibit an amorphous structure.

[0105] Referring to Fig. 26 Silicide layers 142 are formed. The process in question is in process sequence 300, which is in Fig. Figure 38 is shown as process 322. The formation process can include the application of a metal layer (not shown), for example, using a conformal deposition process such as a PVD process. The applied metal layer can contain titanium, cobalt, or the like. Subsequently, an annealing process is carried out to cause the metal layer to react with the silicon in the upper source / drain regions 62U, thus forming silicide layers 142. The remaining metal layer can then be removed, for example, by performing an etching process.

[0106] The silicidal process consumes the outer sections of the upper epitaxial source / drain regions 62U, leaving behind the inner sections. The sections of the silicidal layers 142, which are grown from adjacent (upper and corresponding lower) upper epitaxial source / drain regions 62U, can be arranged individually or interconnected, depending on the sizes of the upper epitaxial source / drain regions 62U and the silicidal layers 142.

[0107] Referring to Fig. 27. Front-facing contact connections 144 (which have contact connections 144A and 144B) are formed to fill the openings 141 and electrically connect them to the silicide layers 142. The process in question is in process sequence 300, which is in Fig. Figure 38 is shown as process 324.

[0108] In accordance with some embodiments, the formation of the contact terminals 144 may include the formation of a barrier layer, which may contain titanium nitride, tantalum nitride, or the like. Next, a metallic material is deposited over and in contact with the barrier layer. The metallic material may include tungsten, cobalt, or the like. Then, a planarization process, such as a CMP process or a mechanical grinding process, is performed to remove excess portions of the barrier layer and the metallic material, leaving the contact terminals 144. In accordance with alternative embodiments, the contact terminals 144 do not have a barrier and may contain tungsten, ruthenium, or the like.

[0109] The deposition process for forming the contact terminals 144 can include a conformal deposition process or a bottom-up deposition process. If the bottom-up deposition process is used, a metal seed layer can be applied. The metal seed layer can be recessed such that only the sections at the bottoms of the openings 141 remain. This recession can be achieved by applying a sacrificial layer (such as a crosslinking photoresist), planarizing it, and then recessing the sacrificial layer to cover the bottom section of the metal seed layer, etching the exposed sidewall sections of the metal seed layer, and removing the sacrificial layer. Subsequently, a metal is deposited starting from the bottom section of the metal seed layer.

[0110] In accordance with some embodiments, for example, when a conformal deposition process is carried out to form the contact terminals 144, cavities 146 can be formed, which may be arranged in the areas overlapped by the silicide layers 142. In other embodiments, no cavities are formed.

[0111] Referring to Fig. In step 28, the wafer 2 is turned over and then attached to a carrier 146 by the release film 146. The process in question is in process sequence 300, which is in Fig. Figure 38 is shown as process 326. The support 146 can be a glass support, a silicon wafer, an organic support, or the like. The separating film 148 can be made of a polymer-based material (such as a light-to-heat conversion material (LTHC material)) that is capable of decomposing under heat-carrying radiation, such as a laser beam, so that the support 146 can be detached from the overlying structures formed in subsequent processes.

[0112] Referring to Fig. In step 29, wafer 2 is thinned from the back side. This process is part of process sequence 300, which is described in Fig. Figure 38 is shown as process 328. The thinning can be carried out by a CMP process or a mechanical grinding process. In accordance with some embodiments, thinning from the back side results in the removal of the base substrate 20, leaving behind sections of the semiconductor strips 20'. Certain sections of the STI regions 32, which are arranged in other planes not shown, may remain.

[0113] In accordance with some embodiments, the semiconductor strips 20' are replaced by a dielectric material forming the dielectric layer 150. The replacement may involve etching the semiconductor strips 20', depositing a dielectric material, such as silicon oxide, between adjacent STI regions 32, and performing a planarization process to remove excess portions of the dielectric material. In accordance with alternative embodiments, the semiconductor strips 20' are not replaced. Accordingly, the regions in question are referred to as regions '20' / 150' to indicate that these regions can be either semiconductor strips 20' or dielectric regions 150.

[0114] Referring to Fig. 30 An etching process is carried out to remove certain sections of areas 20' / 150 and to create openings 152. The process in question is in process sequence 300, which is in Fig. Figure 38 is shown as process 330. Thus, the lower dummy semiconductor regions 62L-D are exposed.

[0115] Fig. Figure 31 shows the formation of dielectric linings 154 in accordance with some embodiments. The process in question is described in process sequence 300, which is in Fig. Figure 38 is shown as process 332. The formation process can include a conformal deposition process to deposit a conformal dielectric layer and an anisotropic etching process to remove the horizontal sections of the conformal dielectric layer. The vertical sections of the conformal dielectric layer remain as the dielectric liners 154. The dielectric liners 154 can contain silicon nitride, silicon oxynitride, silicon carbonitride, or the like.

[0116] In accordance with some embodiments in which the semiconductor strips have been replaced by dielectric areas 150, the formation of the dielectric linings 154 can be omitted.

[0117] Then an etching process is performed to remove the dummy source / drain areas 62U-D. This process is in process flow 300, which is in Fig. Figure 38 is shown as process 334. The resulting structure is in Fig. Figure 32 shows that the etching process can be isotropic, removing all of the dummy source / drain regions 62L-D and exposing the sidewalls of the semiconductor nanostructures 26'L. The first CESL 66 can be used as part of the etch stop layer. Due to the selection of materials for the dummy source / drain regions 62L-D that differ from those of the semiconductor nanostructures 26'L, the semiconductor nanostructures 26'L remain essentially unetched.

[0118] Fig. Figure 33 represents the epitaxial regrowth process for forming the lower epitaxial source / drain regions 62L. The process in question is in process flow 300, which is in Fig. Figure 38 is shown as process 336. The lower epitaxial source / drain regions 62L are in contact with the lower semiconductor nanostructures 26'L, but not with the upper semiconductor nanostructures 26'U.

[0119] In accordance with some embodiments, the lower epitaxial source / drain regions 62L, which are grown from adjacent lower semiconductor nanostructures 26'L, are spaced apart from one another. In the following discussion, the lower epitaxial source / drain regions 62L, which are grown from adjacent lower semiconductor nanostructures 26'L, are also referred to as the sections of a lower semiconductor nanostructure 26'U.

[0120] The lower epitaxial source / drain regions 62L are epitaxially grown and exhibit a conductivity type suitable for the device type (p-type or n-type) of the lower nanostructure FETs. If the lower epitaxial source / drain regions 62L are p-type, the corresponding material can contain silicon or silicon-germanium doped with a p-type dopant, such as boron, indium, or the like. If the lower epitaxial source / drain regions 62L are n-type, the corresponding material can contain silicon or carbon-doped silicon doped with an n-type dopant, such as phosphorus, arsenic, or the like.

[0121] The temperature for the formation of the lower epitaxial source / drain regions 62L is controlled such that it is neither too high nor too low. In accordance with some embodiments, the temperature for the formation of the lower epitaxial source / drain regions 62L can be a relatively low temperature, which may be less than approximately 400°C and may lie in the range of approximately 300°C to approximately 400°C. If the temperature is too high, for example, more than approximately 400°C, this may impair the reliability of back-end-of-line structures. If the temperature is too low, for example, less than approximately 300°C, the lower epitaxial source / drain regions 62L may exhibit an amorphous structure.

[0122] Fig. Figure 34 represents the removal of one of the first ILDs 48 from one of the contact openings 152 in accordance with some embodiments. The sidewall sections of the first CESL 66 may be removed or remain. Accordingly, the sidewall sections of the first CESL 66 are shown with dashed lines to indicate that these sections may or may not be present. The process in question is described in process flow 300, which is in Fig. Figure 38 is shown as process 338. The removal is carried out by forming a structured etching mask (such as a photoresist) 156 before the first CESL 66 and the first ILD 68 are etched through the respective contact opening 152, which is not filled with the structured etching mask 156. The contact terminal 144B is thus exposed. After the etching process, the structured etching mask 156 is removed.

[0123] Referring to Fig. 35 Silicide layers 158 are formed. The process in question is in process sequence 300, which is in Fig. Figure 38 is shown as process 340. The formation process can include the application of a metal layer (not shown), for example, using a conformal deposition process such as a PVD process. The applied metal layer can contain titanium, cobalt, or the like. Subsequently, an annealing process is carried out to cause the metal layer to react with the silicon in the lower source / drain regions 62L, thus forming silicide layers 158. The remaining metal layer can then be removed, for example, by performing an etching process.

[0124] The silicide process consumes the outer sections of the lower epitaxial source / drain regions 62L, leaving behind the inner sections. The silicide layers 158 at adjacent (upper and corresponding lower) lower epitaxial source / drain regions 62L may be separated, with gaps between them, or they may be connected.

[0125] Referring to Fig. 36 (rear) contact connections 160 (which have contact connections 160A and 160B) are formed to fill the openings 152 and electrically connect them to the silicide layers 158. The process in question is in process sequence 300, which is in Fig. Figure 38 is shown as process 342. In accordance with some embodiments, the formation of the contact terminals 160 may include the formation of a barrier layer, which may contain titanium nitride, tantalum nitride, or the like. Next, a metallic material is deposited over and in contact with the barrier layer. The metallic material may contain tungsten, cobalt, or the like. Then, a planarization process, such as a CMP process or a mechanical grinding process, is carried out to remove excess portions of the barrier layer and the metallic material, leaving the contact terminals 160. In accordance with alternative embodiments, the contact terminals 160 do not have a barrier and may contain tungsten, ruthenium, or the like.

[0126] The deposition process for forming the contact terminals 160 can include a conformal deposition process or a bottom-up deposition process. If the bottom-up deposition process is used, a metal seed layer can be applied. The metal seed layer can be recessed such that only the sections at the bottoms of the openings 152 remain. This recession can be achieved by applying a sacrificial layer (such as a cross-linked photoresist), planarizing it, and then recessing the sacrificial layer to cover the bottom section of the metal seed layer, etching the exposed sidewall sections of the metal seed layer, and removing the sacrificial layer. Subsequently, a metal is deposited starting from the bottom section of the metal seed layer.

[0127] In accordance with some embodiments, for example when a conformal deposition process is carried out, cavities 162 can be formed, which may be arranged in the areas that are overlapped (and / or superimposed) by the silicide layers 158. In other embodiments, no cavities are formed.

[0128] In accordance with some embodiments, contact terminal 160B is physically connected to contact terminal 144B. The interface between contact terminals 144B and 160B may be distinguishable. In embodiments where contact terminals 144A and 160B have barriers, the barriers may each be U-shaped, with the U-shape of the barrier of contact terminal 144B having a downward-facing opening, and the U-shape of the barrier of contact terminal 160B having an upward-facing opening. Thus, CFET 10, comprising the upper FET 10U and the lower FET 10L, is formed.

[0129] In a subsequent process, the wafer 2 is detached from the support, for example by directing a laser beam onto the separating film 148 in such a way that the separating film 148 decomposes and thus detaches the wafer 2 from the support 146. Fig.Figure 37 represents a resulting wafer 2, which is shown such that the upper FET 10U overlaps the lower FET 10L.

[0130] The embodiments of the present disclosure exhibit several advantageous features. In accordance with some embodiments, dummy source / drain regions are first formed to facilitate the self-alignment of the subsequently formed low-temperature epitaxy source / drain regions. By applying low-temperature epitaxy to form the source / drain regions, the resistance of the source / drain regions and the corresponding contact terminals is reduced. Furthermore, the low-temperature regrowth also improves the activation rate of the newly regrowthed epitaxial source / drain regions.

[0131] In accordance with some embodiments of the present disclosure, a method comprises forming a lower transistor, comprising forming a lower source / drain region over a semiconductor substrate, wherein the lower source / drain region has a bottom surface facing the semiconductor substrate; forming an upper transistor, comprising forming an upper source / drain region over the lower source / drain region; thinning the semiconductor substrate; forming a contact opening to expose the bottom surface of the lower source / drain region; performing a first epitaxy process to grow a first semiconductor layer on the lower source / drain region; and forming a silicide layer, wherein the silicide layer is electrically connected to the lower source / drain region through the first semiconductor layer.

[0132] In one embodiment, the method further comprises performing a second epitaxial growth process to grow a second semiconductor layer over the first semiconductor layer. In one embodiment, the silicide layer is formed by silicifying a portion of the second semiconductor layer. In one embodiment, both the first and second semiconductor layers contain germanium. In one embodiment, the second semiconductor layer has a higher atomic percentage of germanium than the first semiconductor layer. In one embodiment, the lower source / drain region is formed at a first temperature, and the first epitaxial growth process is performed at a second temperature that is lower than the first temperature.

[0133] In one embodiment, the method further comprises forming an additional silicide layer at the lower source / drain region, wherein the silicide layer and the additional silicide layer are arranged on opposite sides of the lower source / drain region; and forming a contact terminal that contacts the additional silicide layer, the contact terminal penetrating the upper source / drain region. In another embodiment, the method further comprises forming a contact opening from a rear side of the lower source / drain region, wherein the first semiconductor layer is formed in the contact opening.

[0134] In accordance with some embodiments of the present disclosure, a method comprises forming a first transistor having a first source / drain region, wherein the first source / drain region is arranged over a semiconductor substrate; performing a backside thinning process to thin the semiconductor substrate; forming a contact opening from a backside of the semiconductor substrate, exposing a rear face of the first source / drain region; depositing a first semiconductor layer over the rear face of the first source / drain region; depositing a second semiconductor layer over the first semiconductor layer; silicidalizing the second semiconductor layer to form a silicidal layer; and forming a backside contact terminal for connecting to the silicidal layer.In one embodiment, both the first source / drain region and the first semiconductor layer contain silicon germanium.

[0135] In one embodiment, the first semiconductor layer has a higher atomic percentage of germanium than the first source / drain region. In another embodiment, the second semiconductor layer contains germanium and is essentially free of silicon. In yet another embodiment, the first source / drain region is formed at a first temperature, and the first and second semiconductor layers are formed at a second temperature, which is lower than the first temperature.

[0136] In one embodiment, the first semiconductor layer and the second semiconductor layer are deposited by selective epitaxy. In another embodiment, the method further comprises forming a second transistor having a second source / drain region, wherein the second source / drain region overlaps the first source / drain region. In one embodiment, the first transistor and the second transistor together form a complementary field-effect transistor.

[0137] In accordance with some embodiments of the present disclosure, a structure comprises a lower transistor having a lower source / drain region, wherein the lower source / drain region comprises a semiconductor region; and a first semiconductor layer arranged below the semiconductor region; a first silicide layer arranged below the semiconductor region and electrically connected to it by the first semiconductor layer; a contact etch stop layer having a lower portion arranged below the semiconductor region; and a sidewall section contacting a sidewall of the semiconductor region, wherein the first semiconductor layer is lower than the sidewall section of the contact etch stop layer; and a first contact terminal arranged below and connected to the first silicide layer.

[0138] In one embodiment, the structure further comprises a second semiconductor layer between the first semiconductor layer and the first silicide layer. In another embodiment, the structure further comprises a second silicide layer above and in contact with the first semiconductor region; and a second contact terminal above and connected to the second silicide layer. In another embodiment, the structure further comprises an upper transistor which has an upper source / drain region that overlaps the lower source / drain region.

[0139] The foregoing description presents features / elements of various embodiments in such a way that skilled persons may better understand the aspects of the present disclosure. Skilled persons should recognize that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages as the embodiments presented herein. Skilled persons should also recognize that such equivalent designs do not deviate from the concept and scope of the present disclosure, and that they can make a wide variety of changes, substitutions, and adaptations to them without deviating from the concept and scope of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 718,011

[0001]

Claims

[1] Procedure, encompassing: Forming a lower transistor, comprising: Forming a lower source / drain region over a semiconductor substrate, wherein the lower source / drain region has a bottom side facing the semiconductor substrate; Forming an upper transistor, comprising: Forming an upper source / drain area above the lower source / drain area; Diluting the semiconductor substrate; Forming a contact opening to expose the lower side of the lower source / drain area; Executing a first epitaxial process to grow a first semiconductor layer at the lower source / drain region; and Forming a silicide layer, wherein the silicide layer is electrically connected to the lower source / drain region via the first semiconductor layer. [2] Method according to claim 1, further comprising carrying out a second epitaxy process to grow a second semiconductor layer over the first semiconductor layer. [3] Method according to claim 2, wherein the silicide layer is formed by silicidalizing a section of the second semiconductor layer. [4] Method according to claim 2, wherein the first semiconductor layer and the second semiconductor layer contain germanium. [5] Method according to claim 4, wherein the second semiconductor layer has a higher atomic percentage of germanium than the first semiconductor layer. [6] Method according to any one of claims 1 to 5, wherein the lower source / drain region is formed at a first temperature, and the first epitaxy process is carried out at a second temperature which is lower than the first temperature. [7] Method according to any one of claims 1 to 6, further comprising: Forming an additional silicide layer at the lower source / drain region, wherein the silicide layer and the additional silicide layer are located on opposite sides of the lower source / drain region; and Forming a contact connection that contacts the additional silicide layer, with the contact connection penetrating the upper source / drain area. [8] Method according to any one of claims 1 to 7, further comprising forming a contact opening from a rear side of the lower source / drain region, wherein the first semiconductor layer is formed in the contact opening. [9] Procedures, comprehensive: Forming a first transistor which has a first source / drain region, wherein the first source / drain region is arranged over a semiconductor substrate; Performing a backside dilution process to dilute the semiconductor substrate; Forming a contact opening from a rear side of the semiconductor substrate, thereby exposing a rear surface of the first source / drain region; Deposition of a first semiconductor layer over the rear surface of the first source / drain region; Applying a second semiconductor layer over the first semiconductor layer; Silicidalizing the second semiconductor layer to form a silicide layer; and Forming a rear contact connection that connects the silicide layer. [10] Method according to claim 9, wherein both the first source / drain region and the first semiconductor layer contain silicon germanium. [11] Method according to claim 10, wherein the first semiconductor layer has a higher atomic percentage of germanium than the first source / drain region. [12] Method according to claim 11, wherein the second semiconductor layer contains germanium and is substantially free of silicon. [13] Method according to any one of claims 9 to 12, wherein the first source / drain region is formed at a first temperature, and the first semiconductor layer and the second semiconductor layer are formed at a second temperature which is lower than the first temperature. [14] Method according to any one of claims 9 to 13, wherein the first semiconductor layer and the second semiconductor layer are applied by selective epitaxy. [15] Method according to any one of claims 9 to 14, further comprising: Forming a second transistor which has a second source / drain region, wherein the second source / drain region overlaps the first source / drain region. [16] Method according to claim 15, wherein the first transistor and the second transistor together form a complementary field-effect transistor. [17] Structure, exhibiting: a lower transistor which has a lower source / drain region, wherein the lower source / drain region has: a semiconductor area; and a first semiconductor layer, which is located beneath the semiconductor area; a first silicide layer, which is located below the semiconductor area and is electrically connected to it by the first semiconductor layer; having a contact etch stop layer: a lower part, which is located below the semiconductor area; and a sidewall section which contacts a sidewall of the semiconductor region, wherein the first semiconductor layer is lower than the sidewall section of the contact etch stop layer; and a first contact connection, which is located under and connected to the first silicide layer. [18] Structure according to claim 17, further comprising: a second semiconductor layer between the first semiconductor layer and the first silicide layer. [19] Structure according to claim 17 or 18, further comprising: a second silicide layer over and in contact with the semiconductor area; and a second contact connection, which is located above and connected to the second silicide layer. [20] Structure according to any one of claims 17 to 19, further comprising: an upper transistor which has an upper source / drain area that overlaps the lower source / drain area.

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