Semiconductor devices

Abstract

Semiconductor device in which a connection area is formed outside an active area, comprising: - an n-drift layer (1) which has a front surface and a back surface which are opposite each other; - a p-anode layer (2) which is formed on the front surface of the n-drift layer (1) in the active region; - an n-buffer layer (7) which is formed on the rear surface of the n-drift layer (1); - an n-cathode layer (8) and a p-cathode layer (9) which are arranged next to each other on a rear surface of the n-buffer layer (7); - an n-layer (10) which is formed on the rear surface of the n-buffer layer (7) in a transition region between the active region and the connection region next to the n-cathode layer (8) and the p-cathode layer (9); and - a cathode electrode (11) which is formed in the active region and forms an ohmic contact with the n-cathode layer (8) and the p-cathode layer (9), wherein: - an extent length of the n-layer (10) to the side of the active region, with an end section of the active region as a starting point, represented by WGR1, and - WGR1 100 µm ≤ WGR1 ≤ 500 µm is fulfilled.

Description

Technical field

[0001] The present invention relates to semiconductor devices which can be used for a high-standby voltage power module (≥ 600 V). Background of the invention

[0002] Conventional diodes exhibit a reduced forward voltage drop (VF) through the application of a thin-wafer process and optimization of the cathode profile (see, for example, NPL 1). Wafer thinning is also effective for diodes to achieve a low VF, as in the case of an IGBT (insulated-gate bipolar transistor), but this leads to a reduction in the tolerance for a break-up during recovery, thereby increasing the risk of device breakdown.

[0003] Diodes designed for a high withstand voltage class aim to improve a recovery SOA (safe operating area) by reducing carrier concentration in a terminal area in an AN state by means of a p-layer formed on a rear side of the terminal area and avoiding a concentration of charge carriers on a boundary area during recovery (see for example NPL 2).

[0004] Furthermore, it was demonstrated that in low to medium withstand voltage classes of 600 to 1700 V, it is possible to increase the electric field strength on one cathode side in addition to a main junction by means of alternating p-layers and n-layers arranged on the side of the back surface of the active region, to avoid a tear-off phenomenon, and to reduce overall losses by advantageously decreasing the thickness of an n-layer. - -to reduce the drift layer (see for example NPL 3).

[0005] On the other hand, if the substrate concentration is increased and the n - If the drift layer is designed to have a reduced thickness to minimize overall loss when securing a tensile strength, a breakthrough occurs simultaneously with an avalanche near a breakthrough point that significantly exceeds a nominal stress during static dielectric strength measurement. Therefore, for applications requiring operational reliability in the event of an avalanche, there is a limitation to reducing wafer thickness. Citation list: Non-patent literature NPL 1: H. Fujii, M. Inoue, K. Hatade and Y. Tomomatsu, "A Novel Buffer Structure and lifetime control Technique with Poly-Si for Thin Wafer Diode," Proc. ISPSD'09, pp. 140-143, Barcelona, ​​Spain (2009) NPL 2: K. Nakamura, F. Masuoka, A. Nishii, K. Sadamatsu, S. Kitajima and K. Hatade, „ Advanced RFC Technology with New Cathode Structure of Field Limiting Rings for High Voltage Planar Diode," Proc. ISPSD'10, S. 133-136, Hiroshima, Japan (2010) NPL 3: F. Masuoka, K. Nakamura, A. Nishii and T. Terashima, „Great Impact of RFC Technology on Fast Recovery Diode towards 600 V for Low Loss and High Dynamic Ruggedness," Proc. ISPSD'12, S. 373-376, Brügge, Belgien (2012) Weiterer Stand der Technik

[0006] Publication JP 2014-103376A discloses a semiconductor device with improved reliability. An IGBT region is provided on a first electrode and functions as an IGBT. A diode region, functioning as a diode, is provided on the first electrode. An interface region is provided between the IGBT region and the diode region and is adjacent to both. A collector layer of the first conductivity type is provided in the IGBT region and the interface region and functions as a collector of the IGBT within the IGBT region. A cathode layer of the second conductivity type is provided in the diode region, spaced apart from the collector layer, and functions as a cathode of the diode. A drift layer of the second conductivity type is provided on the opposite side of the first electrode of the collector layer and the cathode layer within the IGBT region, the interface region, and the diode region.A diffusion layer of the first conductivity type is provided on the opposite side of the first electrode of the drift layer in the boundary region.

[0007] German patent application DE 11 2012 006 215 T5 describes a diode in which a p-type anode layer is formed on an n-type drift layer in an active region. A p-type diffusion layer is present on the n-type drift layer in a termination region outside the active region. An oxide layer covers an outer circumference of the p-type anode layer. An anode electrode is connected to a section of the p-type anode layer that is not covered by the oxide layer. + A -type cathode layer is present below the n-type drift layer. One cathode electrode is connected to the n +-type cathode layer connected. An area of ​​a section of the p-type anode layer covered with the oxide layer is 5% to 30% of the total area of ​​the p-type anode layer.

[0008] Publication WO 2014 / 156 849 A1 describes a semiconductor device in which a + -cathode layer in a surface layer on the back of a n - is arranged on a semiconductor substrate and extends from an active region to an edge termination region. The entire surface of the n + The cathode layer is covered with a cathode electrode. An n-buffer layer is located in a region of the n - -Drift zone near the n + -cathode layer and also extends from the active area to the boundary region. A free-floating, buried p-layer is located in a region of the n - -Drift zone near the n + -cathode layer, however deeper than the n+ -Cathode layer from the substrate back. The buried p-layer is uniformly arranged in a predetermined area, in which it forms the n + -cathode layer touches. An end region of the buried p-layer is located within a side face of the n - -Semiconductor substrate.

[0009] Publication WO 2014 / 199465 A1 discloses a semiconductor device in which a p-type anode layer is located on an upper surface of an n - A -type drift layer is formed. An n-type cathode layer is formed on a lower surface of the n - A -type drift layer is provided. An n-type buffer layer is located between the n - A -type drift layer and an n-type cathode layer are provided. The highest impurity concentration in the n-type buffer layer is higher than in the n-type layer. --type drift layer and lower than in the n-type cathode layer. A gradient of charge carrier concentration at a junction between the n - The -type drift layer and the n-type buffer layer are 20 cm thick. -4 up to 2000 cm -4 . Brief description: Technical problem

[0010] To reduce the overall loss while maintaining static dielectric strength, the wafer must be made thinner and a higher resistivity developed. However, with such a pin diode design, the electric field weakens not only in the main junction but also in a junction between the n - -layer and the n +The -layer on the cathode side closes during recovery, with charge carriers left behind in the drift layer being drastically flushed out in the final phase of recovery, resulting in a drastic interruption of the tail current (breakdown). The problem is that this triggers an impulse voltage due to an electromotive force back EMF from a parasitic inductance Ls in the circuit, and due to L and C in the circuit, an oscillation phenomenon.

[0011] Conventional pin diodes have a termination back-surface structure whose entire surface consists of a n +A layer is formed, resulting in a high charge carrier concentration in a terminal area from an active (AN) state. Consequently, during a turn-off process, positive holes are concentrated at a contact end in the boundary region between the active and terminal areas, leading to a local temperature rise (≥800 K), which can result in breakdown.

[0012] Furthermore, devices containing a parasitic pnp bipolar transistor setup exhibit a problem of avalanche resistance deterioration during a turn-off and turn-off process compared to devices that do not contain a parasitic setup.

[0013] The present invention was used to solve the problems described above, and it is an object of the present invention to provide a semiconductor device capable of preventing a break-up phenomenon in the final phase of a turn-off process and an oscillation phenomenon triggered thereby, preventing a breakdown in a transition between the active region and the connection region during a turn-off process, and improving the avalanche resistance during a turn-off process and a turn-off process. Solution to the problem

[0014] The problem underlying the invention is solved according to the invention in a semiconductor device by the features of claim 1, alternatively by the features of claim 8, further alternatively by the features of claim 10, and further alternatively by the features of claim 11. Advantageous embodiments are the subject of the respective dependent claims.

[0015] A semiconductor device according to the present invention, wherein a connection area is arranged outside an active region, comprises, among other things: an n-drift layer having a front face and a rear face facing each other; a p-anode layer formed on the front face of the n-drift layer in the active region; an n-buffer layer formed on the rear face of the n-drift layer; an n-cathode layer and a p-cathode layer formed side by side on a rear face of the n-buffer layer;and an n-layer formed on the rear surface of the n-buffer layer in a transition region between the active region and the connection region next to the n-cathode layer and the p-cathode layer, wherein an extent length of the n-layer to the side of the active region with an end section of the active region as a starting point is represented by WGR1 and WGR1 satisfies 10 µm≤WGR1≤500µm.; Advantageous effects of the invention

[0016] In the present invention, an n-layer is formed on the rear surface of the n-buffer layer in the transition region between the active area and the connection area, and WGR1, which represents the extent length of the n-layer to the side of the active area, satisfies 10 µm ≤ WGR1 ≤ 500 µm. This makes it possible to avoid a stall phenomenon and a resulting oscillation phenomenon at the end of the switch-off process and to improve the avalanche resistance during a switch-off process. Brief description of the drawings Fig. Figure 1 is a cross-sectional view showing a semiconductor device according to embodiment 1 of the present invention. Fig. Figure 2 is a bottom view showing the semiconductor device according to embodiment 1 of the present invention. Fig. Figure 3 is a bottom view, which shows a modification of the semiconductor device according to embodiment 1 of the present invention. Fig. Figure 4 is a bottom view, which shows a modification of the semiconductor device according to embodiment 1 of the present invention. Fig. Figure 5 is a diagram showing samples of the conventional setup that were subjected to an avalanche breakthrough. Fig. Figure 6 is a diagram that shows simulation results of an internal state when a blocking bias is applied. Fig. Figure 7 is a diagram that simulates a recovery characteristic. Fig. Figure 8 is a diagram showing the density of positive holes and the electric field strength of a conventional setup. Fig. Figure 9 is a diagram showing the density of positive holes and the electric field strength of the present embodiment. Fig. Figure 10 is a diagram showing the results of a measurement of the room temperature standstill voltage characteristic of a set of 1200 V prototypes. Fig. Figure 11 is a diagram that represents a demolition characteristic. Fig. Figure 12 is a diagram illustrating WGR1 and WGR2 dependencies of a secondary breakdown starting current and a maximum controllable current. Fig. Figure 13 is a cross-sectional view showing a semiconductor device according to embodiment 2 of the present invention. Fig. Figure 14 is a bottom view showing the semiconductor device according to embodiment 2 of the present invention. Fig. Figure 15 is a cross-sectional view showing a semiconductor device according to embodiment 3 of the present invention. Fig. Figure 16 is a bottom view showing the semiconductor device according to embodiment 3 of the present invention. Fig. Figure 17 is a cross-sectional view showing a semiconductor device according to embodiment 4 of the present invention. Fig. Figure 18 is a bottom view showing the semiconductor device according to embodiment 4 of the present invention. Fig. Figure 19 is a cross-sectional view showing a semiconductor device according to embodiment 5 of the present invention. Fig. Figure 20 is a cross-sectional view showing a semiconductor device according to embodiment 6 of the present invention. Fig. Figure 21 is a cross-sectional view showing a semiconductor device according to embodiment 7 of the present invention. Fig. Figure 22 is a cross-sectional view showing a semiconductor device according to embodiment 8 of the present invention. Fig. Figure 23 is a cross-sectional view showing a semiconductor device according to embodiment 9 of the present invention. Fig. Figure 24 is a cross-sectional view showing a semiconductor device according to embodiment 10 of the present invention. Fig. Figure 25 is a cross-sectional view showing a semiconductor device according to embodiment 11 of the present invention. Fig. Figure 26 is a cross-sectional view showing a semiconductor device according to embodiment 12 of the present invention. Fig. Figure 27 is a cross-sectional view showing a semiconductor device according to embodiment 13 of the present invention. Fig. Figure 28 is a cross-sectional view showing a semiconductor device according to embodiment 14 of the present invention. Fig. Figure 29 is a cross-sectional view showing a semiconductor device according to embodiment 15 of the present invention. Fig. Figure 30 is a cross-sectional view showing a semiconductor device according to embodiment 16 of the present invention. Fig. Figure 31 is a bottom view showing the semiconductor device according to embodiment 16 of the present invention. Fig. Figure 32 is a bottom view which represents a modification of the semiconductor device according to embodiment 16 of the present invention. Description of the embodiments

[0017] A semiconductor device according to the embodiments of the present invention is described with reference to the drawings. The same components are identified by the same reference numerals, and their repeated description may be omitted. Design 1

[0018] Fig. Figure 1 is a cross-sectional view showing a semiconductor device according to embodiment 1 of the present invention. A connection area is arranged outside an active area. - -Drift layer 1 has a front surface and a rear surface that are opposite each other.

[0019] A p-anode layer 2 is located on a front surface of the n -A drift layer 1 is formed in the active region. An end section of the p-anode layer 2 overlaps an end section of the active region. A typical p-protection ring layer 3 and a channel stopper layer 4 are located on the surface of the n - A drift layer 1 is formed in the connection area. An anode electrode 5 forms an ohmic contact with the p-anode layer 2 through an opening in an intermediate layer film 6.

[0020] An n-buffer layer 7 is located on a rear surface of the n -A drift layer 1 is formed. An n-cathode layer 8 and a p-cathode layer 9 are formed side by side on a rear surface of the n-buffer layer 7. An n-layer 10 is formed on the rear surface of the n-buffer layer 7 in a transition region between the active region and the connection region, adjacent to the n-cathode layer 8 and the p-cathode layer 9. The n-layer 10 has the same impurity concentration as the n-cathode layer 8. A cathode electrode 11 forms an ohmic contact with the n-cathode layer 8, the p-cathode layer 9, and the n-layer 10.

[0021] The extension length of the n-layer 10 to the side of the active region, with an end section of the active region as a starting point, is represented by WGR1. The extension length of the n-layer 10 to the side of the connection region, with an end section of the active region as a starting point, is represented by WGR2. WGR1 and WGR2 satisfy 10 µm ≤ WGR1 ≤ 500 µm and 10 µm ≤ WGR2 ≤ 500 µm, respectively.

[0022] Electron-hole pairs, generated by collision and ionization at the end section of the p-anode layer 2 when a reverse bias is applied, pass through a strong electric field and move towards the cathode electrode 11. The process of a parasitic pnp transistor can be prevented by ensuring an opening for the electrons through the n-layer 10. To achieve this effect, WGR1 and WGR2 are preferably designed to be on the order of several tens of micrometers. It should be noted that if the extending shape of a depletion layer is taken into account, WGR2 must be designed to be larger than WGR1.

[0023] Fig. Figure 2 is a bottom view showing the semiconductor device according to embodiment 1 of the present invention. A pattern of p-cathode layers 9 and n-cathode layers 8 is arranged in a lattice configuration perpendicular to the long side of the chip. Fig. 3 and Fig. Figure 4 shows bottom views illustrating modifications to the semiconductor device according to the embodiment of the present invention. Fig. Figure 3 shows a pattern of p-cathode layers 9 and n-cathode layers 8 arranged in a lattice configuration parallel to the long side of the chip. Fig. 4 is a pattern of p-cathode layers 9 and n-cathode layers 8 arranged in a ring shape.

[0024] Next, a conventional structure in which the p-cathode layer 9 is formed in the transition region and the terminal region is compared with the present embodiment in which the n-layer 10 is formed. Both are diodes in which an FLR (field limiting ring) structure is formed on the surface of the terminal region and a repeating structure of the p-layer and the n-layer is formed on the rear surface of the active region.

[0025] Fig. Figure 5 is a diagram depicting samples of the conventional setup that underwent avalanche breakdown. In all samples subjected to avalanche breakdown, silicon protrusions were observed at the anode end sections at the corners of the chip, and melt traces were found in the silicon immediately beneath the interlayer films. From this result, it is possible to assume that a thermal breakdown due to an overcurrent may have occurred in the final stage of the breakdown mechanism.

[0026] Fig. Figure 6 is a diagram showing simulation results of an internal state when a reverse bias is applied. As a result of the simulation of a withstand voltage characteristic at room temperature, a region of negative differential resistance (NDR) appeared near a breakdown starting point, which significantly exceeded a rated voltage, and described the withstand voltage waveform as an "S-shape." Based on observations of the device's internal state with respect to the corresponding current values, it was estimated that electrons and positive holes exist in high density in the longitudinal direction of the device at the contact end within the NDR region (bipolar process). This suggests that the avalanche breakdown could be a secondary breakdown of a longitudinal parasitic pnp transistor at the contact end. Furthermore, the aforementioned embodiment has improved the avalanche resistance.With these results, it is possible to assume that the principles of an avalanche breakdown of the conventional setup are essentially similar to the principles of a secondary breakdown of a bipolar transistor: "Process of charge carriers generated by collision and ionization in a strong electric field, which act as a base current and continue an on-process."

[0027] Fig. Figure 7 is a diagram that simulates a recovery characteristic. Fig. Figure 8 is a diagram representing the density of positive holes and the electric field strength of a conventional setup and Fig. Figure 9 is a diagram showing the density of positive holes and the electric field strength of the present embodiment. The present embodiment has obtained results with a higher impulse voltage than the conventional setup. From an internal analysis, which was carried out to investigate the causes of an increase in impulse voltage at each point in time during recovery, it was estimated that in the conventional setup, a depletion layer extends slowly towards the cathode side directly above the p-cathode layer on the rear surface of the terminal area, whereas in the present embodiment, the depletion layer extends drastically towards the cathode side directly above the n-layer on the rear surface of the terminal area.

[0028] Furthermore, when a UIS test of the conventional setup was simulated, a device breakdown near a stress peak was successfully simulated. Results of an internal analysis performed at each time point show that the internal state at the time of a device breakdown is quite similar to the simulated internal state at the time of application of the blocking bias described above. Therefore, it was estimated that an improvement could be achieved by forming the n-layer on the back face of the transition region between the active area and the terminal area.

[0029] Fig. Figure 10 is a diagram showing the results of a room-temperature withstand voltage measurement of a set of 1200 V prototypes. In the case of a conventional setup with a p-cathode layer formed on the rear face of the terminal area, the setup was destroyed simultaneously with the onset of breakdown near 1500 V. On the other hand, in the case of the present embodiment, in which the n-layer is formed on the rear face at an end section of the active area, the avalanche resistance was successfully improved as intended.

[0030] Fig. Figure 11 is a diagram representing a cutoff characteristic. When evaluating a cutoff characteristic of the present embodiment, the peak voltage waveform value Vcutoff is approximately 100 V higher than the conventional setup at Vcc = 850 V, but 300 V or more lower than the pin diode. It is therefore estimated that RFC effects can be retained.

[0031] Fig. Figure 12 is a diagram illustrating the WGR1 and WGR2 dependencies of a secondary breakdown start current and a maximum controllable current. As WGR1 or WGR2 approaches 0, the secondary breakdown start current decreases, while the maximum controllable current increases. Conversely, as WGR1 or WGR2 increases, the maximum controllable current decreases, while the secondary breakdown start current increases. Thus, WGR1 and WGR2 must satisfy the conditions 10 µm ≤ WGR1 ≤ 500 µm and 10 µm ≤ WGR2 ≤ 500 µm, respectively.

[0032] In the present embodiment, as described above, the n-layer 10 is formed on the rear surface in the transition region between the active region and the terminal region, thereby avoiding parasitic pnp transistor operation and thus preventing breakdown in the transition between the active region and the terminal region during a turn-off operation, thereby improving the avalanche resistance during a turn-off operation and a turn-off operation. However, a concentration of electric fields at an end section of the active region is likely to occur due to curvature of a diffusion layer, and a drastic depletion of charge carriers in the device, which triggers a voltage / current waveform vibration during a recovery operation, is likely to occur first.For this reason, the more the p-cathode layer 9 is separated from the end section of the active region, the more likely it is that a voltage / current waveform vibration will occur during a recovery process. Therefore, the present invention incorporates an adjustment such that the extension lengths WGR1 and WGR2 of the n-layer 10, on the side of the active region and on the side of the terminal region, respectively, satisfy the values ​​10 µm ≤ WGR1 ≤ 500 µm and 10 µm ≤ WGR2 ≤ 500 µm. This makes it possible to avoid a stall phenomenon and the resulting oscillation phenomenon at the end of the turn-off process. Design 2

[0033] Fig. Figure 13 is a cross-sectional view showing a semiconductor device according to embodiment 2 of the present invention. Fig. Figure 14 is a bottom view showing the semiconductor device according to embodiment 2 of the present invention. In the present embodiment, the n-layer 10 has the same impurity concentration as the n-buffer layer 7. The rest of the configuration is the same as that from embodiment 1, and effects similar to those of embodiment 1 can be obtained. embodiment 3

[0034] Fig. Figure 15 is a cross-sectional view showing a semiconductor device according to embodiment 3 of the present invention. Fig. Figure 16 is a bottom view showing the semiconductor device according to embodiment 3 of the present invention. In the present embodiment, no p-cathode layer 9 is formed in the connection area. The rest of the configuration is the same as that of embodiment 1, and effects similar to those of embodiment 1 can be obtained. Design 4

[0035] Fig. Figure 17 is a cross-sectional view showing a semiconductor device according to embodiment 4 of the present invention. Fig. Figure 18 is a bottom view showing the semiconductor device according to embodiment 4 of the present invention. In the present embodiment, the n-layer 10 has the same impurity concentration as the n-buffer layer 7, and no p-cathode layer 9 is formed in the terminal area. The rest of the configuration is the same as that of embodiment 1, and effects similar to those of embodiment 1 can be obtained. Design 5

[0036] Fig. Figure 19 is a cross-sectional view showing a semiconductor device according to embodiment 5 of the present invention. In the present embodiment, the p-cathode layer 9, which has a width Wp1, is arranged adjacent to an end section on the active region side of the n-layer 10. The rest of the configuration is the same as that of embodiment 1, and effects similar to those of embodiment 1 can be obtained.

[0037] Here, electrons from electron-hole pairs, which are generated by collision and ionization at the end section of the p-anode layer 2 when a reverse bias is applied, move towards the cathode in a strong electric field. If a voltage drop, caused by an electric current directed to the n-layer 10 in the active region, which bypasses the n-buffer layer 7 immediately above the p-cathode layer 9, exceeds an internal potential Vin between the p-cathode layer 9 and the n-buffer layer 7, a parasitic pnp transistor process is induced. Assuming that the resistivity of the n-buffer layer 7 is ρ Puffer is and an electric current I e is the internal potential Vin by Vin=∫ρ Puffer ·I e ·xdx given. For example, if I e 200 A / cm 2 is an acceptor density NA of the p-cathode layer 9 1E17 / cm² 3is a donor density ND of the n-buffer layer 7 3E16 / cm² 3 is a concentration maximum N Puffer the n-buffer layer 7 3E16 / cm 2 Given that the thickness of the n-buffer layer is 1.5 µm and the temperature is 300 K, it is deduced that to exceed an internal potential of approximately 0.79 V, Wp1 must be approximately 58.5 µm. This makes it possible to avoid the behavior of a parasitic pnp transistor. To achieve this effect, the width Wp1 is preferably designed to be on the order of several tens of µm. Design 6

[0038] Fig. Figure 20 is a cross-sectional view depicting a semiconductor device according to embodiment 6 of the present invention. In the present embodiment, the p-cathode layer 9, which has a width Wp2, is arranged adjacent to an end section on the side of the connection area of ​​the n-layer 10. The remainder of the configuration is the same as that of embodiment 1, and effects similar to those of embodiment 1 can be obtained. The width Wp2 is preferably on the order of several tens of micrometers, as in the case of embodiment 5. Model 7

[0039] Fig. Figure 21 is a cross-sectional view showing a semiconductor device according to embodiment 7 of the present invention. In the present embodiment, the n-layer 10 has the same impurity concentration as the n-buffer layer 7. The rest of the configuration is the same as that of embodiment 5, and effects similar to those of embodiment 5 can be obtained. Design 8

[0040] Fig. Figure 22 is a cross-sectional view showing a semiconductor device according to embodiment 8 of the present invention. In the present embodiment, the n-layer 10 has the same impurity concentration as the n-buffer layer 7. The rest of the configuration is the same as that of embodiment 6, and effects similar to those of embodiment 6 can be obtained. Design 9

[0041] Fig. Figure 23 is a cross-sectional view showing a semiconductor device according to embodiment 9 of the present invention. In the present embodiment, the n-cathode layer 8 is arranged adjacent to an end section on the active region side of the n-layer 10. The remainder of the configuration is the same as that of embodiment 8, and effects similar to those of embodiment 8 can be obtained. Design 10

[0042] Fig. Figure 24 is a cross-sectional view showing a semiconductor device according to embodiment 10 of the present invention. In the present embodiment, p -Layers 12a and 12b, which have a lower concentration than that of the p-cathode layer 9, are formed on the rear surface of the n-buffer layer 7 and are each adjacent to the active region side and the terminal region side of the n-layer 10. The rest of the configuration is the same as that of embodiment 8, and effects similar to those of embodiment 8 can be obtained. The widths Wp1 and Wp2 of the p - Layers 12a and 12b are preferably designed to be on the order of several tens of µm, as in the case of embodiment 5. Design 11

[0043] Fig. Figure 25 is a cross-sectional view showing a semiconductor device according to embodiment 11 of the present invention. In the present embodiment, instead of the n-layer 10 according to embodiment 1, a p -Layer 13, which has a lower concentration than that of p-cathode layer 9, is formed on the rear surface of n-buffer layer 7 in the transition zone between the active region and the connection zone, adjacent to n-cathode layer 8 and p-cathode layer 9. The extent of the p - -Layer 13 to the side of the active area with an end section of the active area as a starting point is WGR1 and an extent length of the p - Layer 13, facing the connection area with the end section of the active area as a starting point, is WGR2, where WGR1 and WGR2 satisfy the conditions 10 µm ≤ WGR1 ≤ 500 µm and 10 µm ≤ WGR2 ≤ 500 µm, respectively. The remainder of the configuration is the same as that of embodiment 1, and effects similar to those of embodiment 1 can be obtained. Design 12

[0044] Fig. Figure 26 is a cross-sectional view showing a semiconductor device according to embodiment 12 of the present invention. The p-cathode layers 9, which have widths Wp1 and Wp2, are located on the active region side and the terminal region side of the p-cathode. - Layer 13 is arranged adjacent to each other. The rest of the configuration is the same as that of embodiment 11, and effects similar to those of embodiment 11 can be obtained. The widths Wp1 and Wp2 are, as in the case of embodiment 5, preferably designed to be on the order of several tens of micrometers. embodiment 13

[0045] Fig. Figure 27 is a cross-sectional view showing a semiconductor device according to embodiment 13 of the present invention. In the present embodiment, the n-cathode layer 8 is located at the end section on the active region side of the p -Layer 13 is arranged adjacently. The rest of the configuration is the same as that of embodiment 11, and effects similar to those of embodiment 11 can be obtained. embodiment 14

[0046] Fig. Figure 28 is a cross-sectional view showing a semiconductor device according to embodiment 14 of the present invention. In the present embodiment, the n-cathode layer 8 is located at the end section on the side of the connection area of ​​the p - Layer 13 is arranged adjacently. The rest of the configuration is the same as that of embodiment 11, and effects similar to those of embodiment 11 can be obtained. Design 15

[0047] Fig. Figure 29 is a cross-sectional view depicting a semiconductor device according to embodiment 15 of the present invention. The n-layer 10 and the n-cathode layer 8 have a greater depth than the p-cathode layer 9 and exhibit a maximum concentration more than twice that of the p-cathode layer 9. Impurities from the p-cathode layer 9 are contained within the n-layer 10 and the n-cathode layer 8. With this configuration, after all p-cathode layers 9 have been formed, the n-layer 10 and the n-cathode layer 8 can be formed by partially abrading them. It is therefore possible to simplify the process and eliminate potential influences of deviations from the pattern on the electrical characteristics. Design 16

[0048] Fig. Figure 30 is a cross-sectional view showing a semiconductor device according to embodiment 16 of the present invention. Fig. Figure 31 is a bottom view showing the semiconductor device according to embodiment 16 of the present invention. The n-layer 10 according to embodiments 1 to 10 is arranged in a plurality of rings in a top view. Fig. Figure 32 is a bottom view, which shows a modification of the semiconductor device according to embodiment 16 of the present invention. The n-layer 10 of embodiments 1 to 10 is arranged in a dot pattern in a top view. Alternatively, the p - Layer 13 of embodiments 11 to 15 can also be arranged in a ring or dot configuration when viewed from above. Effects similar to those of embodiments 1 to 15 can also be obtained in this case.

[0049] It should be noted that semiconductor devices of the embodiments described above are not limited to those made of silicon, but can be made of a wide-bandgap semiconductor with a bandgap wider than silicon. Examples of wide-bandgap semiconductors include silicon carbide, gallium nitride-based material, or diamond. A semiconductor device made of such a wide-bandgap semiconductor exhibits high withstand voltage and high allowable current density and can therefore be miniaturized. The use of this miniaturized semiconductor device allows a semiconductor module in which this semiconductor device is incorporated to also be miniaturized.Furthermore, since the semiconductor device has a high thermal resistance, it is possible to reduce the size of the cooling fins of its heat sink, to use an air cooling system instead of a water cooling system, and to further reduce the size of the semiconductor module. In addition, the device exhibits low power loss and high efficiency, making it possible to provide a more efficient semiconductor module.

[0050] Low and medium voltage ratings of 1200 V and 1700 V were described as examples in the embodiments described above, but the effects described above can be achieved by a semiconductor device using a parasitic bipolar transistor structure such as an IGBT or an RC-IGBT, regardless of the voltage rating. Furthermore, a case has been described where the termination structure is an FLR, but similar effects can be achieved with a VLD (variable side doping) or a RESURF (reduced surface field) structure, without being limited to this. Reference symbol list 1 n - -Drift layer; 2 p-anode layer; 7 n buffer layer; 8 n-cathode layer; 9 p-cathode layer; 10 n layer, 12a, 12b, 13p - -Layer

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