INTEGRATED CIRCUIT STRUCTURES WITH EXTENDED CONDUCTION PATHWAYS AND MANUFACTURING METHOD

Abstract

Package (200) comprising: a package substrate (140) with a top side above a bottom side; a first chip (102) with a device side opposite a rear side, wherein the device side contains a circuit in or on a substrate, the substrate comprising silicon, the circuit being located between the substrate and the top of the package substrate; an electrically insulating layer (110), wherein the electrically insulating layer is in lateral contact with the first chip and the electrically insulating layer is on and in contact with the back of the first chip; conductive paths (112) extending from the circuit of the device side of the first chip through the substrate of the first chip and through the electrically insulating layer, wherein the conductive paths are in electrical contact with the circuit; a connecting layer (116) on the electrically insulating layer and on the conductive paths, wherein the connecting layer is in electrical contact with the conductive paths; and a second chip (126) on and in electrical contact with the interconnect layer, wherein the second chip is connected to the interconnect layer by surface-activated bonding.

Description

background

[0001] As electronic devices become smaller, reducing their footprint becomes important. One approach to reducing device footprints involves stacking multiple electronic assemblies in a module-on-module configuration. Documents US 2016 / 0049383A1 and US 2016 / 0049385A1 describe well-known semiconductor devices. Brief description of the drawing

[0002] The following detailed description, in conjunction with the accompanying drawing, will make the embodiments easy to understand. To facilitate this description, identical reference numbers denote identical structural elements. The embodiments are shown in the figures of the accompanying drawing as examples and are not exhaustive. They show: Fig. 1. A side sectional view of a double-sided integrated circuit (IC) structure according to various embodiments, Fig. 2 a side sectional view of a stacked IC structure including the double-sided IC structure made of Fig. 1 in a double-sided assembly according to various embodiments, Fig. 3. An example top view of the double-sided assembly made of Fig. 2 according to different embodiments, the Fig. 4 to 6 lateral sectional views of other stacked IC structures, which are similar to the double-sided IC structure. Fig. 1 in a double-sided assembly, according to various embodiments, the Fig. 7 - 20 sectional views of different stages in an example process for manufacturing the stacked IC structure from Fig. 2 according to different embodiments, Fig. 21 a flowchart of a process for manufacturing an IC arrangement according to different embodiments, the Fig. 22A and Fig. 22B Top views of a wafer and of dies that can be used with any of the embodiments of the double-sided IC structures disclosed herein, Fig. 23 a lateral sectional view of an IC device that can be used with any of the embodiments of the double-sided IC structures disclosed herein, Fig. 24 a lateral sectional view of an IC device arrangement which may include any of the embodiments of the double-sided IC structures disclosed herein, and Fig. 25 a block diagram of an example computing device which may have any of the embodiments of the double-sided IC structures disclosed herein. Detailed description

[0003] Integrated circuit (IC) structures with extended conduction paths, as well as related structures, devices, and methods, are disclosed herein. For example, according to some embodiments, an IC structure may comprise a die with a device side and an opposite back side, a mold compound located on the back side, and a conduction path extending from the back side into the die and from the back side into the mold compound.

[0004] Conventional assembly-on-assembly architectures were limited in the flexibility with which top-side interconnects could be placed. For example, some conventional assembly-on-assembly arrangements feature a bottom die "sandwich" between an upper and a lower assembly substrate, with the lower die electrically coupled to the lower assembly substrate and solder balls on the top surface of the lower assembly substrate electrically coupling the lower assembly substrate to the upper assembly substrate. An upper die can be placed on top of the upper assembly substrate. In these structures, solder pads are made on the top surface of the lower assembly substrate at the "sides" of the lower die, but interconnects between the lower die and the upper die cannot be placed directly above the lower die.Because the lower assembly substrate and the upper assembly substrate are additionally separated by the lower die, only large intermediate connections can be used to couple the upper and lower assembly substrates (for example, large solder balls), so that other intermediate connection technologies (such as micro contact bumps or surface-activated bonding) cannot be used.

[0005] In another conventional arrangement, a middle die can be placed between an upper die and a lower die without any intervening assembly substrates. The middle die can have through-silicon vias exposed on its back and top surfaces. The stack of three dies can be arranged on an assembly substrate. Signals and current can be routed between the upper and lower dies through the middle die, but no intermediate connections can be formed on the "sides" of the die stack (for example, from the area of ​​the assembly substrate outside the bearing area of ​​the first die). Additionally, this arrangement typically requires the use of micro-contact bumps or surface-activated bonding to couple adjacent dies in the stack, thus precluding the use of more conventional solder ball technology.

[0006] Several of the embodiments disclosed herein can provide extended conduction paths (for example, extended through-silicon vias) in combination with conductive contacts and traces on a molded compound to achieve customizable top-side assembly interconnects. In particular, some of the embodiments disclosed herein provide a molded semiconductor assembly with external interconnects (for example, contacts) that can be positioned anywhere on the top side of the molded compound. One or more additional assemblies can be stacked on the exposed interconnects to form an assembly-on-assembly setup, or one or more additional assemblies can be coupled to the exposed interconnects using surface-activated bonding.Accordingly, various embodiments disclosed herein can provide an assembly whose entire top surface can be used for the arrangement of conductor tracks and contacts, thus increasing the total number of contacts or external interconnects that can be arranged on an assembly compared to conventional approaches. Furthermore, the size, shape, spacing, and arrangement of the contacts and conductor tracks on the top surface of the assembly can be specifically configured to match the location, size, shape, impedance, and pitch of the die or other electronic component stacked on the assembly, thereby providing a design flexibility unattainable with conventional approaches.

[0007] This document also discloses a number of methods for fabricating double-sided assemblies. For example, during wafer processing and treatment, according to some embodiments, a through-silicon via (TSV) formed on the back side of a silicon die can be extended beyond the exposed back side of the silicon wafer. After die fixation, the assembly can be formed such that the mold compound covers the exposed “extended TSV.” The mold compound can then be thinned to form a flat surface with the exposed extended TSV on the mold compound, and lithography can be performed on the thinned mold compound to form metal conductor tracks and metal contact points that are electrically coupled to the exposed extended TSV on the mold compound.An external module can then be connected, for example, to the formed metal contact points in a module-on-module or stacked die-multi-chip assembly. The result is a set of electrically connected extended TSVs on the back side of a silicon die, thereby providing a set of custom-configurable metal traces and external metal contact points on the top side of a molded assembly.

[0008] The following detailed description refers to the accompanying drawing, which forms part of the present document. Reference numerals throughout denote identical parts, and the drawing illustrates embodiments that may be implemented. It is understood that other embodiments may be used and that structural or logical modifications may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be interpreted restrictively.

[0009] Various operations can, in turn, be described as several discrete actions or operations in a manner that is most useful for understanding the claimed subject matter. However, the order of description should not be interpreted in such a way as to imply that these operations necessarily depend on the sequence. In particular, these operations cannot be performed in the order presented. Described operations can be performed in a different order than that of the described embodiment. Various additional operations can be performed, and / or described operations can be omitted in additional embodiments.

[0010] For the purposes of this disclosure, the expression “A and / or B” means (A), (B) or (A and B). For the purposes of this disclosure, the expression “A, B and / or C” means (A), (B), (C), (A and B), (A and C), (B and C) or (A, B and C).

[0011] The description uses the expressions "according to an embodiment" or "according to embodiments," which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "featuring," "with," and the like, which are used in relation to embodiments of the present disclosure, are synonymous. Here, a double-sided IC structure may denote an IC structure that has intermediate connections on at least two opposite sides.

[0012] Fig. Figure 1 is a side sectional view of a double-sided integrated circuit (IC) structure 100 (here also referred to as "structure 100") according to various embodiments. The structure 100 can have a die 102 with a device side 104 and a opposite back side 106. As is known in the field, a circuit arrangement 108 (including, for example, a transistor and other active devices, passive devices, and metallization layers) can be arranged on the device side 104 of the die 102. The circuit arrangement 108 can be formed in and / or on an IC substrate 130. According to some embodiments, the IC substrate 130 can be a semiconductor substrate in the form of a section of a silicon wafer, but any suitable IC substrate 130 can also be used.A molding compound 110 can be arranged on the back side 106 of the die 102, and at least one conduit path 112 can extend from the back side 106 into the die 102 and from the back side 106 into the molding compound 110. Several such conduit paths 112 are shown in . Fig. 1 shown.

[0013] The conductor paths 112 can extend to the circuit arrangement 108 and be in electrical contact with one or more elements in the circuit arrangement 108 (for example, in electrical contact with a device or intermediate connection, as described below with reference to Fig. 23). The mold compound 110 can have a surface 114 spaced apart from the rear side 106 of the die 102, and the conduction paths 112 can extend to the surface 114 such that the conduction paths 112 are at least partially exposed on the surface 114. Accordingly, the structure 100 can provide intermediate connection opportunities on the surface 114 (via the exposed conduction paths 112) and on the device side 104 of the die 102 (for example, via exposed contact points, as is known in the field and described below with reference to Fig. 23 is discussed).

[0014] The thickness 111 of the mold compound 110 on the back 106 of the die 102 can assume any suitable value. The thickness 111 can depend on the coefficient of thermal expansion (CTE) of the mold compound 110, whereby a lower CTE can allow a smaller thickness 111 without risking thermal mismatch or cracking between the conduit paths 112 and an assembly interlinking layer 116 on the surface 114 (see, for example, Figure 1). Fig. 2), while a higher CTE may make a greater thickness 111 more desirable (for example, to provide more material to absorb heat and minimize thermal failure). For example, according to some embodiments, the thickness 111 may be greater than or equal to the thickness 103 of die 102. According to other embodiments, the thickness 111 may be less than the thickness 103 of die 102. According to some embodiments, the thickness 111 may be 0.2 millimeters or more (for example, 0.3–0.5 millimeters).

[0015] The molding compound 110 can consist of any suitable material such as a polymer compound, a poly-resin molding compound, an elastomer molding compound, or any other suitable material. Other examples of molding compounds that may be included in the molding compound 110 are plastic materials, thermosetting polymers, silicon composites, glass, epoxy resins, or glass fiber epoxy resins. The molding compound 110 may also include a filler material. For example, the molding compound 110 may include an epoxy resin with very small grains (for example, on the order of one micrometer) of fused silica or amorphous silicon dioxide. According to some embodiments, the molding compound 110 may be a flexible material (for example, to enable certain applications of portable devices).According to some embodiments, the molding compound 110 can be a thermally conductive (but electrically insulating) material, which can allow the molding compound 110 to act as a heat distributor and distribute the heat generated by the 102 to other areas of the structure 100 (or a larger assembly or arrangement containing the structure 100).

[0016] The conductor paths 112 can consist of one or more conductive materials such as metal (for example, copper). Although the in Fig. Since the conduit paths 112 shown in Figure 1 have substantially parallel side walls, the conduit paths 112 can have any profile (for example, as prescribed by the manufacturing processes used to form the conduit paths 112). For example, the first section 112a and / or the second section 112b can be tapered. According to some embodiments, the width (for example, the diameter) of the first section 112a can differ from the width of the second section 112b. For example, the second section 112b can be wider than the first section 112a (for example, have a larger diameter) to provide the second section 112b with additional mechanical robustness to protect the second section 112b during photoresist removal and / or forming, as shown below with reference to the Fig. 16 and Fig. 17 is discussed. Although they are “enlarged” in relation to the first sections 112a, adjacent second sections 112b can remain electrically isolated from each other.

[0017] Fig. Figure 2 is a side sectional view of a stacked IC structure 200 including the double-sided IC structure 100 made of Fig. 1 in a double-sided assembly 202 according to various embodiments. In particular, in the double-sided assembly 202, the device side 104 of the die 102 can be coupled to an assembly substrate 140 via first-level interconnects (FLI) 136. The assembly substrate 140 can have electrical conduction paths (not shown) for conducting signals or current between the FLI 136 and the second-level interconnects (SLI) 142, as is known in the field. The mold compound 110 can extend around the sides of the die 102, as in Fig. 2 is shown, and according to some embodiments the area between the die 102 and the assembly substrate 140 can be filled with an underfill 138.

[0018] The double-sided assembly 202 can have an assembly interconnect layer 116 (in electrical contact with the conductor paths 112) located on the surface 114 of the molded compound 110. The assembly interconnect layer 116 can provide contact points for electrical connections with an electronic component 124 located on the assembly interconnect layer 116 (discussed below) and can also include conductor path features for redistributing electrical signals within the assembly interconnect layer 116. According to some embodiments, signals and / or current can be routed from the SLI 142 via the FLI 136 and the conductor paths 112 to the assembly interconnect layer 116. In this way, signals and / or current can be transmitted between a printed circuit board on which the double-sided assembly 202 is mounted (not shown) and the assembly interconnect layer 116.According to some embodiments, signals and / or current can be routed from the device side 104 of the die 102 via the conductor paths 112 to the assembly interconnect layer 116. In this way, signals and / or current can be transmitted between the die 102 and the assembly interconnect layer 116. The double-sided assembly 202 can accordingly provide connections to the SLI 142 of the assembly substrate 140 as well as to the assembly interconnect layer 116 on the other side of the double-sided assembly 202.

[0019] As mentioned above, the assembly interconnect layer 116 can have contact points to form electrical connections with an electronic component 124 arranged on the assembly interconnect layer 116, and electrical conduction paths for conducting signals within the assembly interconnect layer 116. Fig. Figure 3 is an example top view of the double-sided assembly made of Fig. 2, wherein the assembly interconnect layer 116 is shown according to various embodiments. The assembly interconnect layer 116 can have contact points 120 for establishing electrical contact with the electronic component 124 and conductor tracks 122 for conducting signals in the assembly interconnect layer 116. According to some embodiments, one or more contact points 120 of the assembly interconnect layer 116 can be located within the contact surface 118 of the die 102 and / or outside the contact surface 118 of the die 102. For example, the embodiment shown Fig. 3 contact points 120 inside the support area 118 and outside the support area 118.

[0020] The stacked IC structure 200 can also include an electronic component 124 arranged on the assembly interconnect layer 116 and in conductive contact with one or more contact points 120 of the assembly interconnect layer 116. According to the Fig. In the embodiment shown in Figure 2, the electronic component 124 has a die 126 which is coupled to an assembly substrate 128 via the FLI 132 (where the FLI 132 are enclosed by an underfill 133). The SLI 134 couple the assembly substrate 128 to the contact points 120 of the assembly interconnect layer 116. According to some embodiments, signals and / or current can be conducted from the SLI 142 to the electronic component 124 via the conductor paths 112 and the assembly interconnect layer 116. In this way, signals and / or current can be transmitted between a printed circuit board on which the double-sided assembly 202 is arranged (not shown) and the electronic component 124. According to some embodiments, signals and / or current can be routed from the device side 104 of the die 102 via the conductor paths 112 and the assembly intermediate layer 116 to the electronic component 124.In this way, signals and / or current can be transmitted between the die 102 and the electronic component 124. According to some embodiments, a single electronic component 124 can be in contact with contact points 120 both inside and outside the support surface 118, while according to other embodiments, a single electronic component 124 can be in contact with contact points 120 both inside (and not outside) the support surface 118, or vice versa.

[0021] The electronic component 124 can take any suitable form, such as a die incorporated into an assembly, a display, a sensor, a storage device, another input or output device, another processing or storage device, or a combination of these devices. For example, the electronic component 124 can be a portable display that can be coupled to the assembly interconnect layer 116, for example, by surface-activated bonding. According to some embodiments, the electronic component 124 itself can have a double-sided IC structure 100 (for example, contained in a double-sided assembly 202) and have additional electronic components 124 (not shown) stacked on it. The electronic component 124 can be coupled to the assembly interconnect layer 116 using a suitable mechanism. For example, [Figure 1] shows Fig. 2. The use of solder balls or contact prongs as SLI 134. The pitch of the SLI 134 can be 30 micrometers or larger (for example, 50 micrometers) according to some embodiments, thereby enabling the use of intermediate connections that are larger than are conventionally achievable. According to the embodiment from Fig. 4 The electronic component 124 can have a die 126 which is coupled to the assembly interlink layer 116 by surface-activated bonding.

[0022] According to some embodiments, the power and ground contact points of the double-sided assembly 202 can be positioned to correspond to the locations of the power and ground contact points of the electronic component 124. Such an arrangement may not be achievable by conventional approaches, where the arrangement of conductive contact points may be limited to areas outside the bearing surface 118 of the die 102. As mentioned above, the spacing, size, and shape of the respective contact points 120 can be adjusted based on the solder ball pitch requirements of the electronic component 124. For example, the contact points 120 can support a sufficiently large solder ball pitch to allow a pre-assembled memory assembly module to be used as the electronic component 124.Such an arrangement cannot be achieved using conventional approaches that are limited to the use of micro-contact bumps to connect upper and lower dies.

[0023] According to some embodiments, the electronic component 124 can be or include a radio chip. According to these embodiments, the size, conductor tracks 122, arrangement, and spacing of the contact points 120 can be designed to match the impedance of the radio chip in order to achieve improved functionality compared to a conventional approach where the layout of the contact points 120 and the conductor tracks 122 is not as flexible.

[0024] According to some embodiments, several electronic components can be coupled to the assembly interconnect layer 116. For example, shows Fig. 5 An embodiment in which two electronic components 124-1 and 124-2 are coupled to the assembly interconnect layer 116. Each electronic component 124 consists of Fig. 5 features a die 126 which is coupled to an assembly substrate 128 via the FLI 132 (optionally surrounded by the underfill 133) and the SLI 134. As in Fig. As shown in Figure 5, the division of the SLI 134-1 of the electronic component 124-1 can differ from the division of the SLI 134-2 of the electronic component 124-2 (in particular, the division of the SLI 134-2 in Fig. 5 smaller than the pitch of the SLI 134-1). The ability of the assembly interlink layer 116 to be structured with contact points 120 and conductor tracks 122 in any desired arrangement makes it possible to stack the double-sided assembly 202 with multiple electronic components 124 with different pitches, thereby achieving considerable design flexibility not provided by conventional approaches.

[0025] As mentioned above, according to some embodiments, an electronic component 124 stacked on a double-sided assembly 202 can have a double-sided IC structure 100 and thus support the stacking of additional electronic components 124 using the mechanisms described above. According to other embodiments, several electronic components 124 can be stacked on the double-sided assembly 202, and these multiple electronic components 124 can be coupled to each other and to the double-sided assembly 202 using other assembly-on-assembly techniques. For example, electronic components 124-1 and 124-2 can be made of Fig. 6 can be coupled using any of the conventional approaches discussed above.

[0026] The Fig. Figures 7-20 show sectional views of various stages in an example process for manufacturing the stacked IC structure 200. Fig. 2 according to different embodiments. Fig. Figures 7-13 can represent the parallel fabrication of multiple arrangements on a single IC substrate, which during fabrication (as below with reference to Fig. 14 discussed) before subsequent work processes are separated. Although below with reference to the Fig. 7-20 certain techniques are discussed; any suitable methods for manufacturing embodiments of the double-sided IC structure 100, the double-sided assembly 202, or the stacked IC structure 200 can be used. Additionally, the following may be used with reference to the Fig. The techniques described in sections 7-20 can be applied analogously to the fabrication of other stacked IC structures 200 disclosed herein (for example, the stacked IC structures 200 from the Fig. 4 - 6).

[0027] Fig. Figure 7 shows an IC substrate 700 with a front side 704 and a back side 702. The IC substrate 700 can take the form of any of the IC substrates discussed above with reference to the IC substrate 130. For example, according to some embodiments, the IC substrate 700 can be a semiconductor substrate in the form of a silicon wafer or a wafer made of another semiconductor material.

[0028] Fig. Figure 8 shows an arrangement 800 after the formation of conduction paths 802 between the back side 702 and the front side 704 of the IC substrate 700. According to some embodiments, these conduction paths 802 can be formed by drilling (for example, laser drilling) through the IC substrate 700 to create openings that can then be filled with a conductive material (for example, copper). According to embodiments in which the IC substrate 700 is made of silicon, the conduction paths 802 can be through-silicon vias (TSVs) and can be formed using any suitable TSV formation techniques. The conduction paths 802 can be in the shape of any of the first sections 112a of the conduction paths 112 discussed above. The arrangement 800 can have a thickness 804 corresponding to the thickness of the IC substrate 700.

[0029] Fig. Figure 9 shows an arrangement 900 after the formation of the circuit arrangement 108 on the front face 704 of the IC substrate 700 of the arrangement 800. The circuit arrangement 108 can include active devices, passive devices, metallization layers, and any other components known in the field and described above with reference to Fig. 1 and below with reference to Fig. The circuit arrangement 108 may be in conductive contact with one or more of the conductor paths 802, as discussed in Section 23. According to some embodiments, active and / or passive devices of the circuit arrangement 108 may be in contact with one or more of the conductor paths 802. According to some embodiments, the conductor paths 802 may be in contact with electrical routing conductor paths in the circuit arrangement 108 to route signals from the front 704 to the rear 702 without contacting any active or passive devices in the circuit arrangement 108.

[0030] Fig. Figure 10 shows an arrangement 1000 after thinning the IC substrate 700 of the arrangement 900 to a thickness 1002 that is less than the thickness 804. The thinning processes can include chemical and / or mechanical polishing (for example, chemical-mechanical polishing (CMP)) to form a new back side 106 of the IC substrate 700. The thickness 1002 can be any suitable value (for example, 200 to 400 micrometers in some applications). The arrangement 1000 can be performed as described above with reference to Fig. 1 discussed The 102 provide. In particular, the resulting diluted IC substrate 700 can be used in the above with reference to Fig. 1. Provide the discussed IC substrate 130 and the resulting thinned conduction paths 802 can be used as described above with reference to Fig. 1. Provide the first section 112a of the pipeline routes discussed.

[0031] Fig. Figure 11 shows an arrangement 1100 after the provision and structuring of a photoresist 1102 on the back side 106 of the IC substrate 130. The photoresist 1102 can be structured with openings 1104 aligned with the first sections 112a. As discussed above, according to some embodiments, the openings 1104 can have a width (for example, a diameter) that differs from a corresponding width of the first sections 112a. For example, the width of the openings 1104 can be greater than the width of the first sections 112a. This can lead to conduction paths 112 with second sections 112b that are correspondingly wider than the first sections 112a, according to the operations discussed below.

[0032] Fig. Figure 12 shows an arrangement 1200 after the provision of a conductive material 1202 on the arrangement 1100. The conductive material 1202 may include a conductive material 1204 that fills the openings 1104 and excess material 1206 that extends over the openings 1104 in the photoresist 1102.

[0033] Fig. Figure 13 shows an arrangement 1300 after thinning the arrangement 1200 to remove the excess material 1206. Thinning processes may include chemical and / or mechanical polishing (for example, CMP). According to some embodiments, during the removal of the excess material 1206, part of a photoresist 1102 (and part of the conductive material 1202 filling the openings 1104) may also be removed.

[0034] Fig. Figure 14 shows an arrangement 1400 after the separation of various arrangements 1300 from one another (for example, using a diamond saw blade). As mentioned above, the work processes can be derived from the Fig. 7 - 13 are essentially carried out in parallel to produce several of the corresponding arrangements on a single IC substrate 700, these arrangements being as shown in Fig. The elements of the arrangement 1400 can be separated from one another before subsequent work processes are started. According to some embodiments, testing of the elements of the arrangement 1400 (for example, functional tests, continuity tests, mechanical tests, etc.) can be carried out after singulation, and / or the testing can be carried out before singulation.

[0035] Fig. Figure 15 shows an arrangement 1500 after the encapsulation of the arrangement 1400 by mounting the arrangement 1400 on the assembly substrate 140 via the FLI 136. The arrangement 1500 can have an underfill 138 and SLI 142, as described above with reference to Fig. 2 was discussed. According to the embodiment from Fig. 15. During encapsulation, the photoresist 1102 can still surround the sections of the conductive material 1204 extending from the die 102. The photoresist 1102 can provide mechanical protection to the conductive material 1204 during the handling required for encapsulation and can therefore advantageously be held in place until it needs to be removed.

[0036] Fig. Figure 16 shows an arrangement 1600 after the removal of the photoresist 1102 from the arrangement 1500 to expose the conductive material 1204 extending from the IC substrate 130. A conventional chemical process can be used to remove the photoresist 1102; however, the specific removal parameters can be adjusted so that the removal is gentle enough not to affect the conductive material 1204.

[0037] Fig. Figure 17 shows an arrangement 1700 after the provision of a molding compound 1702 on the assembly substrate 140 and around the die 102, the underfill 138 and the conductive material 1204. Although in Fig. Figure 17 shows that the molding compound 1702 leaves the ends of the conductive material 1204 exposed. According to some embodiments, the conductive material 1204 can be molded over with the molding compound 1702 so that the conductive material 1204 is completely covered. The molding compound 1702 can have a thickness 1704 measured from the surface of the assembly substrate 140.

[0038] Fig. Figure 18 shows an arrangement 1800 after thinning the molding compound 1702 (and the conductive material 1204) of the arrangement 1700 to a thickness 1802 that is less than the thickness 1704. Thinning processes may include chemical and / or mechanical polishing (for example, CMP). The resulting thinned molding compound 1702 may be the one described above with reference to Fig. 1 provide the discussed mold mixture 110 (for example, with a surface 114), and the resulting thinned conductive material 1204 can perform the above with reference to Fig. 1. Provide the second section 112b of the pipeline routes discussed in section 112.

[0039] Fig. Figure 19 shows an arrangement 1900 after the provision of the assembly interlinking layer 116 on the surface 114 of the mold mixture 110. According to some embodiments, the assembly interlinking layer 116 can be formed using a photolithography process similar to that used on printed circuit boards.For example, the mold compound 110 can be coated with a passivation layer (for example, made of a dielectric material), a photoresist layer can be applied to the passivation layer, the photoresist layer can be exposed and developed to create the desired pattern, the passivation layer can be structured based on the structured photoresist, the photoresist layer can be removed (leaving the structured passivation layer), the passivation layer can be coated with a copper layer or a layer of another conductive material, and the assembly interconnect layer 116 can be finished by grinding off the copper or other conductive material down to the level of the passivation layer.As discussed above, contact points 120 and / or conductor tracks 122 can be in electrical contact with one or more of the conductor paths 112.

[0040] Fig. Figure 20 shows the stacked IC structure 200 formed by attaching an electronic component 124 to the assembly interconnect layer 116 of the arrangement 1900. As above with reference to Fig. As discussed in Section 2, the electronic component 124 can be attached to the assembly interconnect layer 116 using any suitable mechanism (for example, solder bonds, solder balls, or surface-activated bonding). Subsequent processing operations (not shown) may include attaching additional electronic components 124 to the assembly interconnect layer 116, attaching additional electronic components 124 “on” the electronic component 124, or any of the other embodiments discussed herein.

[0041] Fig. 21 is a flowchart of a process 2100 for manufacturing an IC assembly according to various embodiments. Although the following refers to Fig. Although the processes discussed below are described as being carried out in a specific order and each performed only once, these processes can also be carried out several times (for example, in parallel or sequentially) or in a different order, as appropriate. However, the following with reference to Fig. In addition to the processes discussed in Section 21 with reference to various embodiments disclosed herein, Method 2100 can also be used to manufacture any suitable IC arrangement.

[0042] At 2102, a conductive via can be formed in the back side of an IC substrate. The back side of the IC substrate can be located opposite a device side of the IC substrate. For example, the first section 112a of a conductor path 112 can be formed in the back side 106 of the IC substrate 130.

[0043] At 2104, a conductive extension of the conductive via of 2102 can be formed on the back side of the IC substrate. The conductive extension can be in contact with the conductive via. For example, the second section 112b of a conduction path 112 can be made in contact with the first section 112a on the back side 106 of the IC substrate 130.

[0044] For 2106, a molded mixture can be provided around the conductive extension 2104. For example, the molded mixture 110 can be provided around the second section 112b.

[0045] At 2108, a conductive contact can be formed on a surface of the molding compound. The conductive contact can be electrically coupled to the conductive extension. For example, a contact point 120 can be formed on the surface 114 of the molding compound 110 and be in electrical contact with the second section 112b of the conducting path 112.

[0046] The double-sided IC structures 100 disclosed here can be incorporated into any suitable electronic device. Fig. Figures 22-25 show various examples of devices that can be incorporated into or include one or more of the double-sided IC structures 100 disclosed herein.

[0047] The Fig. Figures 22A-B are top views of a wafer 2200 and of dies 2202, which can assume the form of any of the embodiments of the double-sided IC structures 100 disclosed herein. The wafer 2200 can consist of a semiconductor material and have one or more dies 2202 with IC elements formed on a surface of the wafer 2200. Each of the dies 2202 can be a repeating unit of a semiconductor product comprising any suitable IC. After completion of the fabrication of the semiconductor product, the wafer 2200 can be subjected to a singulation process (for example, as above with reference to Fig. (14 discussed), whereby the respective 2202 dies are separated from each other to provide discrete “chips” of the semiconductor product. The 2202 die can contain one or more transistors (for example, some of the 2340 transistors from Fig. 23, as discussed below) and / or a supporting circuit arrangement for routing electrical signals to the transistors and other IC components. The 2202 may have one or more first sections 112a of conduction paths 112, as described above with reference to the Fig. 7-14 discussed, so that the die 2202 can be part of a double-sided IC structure 100. According to some embodiments, the wafer 2200 or the die 2202 can include a storage device (for example, a static random-access memory (SRAM) device), a logic device (for example, an AND, OR, NAND, or NOR gate), or another suitable circuit element. Several of these devices can be combined on a single die 2202. For example, a memory array formed by several storage devices can be placed on the same die 2202 as a processing device (for example, the processing device 2502 from Fig. 25) or other logic designed to store information in the storage devices or to execute instructions stored in the memory field.

[0048] Fig. Figure 23 is a side sectional view of an IC device 2300, which can be used with any of the embodiments of the double-sided IC structures 100 disclosed herein. In particular, one or more of the IC devices 2300 can be incorporated into one or more dies 102. The IC device 2300 can be mounted on a substrate 2302 (for example, the wafer 2200 made of Fig. 22A) are formed and placed into a die (for example, the die 2202 from Fig. 22B). According to some embodiments, the substrate 2302 can provide the IC substrate 130. The substrate 2302 can be a semiconductor substrate consisting of semiconductor material systems, including, for example, N-type or P-type material systems. The substrate 2302 can, for example, comprise a crystalline substrate formed using a bulk silicon or silicon-on-insulator substructure. According to some embodiments, the substrate 2302 can be formed using alternative materials that may be combined with silicon, including, but not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as Group II-VI, III-V, or IV can also be used to form the substrate 2302.Although some examples of materials from which the substrate 2302 can be made are described here, any material that can serve as the basis for an IC device 2300 can be used. The substrate 2302 can be part of a discrete die (for example, the die 2202 from ). Fig. 22B) or a wafer (for example, wafer 2200 from Fig. 22A).

[0049] The IC device 2300 can have one or more device layers 2304 arranged on the substrate 2302. The device layer 2304 can be incorporated into the circuit arrangement 108 on the device side 104 of the die 102 of the double-sided IC structures 100. The device layer 2304 can have features of one or more transistors 2340 (for example, metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed on the substrate 2302. The device layer 2304 can, for example, have one or more source and / or drain (S / D) regions 2320, a gate 2322 for controlling the current flow in the transistors 2340 between the S / D regions 2320, and one or more S / D contacts 2324 for conducting electrical signals to and from the S / D regions 2320. For clarity, the transistors 2340 may have additional features not shown, such as device isolation regions, gate contacts, and the like.The transistors 2340 are not limited to the type and configuration found in . Fig. Figure 23 illustrates these transistors, and they can exhibit a wide variety of other types and configurations, such as planar transistors, non-planar transistors, or a combination of both. Non-planar transistors can include FinFET transistors in the form of dual-gate or tri-gate transistors, and wraparound or all-around-gate transistors in the form of nanofilament and nanowire transistors.

[0050] Each 2340 transistor can have a 2322 gate consisting of at least two layers: a gate dielectric layer and a gate electrode layer. The gate dielectric layer can comprise a single layer or a stack of layers. The single or multiple layers can comprise silicon oxide, silicon dioxide, and / or a material with a high dielectric constant. The material with a high dielectric constant can comprise elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc.Examples of materials with a high dielectric constant that can be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc cniobate. According to some embodiments, a tempering process can be performed on the gate dielectric layer to improve its quality when a material with a high dielectric constant is used.

[0051] The gate electrode layer can be formed on the gate dielectric layer and may include at least one p-type or n-type working metal, depending on whether the 2340 transistor is a PMOS or an NMOS transistor. According to some implementations, the gate electrode layer may consist of a stack of two or more metal layers, one or more of which are working metal layers and at least one of which is a filler metal layer. Additional metal layers may be included for other purposes, such as a depletion layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (for example, ruthenium oxide).For an NMOS transistor, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals and carbides of these metals (for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide and aluminum carbide).

[0052] According to some embodiments, when viewed as a cross-sectional view of transistor 2340 along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure having a lower section that is substantially parallel to the surface of the substrate and two sidewall sections that are substantially perpendicular to the upper surface of the substrate. According to other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer that is substantially parallel to the upper surface of the substrate and has no sidewall sections that are substantially perpendicular to the upper surface of the substrate. According to still other embodiments, the gate electrode may consist of a combination of U-shaped structures and planar non-U-shaped structures.For example, the gate electrode can consist of one or more U-shaped metal layers formed on one or more planar non-U-shaped layers.

[0053] According to some embodiments, a pair of sidewall spacers can be formed on opposite sides of the gate stack to enclose the gate stack. The sidewall spacers can be formed from a material such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are well known in the field and generally involve deposition and etching processes. According to some embodiments, multiple pairs of spacers can be used, for example, two pairs, three pairs, or four pairs of sidewall spacers formed on opposite sides of the gate stack.

[0054] The S / D regions 2320 can be formed within the substrate 2302 adjacent to the gate 2322 of each transistor 2340. The S / D regions 2320 can be formed, for example, using an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic can be ion-implanted into the substrate 2302 to form the S / D regions 2320. An annealing process, which activates the dopants and causes them to diffuse further into the substrate 2302, can follow the ion implantation process. In the latter process, the substrate 2302 can first be etched to form recesses at the locations of the S / D regions 2320. An epitaxial deposition process can then be performed to fill the recesses with material used to create the S / D areas 2320.According to some implementations, the S / D regions 2320 can be fabricated using a silicon alloy such as silicon germanium or silicon carbide. According to some embodiments, the epitaxially deposited silicon alloy can be doped in situ with boron, arsenic, or phosphorus. According to some embodiments, the S / D regions 2320 can be formed using one or more alternative semiconductor materials such as germanium or a Group III-V material or a corresponding alloy. According to further embodiments, one or more layers of metal and / or metal alloys can be used to form the S / D regions 2320.

[0055] Electrical signals of the type of current and / or input / output (I / O) signals can be transmitted through one or more interconnect layers arranged on the device layer 2304 (in Fig. 23 (shown as interconnection layers 2306-2310) to and / or from the transistors 2340 of the device layer 2304. For example, electrically conductive features of the device layer 2304 (e.g., the gate 2322 and the S / D contacts 2324) can be electrically connected to the interconnection structures 2328 of the interconnection layers 2306-2310. One or more interconnection layers 2306-2310 can form an interlayer dielectric (ILD) stack 2319 of the IC device 2300. The conduction paths 112 of the double-sided IC structure 100 can extend to and electrically couple with one or more of the interconnection layers 2306-2310.The transmission paths 112 can carry signals to / from the devices in the device layer 2304, or they can carry signals through the interconnection layers 2306 - 2310 to / from other devices (for example, other electronic components in a stacked IC structure 200 or other components that share a printed circuit board with the IC device 2300).

[0056] The interconnection structures 2328 can be arranged within the interconnection layers 2306–2310 to conduct electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the one in Fig. 23 depicted specific configuration of connection structures 2328 limited). Although a specific number of connection layers 2306 - 2310 in Fig. As shown in Figure 23, embodiments of the present disclosure include IC devices with more or fewer interconnect layers than shown.

[0057] According to some embodiments, the interconnection structures 2328 can comprise trench structures 2328a (sometimes referred to as "conductors") and / or via structures 2328b (sometimes referred to as "holes") filled with an electrically conductive material of a metal type. The trench structures 2328a can be configured to conduct electrical signals in a plane that is substantially parallel to a surface of the substrate 2302 on which the device layer 2304 is formed. For example, the trench structures 2328a can conduct electrical signals in a direction toward the side from the perspective of Fig. 23 and conduct from it. The via structures 2328b can be configured to conduct electrical signals in the direction of a plane that is substantially perpendicular to the surface of the substrate 2302, on which the device layer 2304 is formed. According to some embodiments, the via structures 2328b can electrically couple trench structures 2328a of different interconnect layers 2306–2310 to each other.

[0058] The interconnection layers 2306 - 2310 can have a dielectric material 2326 arranged between the interconnection structures 2328, as shown in Fig. Figure 23 is shown. According to some embodiments, the dielectric material 2326, which is arranged in different of the connection layers 2306 - 2310 between the connection structures 2328, can have different compositions, and according to other embodiments, the composition of the dielectric material 2326 can be the same between different connection layers 2306 - 2310.

[0059] A first interconnect layer 2306 (designated as metal 1 or “M1”) can be formed directly on the device layer 2304. According to some embodiments, the first interconnect layer 2306 can have trench structures 2328a and / or via structures 2328b, as shown. The trench structures 2328a of the first interconnect layer 2306 can be coupled to contacts (for example, the S / D contacts 2324) of the device layer 2304.

[0060] A second interconnect layer 2308 (referred to as metal 2 or “M2”) can be formed directly on the first interconnect layer 2306. According to some embodiments, the second interconnect layer 2308 can have via-hole structures 2328b to couple the trench structures 2328a of the second interconnect layer 2308 to the trench structures 2328a of the first interconnect layer 2306. Although the trench structures 2328a and the via-hole structures 2328b are shown structurally with a line within each interconnect layer for clarity (for example, within the second interconnect layer 2308), according to some embodiments, the trench structures 2328a and the via-hole structures 2328b can be structurally and / or materially interlocked (for example, filled simultaneously during a dual-damascus process).

[0061] A third compound layer 2310 (designated as metal 3 or “M3”) (and additional compound layers, as desired) can be successively formed on the second compound layer 2308 using similar techniques and configurations as described in connection with the second compound layer 2308 or the first compound layer 2306.

[0062] The IC device 2300 can have a solder resist material 2334 (for example, polyimide or a similar material) and one or more bond contact points 2336 formed on the interconnection layers 2306–2310. The bond contact points 2336 can, for example, provide the contacts for coupling with the FLI 136. The bond contact points 2336 can be electrically coupled to the interconnection structures 2328 and configured to conduct the electrical signals from the one or more transistors 2340 to other external devices. For example, solder bonds can be formed on the one or more bond contact points 2336 to mechanically and / or electrically couple a chip having the IC device 2300 to another component (for example, a printed circuit board).The IC device 2300 may have alternative configurations for conducting electrical signals from the interconnect layers 2306-2310 than those shown in other embodiments. For example, the bond contact points 2336 may be replaced by other analog features (e.g., pillars) or may further include features that conduct electrical signals to external components.

[0063] Fig. Figure 24 is a side sectional view of an IC device assembly 2400, which may include any of the embodiments of the double-sided IC structures 100 disclosed herein. The IC device assembly 2400 has a number of components arranged on a printed circuit board 2402 (which may, for example, be a main board). The IC device assembly 2400 has components arranged on a first surface 2440 of the printed circuit board 2402 and on an opposite second surface 2442 of the printed circuit board 2402, and in general, components may be arranged on one or both surfaces 2440 and 2442.

[0064] According to some embodiments, the circuit board 2402 can be a printed circuit board (PCB) comprising several metal layers separated from one another by layers of a dielectric material and interconnected by electrically conductive vias. One or more of the metal layers can be formed in a desired circuit pattern to conduct electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 2402. According to other embodiments, the circuit board 2402 can be a non-PCB substrate.

[0065] The in Fig. The IC device arrangement 2400 shown in Figure 24 has an assembly-on-wiring-layer structure 2436 coupled to the first surface 2440 of the printed circuit board 2402 by coupling components 2416. The coupling components 2416 can electrically and mechanically couple the assembly-on-wiring-layer structure 2436 to the printed circuit board 2402 and solder balls (as in Figure 24) can be attached to the circuit board. Fig. 24), comprising male and female sections of a connector, an adhesive, a backing material and / or another suitable electrical and / or mechanical coupling structure.

[0066] The assembly-on-wiring-layer structure 2436 can include an electronic assembly 2420 coupled to a wiring layer 2404 by coupling components 2418. The coupling components 2418 can assume a form suitable for the application, such as those discussed above with reference to the coupling components 2416. Although in Fig. Figure 24 shows a single electronic assembly 2420; however, multiple electronic assemblies can be coupled to the wiring layer 2404, and additional wiring layers can indeed be coupled to the wiring layer 2404. The wiring layer 2404 can provide an intermediate substrate used to bridge the printed circuit board 2402 and the electronic assembly 2420. For example, the electronic assembly 2420 can be a die (the die 2202 made of Fig. 22B), an IC device (for example, the IC device 2300 from Fig. 23) or another suitable component. In general, the wiring layer 2404 can widen a connection to a larger pitch or redirect a connection to another connection. For example, the wiring layer 2404 can couple the electronic assembly 2420 (for example, a die) to a ball grid array (BGA) of coupling components 2416 for coupling to the printed circuit board 2402. According to the in Fig. In the embodiment shown in Figure 24, the electronic assembly 2420 and the printed circuit board 2402 are mounted on opposite sides of the wiring layer 2404, and in other embodiments, the electronic assembly 2420 and the printed circuit board 2402 can be mounted on the same side of the wiring layer 2404. In some embodiments, three or more components can be connected through the wiring layer 2404. In some embodiments, the electronic assembly 2420 can have a double-sided IC structure 100 (for example, the electronic assembly 2420 can take the form of a double-sided assembly 202). For example, an additional electronic component can be arranged on the electronic assembly 2420 to form a stacked IC structure 200.

[0067] The wiring layer 2404 can consist of an epoxy resin, a glass-fiber-reinforced epoxy resin, a ceramic material, or a polymer material of the polyimide type. According to some embodiments, the wiring layer 2404 can consist of alternating rigid or flexible materials, which may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other Group III-V and Group IV materials. The wiring layer 2404 can include metal interconnects 2408 and vias 2410, including, but not limited to, through-silicon vias (TSVs) 2406. The wiring layer 2404 can further include embedded devices 2414, including both passive and active devices.These devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and storage devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the wiring layer 2404. The assembly-on-wiring-layer structure 2436 may take the form of any assembly-on-wiring-layer structure known in the field.

[0068] The IC device arrangement 2400 can include an electronic assembly 2424 coupled to the first surface 2440 of the printed circuit board 2402 by coupling components 2422. The coupling components 2422 can take the form of any of the embodiments discussed above with reference to the coupling components 2416, and the electronic assembly 2424 can take the form of any of the embodiments discussed above with reference to the electronic assembly 2420. According to some embodiments, the electronic assembly 2424 can have a double-sided IC structure 100 (for example, the electronic assembly 2424 can take the form of a double-sided assembly 202). For example, an additional electronic component can be arranged on the electronic assembly 2424 to form a stacked IC structure 200.

[0069] The in Fig. The IC device arrangement 2400 shown in Figure 24 has a module-on-module structure 2434, which is coupled to the second surface 2442 of the printed circuit board 2402 by coupling components 2428. The module-on-module structure 2434 can include an electronic assembly 2426 and an electronic assembly 2432, which are coupled to each other by coupling components 2430, such that the electronic assembly 2426 is arranged between the printed circuit board 2402 and the electronic assembly 2432. The module-on-module structure 2434 can take the form of a stacked IC structure 200 (for example, the electronic assembly 2426 can be a double-sided assembly 202).The coupling components 2428 and 2430 can take the form of any of the embodiments of coupling components 2416 discussed above, and the electronic assemblies 2426 and 2432 can take the form of any of the embodiments of the electronic assembly 2420 discussed above.

[0070] Fig. Figure 25 is a block diagram of an exemplary computing device 2500, which may have one or more of the embodiments of the double-sided IC structures 100 disclosed herein. For example, a suitable component of the computing device 2500 may have or be incorporated a double-sided IC structure 100 (for example, of the type of die 102) or a stacked IC structure 200 (for example, of the type of electronic component 124) according to one of the embodiments disclosed herein. A number of components are shown in Fig. 25 are shown as being included in the computing device 2500; however, one or more of these components may be omitted or duplicated as is suitable for the application. According to some embodiments, some or all of the components included in the computing device 2500 may be mounted on one or more mainboards. According to some embodiments, some or all of these components are fabricated on a single system-on-a-chip (SoC) die.

[0071] In addition, the computing device 2500 can, according to various embodiments, include one or more of the functions described in Fig.The components shown in Figure 25 do not have the components themselves, but rather an interface circuit arrangement for coupling with one or more of the components. For example, the computing device 2500 may not have a display device 2506, but rather a display device interface circuit arrangement (for example, a connector and driver circuit arrangement) to which a display device 2506 can be coupled. In another example set, the computing device 2500 may not have an audio input device 2524 or an audio output device 2508, but rather an audio input or output device interface circuit arrangement (for example, a connector and support circuit arrangement) to which an audio input device 2524 or an audio output device 2508 can be coupled.

[0072] The computing device 2500 may include a processing device 2502 (for example, one or more processing devices). Here, the term "processing device" or "processor" may refer to a device or part of a device by which electronic data from registers and / or a memory is processed to transform that electronic data into other electronic data that can be stored in registers and / or a memory. The processing device 2502 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or other suitable processing devices.The computing device 2500 can include a memory 2504, which itself can comprise one or more storage devices of the type of volatile memory (for example, dynamic random-access memory (DRAM)), non-volatile memory (for example, read-only memory (ROM)), flash memory, semiconductor memory, and / or a hard disk. According to some embodiments, the memory 2504 can include a memory that shares a die with the processing device 2502. This memory can be used as a cache memory and may include embedded dynamic random-access memory (eDRAM) or magnetic spin transfer torque random-access memory (STT-MRAM).

[0073] According to some embodiments, the computing device 2500 may include a communication chip 2512 (for example, one or more communication chips). For example, the communication chip 2512 may be configured to handle wireless communications for the transmission of data to and from the computing device 2500. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can transmit data over a non-solid medium by using modulated electromagnetic radiation. The term does not imply that the associated devices do not contain wires, although this may be the case according to some embodiments.

[0074] The 2512 communication chip can implement any number of wireless standards or protocols, including but not limited to the following: Standards of the Institute for Electrical and Electronic Engineers (IEEE), including WiFi (IEEE 2302.11 family), IEEE 2302.16 standards (for example, IEEE 2302.16-2005 Amendment), the Long-Term Evolution (LTE) project together with any extensions, updates and / or revisions (for example, the Advanced LTE project, the Ultramobile Broadband (UMB) project (also known as "3GPP2"), etc.). IEEE 2302.16-compliant Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, which is an acronym for Worldwide Interoperability for Microwave Access, a certification mark for products that pass compliance and interoperability tests for the IEEE 2302.16 standards.The 2512 communication chip can operate according to a Global System for Mobile Communications (GSM) network, a General Packet Radio Service (GPRS) network, a Universal Mobile Communications System (UMTS) network, a High-Speed ​​Packet Access (HSPA) network, an Evolved HSPA (E-HSPA) network, or an LTE network. The 2512 communication chip can operate according to Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The 2512 communication chip can operate according to a Code-Separated Multiple Access (CDMA) protocol, a Time-Separated Multiple Access (TDMA) protocol, a Digital Enhanced Cordless Telecommunications (DECT) protocol, an Evolution Data-Optimized (EV-DO) protocol and derivatives thereof, as well as other wireless protocols known as 3G, 4G, 5G, etc.The communication chip 2512 can operate according to other wireless protocols in other embodiments. The computing device 2500 can have an antenna 2522 for enabling wireless communications and / or for receiving other wireless communications (in the form of AM or FM radio transmissions).

[0075] According to some embodiments, the communication chip 2512 can handle wired communications in the form of electrical, optical, or other suitable communication protocols (for example, Ethernet). As mentioned above, the communication chip 2512 can comprise multiple communication chips. For example, a first communication chip 2512 can be provided for short-range wireless communications in the form of WiFi or Bluetooth, and a second communication chip 2512 can be provided for longer-range wireless communications in the form of GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. According to some embodiments, a first communication chip 2512 can be provided for wireless communication and a second communication chip 2512 can be provided for wired communication.

[0076] The computing device 2500 can include a battery / power circuit arrangement 2514. The battery / power circuit arrangement 2514 can include one or more energy storage devices (for example, batteries or capacitors) and / or a circuit arrangement for coupling components of the computing device 2500 to a power source separate from the computing device 2500 (for example, a mains power source).

[0077] The computing device 2500 can include a display device 2506 (or a corresponding interface circuit arrangement, as discussed above). The display device 2506 can include visual indicators, for example, in the form of a heads-up display, a computer screen, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat-panel display.

[0078] The computing device 2500 can include an audio output device 2508 (or a corresponding interface circuit arrangement, as discussed above). The audio output device 2508 can include any device that produces an audible indicator, such as loudspeakers, headsets, or earphones.

[0079] The computing device 2500 can include an audio input device 2524 (or a corresponding interface circuit arrangement as discussed above). The audio input device 2524 can include any device that generates a signal representing a sound, such as microphones, microphone arrays, or digital instruments (for example, instruments with a Musical Instrument Digital Interface (MIDI) output).

[0080] The computing device 2500 can include a global positioning system (GPS) device 2518 (or a corresponding interface circuit arrangement, as discussed above). The GPS device 2518 can communicate with a satellite-based system and receive the location of the computing device 2500, as is known in the field.

[0081] The computing device 2500 may include another output device 2510 (or a corresponding interface circuit arrangement, as discussed above). Examples of the other output device 2510 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0082] The computing device 2500 may include another input device 2520 (or a corresponding interface circuit arrangement, as discussed above). Examples of the other input device 2520 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a quick-response (QR) code reader, a sensor, or a radio frequency identification (RFID) reader.

[0083] The computing device 2500 can have any desired form factor, such as a handheld or mobile computing device (for example, a mobile phone, smartphone, mobile internet device, music player, tablet computer, laptop computer, netbook computer, ultrabook computer, personal digital assistant (PDA), ultrabook personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a display, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a portable computing device. According to some embodiments, the computing device 2500 can be any other electronic device that processes data.

[0084] The following paragraphs provide various examples of the embodiments disclosed herein.

[0085] Example 1 is an integrated circuit (IC) structure comprising: a die with a device side and an opposite back side, a mold compound located on the back side, and a conduit path extending from the back side into the die and from the back side into the mold compound.

[0086] Example 2 may include the subject matter of Example 1 and further specify that the molded mixture has a surface spaced away from the back side, such that the back side is located between the surface and the device side, and wherein the conduit path extends to the surface.

[0087] Example 3 can include the object of Example 2 and further include an assembly interlink layer located on the surface, wherein the conductor path contacts the assembly interlink layer on the surface.

[0088] Example 4 may include the subject matter of Example 3 and further specify that the assembly interconnect layer has a first contact point located in a bearing surface of the die and a second contact point located outside the bearing surface of the die, and that the IC structure further includes an electronic component located on the assembly interconnect layer and in conductive contact with the first contact point and the second contact point.

[0089] Example 5 may include the subject matter of Example 4 and further specify that the electronic component is in conductive contact with the first contact point and the second contact point via solder bumps, solder balls or surface-activated bonding.

[0090] Example 6 may include the subject matter of any of Examples 3 to 5 and further specify that the assembly interconnect layer has contact points positioned to align with power and ground contact points of an electronic component located on the assembly interconnect layer.

[0091] Example 7 may include the subject matter of any of Examples 3 to 6 and further specify that the assembly interconnect layer has multiple contact points with a pitch greater than 30 micrometers and that the IC structure further includes an electronic component located on the assembly interconnect layer and in conductive contact with the multiple contact points.

[0092] Example 8 can feature the object from any of Examples 2 to 7 and further specify that the distance between the surface and the back side is greater than the thickness of the die.

[0093] Example 9 may feature the object of any of Examples 1 to 8 and further specify that the conduit path has a first section in the die and a second section in the mold mixture, wherein the second section is wider than the first section.

[0094] Example 10 may comprise the subject matter of any of Examples 1 to 9 and further specify that the die comprises a semiconductor substrate with a front face and an opposite rear face, wherein the rear face of the substrate provides the back of the die and the conduction path extends from the rear face to the front face in the die.

[0095] Example 11 may include the subject of Example 10 and further specify that the semiconductor substrate is a section of a silicon wafer.

[0096] Example 12 may include the subject matter of any of Examples 1 to 11 and further specify that the conduction path contacts a metallization layer of the die on the device side of the die.

[0097] Example 13 may comprise the subject matter of any of Examples 1 to 12 and may further comprise: an assembly substrate and first-level intermediate connections coupling the fixture side of the die to the assembly substrate.

[0098] Example 14 is a stacked integrated circuit (IC) structure comprising: a die with a fixture side and an opposite back side; a mold compound located on the back side, wherein the mold compound has a surface spaced from the back side such that the back side is located between the surface and the fixture side; an assembly interconnect layer located on the surface, wherein the assembly interconnect layer has a first contact point located in a bearing area of ​​the die and a second contact point located outside the bearing area of ​​the die; at least one conduction path that is in contact with the first and second contact points and extends into the die; and an electronic component.which is located on the assembly interfacing layer and is coupled to the first contact point or the second contact point.

[0099] Example 15 may include the subject matter of Example 14 and further specify that the electronic component is coupled to the first and second contact points.

[0100] Example 16 may include the subject matter of Example 14 and further specify that the electronic component is coupled to the first contact point and another electronic component is coupled to the second contact point.

[0101] Example 17 may include the subject matter of any of Examples 14 to 16 and further specify that the electronic component is a first electronic component and the stacked IC structure further includes a second electronic component located on top of the first electronic component, such that the first electronic component is located between the second electronic component and the molded mixture.

[0102] Example 18 may include the subject matter of any of Examples 14 to 17 and further specify that the at least one conduction path has a first section through the molding mixture and a second section through a substrate of the die.

[0103] Example 19 may include the subject matter of any of Examples 14 to 18 and further specify that the electronic component located on the assembly interconnect layer has a second die coupled to an assembly substrate, the assembly substrate is located between the die and the assembly interconnect layer, and the assembly substrate is in contact with the first contact point or the second contact point.

[0104] Example 20 is a computing device comprising: a printed circuit board and a stacked integrated circuit (IC) structure coupled to the printed circuit board, the stacked IC structure comprising: a die with a device side and an opposite back side, a molded compound located on the back side, the molded compound having a surface spaced from the back side such that the back side is located between the surface and the device side, a conduction path extending from the back side into the die and from the back side into the molded compound, a contact point located on the surface and in conductive contact with the conduction path, and an electronic component located on the surface and conductively coupled to the contact point.

[0105] Example 21 may include the subject of Example 20 and further specify that an assembly substrate is located between the electronic component and the surface.

[0106] Example 22 may include the subject matter of any of Examples 20 to 21 and further specify that the electronic component is a portable display.

[0107] Example 23 may include the object of any of Examples 20 to 22 and further specify that the electronic component includes a radio chip.

[0108] Example 24 may feature the subject of any of Examples 20 to 23 and further specify that the electronic component has a second die.

[0109] Example 25 is a method for fabricating an integrated circuit (IC) assembly comprising: forming a conductive via in the back side of an IC substrate, wherein the back side is opposite a device side of the IC substrate; forming a conductive extension of the conductive via on the back side of the IC substrate after forming the conductive via, wherein the conductive extension is in contact with the conductive via; providing a mold compound around the conductive extension; and forming a conductive contact on a surface of the mold compound, wherein the conductive contact is electrically coupled to the conductive extension.

[0110] Example 26 may include the subject of Example 25 and may further include the thinning of the IC substrate after the formation of the conductive via and before the formation of the conductive extension.

[0111] Example 27 may include the subject matter of any of Examples 25 to 26 and further specify that the formation of the conductive extension comprises: providing and structuring a photoresist on the back side of the IC substrate, wherein the structured photoresist has an opening for conductive vias, and providing a conductive material in the opening to form the conductive extension.

[0112] Example 28 may include the subject matter of Example 27 and further include: singling out the IC substrate after providing the conductive material in the opening, and removing the photoresist after singling out the IC substrate, wherein the mold mixture is provided after removing the photoresist.

[0113] Example 29 may include the subject matter of any of Examples 25 to 28 and further specify that the provision of the mold mixture includes the overmolding of the conductive extension.

[0114] Example 30 may include the object of any of Examples 25 to 29 and may further include the thinning of the molding mixture after the molding mixture has been provided and before the conductive contact has been formed.

[0115] Example 31 may feature the subject of any of Examples 25 to 30 and further specify that the IC substrate is a wafer.

[0116] Example 32 may feature the subject of any of Examples 25 to 31 and further specify that the conductive extension extends away from the conductive via.

Claims

[1] Package (200) comprising: a package substrate (140) with a top side above a bottom side; a first chip (102) with a device side opposite a rear side, wherein the device side contains a circuit in or on a substrate, the substrate comprising silicon, the circuit being located between the substrate and the top of the package substrate; an electrically insulating layer (110), wherein the electrically insulating layer is in lateral contact with the first chip and the electrically insulating layer is on and in contact with the back of the first chip; conductive paths (112) extending from the circuit of the device side of the first chip through the substrate of the first chip and through the electrically insulating layer, wherein the conductive paths are in electrical contact with the circuit; a connecting layer (116) on the electrically insulating layer and on the conductive paths, wherein the connecting layer is in electrical contact with the conductive paths; and a second chip (126) on and in electrical contact with the interconnect layer, wherein the second chip is connected to the interconnect layer by surface-activated bonding. [2] Package according to claim 1, wherein the electrically insulating layer (110) comprises amorphous silicon dioxide. [3] Package according to one of claims 1 to 2, wherein the electrically insulating layer (110) acts as a heat distributor. [4] Package according to any one of claims 1 to 3, wherein the electrically insulating layer (110) comprises silicon and oxygen. [5] Package according to any one of claims 1 to 4, wherein the second chip (126) is a storage device. [6] Package according to any one of claims 1 to 5, wherein the second chip (126) is a packaged integrated circuit. [7] A method for manufacturing a package (200), the method comprising: Providing a package substrate (140) with a top side above a bottom side; Coupling a first chip (102) to the package substrate, wherein the first chip has a device side (104) opposite a rear side (106), wherein the first chip has a first side wall opposite a second side wall, wherein the first side wall and the second side wall are located between the device side and the rear side, wherein the device side contains a circuit in or on a substrate, wherein the substrate comprises silicon and wherein the circuit is located between the substrate and the top side of the package substrate; Forming an electrically insulating layer (110), wherein the electrically insulating layer is in lateral contact with the first chip and the electrically insulating layer is on and in contact with the back of the first chip; Forming conductive paths (112) extending from the circuitry of the device side of the first chip through the substrate of the first chip and through the electrically insulating layer on the back side of the first chip; Forming a junction layer (116) on the electrically insulating layer and on the conductive paths, wherein the junction layer is coupled to the conductive paths; and Coupling of a second chip (126) to the interconnect layer using surface-activated bonding. [8] Method according to claim 7, wherein the interconnect layer (116) is in electrical contact with the conductive paths (112). [9] Method according to one of claims 7-8, wherein the interconnect layer (116) is in electrical contact with the second chip (126). [10] Method according to one of claims 7-9, wherein the conductive paths (112) are in electrical contact with the circuit. [11] Method according to any one of claims 7-10, wherein the conductive paths (112) pass through silicon vias. [12] Method according to one of claims 7-11, wherein the interconnect layer (116) comprises contact surfaces for electrical connections with the second chip (126). [13] Package (200) comprising: a package substrate (140) having a top surface above a bottom surface, wherein the package substrate has electrical conduction paths for conducting signals or current between first-level intermediate connections (136) and second-level intermediate connections (142); a first chip (102) with a device side opposite a back side, wherein the device side contains a circuit in or on a substrate, the substrate comprising silicon, wherein the circuit is located between the substrate and the top of the package substrate, the first chip being connected to the package substrate via the first-level interconnects; an electrically insulating layer (110), wherein the electrically insulating layer is in lateral contact with the first chip and the electrically insulating layer is on and in contact with the back of the first chip; conductive paths (112) extending from the circuit of the device side of the first chip through the substrate of the first chip and through the electrically insulating layer, wherein the conductive paths are in electrical contact with the circuit; a connecting layer (116) on the electrically insulating layer and on the conductive paths, wherein the connecting layer is in electrical contact with the conductive paths; and a second chip (126) on and in electrical contact with the interconnect layer.

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