SEMICONDUCTOR DEVICE

Abstract

Semiconductor device comprising a MIS structure, with: a semiconductor layer (3) having a front surface and a back surface; a gate insulating film (9) formed on the front surface side in the semiconductor layer (3); and a gate electrode (13) formed on the gate insulating film (9); and an intermediate layer insulating film (17) designed to cover the gate electrode (13) and part of the gate insulating film (9), wherein the gate insulating film (9) has a layer structure comprising a SiO2 base layer (10) and a high-k layer (11) on the SiO2 base layer (10) containing Hf, wherein the gate electrode (13) has a first section made of a metallic material with a work function of more than 4.6 eV, wherein the first section is in contact with at least the high-k layer (11), wherein the high-K layer (11) includes an HfAlON layer having an Hf composition (Hf / (Hf + Al)) of 30% to 70%, wherein a lateral end face of the gate insulating film (9) and a lateral end face of the interlayer insulating film (17) are aligned flush with each other, and wherein the high-K layer (11) has an N amount of 5 at-% or less.

Description

Technical field

[0001] The present invention relates to a semiconductor device with a MIS structure. background

[0002] A conventionally known semiconductor device with a MIS structure is disclosed, for example, in patent literature 1.

[0003] The semiconductor device disclosed in patent literature 1 comprises a semiconductor substrate, at least one nMOS device arranged in one region of the semiconductor substrate, and at least one pMOS device arranged in another region of the semiconductor substrate. The at least one nMOS device has a gate stack containing at least one elemental metal with a low work function (less than 4.2 eV) and an in-situ metal capping layer. The at least one pMOS device has a gate stack containing at least one elemental metal with a high work function (more than 4.9 eV) and a metal capping layer.

[0004] Patent literature 2 discloses a semiconductor device with a gate insulating film containing AlON. List of citations from patent literature Patent Literature 1: Japanese translation of the international patent application (Kohyo) JP 2008537359 A Patent Literature 2: Publication of the Japanese patent application JP 2014110402 A

[0005] Document US 020170025515 A1 discloses a semiconductor device with a gate insulating film that has a first layer, e.g. made of Si, and a second layer, e.g. made of HfO2, which have different dielectric constants.

[0006] Document US 020150318372 A1 discloses a semiconductor device with a gate insulating film comprising a layer of SiO2 and a second layer of AlON. Overview of the invention Technical problem

[0007] For example, in some cases a high-k film (film with a high dielectric constant) is used as the gate insulating film for a SiC MISFET. This is because the film thickness can be made relatively thick while maintaining the same gate capacitance, thus suppressing deterioration of the gate insulating film.

[0008] On the other hand, when using a high-k film, a problem can arise in that electrons trapped in the gate insulating film cause a shift in the flat-band voltage V. FB (“flatband voltage”) and lead to a corresponding shift in the gate threshold voltage V thThis can lead to problems. With high-k films, the use of an AlON layer can reduce the number of electrons trapped in the gate insulating film. However, the problem of hole trapping in the gate insulating film remains. Therefore, applying a negative voltage to the gate electrode can shift the gate threshold voltage V. th come.

[0009] A preferred embodiment of the present invention is a semiconductor device capable of reducing both electron trapping and hole trapping in the gate insulating film and of shifting the gate threshold voltage V. th to suppress. Solution to the problem

[0010] A preferred embodiment of the present invention provides a semiconductor device with a MIS structure according to claim 1, comprising a semiconductor layer with a front surface and a back surface, a gate insulating film on the front surface of the semiconductor layer, and a gate electrode on the gate insulating film. The gate insulating film has a layered structure comprising a SiO₂ base layer and a high-k layer on the SiO₂ base layer containing Hf. The gate electrode has a section made of a metal material with a work function of more than 4.6 eV, wherein the section is in contact with at least the high-k layer.

[0011] The electron capture level E TE In a high-K material containing Hf, for example, E is given with respect to the vacuum energy level E0. TE= approximately 3.5 eV to 4.5 eV. If, in this case, the work function Φ of a metallic material in contact with the high-K material is equal to or lower than the electron capture level E TE (Φ ≤ E TE The amount of electrons injected into the high-k material tends to increase when a voltage is applied to the metallic material. Therefore, the flat-band voltage V can increase due to the injected electrons. FB shift and thus the degree of shift of the gate threshold voltage V th increase.

[0012] In contrast, in the configuration described above, the gate electrode has a section made of a metallic material with a work function Φ greater than 4.6 eV, whereby this section comes into contact with at least the high-k layer, thus creating an energy barrier between the gate electrode and the high-k layer. The height of the energy barrier corresponds, for example, to the difference (Φ - E). TE ) between the work function Φ of the metal material and the electron capture level E TEof the high-k layer. Due to this energy barrier, the injection of electrons into the gate insulating film can be suppressed when a positive gate voltage is applied. Furthermore, with the configuration described above, the injection of holes into the gate insulating film can be suppressed when a negative gate voltage is applied. As described above, both electron trapping and hole trapping in the gate insulating film can be reduced, thereby lowering the degree of shift in the gate threshold voltage V. th can be reduced satisfactorily.

[0013] Another preferred embodiment of the present invention provides a semiconductor device with a MIS structure according to claim 2, comprising a semiconductor layer with a front surface and a back surface, a gate insulating film on the front surface side of the semiconductor layer, and a gate electrode on the gate insulating film. The gate insulating film has a layered structure comprising a SiO2 base layer, a high-k layer on the SiO2 base layer containing Hf, and an upper insulating layer between the high-k layer and the gate electrode. The upper insulating layer is made of a material with a difference of less than 4 eV between a lowest energy E and a higher energy E. C in the conduction band and a vacuum energy level.

[0014] In this configuration, the upper insulation layer is positioned between the gate electrode and the high-k layer. This applies even if the work function Φ of the gate electrode is equal to or lower than the electron capture level E. TE in the high-K layer (Φ ≤ E TE The energy barrier between the gate electrode and the upper insulating layer can be used as a barrier, thus suppressing the injection of electrons into the gate insulating film. Furthermore, with the configuration described above, the injection of holes into the gate insulating film can be suppressed when a negative gate voltage is applied. As described above, both electron and hole trapping in the gate insulating film can be reduced, thereby decreasing the degree of shift in the gate threshold voltage V. th can be reduced satisfactorily.

[0015] Another preferred embodiment of the present invention provides a semiconductor device with a MIS structure according to claim 3, comprising a semiconductor layer with a front surface and a back surface, a gate insulating film formed on the front surface side of the semiconductor layer, and a gate electrode on the gate insulating film. The gate insulating film has a layered structure comprising a SiO2 base layer and a high-k layer on the SiO2 base layer, containing Hf. The gate electrode has a section made of Mo, Cu, Au, Ni, Pt, or TiN, wherein the section is in contact with at least the high-k layer.

[0016] The exit works of Mo and TiN are Φ Mo = approx. 4.6 eV or Φ TiN = approx. 5.1 eV. This makes it possible, for example, to create an energy barrier of 0.6 eV or higher (Φ). Mo - E TE) or an energy barrier of 1.1 eV or higher (Φ TiN - E TE ) between the gate electrode and the high-k layer. This energy barrier suppresses the injection of electrons into the gate insulating film when a positive gate voltage is applied. Furthermore, the configuration described above prevents the injection of holes into the gate insulating film when a negative gate voltage is applied. As described above, both electron and hole trapping in the gate insulating film can be reduced, thereby lowering the degree of shift in the gate threshold voltage V. th can be reduced satisfactorily.

[0017] Yet another predetermined embodiment of the present invention provides a semiconductor device with a MIS structure according to claim 4, comprising a semiconductor layer with a front surface and a back surface, a gate insulating film on the front surface side of the semiconductor layer, and a gate electrode on the gate insulating film. The variation rate of a retest threshold voltage, after a negative stress voltage of a predetermined magnitude is applied to the gate electrode for 30 minutes or longer, from an initial threshold voltage of the gate electrode, is within 20%.

[0018] In other words, even after applying a negative stress voltage for 30 minutes or longer, the degree of shift or the shift value of the gate threshold voltage V cannot be changed. th within 20%. Brief description of the drawings [ Fig. 1] Fig. Figure 1 is a cross-sectional view of a semiconductor device according to a preferred embodiment of the present invention. [ Fig. 2] Fig. Figure 2 is a cross-sectional view of a semiconductor device according to another preferred embodiment of the present invention. [ Fig. 3] Fig. Figure 3 is a cross-sectional view of a semiconductor device according to another preferred embodiment of the present invention. [ Fig. 4] Fig. Figure 4 is a cross-sectional view of a semiconductor device according to another preferred embodiment of the present invention. [ Fig. 5] Fig. Figure 5 is a schematic configuration diagram of a reference structure 1, with which the variation rate of a gate threshold voltage V can be determined. th was measured. [ Fig. 6] Fig. Figure 6 is a schematic configuration diagram of a verification structure 1, with which the variation rate of the gate threshold voltage V is measured. th was measured. [ Fig. 7] Fig. Figure 7 is a schematic configuration diagram of a verification structure 2, with which the variation rate of the gate threshold voltage V is determined. th was measured. [ Fig. 8] Fig. Figure 8 is an energy band diagram of the reference structure 1. [ Fig. 9] Fig. Figure 9 is an energy band diagram of verification structure 1. [ Fig. 10] Fig. Figure 10 is an energy band diagram of verification structure 2. [ Fig. 11] Fig. Figure 11 shows the variation rate of the gate threshold voltage V. th in reference structure 1. [ Fig. 12] Fig. Figure 12 shows the variation rate of the gate threshold voltage V. th in the verification structure 1. [ Fig. 13] Fig. Figure 13 shows the variation rate of the gate threshold voltage V. th in the verification structure 2. [ Fig. 14] Fig. Figure 14 shows the variation rates of the gate threshold voltage V. th in reference structure 1 and reference structure 2. Description of exemplary implementations

[0019] Preferred embodiments of the present invention are described below with reference to the accompanying drawings.

[0020] Fig. Figure 1 is a cross-sectional view of a semiconductor device or semiconductor component 1 according to a preferred embodiment of the present invention.

[0021] The semiconductor device 1 includes a SiC substrate 2 of n + -Type (e.g. with a concentration of 1 × 10 19 up to 5 × 10 19 cm -3 ) and a semiconductor layer (epitaxial layer) 3, which consists of SiC from n --Type (e.g. with a concentration of 1 × 10 15 up to 1 × 10 16 cm -3 ) is formed on substrate 2. Substrate 2 and semiconductor layer 3 can be made of a semiconductor with a wider bandwidth or bandgap than SiC (e.g., GaN, Ga2O3, diamond, etc.). Substrate 2 and semiconductor layer 3 act as a drain for semiconductor device 1. Phosphorus (P) or arsenic (As), etc., is present as an n-type impurity. A similar n-type impurity is present in the n-type semiconductor regions mentioned below.

[0022] Gate grooves 4 are formed in semiconductor layer 3 by being excavated from a front surface of semiconductor layer 3 towards the substrate 2. The gate grooves 4 are formed, for example, in a grid or stripe configuration. This creates a multitude of unit cells 5 in semiconductor layer 3, which are subdivided by the gate grooves 4.

[0023] At the edges or peripheries of the gate grooves 4 in the semiconductor layer 3, source regions 6 are isolated from the n + -Type and body regions 7 of the p-type (e.g. with a concentration of 1 × 10 17 up to 5 × 10 17 cm -3 ) in this order, starting from the side closer to the front surface of semiconductor layer 3. The p-type impurity, for example boron (B) or aluminum (Al), etc., is present in body regions 7. A similar p-type impurity is present in the p-type semiconductor regions listed below.

[0024] The source region 6 is configured on a front surface section of each unit cell 5 such that it is exposed at the front surface of the semiconductor layer 3 and defines an upper section (a section) of a side surface of the gate trench 4. On the other hand, the body region 7 is configured such that it contacts the source region 6 on the substrate 2 side (back surface of the semiconductor layer 3) with respect to the source region 6 and defines a lower section (a section) of the side surface of the gate trench 4.

[0025] A region of the semiconductor layer 3 on the side of the substrate 2 with respect to the body region 7 is a drain region 8 of n - -Type, which is maintained in a state following epitaxial growth. The drain region 8 contacts the body region 7 on the side of the substrate 2 with respect to the body region 7 and defines a bottom surface of the gate trench 4.

[0026] On an inner surface of the gate trench 4, a gate insulating film 9 is formed such that it covers the entire inner surface. The gate insulating film 9 comprises a SiO2 base film 10 and a high-k film 11, which are laminated successively starting from the side of the inner surface of the gate trench 4. In the present preferred embodiment, the SiO2 base film 10 is formed such that it contacts the entire inner surface of the gate trench 4, and the high-k film 11 is laminated onto the SiO2 base film 10 such that it covers the entire region of the SiO2 base film 10. It is noted that the two-layer structure of these films can be formed over the entire inner surface of the gate trench 4, as in the present preferred embodiment, or can be formed selectively on channel sections of the inner surface of the gate trench 4 (the sections of the side surface of the gate trench 4 where the body regions 7 are exposed).In this case, other sections of the gate insulating film 9 can be arranged as a single-layer film made of SiO2.

[0027] In the present preferred embodiment, the gate insulating film 9 can also be formed to cover a side edge section at the opening end of the gate trench 4. This side edge section at the opening end of the gate trench 4 defines an enclosed angle between the front surface of the semiconductor layer 3 and the side surface of the gate trench 4. Sections in the respective environments of the front surface of the semiconductor layer 3 in the source region 6 and the side surface of the gate trench 4 are thus covered by the gate insulating film 9.

[0028] The gate insulating film 9 has a thickness of, for example, 55 nm to 150 nm. The preferred thickness ranges of the respective films are not below 5 nm for the SiO2 base film 10 (preferred 5 nm to 20 nm) and not below 10 nm for the high-K film 11 (preferred 10 nm to 200 nm).

[0029] In the present preferred embodiment, the SiO2 base film 10 is formed, for example, by thermal oxidation of the semiconductor layer 3. By arranging the film in contact with the semiconductor layer 3 (in particular the channel section) as a thermal oxide film, transistor properties can be expressed or achieved that are excellent compared to a deposited film, such as a CVD film.

[0030] The high-K film 11 is a film in which hafnium (Hf) atoms are dispersed and is preferably an HfAlON film in which hafnium is added to an AlON film. In this case, the hafnium composition (Hf / (Hf + Al)) of the high-K film 11 made from HfAlON is, for example, 30 to 70%, preferably 40 to 60%. Furthermore, the nitrogen (N) content of the high-K film 11 is, for example, 10 at% or less, preferably 5 at% or less. In addition, the high-K film 11 is preferably amorphous or microcrystalline. If the high-K film 11 has such a structure, the crystal grain boundaries in the gate insulating film 9 can be reduced, thereby reducing the gate leakage current.

[0031] Such a gate insulating film 9 can be formed, for example, by successively laminating the SiO2 base film 10 and the high-k film 11, after forming the gate trench 4 in the semiconductor layer 3. The SiO2 base film 10 can be formed, for example, by a thermal oxidation process (e.g., at 1100°C to 1300°C). Furthermore, the high-k film 11 can be formed by depositing the respective atoms, e.g., by an ALD process (atomic layer deposition), a CVD process, or a PVD process (physical vapor deposition), etc.

[0032] It is noted that PDA (post-deposition annealing) can be carried out at, for example, 700°C to 1000°C after the high-K film 11 has formed. This allows the shift in the flat-band stress V to be reduced. FB be satisfactorily suppressed.

[0033] A gate electrode 13 is embedded in the gate trench 4 on the inside of the gate insulating film 9. A trench-gate type MIS structure is arranged in which the source region 6, the body region 7, and the drain region 8, which define the inner surface of the gate trench 4, are opposite the gate electrode 13 via the gate insulating film 9.

[0034] The gate electrode 13 is made of a metallic material with a work function Φ of more than 4.6 eV. For example, the gate electrode 13 can be made of Mo (Φ Mo = 4.6 eV), Cu (Φ Cu = 4.6 eV), Au (Φ Au = 5.1 eV), Ni (Φ Ni = 5.2 eV), Pt (Φ Pt = 5.6 eV), TiN (Φ TiNThe gate electrode 13 can be manufactured entirely from a metallic material with a work function Φ greater than 4.6 eV. Alternatively, only a section of the gate electrode 13 that contacts the high-k film 11 can be selectively manufactured from a metallic material with Φ > 4.6 eV, and a layer of a metallic material without a work function Φ in the same region can be laminated onto this section. For example, the gate electrode 13 can include a first metal layer of TiN arranged on the high-k film 11 in contact with the high-k film 11, and can include a second metal layer of Al on top of the first metal layer.

[0035] A source trench 14 is formed at a central section of each unit cell 5 by excavating it from the front surface of the semiconductor layer 3 towards the substrate 2. The source trench 14 penetrates the source region 6 and the body region 7 from the front surface of the semiconductor layer 3 and reaches the drain region 8. In the present preferred embodiment, the source trench 14 is formed to the same depth as the gate trench 4.

[0036] In semiconductor layer 3, a p-type region 15 is formed around the perimeter of source trench 14. In a lower region of body region 7, the p-type region 15 is exposed on an inner surface of source trench 14 such that it is continuous (i.e., connected) to body region 7. That is, in the lower region, the p-type region 15 is located between drain region 8 and the inner surface of source trench 14. Therefore, the p-type region 15 is exposed on a bottom surface and on a bottom edge segment or boundary segment of source trench 14.

[0037] Also in region 15 of the p-type is a body contact region 16 of the p-type. +-Type formed on the bottom surface of the source trench 14. In the present preferred embodiment, the body contact region 16 is arranged on a central section which is separated from the inside by an interval or a distance from the side surface of the source trench 14.

[0038] An intermediate insulating film 17 is formed on the semiconductor layer 3 to cover the gate electrodes 13. In regions other than the intermediate insulating film 17, contact holes 18 with a larger diameter than the source trench 14 are formed. The entirety of the source trench 14 (i.e., the entire inner surface of the source trench 14) and a section of the source region 6 of each unit cell 5 are thus exposed within the contact hole 18.

[0039] A source electrode 19 is formed on the intermediate insulating film 17. The source electrode 19 enters the source grooves 14 of all unit cells 5 collectively via the respective contact holes 18. The source electrode 19 contacts the body contact region 16, the p-type region 15, the body region 7, and the source region 6 successively, starting from the bottom side of the source groove 14. That is, the source electrode 19 is a common wiring connection for all unit cells 5. In the present preferred embodiment, the source electrode 19 has a structure in which a Ti / TiN layer and an Al layer are laminated successively, starting from the side in contact with the semiconductor layer 3.

[0040] A drain electrode 20 is formed on the back surface of the substrate 2, covering the entire back surface. The drain electrode 20 is an electrode common to all unit cells 5. For example, a layered structure (Ti / Ni / Au / Ag) can be used as the drain electrode 20, in which Ti, Ni, Au, and Ag are laminated sequentially, starting from the side of the substrate 2.

[0041] Fig. Figure 2 is a cross-sectional view of a semiconductor device 21 according to another preferred embodiment of the present invention. Fig. 2 are sections that contain the in Fig. The sections shown in the description above correspond to the sections shown, are marked with the same reference symbols, and their descriptions are omitted.

[0042] At the in Fig. In the preferred embodiment shown in Figure 1, the MIS structure is arranged as a trench-gate type, wherein the gate electrode 13 is opposite or facing the source region 6, the body region 7 and the drain region 8, which define the inner surface of the gate trench 4, via the gate insulating film 9.

[0043] In contrast, the MIS structure of the semiconductor device 21 according to the present preferred embodiment is arranged as a planar gate type.

[0044] The MIS structure of the planar gate type includes a p-type body region 22, which is selectively formed in a front surface section of the semiconductor layer 3, and a source region 23 of the n +-type, which is selectively formed in the body region 22, a gate insulating film 24 which is formed on the front surface of the semiconductor layer 3, a gate electrode 25 which faces the body region 22 and is exposed on the front surface of the semiconductor layer 3 via the gate insulating film 24, and a body contact region 26 from the p + -Type that penetrates the source region 23 starting from the front surface of the semiconductor layer 3 and has a deepest section reaching the body region 22.

[0045] As in the gate insulating film 9 in the preferred embodiment of Fig. 1 The gate insulating film 24 of the semiconductor device 21 also includes a SiO2 base film 27 and a high-k film 28, which are laminated successively starting from the front surface of the semiconductor layer 3. The gate electrode 25 and the high-k film 28 can be made of the same material as the gate electrode 13 and the high-k film 11, respectively, in the preferred embodiment of Fig. 1 must be manufactured.

[0046] Fig. Figure 3 is a cross-sectional view of a semiconductor device 31 according to a further preferred embodiment of the present invention. Fig. There are 3 sections, each in Fig. The sections shown in the description above correspond to the sections shown, are marked with the same reference symbols, and their descriptions are omitted.

[0047] In the preferred embodiment of the Fig. In the gate insulating film 9, the SiO2 base film 10 and the high-k film 11 are laminated successively, starting from the side of the inner surface of the gate groove 4. Furthermore, in the present preferred embodiment, the semiconductor device 31 includes an upper insulating film 32 on the high-k film 11.

[0048] The upper insulating film, or insulating film 32, is made of an insulating material where the lowest energy Ec of the conduction band is less than 4 eV relative to the vacuum energy level E0. For example, the upper insulating film 32 is made of SiO2 (Ec = 0.9 eV) or the like. Furthermore, the upper insulating film 32 can be formed directly on the high-K film 11 to make contact with it, or a layer of an insulating material that does not have the lowest energy Ec of the same region can be inserted between the upper insulating film 32 and the high-K film 11. The thickness of the upper insulating film 32 can also be 5 nm or more. The upper insulating film 32 can also be formed, for example, by the CVD process.

[0049] Furthermore, in the present preferred embodiment, the gate electrode 33 does not need to be made of a metallic material with a work function Φ of more than 4.6 eV, unlike the gate electrode 13 described above. In other words, the work function Φ of the gate electrode 33 can be 4.6 eV or less. For example, the gate electrode 33 is made of Al (Φ Al = 4.1 eV) or the like.

[0050] Fig. Figure 4 is a cross-sectional view of a semiconductor device 41 according to another preferred embodiment of the present invention. Fig. 4 are sections that correspond to the description above. Fig. 1 to Fig. The 3 sections shown correspond to each other, are provided with the same reference symbols, and their descriptions are omitted.

[0051] At the in Fig. In the preferred embodiment shown in Figure 3, the MIS structure is designed as a trench-gate type, wherein the gate electrode 33 faces the source region 6, the body region 7 and the drain region 8 via the gate insulating film 9, which define the inner surface of the gate trench 4.

[0052] In contrast, the MIS structure of the semiconductor device 41 according to the present preferred embodiment is designed as a planar gate type.

[0053] The MIS structure of the planar gate type includes a p-type body region 42, which is selectively formed in a front surface section of the semiconductor layer 3, and a source region 43 of the n +-type, which is selectively formed in the body region 42, a gate insulating film 44 which is formed on the front surface of the semiconductor layer 3, a gate electrode 45 which faces the body region 42, which is exposed at or where it is exposed to the front surface of the semiconductor layer 3, namely via the gate insulating film 44, and a body contact region 46 from the p + -Type, which passes through the source region 43 starting from the front surface of the semiconductor layer 3 and has a deepest section reaching the body region 42.

[0054] As with the gate insulating film 9 in the preferred embodiment of the Fig. In the gate insulating film 44 of the semiconductor device 41, a SiO2 base film 47, a high-k film 48, and an upper insulating film 49 are laminated successively from the front surface of the semiconductor layer 3. The gate electrode 45 and the high-k film 48 can be made of the same material as the gate electrode 33 and the high-k film 11, respectively, in the preferred embodiment of Fig. 3 must be manufactured.

[0055] Next, with reference to Fig. 5 to Fig. 13 described in detail that the semiconductor devices 1, 21, 31, 41 according to the preferred embodiments described above cause a shift in the gate threshold voltage V th can suppress.

[0056] Fig. 5 to Fig. Figure 7 shows first the reference structure 1, the verification structure 1 and the verification structure 2, which were used to determine the respective variation rate (shift rate) of the gate threshold voltage V. th to eat.

[0057] In particular, the gate insulating film in reference structure 1 of Fig. 5 the two-layer structure of a SiO2 film and a high-K film (HfAlON film), and the gate electrode, which is made of Al (Φ Al = 4.1 eV) is provided on the HfAlON film.

[0058] Verification structure 1 of Fig. 6 is used to verify the variation rate of the gate threshold voltage V. th in the structure of semiconductor devices 1 and 21. In the verification structure 1, the gate insulating film has the two-layer structure of a SiO2 film and a high-k film (HfAlON film), and the gate electrode, which is made of TiN (Φ TiN= 5.1 eV) is provided on the HfAlON film.

[0059] Verification structure 2 of Fig. 7 is used to verify the variation rate of the gate threshold voltage V. th in the structure of semiconductor devices 31 and 41. In the verification structure 2, the gate insulating film has the three-layer structure of a SiO2 film, a high-K film (HfAlON film) and a SiO2 film, and the gate electrode, which is made of Al (Φ Al = 4.1 eV) is provided on the upper SiO2 film.

[0060] Next are the Fig. 8 to Fig. 10 energy band diagrams of reference structure 1, verification structure 1 and verification structure 2. These energy band diagrams describe the degree of electron injection from the gate electrode to the high-K film in each structure.

[0061] As in Fig. As shown in Figure 8, the electron trap level is E TE of the high-K film with respect to the vacuum energy level E0 is approximately 3.5 eV to 4.5 eV, while the work function Φ Al The gate electrode (Al) has a work function of 4.1 eV. This means that the work function Φ Al The gate electrode's electron capture level is nearly equal to or lower than the electron capture level E. TE of the high-k film. Therefore, if a positive voltage is applied to the gate electrode, electrons can easily be injected into the high-k film.

[0062] On the other hand, as in Fig. Figure 9 shows the verification structure 1 based on the semiconductor devices 1 and 21, the work function Φ TiN the gate electrode higher than the electron capture level E TE (= 3.5 eV to 4.5 eV) of the high-K film (Φ TiN = 5.1 eV), and a predetermined energy barrier (Φ TiN - E TEThis energy barrier thus occurs between the gate electrode and the high-k film. Due to this barrier, the injection of electrons into the high-k film can be suppressed when a positive gate voltage is applied.

[0063] Furthermore, as in Fig. 10 shown, in the verification structure 2 based on the semiconductor devices 31 and 41, although the work function Φ Al The gate electrode voltage is approximately equal to or lower than the electron capture level E. TE of the high-K film, the upper insulating film is made of SiO2. Therefore, the energy barrier (Φ) Al - Ec) between the gate electrode (Φ Al = 4.1 eV) and the upper insulating film (Ec = 3.5 eV) are used as a barrier, thus suppressing the injection of electrons into the gate insulating film.

[0064] As described above, the Fig. 8 to Fig. 10, that verification structures 1 and 2 can reduce the amount of electrons injected compared to reference structure 1 from the perspective of the energy band diagram, while the Fig. 11 to Fig. 13 the variation rate of the gate threshold voltage V th in each structure that indicates the reduced injection quantity of electrons and the effect of the reduced injection quantity of holes, which in the Fig. 8 to Fig. 10 are not shown.

[0065] To determine the variation rates of the gate threshold voltage V thTo compare the results, the following gate bias test was performed for each structure. In a temperature environment of 175°C, a positive gate voltage was applied to the gate electrode, causing a drain current to flow between the source and drain. Then, a negative stress voltage (Vg = -10 V) was applied to the gate electrode for a predetermined time. Specifically, after an initial drain current flow, the stress voltage was applied for 1 minute, and then the application time was increased to 3 minutes, 6 minutes, and 20 minutes. During each stress voltage application, a positive gate voltage was applied to the gate electrode, and the drain current and the corresponding gate voltage rise time were measured and plotted. The graphs are shown in the... Fig. 11 to Fig. 13 shown. In the Fig. 11 to Fig. Figure 13, "Initial," represents the initial drain current, while "1 min," "4 min," "10 min," and "30 min" indicate the total application time or on-time of the stress voltage. For example, the "10 min" figure shows the drain current after the stress voltage has been applied in three separate periods of 1 minute, 3 minutes, and 6 minutes, totaling 10 minutes.

[0066] As in Fig. As shown in Figure 11, in reference structure 1, when a stress voltage of Vg = -10 V was applied for 30 minutes or longer, the post-test threshold voltage (30 min) in the positive direction was changed or varied (shifted) by 260% or more compared to the initial threshold voltage of the gate electrode. Since the rising voltage (not shown) of the leakage current on the negative side in reference structure 1 was -15 V, it is determined that the shift is due to the application of a stress voltage of -10 V, which is close to the rising voltage, causing many holes to be injected into and trapped in the high-k film.

[0067] In contrast to how it is described in Fig. 12 and Fig. As shown in Figure 13, in verification structures 1 and 2, even when a stress voltage of Vg = -10 V was applied for 30 minutes or longer, the variation rate of the post-test threshold voltage (30 min) compared to the initial threshold voltage (initial) of the gate electrode was within 20%. Considering that the rising voltages (not shown) of the leakage current on the negative side of verification structures 1 and 2 were -20 V and -30 V, respectively, it can be seen that even when a stress voltage of -10 V was applied, hardly any holes were injected into the high-K film.

[0068] From the above results, it is observed that the semiconductor devices 1, 21, 31 and 41, according to the preferred embodiments described above, exhibit a shift in the gate threshold voltage V. th can suppress.

[0069] The following refers to Fig. 14 describes how the measure or magnitude of the shift in the gate threshold voltage V th This can be reduced by using the high-K film, which contains RF. In particular, the shift magnitudes of the gate threshold voltage V were th The results were compared in reference structure 1 and in reference structure 2, where the high-K film (HfAlON film) in reference structure 1 is replaced by an AlON film. The gate stress tests performed on both structures were similar to those performed in Fig. 11 to Fig. 13 are shown.

[0070] As a result of the tests, it is found that the reference structure 1, using the HfAlON film, exhibits a shift in the gate threshold voltage V. th can suppress better than reference structure 2, which uses the AlON film as a high-K film. In other words, taking into account the in Fig. 11 to Fig.The results shown in Figure 13 show that the combination of (1) the Hf-containing high-K film and (2-1) the gate electrode with a work function of 4.6 eV or more, or (2-2) the upper insulating film between the gate electrode and the high-K film makes it possible to reduce both electron trapping and hole trapping in the gate insulating film, and thus to shift the gate threshold voltage V th to suppress satisfactorily.

[0071] Although the preferred embodiments of the present invention have been described above, the present invention can be implemented in even more ways.

[0072] For example, in semiconductor devices 1, 21, 31 and 41, an arrangement can be adopted in which the conductivity types of the respective semiconductor sections are inverted. Thus, for example, in semiconductor device 1, a p-type section can be an n-type and an n-type section can be a p-type.

[0073] Although in the preferred embodiments described above a trench-gate or planar-gate type MISFET was used as an example of the present invention, the present invention can also be applied to a MIS transistor structure, such as a CMOSFET (Complementary Metal Oxide Semiconductor Field Effect Transistor), etc. Reference symbol list 1 Semiconductor device 2 Substrat 3 Semiconductor layer (epitaxial layer) 4 Gate Trench 9 Gate insulating film 10 SiO2 base film 11 High-K film 13 Gate electrode 21 Semiconductor device 24 Gate insulating film 25 Gate electrode 27 SiO2 base film 28 High-K film 31 Semiconductor device 32 Upper insulating layer 33 Gate electrode 41 Semiconductor device 44 Gate insulating film 45 Gate electrode 47 SiO2 base film 48 High-K film 49 Upper insulating layer

Claims

[1] Semiconductor device comprising a MIS structure, with: a semiconductor layer (3) having a front surface and a back surface; a gate insulating film (9) formed on the front surface side in the semiconductor layer (3); and a gate electrode (13) formed on the gate insulating film (9); and an intermediate layer insulating film (17) designed to cover the gate electrode (13) and part of the gate insulating film (9), wherein the gate insulating film (9) has a layer structure comprising a SiO2 base layer (10) and a high-k layer (11) on the SiO2 base layer (10) containing Hf, wherein the gate electrode (13) has a first section made of a metallic material with a work function of more than 4.6 eV, wherein the first section is in contact with at least the high-k layer (11), wherein the high-K layer (11) includes an HfAlON layer having an Hf composition (Hf / (Hf + Al)) of 30% to 70%, wherein a lateral end face of the gate insulating film (9) and a lateral end face of the interlayer insulating film (17) are aligned flush with each other, and wherein the high-K layer (11) has an N amount of 5 at-% or less. [2] Semiconductor device comprising a MIS structure with: a semiconductor layer (3) having a front surface and a back surface; a gate insulating film (9) which is formed on the front surface side in the semiconductor layer (3); a gate electrode (13) formed on the gate insulating film (9); and an intermediate layer insulating film (17) designed to cover the gate electrode (13) and part of the gate insulating film (9) wherein the gate insulating film (9) has a layer structure comprising a SiO2 base layer (10), a high-k layer (11) on the SiO2 base layer (10) and Hf, and an upper insulating layer (32) between the high-k layer (11) and the gate electrode (13), and wherein the upper insulating layer (32) is made of a material with a difference of less than 4 eV between a lowest energy Ec in the conduction band and a vacuum energy level, wherein the high-K layer (11) includes an HfAlON layer having an Hf composition (Hf / (Hf + Al)) of 30% to 70%, wherein a lateral end face of the gate insulating film (9) and a lateral end face of the interlayer insulating film (17) are aligned flush with each other, and wherein the high-K layer (11) has an N amount of 5 at-% or less. [3] Semiconductor device comprising a MIS structure with: a semiconductor layer (3) having a front surface and a back surface; a gate insulating film (9) which is formed on the front surface side in the semiconductor layer (3); a gate electrode (13) formed on the gate insulating film (9); and an intermediate layer insulating film (17) designed to cover the gate electrode (13) and part of the gate insulating film (9), wherein the gate insulating film (9) has a layer structure comprising a SiO2 base layer (10) and a high-k layer (11) containing the SiO2 base layer (10) and Hf, and wherein the gate electrode (13) has a section made of Mo, Cu, Au, Ni, Pt or TiN, wherein the section is in contact with at least the high-K layer (11), wherein the high-K layer (11) includes an HfAlON layer having an Hf composition (Hf / (Hf + Al)) of 30% to 70%, wherein a lateral end face of the gate insulating film (9) and a lateral end face of the interlayer insulating film (17) are aligned flush with each other, and wherein the high-K layer (11) has an N amount of 5 at-% or less. [4] Semiconductor device comprising a MIS structure with: a semiconductor layer (3) having a front surface and a back surface; a gate insulating film (9) which is formed on the front surface side in the semiconductor layer (3); a gate electrode (13) formed on the gate insulating film (9); and an intermediate layer insulating film (17) designed to cover the gate electrode (13) and part of the gate insulating film (9), wherein the gate insulating film (9) has a layer structure comprising a SiO2 base layer (10) and a high-k layer (11) on the SiO2 base layer (10) containing Hf, wherein a variation rate of a post-test threshold voltage after a negative stress voltage of a predetermined size is applied to the gate electrode (13) for 30 minutes or longer is within 20% of an initial threshold voltage of the gate electrode (13), wherein the high-K layer (11) includes an HfAlON layer having an Hf composition (Hf / (Hf + Al)) of 30% to 70%, wherein a lateral end face of the gate insulating film (9) and a lateral end face of the interlayer insulating film (17) are aligned flush with each other, and wherein the high-K layer (11) has an N amount of 5 at-% or less. [5] Semiconductor device according to claim 2, wherein the upper insulating layer (32) is made of SiO2 and has a thickness of 5 nm or more. [6] Semiconductor device according to any one of claims 1 to 4, wherein the HfAlON layer has a thickness of 10 nm to 200 nm. [7] Semiconductor device according to any one of claims 1 to 4, wherein the HfAlON layer is amorphous or microcrystalline. [8] Semiconductor device according to any one of claims 1 to 7, wherein the SiO2 base layer (10) has a thickness of 5 nm or more. [9] Semiconductor device according to any one of claims 1 to 8, wherein the semiconductor layer (3) is made of SiC, GaN, Ga2O3 or diamond. [10] Semiconductor device according to any one of claims 1 to 9, wherein the MIS structure comprises a gate-trough type structure. [11] Semiconductor device according to any one of claims 1 to 9, wherein the MIS structure includes a planar gate structure. [12] Semiconductor device according to claim 10, wherein the gate insulating film (9) is configured to cover a side surface and a bottom surface of a gate trench (4) formed by excavating from the front surface of the semiconductor layer (3) and a section of the front surface of the semiconductor layer (3). [13] The semiconductor device according to claim 12, wherein the gate electrode (13) is embedded in the gate groove (4), and wherein the semiconductor device comprises: a source region (6) of a first conductivity type formed at the front surface in the semiconductor layer (3) to contact the side surface of the gate trench, a body region (7) of a second conductivity type formed closer to the back surface in the semiconductor layer (3) than the source region (6), a drain region (8) of the first conductivity type formed closer to the back surface in the semiconductor layer (3) than the body region (7), the interlayer insulating film (17) which is designed to cover an upper section of the gate electrode (13), a source electrode (19) which is electrically connected to the source region (6), and a drain electrode (20) which is electrically connected to the drain region (8). [14] Semiconductor device according to claim 13, comprising a source trench formed at a position away from the gate trench to penetrate into the source region (6) and the body region (7) by being excavated from the front surface of the semiconductor layer (3) so that the source electrode (19) is embedded within the source trench. [15] Semiconductor device according to claim 14, wherein a region of the second conductivity type is formed around the source trench to extend continuously to the body region (7).

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