POWER SEMICONDUCTOR UNIT

Abstract

Power semiconductor unit (100) comprising: - a metal layer (3), - a semiconductor element (4) bonded to the metal layer (3) via a solder layer (7), and - a wire bump (9) extending in the direction in the plane of the solder layer (7) and bonded to the metal layer (3), - wherein an alloy of the material of the wire bump (9) and the material of the solder layer (7) is arranged at the interface between the wire bump (9) and the solder layer (7) and - wherein the wire bump (9) is bonded to the metal layer (3) only by a wedge bond connection region.

Description

TECHNICAL FIELDThe present invention relates to a power semiconductor device, and more particularly relates to a power semiconductor device in which a wire bump made of a material capable of alloying with a material of a solder layer is disposed at a predetermined position.PRIOR ARTIn a conventional power semiconductor device, for example, when a base plate and an insulating substrate are bonded with a solder, a wire mainly made of Al or Cu is attached to a copper plate by wedge bonding to form a wire bump to uniformize the thickness of a solder layer (see, for example, JP H11-186 331 A and JP 5 542 567 B2).US 2015 / 0 200 181 A1 discloses a semiconductor device including: a semiconductor chip; an electrode pad made of a metal material containing aluminum and formed on an upper surface of the semiconductor chip; an electrode line disposed at a periphery of the semiconductor chip; a bonding wire having a linearly extending main body portion and having a pad bonding portion and a lead bonding portion formed at respective ends of the main body portion and connected to the electrode pad and the electrode line, respectively; and a resin package sealing the semiconductor chip, the electrode line, and the bonding wire. Here, the bonding wire is made of copper, and the entire electrode pad and pad bonding portion are integrally covered with a water impermeable layer.US 2016 / 0 113 107 A1 shows a power module which has a substrate, a power chip, a bonding material and at least one spacer. The substrate includes a circuit patterned layer. The power chip is connected to the circuit-patterned layer through the bonding material. The spacer is located between the circuit patterned layer and the power chip to keep the power chip spaced from the circuit patterned layer.US 2016 / 0 035 691 A1 discloses a semiconductor device having an alloy layer arranged between a first Ag layer formed on a mounting plate or printed circuit board and a second Ag layer formed on a semiconductor element. Here, the alloy layer contains an intermetallic compound of Ag 3 Sn formed by Ag components of the first Ag layer and the second Ag layer, and Sn. A plurality of wires containing Ag are arranged to extend from an outward facing vicinity of the alloy layer.BRIEF DESCRIPTION OF THE INVENTIONProblems to be Solved by the InventionIn recent years, power semiconductor devices have increasingly higher internal current density in response to demand for downsizing and high output power, and are required to function at high temperature. Thus, it is necessary to transfer heat generated in a semiconductor element to a base plate more efficiently to dissipate the heat. It is also necessary to suppress the development of cracks when cracks are formed in a solder layer that connects a semiconductor element and an insulating substrate or an insulating substrate and a base plate.The object of the present invention is therefore to provide a power semiconductor device having high reliability and high thermal conductivity even in a high temperature operation.Means for Solving the ProblemsThe object is achieved by a power semiconductor unit having the features of claim 1, by a power semiconductor unit having the features of claim 2, and by a power semiconductor unit having the features of claim 3.Effects of the InventionIn the power semiconductor device according to the present invention, as described above, the layer thickness of the solder layer can be made uniform by the wire bumps, and also the occurrence of voids in the solder layer can be prevented. Further, the progress of cracks in the solder layer can be restrained or slowed, so that a power semiconductor device having high reliability and high thermal conductivity can be provided.BRIEF DESCRIPTION OF THE DRAWINGSThe figures show: FIG. 1 is a sectional view of a power semiconductor device according to a first embodiment of the present invention; FIG. 2 is an enlarged sectional view of a portion A of the power semiconductor device of FIG. 1 ; FIG. 3A is an enlarged sectional view of a portion of the power semiconductor device of FIG. 2 ; FIG. 3B is an enlarged sectional view of a portion of the power semiconductor device of FIG. 2 ; FIG. 4A is a plan view showing an arrangement of wire bumps of the power semiconductor device according to the first embodiment of the present invention; FIG. 4B is a plan view showing another arrangement of wire bumps of the power semiconductor device according to the first embodiment of the present invention; FIG. 4C is a plan view showing still another arrangement of wire bumps of the power semiconductor device according to the first embodiment of the present invention; FIG. 5 is a partial cross-sectional view of a power semiconductor device according to a second embodiment of the present invention; FIG. 6A is a plan view showing an arrangement of wire bumps of the power semiconductor device according to the second embodiment of the present invention; FIG. 6B is a sectional view taken along a direction A-A in FIG. 6A.EMBODIMENTS OF THE INVENTIONFirst EmbodimentFIG. 1 is a sectional view of a power semiconductor unit denoted as a whole by 100 according to a first embodiment of the present invention. FIG. 2 is an enlarged sectional view of the region A enclosed by a broken line in FIG. 1.The power semiconductor unit 100 includes a base plate 1. The base plate 1 is made of, for example, Cu. To the upper surface of the base plate 1, an insulating substrate 3 is fixed by a solder layer 7. The solder layer 7 is made of Sn, for example.As shown in FIG. 2, the insulating substrate 3 includes an insulating member 3 band conductor layers 3 a, 3 cdisposed on the front surface and the back surface of the insulating member 3 b, respectively. The insulating member 3 bis made of, for example, aluminum nitride, and the conductor layers 3 aand 3 care made of a metal such as copper. A semiconductor element 4 is fixed to the conductor layer 3 aof the insulating substrate 3 by means of the solder layer 7. The semiconductor element 4 is a power semiconductor element (a power unit) such as a MOSFET or an IGBT. As shown in FIG. 1, the semiconductor element 4 made of, for example, a Schottky barrier diode is fixed to the other conductor layer 3 a.The periphery of the base plate 1 is surrounded by a case 2 made of, for example, polyphenylene sulfide resin (PPS) or polybutylene terephthalate resin (PBT). A line connection 8 is arranged on the outer edge of the housing 2. The terminal 8 is made of, for example, copper or aluminum.An electrode (not shown) of the semiconductor element 4 and the terminal 8 are electrically connected by a bonding wire 6. The bonding wire 6 is made of, for example, copper or aluminum. Further, the inside of the case 2 is filled with a sealing material 5 so that the semiconductor element 4 and the bonding wire 6 are embedded. The sealing material 5 is made of, for example, a silicone gel.As shown in FIG. 2, a wire bump 9 as a spacer is disposed in the solder layer 7 connecting the conductor layer 3 aand the semiconductor element 4. The wire bump 9 is made of a material capable of forming an alloy with the material of the solder layer 7 under the bonding condition of the solder layer 7.The wire bump 9 only needs to be disposed in the solder layer 7 connecting the conductor layer 3 ato the semiconductor element 4; however, bonding connection portions 9 a, 9 bat both ends of a wire loop 9 dto the conductor layer 3 aby wedge bonding is preferable as shown in FIG. 3A, for example, because no positional deviation occurs.As described above, the wire bump 9 is formed by a bonding wire firmly bonded to the conductor layer 3 aof the insulating substrate 3 by wedge bonding. FIG. 3B is a sectional view of the wire bump 9 in a direction from the connection portion 9 ato the connection portion 9 b(hereinafter referred to as a "longitudinal direction"). As shown in FIG. 3 b, the wire bump 9 is preferably made of a bonding wire in which the connection portions 9 a, 9 bare bonded to the conductor layer 3 aat both ends, and further, in order to make the height of the wire bump 9 uniform, a wire loop portion 9 cdisposed sandwiched between the connection portions 9 a, 9 bis preferably in contact with the conductor layer 3 a.It is desirable that the distance between the two wedge bond connection regions 9 a, 9 bis 2.0 mm or less. This is because when the distance is larger than 2.0 mm, it is difficult to arrange the wire loop portion 9 cto be in contact with the conductor layer 3 abecause of a tension of the bonding wire when the one end of the bonding wire is attached to the semiconductor layer 3 aby wedge bonding and then the other end is attached by wedge bonding.When both ends of the one wire bump 9 are attached by wedge bonding and further a plurality of stitch bonding portions are provided therebetween, a wire loop is formed by the tension of the wire, and it becomes difficult to control the height of the bump, and therefore, the distance between the wedge bonding portion and the stitch bonding portion and the distance between adjacent stitch bonding portions are each preferably equal to 2.0 mm.Note that it is possible that the wire bump 9 is bonded to the conductor layer 3a only with a connection portion 9a (or 9b).The upper portion of the wire bump 9 is in contact with the back surface of the semiconductor element 4, and the wire bump 9 supports the semiconductor element 4.Figs. 4A to 4C show the arrangement of the wire bumps 9 on the conductor layer 3a. FIGS. 4A to 4C are plan views in a state where the wire bumps 9 are bonded to the conductor layer 3a, and omit an area above the solder layer 7. Further, broken lines 10 indicate a semiconductor element mounting area obtained by vertically projecting the semiconductor element 4 onto the conductor layer 3 a, and the semiconductor element 4 is placed on this area.As shown in FIG. 4A, the wire bumps 9 are arranged at the four corners of the semiconductor element mounting portion 10 such that the longitudinal direction of the wire bumps 9 is equal to a diagonal direction of the semiconductor element mounting portion 10. The wire bumps 9 may be arranged on a diagonal line of the semiconductor element mounting portion 10, or may be arranged so as not to be on a diagonal line but to be parallel to the diagonal line.In this way, the layer thickness of the solder layer 7 can be made more uniform for supporting the semiconductor element by disposing the wire bumps 9 at the four corners or near the four corners of the semiconductor element mounting portion 10.Moreover, since the wire bump is conventionally formed of an Al wire or the like which does not alloy with the solder 7a, wetting with the solder material and distribution thereof around the wire bump did not occur, and voids were formed in the solder layer 7. On the other hand, in the power semiconductor device 100 according to the first embodiment of the present invention, as described above, the wire bump 9 is formed of a material capable of alloying with the solder material of the solder layer 7 under the solder layer 7 forming condition. Thus, wetting with the solder material and spreading it around the wire bump 9 also occur, so that the generation of voids can be prevented. Further, an alloy may be formed at the interface between the wire bump 9 and the solder layer 7.The diameter of the wire used for the wire bump 9 is preferably equal to about 100 μm, but in order to increase the thickness of the solder layer 7 between the insulating substrate 3 and the semiconductor element 4 to improve the durability of the connection portion, a wire having a diameter of, for example, 150 μm may be used.On the other hand, in order to efficiently remove the heat generated in the semiconductor element 4 from the base plate 1 to the outside, the solder layer 7 is preferably as thin as possible, and in order to set the layer thickness of the solder layer 7 to about 50 μm, for example, the diameter of the wire used for the wire bump 9 may be about 50 μm, for example.Therefore, in the first embodiment of the present invention, as shown in FIG. 4A, the inclination of the semiconductor element 4 can be prevented by disposing the wire bumps 9 at the four corners or in the vicinity of the four corners of the semiconductor element mounting portion 10, and the layer thickness of the solder layer 7 connecting the conductor layer 3 aof the insulating substrate 3 to the semiconductor element 4 can be made more uniform.Further, as shown in FIG. 4B, in addition to the arrangement of FIG. 4A, four wire bumps 19 may be arranged on diagonal lines of the semiconductor element mounting portion 10. The four wire bumps 19 are preferably arranged equidistantly from the intersection of the diagonal lines. In FIG. 4B, the longitudinal direction of the wire bump 19 is a direction parallel to one side of the semiconductor element mounting portion 10, but another direction may be used. The number of the wire bumps 19 is not limited to four, but it is preferable to arrange the wire bumps 19 at equal intervals on the diagonal lines.For example, when the semiconductor element 4 is attached to the conductor layer 3 awith a substrate bonding, the semiconductor element 4 may warp or warp due to the applied heat, but the warping or warping of the semiconductor element 4 may be suppressed by disposing the wire bump 19 so that the layer thickness of the solder layer 7 can be made uniform.Note that the wire bumps 19 need only be relatively uniformly arranged in the semiconductor element mounting region 10, and there is no particular limitation on the position, number, and arrangement direction thereof.Further, as shown in FIG. 4C, the wire bumps 9 of FIG. 4B may be arranged such that the longitudinal direction thereof is perpendicular to the diagonal line of the semiconductor element mounting portion 10.In general, during operation of the semiconductor element 4, stresses generated in the solder layer 7 due to the difference in linear expansion coefficients between the semiconductor element 4 and the insulating substrate 4 concentrate near the four corners of the solder layer 7 of the semiconductor element mounting portion 10, and there cracking starts in the solder layer 7.In the first embodiment of the present invention, the wire bump 9 is made of a material capable of alloying with the solder material of the solder layer 7. Then, in a usual solder bonding process, an alloy such as Cu 6 Sn 5 or Cu 3 Sn is formed at the interface between the solder layer 7 and the wire bump 9. Such alloys have higher mechanical strength and higher fatigue resistance than those of the solder layer 7. Note that in the center of the wire bump 9 having such alloys formed at its interface, Cu may remain.Therefore, the progress of cracks caused at the four corners of the solder layer 7 can be restrained by the wire bumps 9 by arranging such wire bumps 9 having an alloy with such high mechanical strength formed on the surface of the four corners of the semiconductor element mounting portion 10. In particular, the crack stopping effect can be enhanced by arranging the wire bumps 9 such that the longitudinal direction thereof is perpendicular to the diagonal line of the semiconductor element mounting portion 10.As for the arrangement of the wire bumps 9, it is possible to appropriately select between the arrangement in which the longitudinal direction of the wire bumps 9 is parallel to the diagonal line of the semiconductor element mounting portion 10 (see FIG. 4A ) and the arrangement in which the longitudinal direction of the wire bumps 9 is perpendicular thereto (see FIG. 4C ).Although the cracks that have reached and are stopped at the wire bump 9 may continue along the wire bump 9, the stresses generated in the solder layer 7 arise from the four corners toward the center, and therefore the path on which the cracks develop may be extended by arranging the wire bump 9 as shown in FIG. 4C having an angle with respect to the diagonal line. Thereby, destruction of the solder layer 7 can be slowed down, and thus destruction of the semiconductor element 4 can be slowed down.Here, if the semiconductor element 4 is square, it is most efficient to set the longitudinal direction of the wire bump 9 perpendicular to the diagonal line of the semiconductor element mounting portion 10 as described above. On the other hand, when the semiconductor element 4 is not square, the wire bump 9 may be disposed such that the longitudinal direction of the wire bump 9 has a certain angle, that is, an angle of more than 0° and not more than 90° with respect to the diagonal line of the semiconductor element mounting portion 10.Moreover, a plurality of wire bumps 9 may be disposed on the entire semiconductor element mounting region 10 such that the longitudinal direction of the wire bump 9 has a certain angle with respect to the diagonal line of the semiconductor element mounting region 10. In this case, the distance between the centers of adjacent wire bumps 9 is preferably about twice the diameter of the wire bumps 9, thereby considering the fact that the width of the connection portion of the wire bump 9 is increased by ultrasonic bonding up to about twice the diameter of the wire bump 9.Next, the materials of the solder layer 7 capable of forming an alloy and the wire bump 9 will be described. As described above, when the wire bump 9 is formed of a material capable of forming an alloy with the solder material of the solder layer 7, the generation of voids in the solder layer 7 can be prevented, and the heat generated in the semiconductor element 4 can be efficiently dissipated from the base plate 1 via the solder layer 7. When the solder layer 7 is soldered, the wire bump 9 is reduced in a reducing atmosphere, for example, a hydrogen atmosphere or a formic acid atmosphere, and then the solder layer 7 is melted.For the solder layer 7, a Sn-based solder such as a pure Sn solder, a Sn-Ag-Cu-based solder, a Sn-Cu-based solder, and further a solder containing Sn as a main component and to which Ni or Sb is added are used.In this case, as the material of the wire bump 9, Cu or a Cu alloy is used as the material capable of forming an alloy with the Sn type solder material under usual solder conditions. The alloy formed at the interface between the solder layer 7 and the wire bump 9 is made of, for example, Cu 6 Sn 5 or Cu 3 Sn.Table 1 shows the melting point, Young's modulus, tensile strength, linear expansion coefficient, and thermal conductivity of Sn, Cu, Sn-0.7Cu, Cu 6 Sn 5 and Cu 3 Sn. Table 1 Table 1Melting point [° C.]2321083227415676Young's modulus [GPa]53,011034,0110140Tensile Strength [MPa]28,019532,2310507Vickers hardness [Hv]-55 from 120 to 12012,9378343Linear expansion coefficient [× 10-6 / K]22,316,522,616,319,0Thermal conductivity [W / m·K]66,840162,934,170As is apparent from Table 1, the melting points of Cu 6 Sn 5 are higher than the melting point 232° C. of Sn as the base material of the solder layer 7 and are respectively 415° C. and 676 ° C. In terms of mechanical strength, the Young's modulus for Sn, Cu 6 Sn 5 and Cu 3 Sn is 53.0 GPa, 110 GPa and 140 GPa, and the tensile strength for Sn, Cu 6 Sn 5 and Cu 3 Sn is 28.0 MPa, respectively, 310 MPa and 507 MPa, respectively.Therefore, the alloys Cu 6 Sn 5 and Cu 3 Sn formed at the interface between the solder layer 7 and the wire bump 9 are temperature resistant and are highly reliable alloys having melting points higher than those of the Sn solder and the Sn-0.7Cu solder as the base materials of the solder layer 7, and also have high mechanical strength.As a combination of the materials of the solder layer 7 and the wire bump 9, a Zn-based solder material as a material of the solder layer 7 and Al or an Al alloy as a material of the wire bump 9 may be combined.For the insulating member 3 bof the insulating substrate 3, not only ceramics such as Al 2 O 3, AlN, and Si 3 N 4, but also an organic insulating material in which a filler such as silica, alumina, BN, or the like is mixed or kneaded with a binder such as an epoxy or a liquid crystal polymer can be used.The material of the conductor layers 3 a, 3 cof the insulating substrate 3 is preferably Cu, but a material obtained by plating Cu with Ni may also be used. Alternatively, a material obtained by plating Al with Ni may be used.For the base plate 1, for example, a Cu plate or an AlSiC plate is used, but if the power semiconductor unit 100 has sufficient strength for use, a structure without the base plate 1, that is, a structure in which the conductor layer 3 cis exposed on the rear side of the insulating substrate 3 may also be adopted.For the semiconductor element 4, an SiC MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or an SiC-SBD (Schottky Barrier Diode) using SiC as a base material capable of high temperature operation, an Si-IGBT (Insulated Gate Bipolar Transistor) using Si as a base material, or an Si-FWD (Free Wheeling Diode) is used.The bonding wire 6 is, for example, an Al wire, and is bonded to the front surface of the semiconductor element 4 by wedge bonding. The bonding wire 6 may be, for example, a Cu wire. In place of the bonding wire 6, a plate-like conductor may be used. If a plate-like conductor is used for bonding to the semiconductor element 4 instead of the wedge bonding, the upper surface of the semiconductor element 4 is plated with Ni / Au, for example, and a plate-like conductor is bonded thereto by means of a solder or a sintered Ag material.The sealing material 5 is, for example, a silicone gel, but may be an epoxy material mixed or kneaded with a filler as long as the sealing material 5 has sufficient insulating properties for use.Second EmbodimentFIG. 5 is an enlarged sectional view of a partial region of a power semiconductor unit 200 according to a second embodiment of the present invention, and the same reference numerals as those in FIG. 1 denote the same or corresponding regions. In the power semiconductor unit 200, a wire bump 29 capable of forming an alloy with the material of the solder layer 7 is disposed between the base plate 1 and the conductor layer 3 cof the insulating substrate.The wire bumps 29 are arranged substantially in the same manner as in the first embodiment, and the wire bumps 29 are arranged, for example, directly below the conductor layer 3c of the insulating substrate 3, that is, for example, at the four corners of a rectangular conductor layer mounting portion (corresponding to the semiconductor element mounting portion in the first embodiment) obtained by vertically projecting the conductor layer 3c onto the base plate 1 in parallel with a diagonal line of the conductor layer mounting portion. When the wire bumps 29 are formed in this manner, the layer thickness of the solder layer 7 can be made uniform. A plurality of wire bumps 29 may be arranged, as shown in FIG. 4B, for example.Further, as shown in FIG. 4C of the first embodiment, for example, the wire bumps 29 may be disposed at or near the four corners of the conductor layer mounting portion at an angle greater than 0° and equal to or less than 90° with respect to the diagonal line of the conductor layer mounting portion, and more specifically at 90°. Accordingly, the progress of cracks due to a difference in the linear expansion coefficients of the base plate 1 and the insulating substrate 3 can be restrained by the wire bump 29 even if a crack proceeds from the vicinity of the four corners to the solder layer 7.Moreover, by forming the wire bump 29 from a material capable of forming an alloy with the solder layer 7, the generation of voids in the solder layer 7 can be prevented, and the heat generated in the semiconductor element 4 can be efficiently dissipated from the base plate 1 via the solder layer 7.The combination of the material of the wire bump 29 and the material of the solder layer 7 is the same as the combination in the first embodiment.Here, the diameter of the wire bump 9 is preferably equal to about 200 μm, but when the solder layer 7 between the insulating substrate 3 and the base plate 1 has a layer thickness of 300 μm or more, in order to improve the structure of the connection portion in terms of the durability, the diameter of the wire bump 9 may be equal to about 300 μm. In order to efficiently remove the heat from the semiconductor element 4 from the base plate 1, the diameter of the wire bump 9 may be about 100 μm as long as the thickness of the solder layer 7 is reduced to about 100 μm.FIG. 6A is a plan view of the base plate 1 before soldering of the insulating substrate 3. FIG. 6B is a sectional view taken along a direction A-A in FIG. 6A.As shown in FIGS. 6A and 6B, a plurality of wire bumps 39 are arranged in a solder layer forming region 20 on the base plate 1. The wire bumps 39 are arranged at a predetermined angle with respect to a diagonal line of the solder layer forming portion 20. The wire bumps 39 arranged on a diagonal line are preferably parallel to each other and are arranged at equal intervals. In FIGS. 6A and 6B, the solder layer forming portion 20 is surrounded by a photoresist 11 to prevent wetting by and spreading out of the solder layer forming portion 20 at the time of soldering.While the wire bumps are arranged to surround the four sides to divide the region in FIGS. 6A and 6B by four wires, one wire may be arranged to surround the four corners using the stitch bond, but wetting by the solder occurs in a region where the wire is not arranged, and the solder spreads in this region so that respective wires do not contact each other in the end region.When the wire bumps 39 are arranged in this manner, the layer thickness of the solder layer 7 is made uniform, and also the generation of voids in the solder layer 7 can be prevented by forming the wire bump 39 from a material capable of forming an alloy with the material of the solder layer 7.Specifically, by arranging the wire bumps 39 as shown in FIG. 6A, the progress of cracks can be restrained by the wire bumps 39, even if cracks are formed at the four corners of the solder layer 7 due to a difference in the linear expansion coefficients of the base plate 1 and the insulating substrate 3. Specifically, the path on which cracks develop becomes longer by arranging the plurality of wire bumps 39, and the durability of the solder layer 7 is improved.Here, for example, when the Sn-0.7Cu solder is used as a material of the solder layer 7 and Cu is used as a material of the wire bump 39, at room temperature, only 0.7 wt % of Cu forms a mixed crystal with Sn, as can be seen from the state diagram of Cu-Sn. For this reason, Cu, which cannot form mixed crystal for forming an alloy, precipitates around the wire bump 39 made of Cu when Sn-0.7Cu is melted at the time of soldering and cooled to room temperature. After soldering, the Cu wire bump 39 exists as it is as a Cu material.The thermal conductivity of Cu is 401 W / m·K, and thus is larger than that of Sn and an Sn-Cu alloy having a thermal conductivity of 66.8 W / m·K. Thus, the apparent thermal conductivity of a connection portion made up of the solder layer 7 and the wire bump 39 increases, so that the heat dissipation property can be improved compared to a case only with the solder layer 7 without the wire bump 39.Shrinkage of the volume occurs when the solder solidifies from a liquid phase into a solid phase. For this reason, during the cooling process after the soldering, so-called shrinkage cavities or voids may be formed in the solder layer 7 depending on the temperature distribution of the base plate 1. By arranging the wire bumps 39 as shown in FIGS. 6A and 6B, on the other hand, the region where the solder contracts is divided by the wire bump 39, and generation of shrinkage voids or voids is suppressed, so that solder defects can be reduced.Further, the wire bump 39 shown in FIG. 6A may be formed by bonding the wire bumps 39 made of Cu wires having a diameter of, for example, 200 μm at intervals of 400 μm. This is because, when the distance between the wire bumps 39 is decreased, the wedge device comes into contact with the adjacent wire bump 39 at the time of bonding, and desired bonding cannot be achieved. Therefore, the distance between the adjacent wire bumps 39 is preferably equal to or larger than 1.5 times the diameter of the wire bump 39.Moreover, when both ends of the one wire bump 39 are attached to the base plate 1 by wedge bonding and further there are a plurality of stitch bonding portions therebetween, a wire loop is formed by the tension of the wire, so that control of the height of the bump is difficult. Therefore, it is desirable that the distance between the wedge bond connection portion and the stitch bond connection portion and the distance between adjacent stitch bond connection portions are each less than 2.0 mm to prevent the formation of a wire loop.While the first embodiment describes the power semiconductor device 100 in which the wire bump is disposed in the solder layer 7 between the insulating substrate 3 and the semiconductor element 4, and the second embodiment describes the power semiconductor device 200 in which the wire bump is disposed in the solder layer 7 between the base plate 1 and the insulating substrate 3, one power semiconductor device may include both types of wire bumps.Note that the effect of suppressing shrinkage voids or voids is greater when the wire bump 9 is disposed in the solder layer 7 between the base plate 1, which has a large soldering area and a high degree of volume shrinkage at the time of soldering, and the insulating substrate 3.Moreover, the solder layer 7 between the base plate 1 and the insulating substrate 3 described in the first embodiment and the solder layer 7 between the insulating substrate 3 and the semiconductor element 4 described in the second embodiment may be formed of the same material or different materials.The invention encompasses in particular the following aspects.Aspect 1. power semiconductor device comprising:an insulating substrate having a conductor layer at least on a front surface of the insulating substrate;a wire bump disposed on the conductor layer;a semiconductor element placed on the wire bump; anda solder layer for bonding the conductor layer and the semiconductor element on the conductor layer, wherein an alloy consisting of a material of the wire bump and a material of the solder layer is disposed at an interface between the wire bump and the solder layer.Aspect 2. the power semiconductor device according to aspect 1, wherein the thermal conductivity of the wire bump is greater than the thermal conductivity of the solder layer.Aspect 3. The power semiconductor device according to Aspect 1, wherein the wire bump is made of a bonding wire in which both ends of the wire bump have wedge bonding connection portions in the conductor layer.Aspect 4. the power semiconductor device according to Aspect 3, wherein the bonding wire further includes a plurality of stitch bonding regions in the conductor layer between the wedge bonding regions, and the distance between each of the wedge bonding regions and each of the stitch bonding regions and the distance between the stitch bonding regions adjacent to each other are each 2 mm or less.Aspect 5. the power semiconductor device according to Aspect 1, wherein the wire bump is disposed at each of four corners of a semiconductor element mounting portion in a rectangular shape obtained by vertically projecting the semiconductor element onto the conductor layer.Aspect 6. the power semiconductor device according to Aspect 5, wherein a longitudinal direction of the wire bump is orthogonal to a diagonal line of the semiconductor element mounting portion.Aspect 7. the power semiconductor device according to Aspect 5, wherein the longitudinal direction of the wire bump crosses with a diagonal line of the semiconductor element mounting portion at an angle of more than 0° and equal to or less than 90°.Aspect 8. the power semiconductor device according to any one of Aspects 5 to 7, wherein the wire bump is further disposed in the semiconductor element mounting region.Aspect 9: A power semiconductor device comprising:a base plate;a plurality of wire bumps disposed on the base plate;an insulating substrate placed on the wire bumps and having a conductor layer at least on a back surface of the insulating substrate; anda solder layer for bonding the conductor layer of the insulating substrate to the base plate,wherein an alloy made of a material of the wire bumps and a material of the solder layer is formed at an interface between each of the wire bumps and the solder layer.Aspect 10. the power semiconductor device according to aspect 9, wherein the thermal conductivity of the wire bump is greater than the thermal conductivity of the solder layer.Aspect 11: The power semiconductor device according to Aspect 9, wherein each of the wire bumps includes wedge bond connection portions attached to the conductor layer by wedge bonding at both ends of the wire bump, and a plurality of stitch bond connection portions in which a bonding wire is attached to the conductor layer by stitch bonding between the wedge bond connection portions, and the distance between each of the wedge bond connection portions and each of the stitch bond connection portions and the distance between the stitch bond connection portions adjacent to each other are each equal to or less than 2.0 mm.Aspect 12 The power semiconductor device according to Aspect 9, wherein the wire bumps are respectively disposed at the four corners of a semiconductor element mounting portion in a conductor layer mounting portion in a rectangular shape obtained by vertically projecting the conductor layer onto the base plate.Aspect 13. the power semiconductor device according to Aspect 12, wherein the longitudinal direction of each of the wire bumps crosses with a diagonal line of the conductor layer mounting portion at an angle of more than 0° and equal to or less than 90°.Aspect 14. The power semiconductor device according to Aspect 9, further comprising a solder layer forming portion on the base plate in which the solder layer is disposed, wherein the wire bumps are disposed at the four corners of the solder layer forming portion and inside the solder layer forming portion.Aspect 15. The power semiconductor device according to any one of aspects 1 to 14, wherein each of the wire bumps is made of Cu, and the solder layer is made of a Sn-based solder material.Aspect 16. The power semiconductor device according to aspect 15, wherein the alloy made of a material of the wire bump and a material of the solder layer is Cu 6 Sn 5 or Cu 3 Sn.Aspect 17. The power semiconductor device according to any one of aspects 1 to 16, wherein the solder layer between the base plate and the insulating substrate and the solder layer between the insulating substrate and the semiconductor element are made of different materials.DESCRIPTION OF REFERENCE NUMERALS1 Base plate 2 Case 3 Insulating substrate 4 Semiconductor element 5 Sealing material 6 Bonding wire 7 Solder layer 8 Terminal 9 Wire bump 10 Semiconductor element mounting portion 11 Photoresist 20 Solder layer forming portion 100 Power semiconductor unit 200 Power semiconductor unit

Claims

A power semiconductor device (100) comprising: - a metal layer (3), - a semiconductor element (4) bonded to the metal layer (3) via a solder layer (7), and - a wire bump (9) extending in the in-plane direction of the solder layer (7) and bonded to the metal layer (3), - wherein an alloy of the material of the wire bump (9) and the material of the solder layer (7) is disposed at the interface between the wire bump (9) and the solder layer (7), and - wherein the wire bump (9) is bonded to the metal layer (3) only through a wedge bond connection portion.A power semiconductor device (100) comprising: - a metal layer (3), - a semiconductor element (4) bonded to the metal layer (3) via a solder layer (7), and - a wire bump (9) extending in the in-plane direction of the solder layer (7) and disposed on the metal layer (3) without having a connection portion with the metal layer (3), - wherein an alloy of the material of the wire bump (9) and the material of the solder layer (7) is disposed at the interface between the wire bump (9) and the solder layer (7).A power semiconductor device (100) comprising: - a metal layer (3), - a semiconductor element (4) bonded to the metal layer (3) via a solder layer (7), and - a wire bump (9) extending in the in-plane direction of the solder layer (7) and bonded to the metal layer (3), - wherein an alloy of the material of the wire bump (9) and the material of the solder layer (7) is disposed at the interface between the wire bump (9) and the solder layer (7), and - wherein the wire bump (9) is a bonding wire having wedge bond connection portions at both ends with the metal layer (3).The power semiconductor device (100) according to any one of claims 1 to 3, wherein the wire bump (9) suppresses generation of cracks in the solder layer (7).The power semiconductor device (100) according to claim 3, wherein the distance between the wedge bond connection regions is 2.0 mm or less.The power semiconductor device (100) according to claim 3, wherein the bonding wire includes a plurality of stitch bonding regions with the metal layer (3) between the wedge bonding regions.The power semiconductor device (100) according to claim 6, wherein the distance between the wedge bond connection region and the stitch bond connection region and the distance between the adjacent stitch bond connection regions, respectively, are equal to or less than 2 mm.The power semiconductor device (100) according to any one of claims 1 to 7, wherein the thermal conductivity of the wire bump (9) is higher than the thermal conductivity of the solder layer (7).The power semiconductor device (100) according to any one of claims 1 to 8, wherein the wire bump (9) is made of Cu or an alloy of Cu.The power semiconductor device (100) according to claim 9, wherein the alloy consisting of the material of the wire bump (9) and the material of the solder layer (7) is Cu 6 Sn 5 or Cu 3 Sn.The power semiconductor device (100) according to any one of claims 1 to 10, wherein the wire diameter of the wire bump (9) is 50 μm or larger.The power semiconductor device (100) according to any one of claims 1 to 10, wherein the wire diameter of the wire bump (9) is 100 μm or larger.

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