METHOD AND DEVICE FOR REDUCING OUTPUT VOLTAGE RISP IN HYSTERETIC UPWARD OR DOWNWARD UPWARD CONVERTER

Abstract

Control unit for a converter (500), the control unit comprising: a clock generation circuit (506) that generates a periodic clock signal containing periodic clock pulses; and a control circuit (550) that causes the clock generation circuit (506) to asynchronously initiate a clock pulse based on a difference between a feedback voltage of the converter (500) and a reference voltage, wherein the control circuit (550) causes the clock generation circuit (506) to generate the clock pulse asynchronously based on a determination that the to initiate feedback voltage is smaller than the reference voltage, wherein the clock generation circuit (506) comprises a current source (521) coupled to a capacitor (522); and wherein the control circuit (550) includes a pull-up circuit (530) which pulls up a voltage of the capacitor (522) when the feedback voltage is less than the reference voltage in order to cause the clock generation circuit (506) to initiate a clock pulse asynchronously.

Description

CROSS-REFERENCE TO RELATED REGISTRATION

[0001] This application claims the benefits of the preliminary US patent application No. 62 / 617,931 filed on January 16, 2018. TECHNICAL AREA

[0002] The present application relates generally to controls for boost, buck-boost or flyback converters and specifically to reducing the output voltage ripple in hysteretic boost or buck-boost converters. SUMMARY

[0003] Hysteretic boost-up or buck-boost converters, and especially hysteretic boost-up or buck-boost converters with non-continuous current-flow mode or limiting-line mode, are commonly used for low-power applications and have a relatively simple construction. These converters typically include a switch, such as a switching field-effect transistor (FET), an inductor, a diode, and an output capacitor. When the FET is on, the inductor is charged, and no power is delivered to the output. In this state, the output capacitor is discharged. When the FET is off, the diode turns on, and the energy in the inductor is discharged to charge the output capacitor.

[0004] The converter is typically designed for operation with a fixed duty cycle and frequency and monitors the output voltage. The FET is controlled by a clock pulse and switches on based on the monitored output voltage. Specifically, the rising edge of the clock pulse represents a decision point where, by comparing the output voltage to a fixed reference voltage, it is determined whether the next pulse should be initiated to switch on the FET. If the output voltage is lower than the fixed reference voltage, the next switching pulse is initiated with the fixed duty cycle and frequency. However, if the output voltage is higher than the reference voltage, the pulse is not initiated.The resulting output voltage includes an unwanted ripple that varies depending on the load, and the variation in ripple can become relatively large if the output capacitor is relatively small.

[0005] Document US 2006 / 0 055 387 A1 discloses a PWM power control that sets a PWM control signal synchronously to a clock signal of the PWM control and also asynchronously to the clock signal.

[0006] Document US 2016 / 0172967A1 discloses a switching power supply circuit that includes a comparator circuit and an operating control circuit.

[0007] Document US 8 330 437 B1 discloses a device comprising a sawtooth generator configured to produce a sawtooth voltage, wherein the sawtooth generator is configured to repeatedly reset the sawtooth voltage using a clock signal.

[0008] Document US 5 956 239 A discloses an error summation block containing a window comparator, the input of which is fed with the output voltage of the converter before filtering by the low-pass filter, and to which a low-threshold and a high-threshold reference voltage are applied, both referenced to the reference voltage of the converter.

[0009] Document US 2017 / 0187286A1 discloses methods and devices for DC-DC power regulators.

[0010] In particular, it shows Fig. 1. The waveforms of a boost converter (or buck-boost converter) implemented with a controller such as the Microchip® HV9150 when operating under full load. As shown in Fig. As shown in Figure 1, the output voltage Vo is indeed reduced when the gate of the switching FET is high (voltage GT, shown in waveform 101, is high), as shown in waveform 102. As stated above, in a boost converter (or buck-boost converter), when the switching FET is on, the inductor is charged and no power is delivered to the output, and the output capacitor is discharged. When the switching FET is off, the diode turns on, and the energy in the inductor is supplied to the output capacitor and the load.

[0011] As stated above, during operation the rising edge of each gate pulse (GT) is a decision point at which the output voltage Vo is compared to a reference voltage REF. If the output voltage Vo is less than the reference voltage REF, the next gate pulse is initiated, as in the first three gate pulses (GT) in Fig. Figure 1 shows that if the output voltage Vo exceeds the reference voltage REF at the decision point, the next gate pulse to charge the inductor is not initiated. As shown in Figure 1, the following applies: Fig. As shown in Figure 1, the fourth gate pulse 103 (shown in dashed lines) is skipped because, at the moment the fourth gate pulse is initiated (decision point), the output voltage Vo would exceed the reference voltage REF. As also shown in Figure 1, the fourth gate pulse 103 (shown in dashed lines) is skipped because the output voltage Vo would exceed the reference voltage REF at the moment the fourth gate pulse is initiated (decision point). Fig. As shown in Figure 1, the next gate pulse is initiated according to the fixed frequency, since the gate pulse has a fixed frequency, even if the output voltage falls below the reference voltage REF before the next gate pulse is initiated. In other words, there is a delay t. d1 from the moment the output voltage Vo becomes less than the reference voltage REF until the next gate pulse is initiated. There is also a further delay t. d2from the initiation of the pulse until the moment the boost diode begins to conduct and supplies energy to the output capacitor and the load. The delay t d2 is a fixed delay that corresponds to the programmed switch-on time of the switch. The delay t d1 is variable based on the load condition and can be any number from zero up to one switching cycle.

[0012] Synchronizing the gate pulse with the comparator output (i.e., resetting the clock when the output voltage Vo falls below the reference voltage REF) can help to reduce either the delay t d1 to completely eliminate or t d1to a fixed delay, which would eliminate variability. This will help to significantly reduce the ripple (typical figures are about a 40-50% reduction in output ripple at full load). According to one or more exemplary embodiments, a controller is provided for controlling a converter, wherein the controller may include a clock generation circuit that generates a periodic clock signal containing periodic clock pulses, and a control circuit that causes the clock generation circuit to asynchronously initiate a clock pulse based on a difference between a feedback voltage of the converter and a reference voltage. The asynchronously initiated clock pulse may be configured to activate a switch of the converter.

[0013] The control circuit can cause the clock generation circuit to initiate the clock pulse asynchronously based on a determination that the feedback voltage is smaller than the reference voltage.

[0014] In one or more exemplary embodiments, the clock generation circuit can include a current source coupled to a capacitor. The control circuit can include a pull-up circuit that pulls up the capacitor voltage when the feedback voltage is lower than the reference voltage, causing the clock generation circuit to asynchronously initiate a clock pulse.

[0015] The controller can also include a pulse-width modulation (PWM) circuit that modulates the width of the asynchronously introduced clock pulse based on a difference between the feedback voltage and the reference voltage. The PWM circuit can include a sample-and-hold circuit that samples the feedback voltage, and a comparator that compares the sampled feedback voltage to the reference voltage. Compared to using a fixed pulse width, modulating the pulse width can help reduce output voltage ripple.

[0016] The pulse-width modulation circuit can linearly reduce the width of the asynchronously introduced clock pulse if the sampled feedback voltage is greater than the reference voltage or a fraction thereof. Conversely, the pulse-width modulation circuit can control the width of the asynchronously introduced clock pulse according to a maximum on-time if the sampled feedback voltage is less than the reference voltage.

[0017] According to one aspect of one or more exemplary embodiments, a method for controlling the output voltage ripple of a converter may also be provided. The method may include generating a periodic clock signal containing periodic clock pulses, determining a difference between a feedback voltage of the converter and a reference voltage, and asynchronously introducing a clock pulse based on this difference. The method may also include activating a switch of the converter using the asynchronously introduced clock pulse.

[0018] The asynchronous clock pulse can be initiated when it is determined that the feedback voltage is lower than the reference voltage. The step of asynchronously initiating a clock pulse may involve using a pull-up circuit to asynchronously initiate the clock pulse when the feedback voltage is lower than the reference voltage.

[0019] The method according to one or more exemplary embodiments can include modulating the width of the asynchronously introduced clock pulse based on a difference between the feedback voltage and the reference voltage. The step of modulating the width of the clock pulses can include reducing the width of the asynchronously introduced clock pulse as the feedback voltage approaches the reference voltage. The method can also include sampling the feedback voltage and comparing the sampled feedback voltage with the reference voltage. The step of modulating the width of the asynchronously introduced clock pulse can include linearly reducing the width of the asynchronously introduced clock pulse when the sampled feedback voltage is greater than a fraction of the reference voltage.The step of modulating the width of the asynchronously introduced clock pulse can include controlling the width of the asynchronously introduced clock pulse according to a maximum on-time if the sampled feedback voltage is smaller than the reference voltage. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 illustrates voltage waveforms of a step-up or step-down step-up converter according to the state of the art. Fig. Figure 2 illustrates voltage waveforms of a boost or buck-boost converter controlled by a control circuit according to an exemplary embodiment. Fig. Figure 3 illustrates voltage waveforms of a boost or buck-boost converter at low load, controlled by a state-of-the-art control circuit. Fig. Figure 4 illustrates voltage waveforms of a boost or buck-boost converter at low load, controlled by a control circuit according to an exemplary embodiment. Fig. Figure 5A illustrates a converter and a control circuit for controlling the converter according to an exemplary embodiment. Fig. Figure 5B illustrates an exemplary embodiment of the clock circuit of Fig. 5. Fig. Figure 6 illustrates voltage waveforms of a boost or buck-boost converter with turn-on time modulation at full load according to an exemplary embodiment. Fig. Figure 7 illustrates voltage waveforms of a boost or buck-boost converter, controlled by turn-on time modulation at low load according to an exemplary embodiment. Fig. Figure 8 illustrates a switch-on time modulation control circuit according to an exemplary embodiment. DETAILED DESCRIPTION OF EXAMPLE EXECUTIONS

[0020] Detailed reference is now made to the following exemplary embodiments, which are illustrated in the accompanying drawings, where identical reference numerals consistently refer to identical elements. The exemplary embodiments can be implemented in various forms, without being limited to those presented herein. Descriptions of well-known parts are omitted for clarity.

[0021] Fig. Figure 2 shows the effect of synchronizing the clock with the comparator output according to one or more exemplary embodiments. By synchronizing the gate pulse with the comparator output (i.e., resetting the clock when the output voltage Vo falls below the reference voltage REF), the delay t can be reduced. d1completely eliminated or the delay t d1 fixed, which would eliminate the variability. This will help to significantly reduce the ripple (typical figures are around a 40-50% reduction of the initial ripple at full load). It should be noted that the waveforms shown are not completely steady state (for both Fig. 1 and Fig. 2), but they show the ripple reduction with reasonable accuracy. As in Fig. As shown in Figure 2, the fourth gate pulse of gate voltage waveform 201 is initiated when the output voltage Vo, shown in waveform 202, equals the reference voltage Vo, instead of waiting for the next pulse to be initiated based on the fixed frequency. In other words, the decision point at which the converter compares the output voltage to the reference voltage to decide whether to initiate or skip the next cycle has shifted compared to Fig. 1 changed. In Fig. 1. The decision point is based on the fixed duty cycle and corresponds to the time at which the next rising pulse edge would occur, regardless of whether the output voltage is lower than the reference voltage. In contrast, in Fig. 2. The decision point is not fixed, but corresponds to the time at which the output voltage falls below the reference voltage. This results in a delay t. d1eliminated, and the ripple of the output voltage Vo is also reduced.

[0022] Fig. Figure 3 shows the operation of the converter for a low-load case according to the state of the art. In this case, the delay times t play a role. d1 and t d2 no significant role, as the rate of decline of the output voltage is very small (because it is lightly loaded).

[0023] The main cause of the ripple is the amount of energy pumped into the capacitor. When the output is lightly loaded, the output voltage Vo, shown in waveform 302, does not fall much below the reference voltage REF when the next pulse of the gate voltage GT, shown in waveform 301, is initiated. At this point, the pre-programmed keying pulse of the gate voltage GT is initiated, causing the output voltage Vo to overshoot significantly above the reference voltage REF.

[0024] This effect can be mitigated by internally reducing the pulse width to a fraction of the pre-programmed pulse width. The extent of the required reduction can be determined based on measuring the overshoot of a previous cycle. To measure the output voltage overshoot during the previous cycle, the output voltage is sampled at a specified sampling time. The sampling time can be optimized to measure as close as possible to the peak output voltage. Fig. Figure 4 shows the effect of reducing the on-time during low-load operation and thus reducing the amount of energy that must be supplied to the output capacitor and the load during the off-time, according to one or more exemplary embodiments. As shown in Fig. As shown in Figure 4, the duty cycle of the gate pulse (waveform 401) is reduced, thereby decreasing the amount by which the output voltage Vo (waveform 402) exceeds the reference voltage REF after the gate pulse has been reintroduced.

[0025] Fig. Figure 5A shows a converter 500 and a control circuit 550 for controlling the converter 500 according to an exemplary embodiment. With reference to Fig. In the exemplary embodiment shown, converter 500 includes a switching FET 501, an inductor 502, a diode 503, and an output capacitor 504, which serve to supply energy to a load 505. As explained above, when FET 501 is switched on, inductor 502 is charged, and no power is delivered to output capacitor 504. In this state, output capacitor 504 is discharged and supplies energy to the load 505. When FET 501 switches off, diode 503 switches on, and the energy in inductor 502 is discharged to charge output capacitor 504.

[0026] The control circuit 550 of the exemplary embodiment of Fig. 5 controls the switching of FET 501 and may include an internal clock generator 506, which generates a clock signal CLK that is output via a bistable flip-flop 508 to one input of an AND gate 507. The other input of the AND gate 507 receives the output of a comparator 509, which compares a feedback voltage VFB with a reference voltage VREF. According to one or more exemplary embodiments, the feedback voltage VFB can represent the output voltage Vo after being divided by a resistor divider 510. When the feedback voltage VFB falls below the reference voltage VREF, the output of the comparator 509 goes high, causing the AND gate 507 to output Q (Q). out) of the bistable multivibrator 508, which can represent the clock signal CLK to the switching FET 501, and turns the switching FET 501 on. The exemplary control circuit 550 can also include a pulse-width modulation circuit 511, which can control the duration of the turn-on time of the switching FET 501. For example, the pulse-width modulation circuit 511 can output a reset signal RST to a reset input of the bistable multivibrator 508. According to an exemplary embodiment, the output of the bistable multivibrator 508 goes low when the reset signal RST goes high, thereby turning off the switching FET 501. Accordingly, the width of the gate signal applied to the switching FET 501 can be controlled, as described below with reference to Fig. 8 explained in more detail.

[0027] Fig. Figure 5B shows an exemplary embodiment of the [document / model] described in [reference]. Fig. Figure 5A shows clock 506, which can synchronize the gate pulse with the output of comparator 509, which compares the feedback voltage VFB with the reference voltage REF. In this configuration, the gate pulse signal of FET 501 is synchronized with the output of comparator 509, so that the gate signal becomes high when the feedback voltage VFB falls below the reference voltage VREF. Synchronizing the clock in this way can reduce the ripple of the output voltage under higher load conditions.

[0028] More specifically, as in Fig. As shown in Figure 5B, the internal clock signal Ramp is generated by a current source 521 into a capacitor 522. The current source 521 can be programmed via an external resistor (not shown). The internal clock signal Ramp is reset to zero when the voltage across the capacitor 522 reaches an internal fixed voltage VTS. Specifically, a comparator 523 receives the internal clock signal Ramp at one input and the internal fixed voltage VTS at the other input. The comparator 523 outputs a positive clock signal CLK when the internal clock signal Ramp is greater than the internal fixed voltage VTS. A pulse of the clock signal CLK to turn on the FET 501 of the boost or buck-boost converter is introduced at this point via a set input of the bistable flip-flop 508, with this pulse of the clock signal CLK also closing a switch that discharges the capacitor 522, thereby resetting the internal clock signal Ramp.

[0029] To synchronize the clock signal CLK to the feedback voltage VFB, the exemplary embodiment of Fig. Component 5B includes a pull-up circuit 530 that can pull the voltage of capacitor 522 up to VDD (or a value greater than VTS) when the feedback voltage VFB falls below the reference voltage VREF. For example, comparator 509 can receive the feedback voltage VFB and the reference voltage VREF as inputs and output a SYNC signal that closes a switch, connecting capacitor 522 to VDD. Thus, when the feedback voltage VFB falls below the reference voltage VREF, the clock signal CLK is pulled high without waiting for the next pulse to be initiated based on the fixed frequency.

[0030] In addition to synchronizing the clock signal CLK with the output of comparator 509, one or more exemplary embodiments can also modulate the width of the gate pulses or the turn-on time of FET 501 based on the difference between the feedback voltage VFB and the reference voltage VREF. In light-load operation, this can reduce the amount by which the output voltage Vo overshoots the reference voltage. For this purpose, although the maximum turn-on time (tone) max ) programmed by the user, the actual tone activation time is determined based on the sampled feedback voltage, as below with reference to Fig. 8 explained. For example, if the sampled feedback voltage VFB SH If K1 is smaller than the reference voltage VREF (where K1 is a number between zero and one), the tone on-time is equal to the maximum tone on-time. maxIf the sampled feedback voltage VFB SH If K1 is greater than the reference voltage VREF, then the tone on-time can be calculated according to equation (1): Tone=Tonmax−K*(VFBSH−VFB); where VFB is the feedback voltage, VFB SH the sampled and held feedback voltage, K a constant and tone max The maximum on-time is shown. Although Equation 1 illustrates a linear reduction of tone based on the measured feedback voltage, this is only an exemplary embodiment, and the on-time of tone can be reduced quadratically or exponentially with respect to the measured feedback voltage, among other things.

[0031] According to one or more exemplary embodiments, the feedback voltage VFB can be sampled shortly before the FET 501 is switched on. In operation of the boost converter (or buck-boost converter), this is the point in time at which the full energy stored in the inductor 502 (during the switch-on time) is supplied to the output capacitor 504 and the voltage of the output capacitor has reached its maximum. Fig. Figure 6 shows the sampling process and the waveforms at maximum load, and Fig. Figure 7 shows the same waveforms at low load, according to an exemplary embodiment, in the VFB SH is sampled and the feedback voltage is maintained.

[0032] Fig. Figure 8 shows an architecture according to an exemplary embodiment for implementing the above-described switch-on time modulation by pulse width modulation circuit 511. With reference to Fig. 8 The feedback voltage VFB is sampled and held by a sample-and-hold circuit 801 shortly before the FET 501 is switched on, and outputs the sampled and held feedback voltage VFB. SH The sample-and-hold circuit 801 samples the feedback voltage VFB based on the Q output signal Q. out the bistable flip-flop circuit 508. The feedback voltage VFB and the sampled and held feedback voltage VFB SH The values ​​are fed into a differential circuit 802, whose output is multiplied by a constant K. The sampled and held feedback voltage VFB SHThe signal is also fed into a comparator 803, whose other input receives a signal that is 90% of the reference voltage VREF. Inputting 90% of the reference voltage VREF into the second input of the comparator 803 is purely exemplary, and other percentages of the reference voltage VREF, including 100%, can be used. The output of the comparator 803 is fed as a control input to a multiplexer MUX 804. When the sampled and held feedback voltage VFB SH When the reference voltage VREF is less than 90%, the output of comparator 803 is low, and the output of multiplexer MUX 804 is zero. When the sampled and held feedback voltage VFB SH If the value is greater than 90% of the reference voltage VREF, the output of comparator 803 is high, and multiplexer MUX 804 outputs the difference between the sampled and held feedback voltage VFB. SHand the feedback voltage VFB, multiplied by the constant K. The output of the multiplexer MUX 804 is fed into a differential circuit 805, which calculates the difference between the maximum on-time (set by a resistor divider) and the tone. max and outputs to the multiplexer MUX 804. The output of the differential circuit 805 is the turn-on signal (tone), which is fed into a comparator 806, whose other input receives the internal clock ramp. When the internal clock ramp is greater than the turn-on signal (tone), the output of the comparator Dt is high, which is fed to a monostable multivibrator. In response, the monostable multivibrator generates a signal pulse, which is fed as the reset signal RST to the input of the bistable multivibrator 508. Thus, the reset signal RST is set based on the feedback voltage.

[0033] Returning to Fig. The reset signal RST (5) causes the output of the bistable flip-flop 508 to go low, which limits the width of the gate pulse that turns on the FET 501. By limiting the turn-on time, the output voltage Vo remains closer to the reference voltage VREF, as shown in Fig. 7 shown.

[0034] Although the inventive concepts of the present disclosure have been described and illustrated with regard to their exemplary embodiments, it is not limited to the exemplary embodiments disclosed herein, and changes may be made therein without departing from the scope of the inventive concepts.

Claims

[1] Control unit for a converter (500), the control unit comprising: a clock generation circuit (506) that generates a periodic clock signal containing periodic clock pulses; and a control circuit (550) that causes the clock generation circuit (506) to asynchronously initiate a clock pulse based on a difference between a feedback voltage of the converter (500) and a reference voltage, wherein the control circuit (550) causes the clock generation circuit (506) to generate the clock pulse asynchronously based on a determination that the to initiate feedback voltage is smaller than the reference voltage, wherein the clock generation circuit (506) comprises a current source (521) coupled to a capacitor (522); and wherein the control circuit (550) includes a pull-up circuit (530) which pulls up a voltage of the capacitor (522) when the feedback voltage is less than the reference voltage in order to cause the clock generation circuit (506) to initiate a clock pulse asynchronously. [2] Control according to claim 1, wherein the asynchronously introduced clock pulse is configured to activate a switch of the converter (500). [3] Control according to claim 1, further comprising a pulse width modulation circuit (511) which modulates the width of the asynchronously introduced clock pulse based on a difference between the feedback voltage and the reference voltage. [4] Control according to claim 3, wherein the pulse width modulation circuit (511) reduces the width of the asynchronously introduced clock pulse as the feedback voltage approaches the reference voltage. [5] Control according to claim 3, wherein the pulse width modulation circuit (511) comprises: a sampling and holding circuit (801) that samples the feedback voltage; and a comparator (803) that compares the sampled feedback voltage with the reference voltage. [6] Control according to claim 5, wherein the pulse width modulation circuit (511) linearly reduces the width of the asynchronously introduced clock pulse when the sampled feedback voltage is greater than the reference voltage. [7] Control according to claim 5, wherein the pulse width modulation circuit (511) linearly reduces the width of the asynchronously introduced clock pulse when the sampled feedback voltage is greater than a predetermined fraction of the reference voltage. [8] Control according to claim 5, wherein the pulse width modulation circuit (511) controls the width of the asynchronously introduced clock pulse based on whether the sampled feedback voltage is smaller than the reference voltage. [9] Method for controlling an output voltage ripple of a converter (500), the method comprising: Generating a periodic clock signal containing periodic clock pulses; Determining the difference between a feedback voltage of the converter (500) and a reference voltage; and asynchronous initiation of a clock pulse based on the difference between the converter's feedback voltage (500) and the reference voltage, the asynchronous clock pulse is initiated when it is determined that the feedback voltage is smaller than the reference voltage, wherein the step of asynchronously initiating a clock pulse includes using a pull-up circuit (530) to asynchronously initiate the clock pulse when the feedback voltage is smaller than the reference voltage. [10] Method according to claim 9, further comprising activating a switch of the converter (500) using the asynchronously introduced clock pulse. [11] Method according to claim 9, further comprising modulating the width of the asynchronously introduced clock pulse based on a difference between the feedback voltage and the reference voltage. [12] Method according to claim 11, wherein the step of modulating the width of the clock pulses comprises reducing the width of the asynchronously introduced clock pulse as the feedback voltage approaches the reference voltage. [13] The method of claim 11, further comprising: Sampling the feedback voltage; and Comparing the sampled feedback voltage with the reference voltage. [14] Method according to claim 13, wherein the step of modulating the width of the asynchronously introduced clock pulse comprises a linear reduction of the width of the asynchronously introduced clock pulse when the sampled feedback voltage is greater than the reference voltage. [15] Method according to claim 13, wherein the step of modulating the width of the asynchronously introduced clock pulse comprises a linear reduction of the width of the asynchronously introduced clock pulse when the sampled feedback voltage is greater than a fraction of the reference voltage. [16] Method according to claim 13, wherein the step of modulating the width of the asynchronously introduced clock pulses comprises controlling the width of the asynchronously introduced clock pulse according to a maximum on-time when the sampled feedback voltage is smaller than the reference voltage.

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