Connection setup, circuit, and electronic device containing the connection setup or circuit

Abstract

Interconnection structure for a plurality of semiconductor devices formed on a substrate (1001), wherein the interconnection structure is arranged under the plurality of semiconductor devices and comprises: at least one via layer (1003a-1, 1003a-2, 1003a-3, 2003a-1, 2003a-2, 2003a-3) and at least one interconnect layer (1003b-1, 1003b-2, 2003b-1, 2003b-2) arranged alternately in one direction from each semiconductor device to the substrate (1001), wherein via holes are arranged in each via layer under a first group of source / drain regions (1005, 1009) in the plurality of semiconductor devices and insulating parts (1035-2a, 1035-3a, 2035-2a, 2035-3a) are arranged in each via layer under a second group of source / drain regions (1005, 1009) in the plurality of semiconductor devices, wherein each interconnect layer comprises conductive nodes, each of which is arranged under at least a portion of the plurality of semiconductor devices, and wherein in each interconnect layer a conductive channel is provided between at least one conductive node and at least one other node, and the via holes in each via layer and the conductive nodes in each interconnect layer overlap at least partially in one direction from each semiconductor device to the substrate (1001) in accordance with the via holes.

Description

TECHNICAL FIELD

[0001] The present invention relates to the field of semiconductors and, more particularly, to an interconnect structure between device layers, a circuit including an interconnect structure between device layers, and an electronic device including the interconnect structure or circuit. BACKGROUND

[0002] Interconnection between component layers can reduce parasitic resistance and capacitance, thereby reducing resistance and capacitance (RC) delay and power consumption of an integrated circuit (IC). It can also increase the integration density of the IC and, accordingly, reduce IC manufacturing costs. However, providing interconnection between component layers is difficult because the interconnection process is incompatible with the component integration process.

[0003] A manufacturing process for RRAM memory cells using metal oxide as a material with switchable resistance is known from US 9 054 308 B1 as well as a lower electrode for an RRAM structure from DE 10 2016 117 561 A1. SUMMARY

[0004] Against this background, it is an object of the present invention to at least partially provide an interconnection structure between component layers, a circuit containing an interconnection between component layers, and an electronic device containing the interconnection structure or the circuit.

[0005] According to the invention, a connection structure according to claim 1 and a circuit according to claim 10. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In the following, embodiments of the present invention will be described with reference to the accompanying drawings in order to clarify the above and other objects, features and advantages of the present invention. Fig. 1 to 52(d) are schematic views showing some stages in a process for manufacturing a vertical semiconductor device according to embodiments of the present invention, wherein Fig. 2(a), Fig. 8(a), Fig. 9(a), Fig. 12(a), Fig. 14(a), 15(a), 23(a), 25(a), 27(a), 32(a), 35(a), 43(a), 49(a), 52(a) are plan views, Fig. 1, Fig. 2(b), Fig. 3, Fig. 4(b), Fig. 5(b), Fig. 6(b), Fig. 7(b), Fig. 8(b), Fig. 10(b), Fig. 11(b), Fig. 12(c), Fig. 13(b), Fig. 14(c), Fig. 15(c), Fig. 16(b), Fig. 17(b), Fig. 18(b), Fig. 19(b), Fig. 20(b), Fig. 21(b), Fig. 22(b), Fig. 23(c), Fig. 24(b), Fig. 25(c) are cross-sectional views along the line BB', Fig. 4(a), Fig. 5(a), Fig. 6(a), Fig. 7(a), Fig. 9(b), Fig. 10(a), Fig. 11(a), Fig. 12(b), Fig. 13(a), Fig. 14(b), Fig. 15(b), Fig. 16(a), Fig. 17(a), Fig. 18(a), Fig. 19(a), Fig. 20(a), Fig. 21(a), Fig. 22(a), Fig. 23(b), Fig. 24(a), Fig. 25(b), Fig. 30, Fig. 31(a), Fig. 32(b), Fig. 33(a), Fig. 34(a), Fig. 35(b), Fig. 36, Fig. 37, Fig. 38(a), Fig. 39(a), Fig. 40(a), Fig. 41, Fig. 42(a), Fig. 43(b), Fig. 44, Fig. 47(a), Fig. 49(b), Fig. 50(a), Fig. 51(a), Fig. 52(b) are cross-sectional views along the line AA', Fig. 23(d), Fig. 24(c) and Fig. 25(d) are cross-sectional views along the line CC', Fig. 25(e), Fig. 26, Fig. 47(b), Fig. 49(c), Fig. 50(b), Fig. 51(b), Fig. 52(c) are cross-sectional views along the line FF', Fig. 25(f-1), 25(f-2), 25(f-3), 25(f-4), 27(b), 28(a), 29(a), 31(b-1), 31(b-2), 33(b-1), 33(b-2), 34(b), 38(b), 39(b), 40(b) are cross-sectional views along the line DD', Fig. 27(c), Fig. 28(b), Fig. 29(b), Fig. 49(d), Fig. 50(c), Fig. 51(c) are cross-sectional views along the line EE', Fig. 42(b), Fig. 45, Fig. 46, Fig. 47(c), Fig. 48 cross-sectional views along the line GG' are and Fig. 50(d), Fig. 51(d), Fig. 52(d) are cross-sectional views along line 1-1'. Fig. 53 to 66(b) are schematic views of some stages in a process for manufacturing a FinFET according to embodiments of the present invention, wherein Fig. 54(a), Fig. 59(a), Fig. 60(a), Fig. 62(a), Fig. 63(a), Fig. 64(a), Fig. 65(a), Fig. 66(a) Plan views are, Fig. 53, Fig. 54(b), Fig. 55(b), Fig. 56, Fig. 59(c), Fig. 60(c), Fig. 63(c), Fig. 64(c) are cross-sectional views along the line BB', Fig. 55(a), Fig. 57(a), Fig. 59(b), Fig. 60(b), Fig. 61, Fig. 62(b), Fig. 63(b), Fig. 64(b), Fig. 65(b), Fig. 66(b) are cross-sectional views along the line AA', Fig. 57(b) is a cross-sectional view taken along the line FF', Fig. 57(d), Fig. 58, Fig. 59(d) are cross-sectional views along the line GG', Fig. 65(c) is a cross-sectional view taken along the line HH' and Fig. 57(c) is a cross-sectional view taken along line 1-1'. Fig. 67 to 70(b) are schematic views of some stages in a process for manufacturing a planar semiconductor device according to embodiments of the present invention, wherein Fig. 68(a), Fig. 69(a), Fig. 70(a) Plan views are, Fig. 67 is a cross-sectional view along the line BB' and Fig. 68(b), Fig. 69(b) and Fig. 70(b) are cross-sectional views along the line GG'.

[0007] Throughout the drawings, the same or similar reference numerals are used to indicate the same or similar components. DETAILED DESCRIPTION OF EMBODIMENTS

[0008] Embodiments of the present invention will be described below with reference to the accompanying drawings. In the following description, well-known structures and techniques will not be described in detail. Instead, the description will focus on the concept of the present invention.

[0009] The accompanying drawings are schematic views. The drawings are not drawn to scale; some details may be enlarged and other details omitted for clarity. The shapes of various regions and layers shown in the drawings, as well as the relative sizes and positional relationships between them, are merely examples. In practice, variations may occur due to manufacturing tolerances or technical limitations. Those skilled in the art are free to choose different shapes, sizes, and relative positions for regions / layers as needed.

[0010] When the description states that a layer / element is disposed "on top" of another layer / element, the layer / element may be disposed directly on top of the other layer / element, or another layer / element may be disposed between them. And when a layer / element is disposed "above" another layer / element in one orientation, the layer / element may be disposed "below" the other layer / element if the orientation is reversed.

[0011] According to embodiments of the present invention, an interconnect structure is provided. In contrast to the prior art formation of an interconnect structure, for example, with a metallization layer over a semiconductor device after the semiconductor device has been formed on a substrate, an interconnect structure according to embodiments of the present invention can be arranged beneath the device and, for example, between the device and the substrate. The interconnect structure can, for example, comprise at least one via layer and at least one interconnect layer that are alternately stacked.Each via layer is provided with a via hole to provide electrical connection between a layer below the via layer and a layer above the via layer (the layer below the via layer and the layer above the via layer are each interconnect layers). Conductive channels are provided in each interconnect layer to provide routing within the interconnect layer. Generally, the side of the interconnect structure closest to the component is the via layer to carry the electrical connection from the corresponding component.

[0012] In each via layer, the via hole may be arranged below the corresponding semiconductor device (and in particular an active region of the semiconductor device, such as a source / drain region). The reason for this is, for example, that the via hole and the semiconductor device may be defined with substantially the same pattern, as described further below. The via hole and the corresponding semiconductor device (in particular the active region of the semiconductor device, such as the source / drain region) may at least partially overlap in an etching direction and may be substantially aligned with each other, e.g., center-aligned. Of course, the via holes in each via layer do not have to be formed below all semiconductor components (in particular the source / drain regions).The via holes are formed only under a portion of the source / drain regions (which may also be referred to as a "first group of source / drain regions"), and insulating portions are formed under another portion of the source / drain regions (which may also be referred to as a "second group of source / drain regions"). The layout of the via holes and the insulating portions in the via layers can be determined according to an interconnection layout dictated by the circuit design.

[0013] Accordingly, in each interconnect layer, a conductive node may be provided beneath the corresponding semiconductor device (in particular beneath the active region of the semiconductor device, such as the source / drain region). The reason for this is that the conductive node and the semiconductor device may be defined by a substantially identical pattern as described further below. The conductive node and the corresponding semiconductor device (in particular beneath the active region of the semiconductor device, such as the source / drain region) may at least partially overlap in the etching direction or may be substantially aligned with each other, e.g., center-aligned. Accordingly, in each interconnect layer, the conductive nodes do not have to be formed beneath all semiconductor devices (and in particular beneath the source / drain regions) and may also be formed beneath only a portion of the source / drain regions.

[0014] In each interconnect layer, the conductive channels extend between corresponding conductive nodes. According to embodiments of the present invention, the conductive channels may extend in stages between adjacent conductive nodes, with non-adjacent conductive channels not directly connected by a conductive channel (a "direct connection" is understood to mean a connection that does not pass through other conductive nodes).

[0015] For each via hole, a layer above the via hole and a layer below the via hole may have corresponding conductive nodes that contact the via hole to establish electrical connection between the layer above the via hole and the layer below the via hole. For each conductive node, there may be no corresponding via holes in a layer above the conductive node and in a layer below the conductive node, so that the conductive node can be used as an intermediate node in a conductive channel. Alternatively, the layer above the conductive node and / or the layer below the conductive node may have corresponding via holes that contact the conductive node to establish electrical connection between the layer above the conductive node and the layer below the conductive node.

[0016] Therefore, each layer in the interconnect structure can have a layout similar to that of the semiconductor device. The layout is referred to herein as an "array" and is approximately a two-dimensional array in rows and columns (of course, other array forms can also be used), and the elements in the layout (for example, the semiconductor device in the device layer, the via hole in the via layer, or the conductive node in the interconnect layer) are referred to as "nodes." The arrangement of each via layer and the arrangement of the device layer can be essentially the same, although some nodes may be lost (as described below, these nodes may be provided with insulating parts). The arrangement of each interconnect layer and the arrangement of the device layer can be essentially the same, although some nodes may be lost.

[0017] In some embodiments, the conductive nodes may be formed at all nodes in each interconnect layer. For an unnecessary conductive node, the insulating parts may be provided at corresponding positions in a via layer above the unnecessary conductive node and in a via layer below the unnecessary conductive node. And the conductive channels between the unnecessary conductive node and adjacent conductive nodes may be interrupted to make the unnecessary conductive node an isolated dummy node. This allows the treatment of the conductive nodes in the interconnect layers to be consistent, making the process easier to perform.

[0018] The interconnect structure can therefore be a three-dimensional (3D) lattice structure. The conductive channels in each interconnect layer can extend along sides of the lattice (e.g., in a row or column direction) in the array.

[0019] The interconnect structure is particularly suitable for a vertical semiconductor device. The vertical semiconductor device may comprise an active region extending in a vertical direction (for example, in a direction substantially perpendicular to a surface of the substrate). Each node in the interconnect structure may be arranged below the active region of each vertical semiconductor device in the vertical direction and may be aligned in the vertical direction, e.g., center-aligned.

[0020] The vertical active region may include source / drain regions, each arranged at an upper end and a lower end; and a channel region between the source / drain regions. A conductive channel may be formed between the source / drain regions through the channel region. Such an active region may be provided, for example, by a first source / drain layer, a channel layer, and a second source / drain layer that are sequentially stacked. The source / drain regions may be substantially formed in the first source / drain layer and the second source / drain layer, and the channel region may be substantially formed in the channel layer. The active region, and in particular the channel layer, may have the shape of a nanowire, thus obtaining a nanowire device.Alternatively, the active region and in particular the channel layer may have the shape of a nanosheet, thus resulting in a nanosheet device.

[0021] The channel layer may be formed from a single-crystal semiconductor material to improve device performance. Of course, the first and second source / drain layers may also be formed from a single-crystal semiconductor material. In this case, the single-crystal semiconductor material of the channel layer and the single-crystal semiconductor material of the source / drain layers may be eutectic.

[0022] According to embodiments of the present invention, the semiconductor device may be a conventional field-effect transistor (FET). In a FET, the source / drain regions on both sides of the channel region may be doped with the same conductivity type (e.g., n-type or p-type). A conductive channel may be formed between the source / drain regions and through the channel region at both ends of the channel region.

[0023] Alternatively, the semiconductor device can be a tunnel FET. In a tunnel FET, the source / drain regions on either side of the channel region can be doped with different conduction types (e.g., n-type and p-type, respectively). In this case, charged particles such as electrons can tunnel from the source region through the channel region and enter the drain region, forming a conduction path between the source and drain regions. Although the conduction mechanism in conventional FETs and the conduction mechanism in tunnel FETs are not the same, they can each have electrical properties that can control conduction between the source / drain regions through a gate. Therefore, the terms "source / drain layers (source / drain regions)" and "channel layer (channel region)" are used interchangeably for conventional FETs and tunnel FETs, although tunnel FETs do not have a "channel" in the usual sense.

[0024] A gate electrode may be formed around at least a portion of the periphery of the channel region. The gate electrode may be self-aligned with the channel layer. For example, a sidewall of the gate electrode near the channel layer may be aligned with a peripheral sidewall of the channel layer to occupy substantially the same area in the vertical direction. In this way, overlap between the gate electrode and the source / drain regions may be reduced or even prevented, helping to reduce parasitic capacitance between the gate and the source / drain regions.

[0025] To establish a connection between the gate electrodes in different devices and to apply electrical signals to the gate electrodes, each gate electrode may include an extension portion extending outward from a main body portion, in addition to the main body portion around the channel region. The extension portion may also extend along the side of the grid (e.g., in the row or column direction) in the array. Extension portions of at least some of the adjacent and facing gate electrodes may contact each other, thereby being electrically connected.

[0026] According to embodiments of the present invention, a contact plug may also be provided for introducing an electrical signal into the interconnect structure. For example, a contact plug is in contact with a corresponding via hole in a via layer at the very top of the interconnect structure to apply the electrical signal to the interconnect structure. The contact plug may thus be arranged at a corresponding node in the array. According to embodiments of the present invention, the contact plug may be formed by converting the active area at the corresponding node to a conductive material (for example, a silicide obtained by a silicification process), wherein the contact plug may then be self-aligned with the corresponding node (and in other words, with the via hole at the corresponding node).In the arrangement of the component layer, some nodes can be true active nodes of the component and other nodes can be contact plugs.

[0027] According to embodiments of the present invention, a contact plug for applying an electrical signal to the gate electrode may also be provided. For process consistency, this contact plug may also be formed by converting the active area at the corresponding node to a conductive material as described above (to form the "main body portion"). In addition to the main body portion at the node, the contact plug may further comprise an extension portion extending from the main body portion to be in contact with the gate electrode. The extension portion may also extend along the side of the grid (e.g., in the row or column direction) in the array.

[0028] According to embodiments of the present invention, the semiconductor device may also be a different type of semiconductor device, such as a fin field-effect transistor (FinFET) or a planar semiconductor device, whose fins or active regions may extend along a lateral direction (e.g., in a direction substantially parallel to the surface of the substrate). For example, the fins or active regions may extend along the side of the grid (e.g., in the row or column direction) in the array. The source / drain regions of the device may be arranged at the node in the array. In this way, an electrical connection to at least a portion of the source / drain regions in the device array may be established by the interconnect structure configured as explained further below.

[0029] Such a connection structure can be designed, for example, as follows.

[0030] According to embodiments of the present invention, a first stack of alternately stacked first sacrificial layers and second sacrificial layers may be provided on a substrate. The first stack is then used to form an interconnect structure. For simplicity, a sacrificial layer defining a position of a via layer is referred to herein as a first sacrificial layer, and a sacrificial layer defining a position of an interconnect layer is referred to as a second sacrificial layer. Therefore, the uppermost sacrificial layer of the first stack may be one of the first sacrificial layers. The first sacrificial layer and the second sacrificial layer may have etch selectivity with respect to each other.

[0031] A semiconductor material, which is subsequently used to form an active region of a device, may be provided on the first stack. For example, when forming a vertical semiconductor device, a second stack of a first source / drain layer, a channel layer, and a second source / drain layer, which are stacked sequentially, may be provided. The channel layer may have etch selectivity with respect to the first source / drain layer and the second source / drain layer. Furthermore, the first source / drain layer and the second source / drain layer may comprise a same semiconductor material. At least adjacent layers between the first stack and the second stack (i.e., a topmost layer of the first stack and a bottommost layer of the second stack) have etch selectivity with respect to each other. For example, these layers may be formed by epitaxial growth.Due to the epitaxial growth, at least one pair of adjacent layers may have a clear crystalline surface. Furthermore, each layer, and in particular each layer in the second stack, may be doped, so that at least one pair of adjacent layers may have a doping concentration interface.

[0032] To perform patterning, a hard mask layer may be provided on the semiconductor material of the active region, such as on the top side of the second stack. The hard mask layer may have a grid pattern. For example, the hard mask layer may include lines arranged in rows and columns. Intersections of the rows and columns in the hard mask layer are referred to as "nodes," and lines between the nodes are referred to as "bridge parts." If a grid pattern is created in other layers, it may also be referred to as such. In the case of a vertical semiconductor device, the nodes of the grid pattern of the hard mask layer may define a main body position of the vertical active region, and the line width of each node may be increased to be thicker than that of each bridge part.In the case of a FinFET or a planar semiconductor device, an approximately central portion of the bridge part in the lattice pattern of the hard mask layer may define the channel region, and portions on both sides of the channel region (the node and the bridge parts around the node) may define the source / drain regions.

[0033] The hard mask layer can be used to define the active region in the semiconductor material of the active region, such as in the second stack. For example, the pattern of the hard mask layer can be transferred to the second stack. In the case of a vertical semiconductor device, the active region can be arranged at corresponding positions of each node. A portion corresponding to the bridge portions in the second stack can be removed (replaced with a support material for structural support) and a portion corresponding to the nodes in the second stack can be retained to form a plurality of separate active regions. Some active regions can be used to form the devices, and other active regions can subsequently be converted into conductive contact plugs, for example, through a silicification process.

[0034] The mask layer can then be used to define a framework for the interconnect structure in the first stack. This can be achieved by transferring the pattern of the hard mask layer to the first stack and tailoring the pattern in each layer according to an interconnect design of the interconnect structure.

[0035] In the via layer, a via hole extending through the via layer must be provided to achieve a connection between an interconnect layer above the via layer and an interconnect layer below the via layer. Such a via hole can extend in the vertical direction without requiring a laterally extending configuration in the via layer. Therefore, the nodes of the hard mask layer can be used to define the pattern of the via hole in the first sacrificial layer. In particular, the layout of the nodes can be transferred to the first sacrificial layer. For example, after the pattern of the hard mask layer has been transferred to the first sacrificial layer, the bridge parts in the first sacrificial layer can be removed and the nodes can be retained in the first sacrificial layer.The nodes in the corresponding first sacrificial layer may be removed or retained according to a via layout in each via layer to achieve the required via hole layout.

[0036] Conductive channels extending laterally in the interconnect layer must be provided in the interconnect layer to achieve routing. Therefore, the bridge portions in the hard mask layer can be used to define orientations of the conductive channels in the second sacrificial layer. In particular, the pattern of the hard mask layer can be transferred to the second sacrificial layer, and the nodes in the second sacrificial layer can be used as relay points between the bridge portions of the conductive channels. Furthermore, the nodes in the second sacrificial layer can also be in contact with the corresponding nodes in the first sacrificial layer to establish a connection between the upper and lower layers. According to the interconnect design in each interconnect layer, the bridge portions in the corresponding second sacrificial layer can be removed or retained to achieve the required routing.

[0037] Cutting the pattern in the first stack can be performed layer by layer, for example, sequentially from top to bottom. A shielding layer can be used to shield the first stack, with the shielding layer gradually being etched back downward to expose each layer in the first stack in turn. When a specific layer in the first stack is being processed, a layer below the specific layer can be shielded by the shielding layer to prevent it from being impacted.

[0038] In general, the designs of the various layers in the interconnect structure are not necessarily identical. As the shielding layer is gradually etched back and a lower layer is processed, an upper layer may be exposed and impacted. To avoid impacting the upper layer during lower layer processing, a portion of the first or second sacrificial layer that is to be retained can be replaced with a different material. This can be accomplished using an etch-fill-etch-fill (EFEF) method, described below.

[0039] The present invention can be implemented in various embodiments, some examples of which are described below. In the following description, various materials are selected. In addition to the material functions (for example, semiconductor materials are used to form active regions and dielectric materials are used to form electrical insulation), etch selectivity is also taken into account when selecting the materials. In the following description, the required etch selectivity may or may not be specified.If it is stated below that a certain material layer is etched, but it is not mentioned that other layers are also etched, or the drawings do not show that other layers are also etched, this type of etching may be selective, whereby the certain material layer may have an etch selectivity relative to other layers exposed to the same etch recipe.

[0040] Fig. 1 to Fig. 52(d) are schematic views of some stages in a process for manufacturing a vertical semiconductor device according to embodiments of the present invention.

[0041] As in Fig. 1, a substrate 1001 is provided. The substrate 1001 may be a substrate of various shapes, for example, a bulk semiconductor material substrate such as a bulk Si substrate, a semiconductor-on-insulator (SOI) substrate, a compound semiconductor substrate such as a SiGe substrate, and the like. In the following description, the example of a bulk Si substrate is described for simplicity.

[0042] A well region (not shown) may be formed in the substrate 1001. When a p-type device is formed, the well region may be an n-type well. And when an n-type device is formed, the well region may be a p-type well. The well region may be formed, for example, by injecting dopants of corresponding conductivity types (p-type dopants such as B or In, or n-type dopants such as As or P) into the substrate 1001 and a subsequent thermal treatment. Such a well region may be provided in various ways, which will not be explained in detail here.

[0043] A first stack of alternately arranged first sacrificial layers 1003a-1, 1003a-2, 1003a-3 and second sacrificial layers 1003b-1, 1003b-2 may be formed on the substrate 1001, for example, by epitaxial growth. As described above, the first sacrificial layer and the second sacrificial layer may have etch selectivity with respect to each other. Because a material (generally a semiconductor material) of an active region may be later formed on the first stack, the first stack may be formed from a semiconductor material to achieve high-quality growth of the active region. For example, each of the first sacrificial layers 1003a-1, 1003a-2 and 1003a-3 may contain SiGe with an atomic percentage of Ge of approximately 10 to 40% and have a thickness between 20 and 100 nm, and each of the second sacrificial layers 1003b-1, 1003b-2 may contain Si and have a thickness of approximately 20 to 100 nm.Each of the first sacrificial layers and the second sacrificial layers may have substantially the same thickness. The number of the first sacrificial layers and the second sacrificial layers may be determined in accordance with the number of via layers and interconnect layers in an interconnect structure to be formed and is not limited to the number of layers shown in the drawing. A lowermost first sacrificial layer 1003a-1 may subsequently be replaced with an insulating layer to achieve electrical insulation between the interconnect structure and the substrate.

[0044] A second stack of a first source / drain layer 1005, a channel layer 1007, and a second source / drain layer 1009 may be formed on the first stack by, for example, epitaxial growth, wherein the first source / drain layer 1005, the channel layer 1007, and the second source / drain layer 1009 may all be formed from semiconductor materials. As described above, the channel layer and the first source / drain layer may have etch selectivity with respect to each other, and the channel layer and the second source / drain layer may have etch selectivity with respect to each other. And to facilitate processing of each of the first stack and the second stack, at least adjacent layers between the first stack and the second stack may have etch selectivity with respect to each other.For example, the channel layer 1007 may contain SiGe with an atomic percentage of Ge of about 10 to 40% and have a thickness of about 20 to 100 nm, and the first source / drain layer 1006 and the second source / drain layer 1009 may contain Si and have a thickness of about 20 to 100 nm.

[0045] According to the embodiments, a contact layer may further be provided. For example, a contact interface layer (not shown) may be formed between the first stack and the second stack, for example, by epitaxial growth. The contact interface layer may, for example, contain silicon and may be doped to an n-type or a p-type by, for example, in-situ doping, wherein the doping type is preferably the same as that described in connection with Fig. 25 and the doping concentration is approximately 1∙10 19 up to 5∙10 21 cm -3This allows a resistance between the source / drain electrode and the connection structure to be reduced. Because the contact interface layer contains the same material (Si) as the first source / drain layer 1005, it can subsequently be processed in the same way as the first source / drain layer 1005. Alternatively or additionally, before forming the first stack, a contact layer (not shown) is formed on the substrate, for example by epitaxial growth. Accordingly, the contact layer can contain silicon, for example, and be doped to an n-type or p-type, for example by in-situ doping, wherein the doping type is preferably the same as that used in connection with Fig. 25 and the doping concentration is 1∙10 19 up to 5∙10 21 cm -3 amounts.

[0046] A hard mask layer may be formed on the second stack. The hard mask layer may have a stacked structure and may include, for example, a first sublayer 1011 and a second sublayer 1013. The first sublayer 1011 may be used for protection and / or etch stop and other purposes. For example, the first sublayer 1011 may contain oxide (e.g., silicon oxide) and have a thickness of approximately 2 to 5 nm. The first sublayer 1011 may be formed by deposition or thermal oxidation (the quality of an oxide formed by thermal oxidation is better). The second sublayer 1013 may be used for masking and / or isolation and other purposes.For example, the second sublayer 1013 may include nitride (e.g., silicon nitride) or a low-k dielectric material (e.g., a silicon carbide-based material) and may have a thickness of approximately 10 to 100 nm. The second sublayer 1013 may be formed by deposition. Of course, the materials of the hard mask layer are not limited thereto and may also include materials retained in various subsequent etching processes. Furthermore, the hard mask layer may also include multiple sublayers to provide better etch selectivity.

[0047] The hard mask layer can be patterned into a desired pattern. As described above, a grid pattern can be formed. For this purpose, as shown in Fig. 2(a) and Fig. As shown in Figure 2(b), a photoresist 1015 is formed on the hard mask layer. The photoresist 1015 is patterned into a grid pattern by photolithography (exposure and development). Nodes of the grid can be thickened to define the positions of the active regions. The grid nodes are essentially circular, so that nanowire devices can subsequently be formed. Of course, the shapes of the grid nodes are not limited to this, but can also have any other suitable shapes, such as an ellipse, a rectangle, a square, etc., or even a combination of different shapes (some nodes have one shape while others have a different shape). When rectangular or square nodes are formed, a cross-spaced pattern transfer technique (xSIT) can be used, and nanosheet devices can then be formed.

[0048] The active area can then be defined. For example, this can be done as follows.

[0049] The pattern of the photoresist 1015 can be transferred to the hard mask layer and then to the second stack under the hard mask layer. In particular, as shown in Fig. As shown in Figure 3, the patterned photoresist 1015 may be used as a mask, and the hard mask layer (1013, 1011), the second source / drain layer 1009, the channel layer 1007, and the first source / drain layer 1005 may be selectively etched sequentially, for example, by reactive ion etching (RIE). For example, RIE may be performed in a direction substantially perpendicular to the surface of the substrate, so that a pattern formed in the second stack and the pattern of the hard mask layer may be aligned substantially in a vertical direction.

[0050] In this example, the etching of the first source / drain layer 1005 does not progress to a lower surface of the first source / drain layer 1005. Therefore, a thin layer of Si remains on the upper surface of the first stack. Because the first sacrificial layer 1003a-3 and the channel layer 1007 contain SiGe in this example, this thin layer of Si can then protect the first sacrificial layer 1003a-3 in the first stack when the channel layer 1007 is selectively etched. If the first sacrificial layer 1003a-3 has etch selectivity with respect to the channel layer 1007, the etching of the first source / drain layer 1005 can proceed further to the lower surface of the first source / drain layer.

[0051] At this point, the second stack has the same grid pattern as the hard mask layer. Preferably, the second stack is separated into active regions for individual devices at corresponding nodes. To this end, the first source / drain layer 1005, the channel layer 1007, and the second source / drain layer 1009 can be further selectively etched to remove bridge portions, while retaining the nodes. This is possible because the line widths of the nodes are relatively thick, as described above.

[0052] For example in Fig. 4(a) and Fig. As shown in Figure 4(b), the channel layer 1007 (SiGe) can be selectively etched relative to the first source / drain layer 1005 and the second source / drain layer 1009 (Si). The size of the etching is controlled such that the bridge portions in the channel layer 1007 are removed (see Fig. 4(b)), while the nodes are retained in the channel layer 1007 (see Fig. 4(a)). As in Fig. As shown in Figure 4(a), the channel layer 1007 is divided into a plurality of parts located at the corresponding nodes, and channels of the device can be formed in the plurality of parts at the corresponding nodes. The outer peripheries of these separated parts are recessed inward with respect to the outer peripheries of the corresponding nodes in the hard mask layer. To facilitate control of the etching size, atomic layer etching (ALE) can be used. Because a continuous bottom of the first source / drain layer 1005 is present, the first sacrificial layer 1003a-3, which is made of SiGe like the channel layer 1007, cannot be affected.

[0053] For structural support and protection of the channel layer, as in Fig. 5(a) and Fig. 5(b), a position-maintaining layer 1017 may be formed in a gap of the second stack under the hard mask layer. For example, a dielectric material may be deposited on the Fig. 4(a) and Fig. 4(b) in a sufficient amount to fill the gap of the second stack, wherein the hard mask layer is used as a mask for etching back, such as by RIE of the deposited dielectric material. The RIE may be performed in the direction substantially perpendicular to the surface of the substrate, leaving the dielectric material beneath the hard mask layer to form the position-maintaining layer 1017. Therefore, the position-maintaining layer 1017 is filled in positions where the bridge portions are originally located in the channel layer and in recesses formed by further selective etching of the nodes in the channel layer as described above, wherein the position-maintaining layer is self-aligned with the channel layer and surrounds a periphery of the channel layer to protect the channel layer.In this case, a material of the position-holding layer 1017, such as oxynitride (for example, silicon oxynitride), is selected so that the position-holding layer 1017 has etch selectivity with respect to the hard mask layer.

[0054] Accordingly, as in Fig. 6(a) and Fig. 6(b), with respect to the channel layer 1007 and the first sacrificial layer 1003a-3 (SiGe), the first source / drain layer 1005 and the second source / drain layer 1009 (Si) are selectively etched. The size of the etching is controlled such that bridge portions in the first source / drain layer 1005 and the second source / drain layer 1009 are removed (see Fig. 6(b)) and nodes in the first source / drain layer 1005 and the second source / drain layer 1009 are retained (see Fig. 6(a)). As in Fig. As shown in Figure 6(a), the first source / drain layer 1005 and the second source / drain layer 1009 are both separated into a plurality of parts located at the corresponding nodes, and the source / drain regions of the device can be formed in the plurality of parts. The outer peripheries of these separated parts are recessed inward with respect to the outer peripheries of the corresponding nodes in the hard mask layer. To simplify the control of the etch size, an ALE can be used. Furthermore, the thickness of the continuous thin layer at the bottom of the first source / drain layer 1005 is small, so that the continuous thin layer can be removed during this further etching process to expose the first sacrificial layer 1003a-3 for further processing of the first stack.

[0055] Accordingly, for structural support and protection of the source / drain layer as in Fig. 7(a) and Fig. As shown in Figure 7(b), a position-maintaining layer 1019 may be formed in a gap of the second stack under the hard mask layer. The position-maintaining layer 1019 may be formed in the same manner as the position-maintaining layer 1017. Therefore, the position-maintaining layer 1019 is filled at positions where the bridge portions of the first source / drain layer 1005 and the second source / drain layer 1009 are originally located and in recesses formed by further selective etching of the node portions. The position-maintaining layer is self-aligned with the first source / drain layer 1005 and the second source / drain layer 1009 and surrounds outer peripheries of the first source / drain layer 1005 and the second source / drain layer 1009 to protect the source / drain layers.In this case, a material such as SiC of the position holding layer 1019 is selected so that the position holding layer 1019 has etch selectivity with respect to the hard mask layer and the position holding layer 1017.

[0056] The respective separated portions of the etched first source / drain layer 1005, the channel layer 1007, and the second source / drain layer 1009 form a columnar shape (in this example, the cross-section has an approximately circular columnar shape) that defines the active regions. The columnar active regions may extend substantially perpendicular to the surface of the substrate.

[0057] Subsequently, positions of conductive parts of the interconnect structure (the via hole, the conductive node and the conductive channel as described above) can be defined in the first stack.

[0058] For example, the pattern of the hard mask layer can be transferred to the first stack. Because the second stack (together with the holding material) has been patterned over the first stack as described above like the hard mask layer, this pattern transfer is possible. In particular, as shown in Fig. 8(a) and Fig. As shown in Figure 8(b), the hard mask layer (1013, 1011) may be used as a mask, and the first sacrificial layer 1003a-3, the second sacrificial layer 1003b-2, the first sacrificial layer 1003a-2, the second sacrificial layer 1003b-1, and the first sacrificial layer 1003a-1 may be selectively etched sequentially, such as by RIE. For example, RIE may be performed in the direction substantially perpendicular to the surface of the substrate, so that the pattern formed in the first stack and the pattern of the hard mask layer may be substantially aligned in the vertical direction.

[0059] At this point, the first stack has the same grid pattern as the hard mask layer. Regarding the first sacrificial layer of the via layer, bridge portions can be removed as described above. This removal can be accomplished by further selective etching of the first sacrificial layer as in the above-mentioned separation of the active areas. However, the remaining nodes are smaller in this case (as described above, the remaining nodes are recessed inward with respect to the nodes of the hard mask layer). To ensure a process margin and reduce contact resistance, photolithography can be used to make the remaining nodes larger. For example, as in Fig. 9(a) and Fig. 9(b) shows a photoresist 1021 on the Fig. 8(a) and Fig. 8(b), and the photoresist 1021 may be patterned into separate nodes in accordance with the pattern of the hard mask layer to cover the corresponding nodes in the first sacrificial layer and expose the bridge parts between the nodes. As shown in Fig. As shown in Figure 9(a), the nodes of the photoresist 1021 may be larger than the nodes of the hard mask layer, so that the nodes subsequently left in the first sacrificial layer may be larger, and may also cover the separate active regions to prevent the active regions from being affected when the first sacrificial layer is etched. Alternatively, a thin layer may be deposited as a hard mask layer, and then the hard mask layer may be patterned using the photoresist described above.

[0060] Then, as in Fig. 10(a) and Fig. As shown in Figure 10(b), the first sacrificial layer (SiGe) is further selectively etched with respect to the second sacrificial layer (Si). This results in the removal of the parts of the first sacrificial layer exposed by the photoresist 1021 (see Fig. 10(b)) and the nodes of the first sacrificial layer are retained (see Fig. 10(a)) (because the nodes of the photoresist 1021 are relatively large as described above, a certain length of the bridge parts may remain around the outer peripheries of the nodes of the first sacrificial layer). The photoresist 1021 may then be removed.

[0061] Thus, an interconnect framework is defined in the first stack, and then the pattern in the first stack (the node patterns in the first sacrificial layer and the grid patterns in the second sacrificial layer) can be tailored according to a design of the interconnect. This tailoring can be performed layer by layer.

[0062] To facilitate layer-by-layer cutting, a dielectric layer may be formed in the gaps between the first stack and the second stack. As shown in Fig. 11(a) and Fig. As shown in Figure 11(b), a dielectric layer 1023 (e.g., an oxide) may be formed on the substrate 1001, for example, by deposition. The deposited dielectric layer 1023 may be planarized, for example, by chemical mechanical polishing (CMP), wherein the CMP may stop at the second sublayer 1013 of the hard mask layer. Therefore, an upper surface of the dielectric layer 1023 may be substantially coplanar with an upper surface of the second sublayer 1013. Thereafter, the upper surface (in a certain region) of the dielectric layer 1023 may be gradually made lower to sequentially expose corresponding layers in the first stack, thereby achieving layer-by-layer cutting.

[0063] The following first describes the pattern cutting of the second sacrificial layer as an example. At this time, the bridge parts between each node are provided in every second sacrificial layer. The bridge parts between some nodes can be cut according to the interconnect design of each interconnect layer to define paths that correspond to the interconnect design of the corresponding interconnect layer. Cutting the bridge parts requires processing channels to the bridge parts.

[0064] For example, openings exposing the bridge parts may be formed in the dielectric layer 1023. This may be achieved using an additional hard mask layer. As shown in Fig. 12(a), Fig. 12(b) and Fig. As shown in Figure 12(c), another hard mask layer may be formed on the top surface of the dielectric layer 1023 and on the top surface of the hard mask layer (1011 / 1013). Accordingly, the hard mask layer may also be a stack comprising a first sublayer 1025, consisting, for example, of an oxide with a thickness of approximately 2 to 10 nm, and a second sublayer 1027, consisting, for example, of nitride or a low-k dielectric material with a thickness of 10 to 150 nm. The first sublayer 1025 and the second sublayer 1027 are configured as described above for the first sublayer 1011 and the second sublayer 1013.

[0065] The hard mask layer can be patterned into a desired pattern as described above to expose the bridge portions. For this purpose, a photoresist 1029 can be formed on the hard mask layer. The photoresist 1029 is patterned by photolithography (exposure and development) to include a series of openings, each arranged at each bridge portion and, for example, at a central portion of each bridge portion. In this example, the opening has the shape of an ellipse, but the present invention is not limited thereto, and the opening can also have various other shapes suitable for processing, such as a circular shape or the like.

[0066] Then the processing channels can be formed. For example, as in Fig. 13(a) and Fig. As shown in Figure 13(b), the photoresist 1029 can be used as a mask for selectively etching the second sublayer 1027 (nitride), for example, by RIE. For example, RIE can be performed in the direction substantially perpendicular to the surface of the substrate and can stop at the first sublayer 1025 (oxide). Then, as shown in Fig. 14(a), Fig. 14(b) and Fig. 14(c), the first sublayer 1025 and the dielectric layer 1023 (both made of oxide) are selectively etched by RIE. For example, the RIE may be performed in the direction substantially perpendicular to the surface of the substrate until the top second sacrificial layer 1003b-2 is exposed to form processing channels T1 as shown in Fig. 14(c). For example, a bottom surface of the processing channel T1 may be disposed between the lower surface and the upper surface of the first sacrificial layer 1003a-2 below the second sacrificial layer 1003b-2 to be exposed, thereby ensuring that the second sacrificial layer 1003b-2 is fully exposed and preventing the second sacrificial layer 1003b-1 from being exposed thereunder. To precisely control the size of the etch, an ALE may be used. Afterward, the photoresist 1029 may be removed.

[0067] As in Fig. As shown in Figure 14(a), each processing channel T1 is located approximately in the center of each bridge part, and each node (and thus the active area and the first sacrificial layer at each node) is shielded. As shown in Fig. As shown in Figure 14(c), in each processing channel T1, except for the second sacrificial layer 1003b-2, the remaining exposed material layers are all dielectric materials (the oxide and nitride hard mask layers, the oxynitride position-maintaining layer 1017, the SiC position-maintaining layer 1019, and the oxide dielectric layer 1023).

[0068] All bridge parts present at this time (especially the middle parts of the bridge parts) are exposed in the corresponding processing channels T1. Some of these bridge parts need to be cut off, while others need to be retained. The bridge parts that need to be cut off and the bridge parts that need to be retained can be processed separately.

[0069] In addition, there are usually a plurality of interconnect layers (and thus a plurality of second sacrificial layers) in the interconnect structure, where the routing in the different interconnect layers is not necessarily the same. For example, for an upper layer and a lower layer of the second sacrificial layer in the same processing channel T1, a bridge part of one layer (e.g., the upper layer) must be retained, while a bridge part of another layer (e.g., the lower layer) must be cut off. Thus, if the bridge part of the lower layer is cut off by the processing channel T1, the bridge part of the upper layer (which contains the same material as the lower layer; both are the second sacrificial layers), which may also be exposed in the processing channel T1, may also be cut off because the upper layer is disposed above the lower layer.According to embodiments of the present invention, the bridge parts that need to be retained may be replaced by a material having etch selectivity with respect to the second sacrificial layer to avoid being affected when processing the lower layer of the second sacrificial layer.

[0070] For example, as in Fig. 15(a), Fig. 15(b) and Fig. 15(c) shows a photoresist 1031 on the Fig. 14(a), Fig. 14(b) and Fig. 14(c) (with the photoresist 1029 removed), and the photoresist 1031 is patterned by photolithography to expose the processing channels T1 where the bridge parts need to be retained and to cover the processing channels T1 where the bridge parts need to be cut off.

[0071] Then, as in Fig. 16(a) and Fig. As shown in Figure 16(b), the second sacrificial layer 1003b-2 (Si) may be selectively etched (first etch) through the processing channels T1 exposed by the photoresist 1031 relative to the dielectric material exposed in the processing channels T1 (the oxide, nitride, oxynitride, SiC as described above). In this way, a portion of the second sacrificial layer 1003b-2 in these exposed processing channels T1 may be removed. In this way, gaps are formed at some of the bridge portions of the second sacrificial layer 1003b-2. Afterward, the photoresist 1031 may be removed.

[0072] Afterwards, as in Fig. 17(a) and Fig. As shown in Figure 17(b), a position-maintaining layer 1033-2b may be filled into the gaps in the bridge portions of the second sacrificial layer 1003b-2 through the processing channels T1 (first filling). The position-maintaining layer 1033-2b may contain a material with an etch selectivity with respect to the second sacrificial layer (Si), such as SiGe with an atomic percentage of Ge of approximately 25 to 75%. The filling may be accomplished by depositing SiGe through the processing channels T1 and then etching back the deposited SiGe (relative to the surrounding dielectric material), such as by an RIE. An RIE may be performed in the direction substantially perpendicular to the surface of the substrate. Due to the presence of the hard mask layer 1011 / 1013, the SiGe may be completely filled into the gaps of the bridge portions after etching back and may extend along the corresponding bridge portions.

[0073] Then, some of the bridge parts of the second sacrificial layer 1003b-2 are cut off.

[0074] For example, as in Fig. 18(a) and Fig. As shown in Figure 18(b), the second sacrificial layer 1003b-2 (Si) may be selectively etched through the processing channels T1 relative to other material layers exposed in the processing channels T1 (e.g., the dielectric material and the above-described position-maintaining layer 1033-2b made of SiGe). In this way, a portion of the second sacrificial layer 1003b-2 originally covered by the photoresist 1031 in the processing channels T1 may be removed. Although the bridge portions replaced by the position-maintaining layer 1033-2b as described above are also exposed in the processing channels T1, the position-maintaining layer 1033-2b may be substantially unaffected due to the etch selectivity. Thus, gaps are formed at some of the bridge portions of the second sacrificial layer 1003b-2. Insulating portions 1035-2b may be filled into these gaps (second filling).Given the etch selectivity required in the subsequent processes (e.g., the etch selectivity with respect to the dielectric layer 1023), the insulating portions 1035-2b may, for example, contain SiC. This filling may be accomplished by deposition and subsequent etching back as described above. Accordingly, the insulating portions 1035-2b may be completely filled into the gaps of the bridge portions and extend along the corresponding bridge portions.

[0075] Then, as in Fig. 18(a), the second sacrificial layer 1003b-2 is isolated in a first etch-first fill-second etch-second fill (EFEF) process by the insulating parts 1035-2b, which may then form various conductive channels (a part thereof).

[0076] Subsequently, a similar process can be performed on the lower second sacrificial layer 1003b-1.

[0077] For example, as above with reference to Fig. 14(a), Fig. 14(b) and Fig. As described in Figure 14(c), the dielectric layer 1023 may be selectively etched, for example, by an RIE to deepen the processing channels T1 and thereby expose the second sacrificial layer 1003b-1. For example, a bottom surface of a processing channel T1 may be disposed between a top surface and a bottom surface of the first sacrificial layer 1003a-1 under the second sacrificial layer 1003b-1 to be exposed. To precisely control the etch depth, an ALE may be used. Then, the above-mentioned EFEF process may be performed through the deepened processing channel T1 to achieve a desired routing on the second sacrificial layer 1003b-1.

[0078] In particular, as mentioned above with reference to Fig. 15(a), Fig. 15(b) and Fig. 15(c) describes a photoresist (not shown) on the in Fig. 18(a) and Fig. 18(b) (the processing channels T1 are recessed as described above) and patterned to expose the processing channels T1 where the bridge parts need to be retained and to cover the processing channels T1 where the bridge parts need to be cut off. The pattern of the photoresist may be different from the pattern of the photoresist 1031 described above, thus exposing / covering different processing channels T1.

[0079] Through the processing channels T1 exposed by the photoresist, the exposed bridge portions of the second sacrificial layer 1003b-2 can be replaced by a positioning retaining layer 1033-1b in an etch and fill process. Regarding the positioning retaining layer 1033-1b, reference can be made to the above description of the positioning retaining layer 1033-2b. The photoresist can then be removed. Then, through the processing channels T1, the bridge portions of the second sacrificial layer 1003b-1, originally covered by the photoresist, in the processing channels T1 can be replaced by insulating portions 1035-1b in an etch and fill process. Regarding the insulating portions 1035-1b, reference is made to the above description of the insulating portions 1035-2b.And although the position-holding layer 1033-2b and the insulating parts 1035-2b formed thereover for the second sacrificial layer 1003b-2 are also exposed in the processing channels T1, the position-holding layer 1033-2b and the insulating parts 1035-2b cannot be substantially affected due to the etch selectivity.

[0080] So it will be the Fig. 19(a) and Fig. 19(b) shown structure is obtained. As shown in Fig. As shown in Figure 19(a), the second sacrificial layer 1003b-1 is divided into different parts by the insulating parts 1035-1 in the EFEF process, which parts may then form different conductive channels (or a part thereof).

[0081] To prevent subsequent processing of the first sacrificial layer (SiGe in this example) from affecting the position-maintaining layers 1033-1b and 1033-2b (both consisting of SiGe in this example, where the atomic percentages of Ge may be different), the position-maintaining layers 1033-1b and 1033-2b may be replaced by new position-maintaining layers with an etch selectivity with respect to the first sacrificial layer. For example, as in Fig. 20(a) and Fig. As shown in Figure 20(b), the position-maintaining layers 1033-1b, 1033-2b (SiGe) are selectively etched to be removed relative to the second sacrificial layer (Si) and the dielectric material around the second sacrificial layer through the processing channels T1. Then, new position-maintaining layers 1037-1b, 1037-2b ​​may be filled at the original positions of the position-maintaining layers 1033-1b, 1033-2b by a deposition-followed-etch-back method. For example, the position-maintaining layers 1037-1b and 1037-2b ​​may include Si, such as polysilicon or amorphous silicon, formed by a deposition such as chemical vapor deposition (CVD).

[0082] In addition, the processing channels T1 can be shielded to prevent the corresponding bridge parts from being affected in the subsequent processing. For example, as in Fig. 21(a) and Fig. 21(b) shows an oxide on the Fig. 20(a) and Fig. 20(b) in a sufficient amount to fill the gaps in the structure. The deposited oxide may then be planarized, for example, by CMP, which may be stopped at the second nitride sublayer 1027. Therefore, the corresponding layers 1011, 1023, 1025, which are also oxides, and the oxide formed here are collectively indicated by reference numeral 1039.

[0083] In addition, the previously formed hard mask layer 1025 / 1027 is used to define the processing channels T1 to the bridge parts, which can be removed here. For example, as in Fig. 22(a) and Fig. 22(b) shown in the Fig. 21(a) and Fig. In the structure shown in Figure 21(b), the second nitride sublayer 1027 is etched, for example, by hot phosphoric acid, to be removed. Then, a planarization process such as CMP may be performed on the resulting structure, and the CMP may stop at the second nitride sublayer 1013. In this way, the hard mask layer 1025 / 1027 defining the processing channels T1 is removed, while the hard mask layer 1011 / 1013 with a grid pattern remains.

[0084] Then, pattern cutting can be performed on the first sacrificial layer. At this time, each node exists in each first sacrificial layer. Some nodes can be removed according to a layout design of each via layer. To remove the nodes, processing channels to the nodes are required. Cutting the first sacrificial layer can be performed in essentially the same way as cutting the second sacrificial layer, except that the positions of the processing channels are different.

[0085] For example, openings exposing the nodes may be formed in the dielectric layer 1039. This may be accomplished using an additional hard mask layer. As shown in Fig. 23(a), Fig. 23(b), Fig. 23(c) and Fig. As shown in Figure 23(d), another hard mask layer may be formed on a top surface of the dielectric layer 1039 and on the top surface of the hard mask layer (1011 / 1013). Accordingly, the hard mask layer may also include a stack comprising a first sublayer 1041, for example, made of oxide with a thickness of 2 to 10 nm, and a second sublayer 1043, for example, made of nitride or a low-k dielectric material with a thickness of approximately 10 to 150 nm. Regarding the first sublayer 1041 and the second sublayer 1043, reference is made to the description of the first sublayer 1011 and the second sublayer 1013 given above.

[0086] The hard mask layer can be patterned into a desired pattern to expose the nodes, as described above. For this purpose, a photoresist 1045 can be formed on the hard mask layer. The photoresist 1045 is patterned by photolithography (exposure and development) to provide a series of openings, each centered, for example, at each node. To ensure that a downward-facing channel can be formed, the outer peripheries of the openings can protrude outward relative to the outer peripheries of the nodes in the hard mask layer 1011 / 1013. And to ensure that the nodes to be removed in the first sacrificial layer are completely removed, the dimensions of the openings can be larger than the dimensions of the nodes of the photoresist 1021 used to expose the nodes in the first sacrificial layer, as described above with reference to Fig. 9(a). In this example, the openings are shown as circular, but the present invention is not limited thereto, and the openings may also have various other shapes suitable for processing, such as an ellipse and the like.

[0087] Then processing channels can be formed. For example, as in Fig. 24(a), Fig. 24(b) and Fig. 24(c), the photoresist 1045 may be used as a mask to selectively etch the second sublayer 1043 (nitride), for example, by an RIE. For example, an RIE may be performed in the direction substantially perpendicular to the surface of the substrate and may stop at the first sublayer 1041 (oxide). Then, the first sublayer 1041 and the dielectric layer 1039 (here, both oxides) may be selectively etched, for example, by an RIE. For example, an RIE may be performed in the direction substantially perpendicular to the surface of the substrate until the top sacrificial layer 1003a-3 is exposed, thereby forming processing channels T2 as shown in Fig. 24(c). For example, a bottom surface of the processing channel T2 may be disposed between an upper surface and a lower surface of the second sacrificial layer 1003b-2 below the first sacrificial layer 1003a-3 to be exposed, thereby ensuring that the first sacrificial layer 1003a-3 is fully exposed and preventing the first sacrificial layer 1003a-2 disposed thereunder from being exposed. To precisely control an etching size, an ALE may be used. Afterward, the photoresist 1045 may be removed.

[0088] As in Fig. 25(a), each processing channel T2 is approximately centered at each node and each bridge part is substantially shielded (a part of the bridge parts may be exposed in the processing channels T2, which is why the position-holding layers 1033-1b, 1033-2b are replaced above, because the position-holding layers 1033-1b and 1033-2b may be exposed from the processing channel T2, especially when the device is miniaturized). As shown in Fig. As shown in Figure 24(c), in each processing channel T2, except for the first sacrificial layer 1003a-3, the remaining exposed material layers are all dielectric materials (the hard mask layers are made of oxide and nitride, the position-maintaining layer 1017 is made of oxynitride, the position-maintaining layer 1019 is made of SiC, the electrical layer 1039 is made of oxide, and the insulating part 1035-2b is made of SiC). Furthermore, in this example, the position-maintaining layer 1037-2b ​​is also exposed in the processing channel T2. It should be noted that in the cross section of Fig. 24(c) the first sacrificial layer 1003a-3 is not visible because the line CC' is positioned at the bridge parts (see Fig. 23(a)) and the bridge portions in the first sacrificial layer 1003a-3 are substantially removed.

[0089] All currently present nodes are exposed in the corresponding processing channels T2. Some of these nodes must be removed (replaced with insulating parts), and others must be retained. The nodes that must be removed and those that must be retained can be processed separately. To avoid mutual interference with the processing of the various layers, as described above, the nodes that must be retained can be replaced with a material that exhibits etch selectivity with respect to the first sacrificial layer.

[0090] For example, as in Fig. 25(a) to 25(f-4) show a photoresist 1047 on the Fig. 24(a), Fig. 24(b) and Fig. 24(c) (the photoresist 1045 is removed) and patterned by photolithography to expose processing channels T2 where the nodes need to be retained and to cover processing channels T2 where the nodes need to be removed. With the processing channels T2 exposed by the photoresist 1047, the first sacrificial layer 1003a-3 can be replaced with the position-maintaining layer 1037-3a by a method similar to the first etching and first filling method described above. The position-maintaining layer 1037-a may include a material having etch selectivity with respect to the first sacrificial layer, such as Si.

[0091] Fig. 25(f-1) to 25(f-4) show this process in detail. In particular, Fig. 25(f-1) a processing channel T2 exposed by the photoresist 1047. As in Fig. As shown in Figure 25(f-2), the exposed first sacrificial layer 1003a-3 (here SiGe) can be selectively etched through the processing channel T2 to be removed. Afterward, the photoresist 1047 can be removed. Then, as shown in Fig. 25(f-3), a (polycrystalline or amorphous) silicon 1037p (which can be converted to n-type or p-type by, for example, in-situ doping with a doping concentration of approximately 1∙10 19 up to 5∙10 21 cm -3 may be doped) through the processing channel T2, and the deposited silicon 1037p is etched back, such as by an RIE, to fill the position-maintaining layer 1037-3a at the position where the node of the removed first sacrificial layer 1003-a3 was originally located. Multiple deposition and etch-back steps may be performed to better fill the position-maintaining layer 1037-3a.

[0092] Then, some of the nodes of the first sacrificial layer 1003a-3 may be removed. Some of the nodes of the first sacrificial layer 1003a-3 may be replaced with insulating parts using a method similar to the second etching and second filling method described above. For example, as shown in Fig. As shown in Figure 26, the first sacrificial layer 1003a-3 (SiGe) may be selectively etched through the processing channels T2. In this way, a portion of the first sacrificial layer 1003a-3 originally covered by the photoresist 1047 may be removed in the processing channels T2. The nodes replaced by the position-maintaining layer 1037-3a, although the position-maintaining layer 1037-3a is also exposed in the processing channels T2, may be substantially unaffected due to the etch selectivity. Thus, gaps are formed at some of the nodes of the first sacrificial layer 1003a-3. The insulating portions 1035-3a may be filled in these gaps. The insulating portions 1035-3a may contain the same dielectric material, such as SiC, as the preceding insulating portions 1035-1b, 1035-2b. This filling can be achieved by etching back after deposition as described above.

[0093] Therefore, as in Fig. 26, by the EFEF process described above, some of the nodes in the first sacrificial layer 1003a-3 are replaced by the insulating parts 1035-3a, while the remaining nodes are preserved (actually, for etch selectivity, the remaining nodes are replaced by the position-holding layer 1037-3a) to subsequently define via holes.

[0094] Then, similar processing may be performed on the lower first sacrificial layer 1003a-2.

[0095] For example, the dielectric layer 1039 may be selectively etched, such as by RIE, to recess the processing channels T2, thereby exposing the first sacrificial layer 1003a-2. For example, the lower surface of the processing channels T2 may be disposed between an upper surface and a lower surface of the second sacrificial layer 1003b-1 below the first sacrificial layer 1003a-2 to be exposed. Then, the above-mentioned EFEF process may be performed to achieve the required via hole layout in the first sacrificial layer 1003a-2 through the recessed processing channels T2.

[0096] In particular, as in Fig. 27(a), Fig. 27(b) and Fig. 27(c) shows a photoresist 1053 on the structure of Fig. 26 (the processing channels T2 are recessed as described above) and patterned to expose the processing channels T2 where the nodes need to be retained and to cover the processing channels T2 where the nodes need to be removed. The pattern of the photoresist 1052 may be different from the pattern of the photoresist 1047 described above.

[0097] As in Fig. 28(a) and Fig. As shown in Figure 28(b), the exposed nodes of the first sacrificial layer 1003a-2 can be replaced by the position-maintaining layer 1037-2a in an etch and fill process through the processing channels T2 exposed by the photoresist. Regarding the position-maintaining layer 1037-2a, reference can be made to the above description of the position-maintaining layer 1037-3a. After that, the photoresist 1053 can be removed. Then, as shown in Fig. 29(a) and Fig.29(b), the nodes of the first sacrificial layer 1003a-2 in the processing channels T2, originally covered by the photoresist 1053, are replaced by insulating parts 1035-2a in an etch and fill process through the processing channels T2. Regarding the insulating parts 1035-2a, reference can be made to the above description of the insulating parts 1035-3a.

[0098] Fig. 30 shows a structure obtained by performing the EFEF process on each layer in the first stack (in fact, in this example, because the bottom sacrificial layer 1003a-1 is ultimately used to define an insulating layer, it is not necessary to further cut a pattern of the first sacrificial layer 1003a-1) as described above. As indicated by the arrows in the drawing, various interconnections are defined in the first stack.

[0099] Then, as in Fig. 31(a), the lowermost first sacrificial layer 1003a-1 may be replaced by an insulating material to achieve isolation between the interconnect structure and the substrate. For example, as shown in Fig. 31(b-1), the processing channels T2 may be further deepened to expose the first sacrificial layer 1003a-1. For example, the etching back to the dielectric layer 1039 may be stopped at the surface of the substrate 1001, so that bottom surfaces of the processing channels T2 may be defined by the upper surface of the substrate 1001. Then, the exposed first sacrificial layer 1003a-1 is selectively etched to be removed. Then, as shown in Fig. As shown in Figure 31(b-2), a dielectric material such as an oxide may be filled into the gaps of the resulting structure to achieve electrical insulation. A sufficient amount is deposited to fill the gaps in the structure. The deposited oxide may then be planarized, such as by CMP, which may be stopped at the second nitride sublayer 1043. All oxides in the structure are collectively indicated by reference numeral 1055.

[0100] In addition, the previously formed hard mask layer 1041 / 1043 is used to define the processing channels T2 and can be removed here. For example, the second nitride sublayer 1043 can be selectively etched by hot phosphoric acid to be removed. Then, a planarization process such as CMP can be performed on the resulting structure, and the CMP can be stopped at the second nitride sublayer 1013. In this way, the hard mask layer 1041 / 1043 defining the processing channels T2 is removed, while the hard mask layer 1011 / 1013 is formed with a grid pattern as in Fig. 32(a) and Fig. 32(b) still exists.

[0101] In the example described above, the second sacrificial layer is cut layer by layer, and then the first sacrificial layer is cut layer by layer. However, the present invention is not limited to this. For example, the first sacrificial layer can also be cut layer by layer, and then the second sacrificial layer can be cut layer by layer.

[0102] Then, a vertical device can be fabricated based on each active region in the second stack.

[0103] For this purpose, the dielectric layer 1055 can be etched back to expose the second stack. For example, as in Fig. As shown in Figure 33(b-1), the dielectric layer 1055 may be etched back, for example, by an RIE. The RIE may be performed in the direction substantially perpendicular to the surface of the substrate until the second stack is exposed. For example, an upper surface of the dielectric layer 1055 after the etchback may be arranged between an upper surface and a lower surface of the uppermost layer in the first stack. To precisely control the amount of etchback, an ALE may be used. Due to the presence of the hard mask layer 1011 / 1013, the exposed second stack may have a grid pattern. Then, as shown in Fig. 33(a) and Fig. 33(b-2), the position-holding layer 1019 may be selectively etched to be removed, thereby exposing the first source / drain layer 1005 and the second source / drain layer 1009.

[0104] The exposed first source / drain layer 1005 and the second source / drain layer 1009 may be doped to form source / drain regions therein. According to embodiments of the present invention, the doping may be performed by a fixed dopant source. However, the present invention is not limited thereto. For example, the first source / drain layer 1005 and the second source / drain layer 1009 may be doped in situ during growth, or the first source / drain layer 1005 and the second source / drain layer 1009 may be doped by ion implantation.

[0105] As in Fig. 34(a) and Fig. As shown in Figure 34(b), a solid dopant source layer 1057 may be formed on surfaces of the first source / drain layer 1005 and the second source / drain layer 1009. For example, to form an n-type device, the solid dopant source layer 1057 may include an oxide film containing n-type dopant and having a thickness of approximately 0.5 to 5 nm. The n-type dopant may include P or As in a proportion of approximately 0.01 to 3%. The solid dopant source layer 1057 may be formed on the Fig. 33(a) and 33(b-2) may be formed substantially uniformly by a deposition such as CVD or atomic layer deposition (ALD) to sufficiently cover the surfaces of the first source / drain layer 1005 and the second source / drain layer 1009. To avoid cross-contamination, a diffusion barrier layer 1059 may be formed on the solid dopant source layer 1057. For example, the diffusion barrier layer 1059 may include SiC and have a thickness of approximately 1 to 5 nm. The diffusion barrier layer 1059 may be formed substantially uniformly on the solid dopant source layer 1057 by a deposition such as CVD or ALD.

[0106] The above describes how the solid dopant source layer 1057 is formed for the n-type device. When a p-type device is also formed on the substrate, a solid dopant source layer for the p-type device may also be formed.

[0107] For example, as in Fig. 35(a) and Fig. 35(b) shows a photoresist 1061 on the Fig. 34(a) and Fig. 34(b). Through photolithography, the photoresist 1061 can shield a region where an n-type device is to be formed and thus the n-type dopant source layer 1057 in the region, and expose a region where a p-type device is to be formed and thus the fixed p-type dopant source layer 1057 in the region.

[0108] As in Fig. As shown in Figure 36, the exposed diffusion barrier layer 1059 and the solid n-type dopant source layer 1057 may be sequentially etched by a selective etch such as a vapor-phase HF to remove them. During the etching process, an exposed portion of the first oxide sublayer 1011 in the hard mask layer may also be removed. Thereafter, the photoresist 1061 may be removed.

[0109] Then, as in Fig. 37, a solid dopant source layer 1063 for a p-type device may be formed. For example, the p-type solid dopant source layer 1063 may comprise an oxide film containing a p-type dopant and having a thickness of approximately 0.5 nm to 5 nm. The p-type dopant may contain B at a level of approximately 0.01% to 3%. The solid dopant source layer 1063 may be formed substantially uniformly by a deposition such as CVD or ALD.

[0110] Although it is described here that the n-type solid dopant source layer 1057 is formed first and then the p-type solid dopant source layer 1063 is formed, the present invention is not limited thereto, and the formation order of the n-type dopant source layer 1057 and the p-type dopant source layer 1063 may be interchanged.

[0111] Thereafter, the dopant in the dopant source layer may be driven into the first source / drain layer 1005 and the second source / drain layer 1009, respectively, by a heat treatment to form source / drain regions therein. In the drawings, the n-type doping and the p-type doping are each represented by different gray levels. According to the embodiments, the concentration of the n-type doping may be approximately 1 10 18 - 1∙10 21 cm -3and the concentration of the p-type doping can be 1∙10 18 - 1∙10 21 cm -3 The solid dopant source layer and the diffusion interface layer can then be removed by a selective etching such as gas-phase HF.

[0112] Subsequently, a gate electrode can be formed around an outer periphery of the channel layer to complete the device fabrication. To form a gate electrode that can be self-aligned with the channel layer, the original position-holding layer can be restored around the source / drain layer. For example, as shown in Fig. 38(a) and Fig. As shown in Figure 38(b), a position-maintaining layer 1065 may be formed in the gaps of the second stack beneath the hard mask layer. Regarding the position-maintaining layer 1065, reference may be made to the above description of the position-maintaining layer 1019.

[0113] Furthermore, to reduce contact resistance, a silicide layer may be formed on the surfaces of the first source / drain layer 1005 and the second source / drain layer 1009. For example, prior to forming the position-maintaining layer 1065, a metal such as NiPt, Co, or Ti may be substantially uniformly deposited to a thickness of approximately 0.5 nm to 5 nm and heat-treated to cause the deposited metal to react with the first source / drain layer 1005 and the second source / drain layer 1009 (Si) to form a silicide (not shown). Afterward, the unreacted metal may be removed.

[0114] A gate stack can then be formed. Different gate stacks (e.g., with different equivalent work functions) can be formed for an n-type device and a p-type device.

[0115] For this reason, as in Fig. 39(a) and Fig. 39(b), the position-holding layer 1017 may be removed by selective etching. Thus, the surface of the channel layer 1007 is exposed. A gate dielectric layer 1067 may be formed around the surface of the channel layer 1007 by deposition. The gate dielectric layer 1067 may be deposited on the Fig. 38(a) and Fig. 38(b) may be formed substantially uniformly with a thickness of, for example, approximately 1 nm to 5 nm. For example, the gate dielectric layer 1067 may include a high-k gate dielectric such as HfO2. Before the high-k gate dielectric is formed, an interface layer may also be formed on the surface of the channel layer 1007, such as an oxide formed by thermal oxidation, with a thickness of approximately 0.3 nm to 2 nm.

[0116] Then, as in Fig. 40(a) and Fig. 40(b) shows a gate electrode material on the Fig. 39(a) and Fig. 39(b). For example, a work function adjustment metal for an n-type device may be deposited, and optionally, a conductive gate metal may also be deposited to completely fill the gaps in the structure. The deposited gate electrode material is etched back, such as by RIE, to obtain a gate electrode 1069. The RIE may be performed in the direction substantially perpendicular to the surface of the substrate. Due to the presence of the hard mask layer 1011 / 1013, the gate electrode 1069 has a grid pattern even after etching back. The gate electrode 1069 may thus be disposed at the position where the position-maintaining layer 1017 was originally disposed, and thus be self-aligned with the channel layer 1007.

[0117] The above describes how the gate electrode 1069 is formed for the n-type device. However, a gate electrode for the p-type device can also be formed.

[0118] For example, as in Fig. 41 shows a photoresist 1071 on which Fig. 40(a) and Fig. 40(b). Through photolithography, the photoresist 1071 can shield a region where an n-type device is to be formed, and thus the gate electrode 1069 in the region, and can expose a region where a p-type device is to be formed, and thus the gate electrode 1069 in the region. The exposed gate electrode 1069 can be removed by selective etching. Thereafter, the photoresist 1071 can be removed.

[0119] Then, as in Fig. 42(a) and Fig. As shown in Figure 42(b), a gate electrode 1073 for a p-type device may be formed in a space freed by removing the gate electrode 1069. The gate electrode 1073 may be formed in the same manner as the gate electrode 1069, but may include a different material than the gate electrode 1069 (e.g., have a different work function than the gate electrode 1069). Accordingly, the gate electrode 1073 may be self-aligned with the channel layer 1007.

[0120] In this example, the gate stacks of the n-type device and the p-type device share the same gate dielectric layer 1067, but the present invention is not limited thereto. For example, the gate dielectric layer 1067 may also be removed in a portion of the p-type device, and an additional gate dielectric layer may be formed for the p-type device. Accordingly, the formation order for the gate stack of the n-type device and the gate stack of the p-type device may be reversed.

[0121] As described above, gate electrode 1069 and gate electrode 1073 have the same grid pattern as the entire hard mask layer 1011 / 1013, so the gate electrodes are connected in the plane where the channel layer 1007 is arranged by the bridge parts. Unneeded connections between the gate electrodes can be cut off according to the circuit interconnection design.

[0122] For example, as in Fig. 43(a) and Fig. 43(b) shows a photoresist 1075 on the Fig. 42(a) and Fig. 42(b). The photoresist 1075 can be patterned by photolithography to cover the connections between the gate electrodes that need to be retained and to expose the connections between the gate electrodes that need to be cut off. Then, the exposed gate electrodes can be removed by selective etching. As shown in Fig. 43(b), the gate electrodes are cut off. After that, the photoresist 1075 can be removed. Then, as shown in Fig. 44, a dielectric material such as SiC may be filled into a gap created by cutting the gate electrodes to form insulating portions 1077, thereby achieving insulation between the gate electrodes. Filling the insulating portions 1077 may be achieved by the deposition-then-etch-back method described above, and thus corresponds to the pattern of the hard mask 1011 / 1013, with the insulating portions being arranged at positions where originally removed portions of the gate electrodes were arranged.

[0123] After the device is fabricated, interconnection can be performed. Interconnection includes forming conductive paths in the first stack; forming contact plugs that apply electrical signals to conductive channels or gate electrodes in the first stack, etc.

[0124] As described above, the interconnect channels are defined by the semiconductor material (in this example, silicon) in the first stack (other parts in the first stack are dielectric materials to achieve electrical isolation). The semiconductor material in the first stack can be replaced or converted to a conductive material to form an interconnect structure. For example, the semiconductor material can be converted to a conductive silicide through a silicification reaction. Alternatively, the semiconductor material can be replaced by other conductive materials. The silicification reaction is described here as an example.

[0125] To prevent the metal in the gate electrode from corroding during the silicification process, as in Fig. 45, a protective layer 1079 may be formed covering and thereby protecting the gate electrode. According to embodiments, the protective layer 1079 may be formed in the shape of a spacer by a spacer formation process. For example, a layer of SiC having a thickness of approximately 1 nm to 5 nm may be formed on the Fig. 44, and an RIE may be performed on the deposited SiC in the direction substantially perpendicular to the surface of the substrate to remove a laterally extending portion of the deposited SiC while leaving a vertically extending portion of the deposited SiC to obtain the protection layer 1079. The protection layer 1079 may be formed around an outer periphery of each node and the bridge portion in the second stack to cover the gate electrode formed around the channel layer.

[0126] In addition, the first stack is currently covered by the dielectric layer 1055. To silicify the semiconductor material in the first stack, the dielectric layer can be covered as in Fig. 46, for example, by an RIE (of course, before the dielectric layer 1055 is etched back, the gate dielectric layer 1067 on the surface of the dielectric layer 1055 must be selectively etched, for example, by an RIE). To precisely control the amount of etching back, an ALE can be used.

[0127] Then, as in Fig. 47(a), Fig. 47(b) and Fig. As shown in Figure 47(c), the dielectric layer 1055 may be further selectively etched to expose sidewalls of the semiconductor material in the first stack. The extent of the etch may be controlled so that the bottom of the dielectric layer 1005 continues to cover the substrate 1001. To precisely control the extent of the etch, an ALE may be used.

[0128] For the semiconductor material in the first stack, the silicification process can be performed through the exposed sidewalls of the first stack. For example, a metal such as NiPt, Co, or Ti can be deposited to a thickness of approximately 1 nm to 10 nm, and a heat treatment is performed to cause the deposited metal to react with the semiconductor material (Si) in the first stack to form a silicide 1081. Afterward, the unreacted metal can be removed.

[0129] When the contact layer is formed between the first stack and the second stack as described above, the first source / drain layer 1005 can be connected to the silicide 1081 through the contact layer, whereby the contact resistance can be reduced.

[0130] In the example described above, the silicification process of the semiconductor material in the first stack is performed after the gate electrode has been formed. This is because the high-k metal gate can be designed for a wider range of heat treatment (temperature), thereby allowing a larger process window to be obtained. However, the present invention is not limited to this. For example, after the interconnect structure has been formed in the first stack, the device can be fabricated in the second stack.

[0131] For the first stack, the dielectric layer in the first stack can be supplemented to achieve electrical isolation. For example, as in Fig. 48 shows an oxide on the Fig. 47(a), Fig. 47(b) and Fig. 47(c), and the deposited oxide may be etched back to form a dielectric layer 1055'. Prior to etching back, the deposited oxide may be planarized, such as by CMP, and may stop the CMP at the second nitride sublayer 1013. A top surface of the etched back dielectric layer 1055' may be disposed near the boundary between the first stack and the second stack to expose the protection layer 1079.

[0132] Contact plugs can then be formed. Such contact plugs can be connected to the interconnect structure in the first stack or can be connected to the gate electrodes to apply electrical signals. As described above, the contact plugs can be formed by converting a portion of the active area to a conductive material, so that the contact plugs are self-aligned with the gate electrodes to be connected or with the via holes in the interconnect structure.

[0133] At this time, a periphery of each active region is covered by the protective layer 1079. The contact plug can be formed by removing the protective layer 1079 around the active region to be converted or replaced by the contact plug and subjecting the thus exposed active region to silicification processing.

[0134] For example, as in Fig. 49(a), Fig. 49(b), Fig. 49(c) and Fig. 49(d) shows a photoresist 1083 on the Fig. 48. A series of openings may be formed in the photoresist 1083 by photolithography, and these openings are arranged at nodes where contact plugs are to be formed. The exposed protective layer 1079 may be removed by selective etching through the openings in the photoresist 1083. And the gate dielectric layer, the gate electrodes, etc., exposed by removing the protective layer 1079, may be sequentially removed to expose the sidewalls of the corresponding active regions. Thereafter, the photoresist 1083 may be removed.

[0135] This etching allows the gate electrodes, which may otherwise be connected between the active regions with exposed sidewalls, and also the adjacent active regions to be cut off. As described above, the connections between the gate electrodes are determined according to a circuit interconnection layout. To compensate for the truncation of the gate electrodes, as shown in Fig. 50(a), Fig. 50(b), Fig. 50(c) and Fig. 50(d) shows that the gaps of the first stack under the hard mask layer are filled with a semiconductor material 1085 such as a deposited polysilicon or an amorphous silicon, which may later also be replaced by or converted to a conductive material.

[0136] Afterwards, as in Fig. 51(a), Fig. 51(b), Fig. 51(c) and Fig. 51(d), a silicification process may be performed to convert the semiconductor material not covered by the protective layer 1079 into a conductive silicide for use as a contact plug 1087. Regarding the silicification process, reference may be made to the description given above, which will not be repeated here.

[0137] As in Fig. 51(a), a portion of the contact plugs may be in contact with the interconnect structure below to apply electrical signals to the interconnect structure. In addition, as shown in Fig. 51(b), Fig. 51(c) and Fig. As shown in Figure 51(d), a portion of the contact plugs is electrically insulated from the interconnect structure below by the insulating portions 1035-3a, and the contact plugs can be used to apply electrical signals to the gate electrodes. As shown in Fig. As shown in Figure 51(d), a laterally extending portion of the contact plug 1087 contacts the gate electrode 1073. As described above, this laterally extending portion is aligned with the bridge portion in the grid pattern of the hard mask layer and is located at a position where the gate electrode was originally located.

[0138] The processing described above achieves connections between the lower source / drain regions and the gate electrodes of the device. Furthermore, contact parts for the upper source / drain regions and the contact plugs of the device can be formed above the device. For example, as shown in Fig. 52(a), Fig. 52(b), Fig. 52(c) and Fig. 52(d), a dielectric layer such as an oxide (further indicated here by 1055') may be deposited to fill the gaps in the structure and provide electrical isolation between devices. Furthermore, contact portions 1091 extending into the hard mask layer and / or the dielectric layer 1055' may be formed to apply electrical signals to the upper source / drain regions and contact plugs of the device. These contact portions may be formed by etching holes and filling the holes with a conductive material such as a metal.

[0139] A vertical component has been described above by way of example, but the present invention is not limited thereto and can also be applied to other types of components such as a FinFET or a planar semiconductor component.

[0140] Fig. 53 to 66(b) are schematic views of some stages in a process for manufacturing a FinFET according to embodiments of the present invention. The following mainly describes differences from the previously described embodiments, and duplicate descriptions of the same parts as in the previously described embodiments are omitted or simplified.

[0141] As in Fig. 53, a first stack of alternately arranged first sacrificial layers 2003a-1, 2003a-2, 2003a-3 and second sacrificial layers 2003b-1, 2003b-2 may be formed on a substrate 2001. For details on the substrate 2001, the first sacrificial layers 2003a-1, 2003a-2, 2003a-3, and the second sacrificial layers 2003b-1, 2003b-2, reference is made to the above description of the substrate 1001, the first sacrificial layers 1003a-1, 1003a-2, 1003a-3, and the second sacrificial layers 1003b-1, 1003b-2. Furthermore, a contact layer may be provided on the substrate prior to forming the first stack.

[0142] A fin precursor layer 2005 can be formed on the first stack, for example, by epitaxial growth. The fin precursor layer 2005 can contain a suitable semiconductor material, such as Si, to subsequently form a fin used as an active region of the FinFET. The fin precursor layer 2005 can be formed with a specific height, such as 20 nm to 100 nm.

[0143] A hard mask layer may be formed on the fin precursor layer 2005. For example, the hard mask layer may include a first sublayer 2011 and a second sublayer 2013. For details on the first sublayer 2011 and the second sublayer 2013, reference may be made to the description of the first sublayer 1011 and the second sublayer 1013 given above.

[0144] Similar to the embodiment described above, a grid pattern can be defined in the first stack and in the fin precursor layer 2005. For this purpose, as shown in Fig. 54(a) and Fig. 54(b), a photoresist 2015 having a grid pattern may be formed. For details of the photoresist 2015 and the grid pattern, reference may be made to the details of the photoresist 1015 and its grid pattern described above.

[0145] Note that in the photoresist 2015 of this example, each node portion in the grid pattern is thicker than each bridge portion in the grid pattern, which is similar to the photoresist 1015 described above. This is advantageous for subsequently making contact with a source / drain region formed at each node. However, the present invention is not limited thereto. The line width of the node portion may be substantially equal to the line width of the bridge portion. For example, the grid pattern may be defined by straight lines that cross each other with a uniform thickness.

[0146] Then an active area can be defined.

[0147] Similar to the embodiment described above, the pattern of the photoresist 2015 may be transferred to the hard mask layer and then transferred to the fin precursor layer 2005 thereunder. In particular, as shown in Fig. 55(a) and Fig. As shown in Figure 55(b), the patterned photoresist 2015 may be used as a mask, and the hard mask layer (2013, 2011) and the fin precursor layer 2005 may be selectively etched sequentially, such as by RIE. For example, RIE may be performed in the direction substantially perpendicular to a surface of the substrate and stop at a top surface of the first stack. Therefore, the fin precursor layer 2005 may have the same grid pattern as the hard mask layer. Edges of the grid (lines extending in a row or column direction) may define the positions of fins. In particular, an approximately central part of the bridge portion of the fin precursor layer 2005 may be used as a channel region, and portions on both sides of the channel region (a node region and bridge portions with a certain length around the node portion) may be used as source / drain regions. After that, the photoresist 2015 may be removed.

[0148] To avoid impacting the fin precursor layer 2005 (in this example, the first fin precursor layer 2005 and the second sacrificial layer in the first stack are made of Si), when subsequently processing the first stack, a protective layer may be formed on a surface of the fin precursor layer 2005. For example, as shown in Fig. As shown in Figure 56, a protective layer 2101 may be formed on sidewalls of the fin precursor layer 2005 in a gap formation process. For example, the protective layer 2101 may include nitride and may have a thickness of approximately 1 nm to 10 nm.

[0149] Then, a connection setup can be defined in the first stack according to the EFEF process described above. For this purpose, reference can be made to the steps described above with reference to Fig. 8(a) to 47(c). The description given above with reference to Fig. However, the processes for source / drain doping and metal gate formation described in Figures 33(a) to 45 are omitted here.

[0150] The Fig. 57(a), Fig. 57(b), Fig. 57(c) and Fig. 57(d) can be obtained. As shown in the drawings, a silicide interconnect path 2081 is formed in the first stack, including a via hole in the via layer and a conductive channel in the interconnect layer. For details on the interconnect path 2081, reference is made to the description of the silicide 1081 given above. Furthermore, the drawings also show insulating parts 2035-2a, 2035-3a, 2035-1b, 2035-2b in the first stack and a dielectric layer 2055 in the first stack. For details of the insulating parts 2035-2a, 2035-3a, 2035-1b, 2035-2b and the dielectric layer 2055, reference is made here to the description of the insulating parts 1035-2a, 1035-3a, 1035-1b, 1035-2b and the dielectric layer 1055 given above.

[0151] After defining the connection structure, the component can be formed. For this purpose, as in Fig. 58, the protective layer 2101 can be removed by selective etching.

[0152] When the protective layer 2101 is removed, the second sublayer 2013, which in this example also consists of nitride, can also be removed.

[0153] Furthermore, a dielectric may be filled into the first stack to achieve electrical isolation. For example, an oxide may be deposited, and the deposited oxide may be etched back to form a dielectric layer 2055'. Before etching back, the deposited oxide may be planarized, for example, by CMP. A top surface of the etched back dielectric layer 2055' may be disposed near a boundary between the first stack and the second stack, for example, below the boundary.

[0154] The fin precursor layer 2005 may extend vertically relative to the underlying fin-like structure. Various techniques are known for fabricating a finFET based on fins, the following description being only one example.

[0155] At this point, the fin precursor layer 2005 is continuous, thus connecting the active regions of each device. The fin precursor layer 2005 can be separated into different active regions according to the device layout design. Gate electrodes crossing these active regions (fins) can be formed to fabricate the devices. According to embodiments of the present invention, the separation of the active regions of the devices and the fabrication of the gate electrodes can be combined.

[0156] For example, as in Fig. 59(a), Fig. 59(b), Fig. 59(c) and Fig. 59(d), sacrificial gates crossing each bridge portion of the fin precursor layer 2005 may be formed on the dielectric layer 2055'. For example, a sacrificial gate dielectric layer 2103 and the sacrificial gate electrode 2105 may be formed on the dielectric layer 2055' by deposition. For example, the sacrificial gate dielectric layer 2103 may include an oxide and have a thickness of approximately 1 nm to 5 nm, the sacrificial gate electrode layer 2105 may include amorphous silicon or polysilicon, and a top surface of the sacrificial gate electrode layer 2105 may be higher than a top surface of the fin precursor layer 2005 to cover sidewalls and a top surface of each bridge portion. To facilitate patterning, a hard mask layer 2107 may be formed on the sacrificial gate electrode layer 2105 by, for example, deposition.For example, the hard mask layer 2107 may contain nitride and have a thickness of approximately 10 nm to 150 nm. The hard mask layer 2107 and the sacrificial gate electrode layer 2105 may be patterned into a desired shape through a photoresist (not shown) by a selective etching such as RIE, where the desired shape may, for example, consist of stripes crossing each bridge portion (e.g., perpendicularly). The etching may stop at the oxide dielectric sacrificial gate layer 2103.

[0157] As in Fig. As shown in Figure 59(a), a sacrificial gate is formed at an approximately central portion of each bridge portion of the fin precursor layer 2005, crossing the bridge portion. According to the layout design, some of the sacrificial gates may be connected to each other. Note that these sacrificial gates are not necessarily subsequently replaced with real gates; some of the sacrificial gates may define isolation positions between the active regions.

[0158] In Fig. In Figure 59(b), the structure in the first stack is not shown for simplicity. Regarding the structure in the first stack, reference can be made to the corresponding sections of the embodiment described above.

[0159] Then you can Fig. 60(a), Fig. 60(b) and Fig. 60(c), gate spacers 2109 may be formed on sidewalls of a sacrificial gate. For example, the gate spacers 2109 may include nitride. There are many different known methods for forming gate spacers, which will not be discussed in detail here. It should be clear that the gate spacers 2109 may also be formed on vertical sidewalls of the fin precursor layer 2005, but this is not shown here for simplicity.

[0160] For example, ion implantation can be used to dope the fin precursor layer 2005 (and in particular, a portion of the fin precursor layer 2005 not covered by the sacrificial gates, such as each node and a certain length of the bridge portions around the node) to form the source / drain regions. Different conductivity types can be doped for n-type and p-type devices, respectively.

[0161] According to embodiments of the present invention, a technique for straining source / drain regions may be used. For example, a portion of the fin precursor layer 2005 not covered by the sacrificial gate may be selectively etched, such as by RIE, to partially remove the fin precursor layer 2005, while a portion of the fin precursor layer 2005 may be left as a seed layer. Then, the source / drain regions may be formed on the remaining seed layer, for example, by epitaxial growth. The grown source / drain regions may comprise a different material than the material of the fin precursor layer 2005 (for example, have a different lattice constant than the lattice constant of the fin precursor layer 2005) to exert mechanical stress on the channel regions formed in the fin precursor layer 2005.For example, in n-type devices, the source / drain regions can contain 2111 Si:C, and in p-type devices, the source / drain regions can contain 2113 SiGe. The source / drain regions can be doped in situ during growth.

[0162] In addition, a heat treatment may be performed to diffuse the dopant, thereby improving electrical connections between the source / drain regions and via holes beneath the source / drain regions.

[0163] Then the active areas can be separated and the sacrificial gates replaced.

[0164] For this purpose, as in Fig. 61 shows an oxide on the Fig. 60(a), Fig. 60(b) and Fig. 60(c), and the deposited oxide may be planarized, such as by CMP (which may stop at sacrificial gate 2105), to fill gaps within the devices. The deposited oxide and dielectric layer 2055' are further indicated collectively by reference numeral 2055'.

[0165] Then, as in Fig. 62(a) and Fig. 62(b), a photoresist 2111 may be formed on the dielectric layer 2055' and patterned to cover sacrificial gates that need to be replaced with real gates and to expose sacrificial gates that define isolation positions between the active areas according to the layout design. Subsequently, the photoresist 2111 may be coated as shown in Fig. 63(a), Fig. 63(b) and Fig. 63(c) may be used as a mask for selectively etching the sacrificial gate electrode layer 2105 and the sacrificial gate dielectric layer 2013 to expose the underlying fin precursor layer 2005 (the middle part of the corresponding bridge part). The exposed fin precursor layer 2005 may be selectively etched, for example, by an RIE, wherein the RIE may stop at the underlying dielectric layer 2055' so that the fin precursor layer 2005 is cut off at corresponding positions. Thereafter, the photoresist 2111 may be removed. On an inner side of the corresponding sacrificial gate spacers, a dielectric such as an oxide may be filled by deposition and then CMP to achieve electrical isolation. The filled dielectric and the dielectric layer 2055' are collectively indicated by reference numeral 2113.

[0166] Then the gate replacement can be performed. As in Fig. 64(a), Fig. 64(b) and Fig. As shown in Figure 64(c), the sacrificial gate electrode layer 2105 and the sacrificial gate dielectric layer 2103 may be removed by selective etching, and a gate dielectric layer 2067 and gate electrode layers 2069 and 2073 are formed in a gap left by the removal of the sacrificial gate electrode layer 2105 and the sacrificial gate dielectric layer 2103. For details on the gate dielectric layer 2067 and the gate electrode layers 2069 and 2073, reference can be made to the description of the gate dielectric layer 1067 and the gate electrode layers 1069 and 1073 given above. Various methods for performing gate replacement are known, which will not be explained in detail here.

[0167] Similar to the embodiments described above, some of the source / drain regions may define contact plugs. As in Fig. 65(a), Fig. 65(b) and Fig. As shown in Figure 65(c), a photoresist 2083 may be formed and patterned to have openings where contact plugs are to be formed. The dielectric layer 2113 may be recessed through the openings in the photoresist 2083 by a selective etch such as RIE to expose the source / drain regions at the corresponding positions. The exposed source / drain regions may be converted into contact plugs 2087 by silicification processing. For details on the silicification processing, reference may be made to the description given above.

[0168] Connections between some of the source / drain regions of the components and the interconnect structure are achieved by the processing described above. Furthermore, for some source / drain regions, gate electrodes and contact plugs of the components can be formed over the components. For example, as shown in Fig. 66(a) and Fig. As shown in Figure 66(b), a dielectric such as an oxide (here indicated together with the dielectric layer 2113 by reference numeral 2113') may be deposited to fill the gaps in the structure and achieve electrical isolation between the devices. Furthermore, contact portions 2091 extending through the dielectric layer 2113' may be formed. Because electrical connections to some source / drain regions can be achieved through the interconnect structure beneath the devices, a more extensive area of ​​metal interconnects may be provided above the devices, which is advantageous for device miniaturization.

[0169] Fig. 67 to 70(b) are schematic views of some stages in a process for manufacturing a planar semiconductor device according to embodiments of the present invention. The following mainly describes the differences from the above-described embodiments; descriptions of the same parts as in the above-described embodiments may be simplified or omitted.

[0170] As in Fig. 67, a first stack of alternately arranged first sacrificial layers 3003a-1, 3003a-2, 3003a-3 and second sacrificial layers 3003b-1, 3003b-2 may be formed on a substrate 3001. For details on the substrate 3001 and the first sacrificial layers 3003a-1, 3003a-2, 3003a-3 and the second sacrificial layers 3003b-1, 3003b-2, reference may be made to the above description of the substrate 1001 and the first sacrificial layers 1003a-1, 1003a-2, 1003a-3 and the second sacrificial layers 1003b-1, 1003b-2.

[0171] An active layer 3005 may be formed on the first stack, for example, by epitaxial growth. The active layer 3005 may contain a suitable semiconductor material, such as Si. Compared to the fin precursor layer 2005, the active layer 3005 may be relatively thin, having a thickness of, for example, 5 nm to 70 nm.

[0172] Similar to the embodiments described above, a grid pattern may be defined in the first stack and in the active layer 3005. For this reason, reference may be made to the description given above in connection with Fig. 54(a) to 57(d) may be referred to. Then, as with reference to Fig. 58, a protective layer on sidewalls of the grid pattern of the active layer 3005 may be removed and a dielectric layer 3055 may be formed. A difference from the embodiments described above is that when forming the dielectric layer 3055, the CMP may stop at an upper surface of the active layer 3005 without re-etching the dielectric layer 3055 to achieve the Fig. 68(a) and Fig. 68(b). Thus, in this embodiment, unlike the FinFET, the active layer does not need to protrude relatively. Regarding 3081, 3055-2a in the figures, reference can be made to the description of 1081, 1035-2a given above.

[0173] Thereafter, a device based on the active layer 3005 may be fabricated. The process for fabricating the device may be substantially the same as the process for fabricating the FinFET described above, except that the shapes of the active regions are different.

[0174] According to embodiments of the present invention, as shown in Fig. 69(a) and Fig. 69(b) after defining the grid pattern as above with reference to Fig. 54(a) to 57(d), the protective layer 3101 on the sidewalls of the active layer 3005 in the grid pattern is not removed. Regarding the protective layer 3101, reference can be made to the description of the protective layer 2101 given above. While the protective layer 3101 remains, a dielectric layer 3055 is formed. When the dielectric layer 3055 is formed, the CMP can stop at a second sublayer 3013 of the hard mask layer. This can reduce damage to the active layer 3005 by the CMP. Thereafter, as shown in Fig. 70(a) and Fig.As shown in Figure 70(b), the second sublayer 3013 and the nitride protection layer 3101 may be etched back by selective etching to expose the underlying first sublayer 3011. To precisely control the amount of etching back, an ALE may be used. Then, the first sublayer 3013 may be selectively etched to expose an area of ​​the active layer 3005. Thereafter, a device based on the active layer 3005 may be fabricated. Regarding the first sublayer 3011 and the second sublayer 3013, reference may be made to the description of the first sublayer 1011 and the second sublayer 1013 given above.

[0175] The interconnection structure and circuitry according to embodiments of the present invention can be applied to various electronic devices. For example, an integrated circuit (IC) can be formed based on such an interconnection structure or circuitry, and an electronic device can be constructed therefrom. Therefore, the present invention also provides an electronic device including the above-mentioned semiconductor device. The electronic device may also include components such as a display screen provided with the integrated circuit or a wireless transceiver provided with the integrated circuit. Such an electronic device may be a smartphone, a computer, a tablet computer (PC), a portable smart device, a mobile power supply, etc.

[0176] According to embodiments of the present invention, a method for manufacturing a system-on-chip (SoC) is also provided. The method may use the methods described above. In particular, a variety of types of components may be integrated on the chip, at least some of which are manufactured according to the method of the present invention.

Claims

[1] An interconnection structure for a plurality of semiconductor devices formed on a substrate (1001), the interconnection structure being arranged under the plurality of semiconductor devices and comprising: at least one via layer (1003a-1, 1003a-2, 1003a-3, 2003a-1, 2003a-2, 2003a-3) and at least one connecting layer (1003b-1, 1003b-2, 2003b-1, 2003b-2) arranged alternately in a direction from each semiconductor device to the substrate (1001), wherein via holes in each via layer are arranged under a first group of source / drain regions (1005, 1009) in the plurality of semiconductor devices, and insulating parts (1035-2a, 1035-3a, 2035-2a, 2035-3a) in each via layer are arranged under a second group of source / drain regions (1005, 1009) in the plurality of semiconductor devices, wherein each interconnect layer comprises conductive nodes each disposed beneath at least a portion of the plurality of semiconductor devices, and wherein a conductive channel is provided in each interconnect layer between at least one conductive node and at least one other node, and the via holes in each via layer and the conductive nodes in each interconnect layer corresponding to the via holes at least partially overlap in a direction from each semiconductor device to the substrate (1001). [2] The interconnect structure of claim 1, wherein the via holes in each via layer and the corresponding conductive nodes in each interconnect layer are substantially aligned with each other in the direction from the semiconductor device to the substrate (1001). [3] The interconnect structure of claim 1, wherein the plurality of semiconductor devices comprise a vertical semiconductor device, a planar semiconductor device and / or a fin field effect transistor. [4] The interconnect structure of claim 1, wherein at least one via hole in each via layer, the corresponding conductive nodes in each interconnect layer, and the source / drain regions (1005, 1009) of corresponding semiconductor devices are substantially aligned with each other in the direction from the semiconductor device to the substrate (1001). [5] The interconnection structure according to claim 1, wherein the direction from the semiconductor device to the substrate (1001) is a direction substantially perpendicular to a surface of the substrate (1001). [6] The interconnect structure of claim 1, wherein the via holes in each via layer are substantially coplanar and the conductive nodes and conductive channels in each interconnect layer are substantially coplanar. [7] The interconnect structure according to claim 1, wherein the insulating parts in each via layer and the corresponding conductive nodes in each interconnect layer at least partially overlap with each other in the direction from the semiconductor device to the substrate (1001). [8] The interconnect structure of claim 7, wherein the via holes in each via layer and the corresponding conductive nodes in each interconnect layer are substantially aligned with each other in the direction from the semiconductor device to the substrate (1001), and wherein the insulating parts in each via layer and the corresponding conductive nodes in each interconnect layer are substantially aligned with each other in the direction from the semiconductor device to the substrate (1001), wherein the via holes in each via layer, the corresponding conductive nodes in each interconnect layer, and the source / drain regions (1005, 1009) of corresponding semiconductor devices are substantially aligned with each other in the direction from the semiconductor device to the substrate (1001), and the insulating parts in each via layer, the corresponding conductive nodes in each interconnect layer, and the source / drain regions (1005, 1009) of the corresponding semiconductor devices are substantially aligned with each other in the direction from the semiconductor device to the substrate (1001), wherein the layout of the via holes and the insulating parts in each via layer is substantially the same as the layout of the conductive nodes in each interconnect layer, wherein the via holes and the insulating parts in each via layer are substantially coplanar and the conductive nodes and the conductive channels in each interconnect layer are substantially coplanar, wherein the insulating material of the insulating parts is different from the insulating material of a dielectric interlayer (1055) in the interconnect structure, wherein the via holes and the insulating parts have substantially the same lateral dimension. [9] The interconnect structure of claim 1, wherein the via holes, the conductive nodes, and the conductive channels comprise a metal silicide, wherein a channel material of at least a portion of each semiconductor device is a single-crystal semiconductor material. [10] Circuit comprising: a substrate (1001), a connection structure arranged on the substrate (1001), wherein the connection structure comprises at least one via layer (1003a-1, 1003a-2, 1003a-3, 2003a-1, 2003a-2, 2003a-3) and at least one connection layer (1003b-1, 1003b-2, 2003b-1, 2003b-2) arranged alternately in a direction substantially perpendicular to a surface of the substrate (1001), wherein the uppermost layer of the connection structure is a via layer, and a plurality of semiconductor components arranged on the connection structure, wherein via holes in each via layer are arranged at a first group of points in a two-dimensional grid under a first group of the plurality of semiconductor components, and insulating parts (1035-2a, 1035-3a, 2035-2a, 2035-3a) in each via layer are arranged at a second group of points, different from the first group of points in the two-dimensional grid, under a second group of the plurality of semiconductor components, wherein each connecting layer comprises main body parts arranged at positions of at least some points in the two-dimensional grid, and extension parts extending from the main body parts in a row or column direction, and the mutually facing extension parts of at least some of adjacent main body parts are in contact, and Source / drain regions (1005, 1009) of at least a portion of the plurality of semiconductor devices are in contact with corresponding via holes in the uppermost via layer. [11] The circuit of claim 10, wherein in each interconnect layer, insulating portions (1035-1b, 1035-2b, 2035-1b, 2035-2b) are disposed between mutually facing extension portions extending from at least a portion of adjacent main body portions, and wherein the insulating portion and the extension portions extend in the same direction and are substantially coplanar. [12] The circuit of claim 10, wherein the main body portion in each interconnect layer has a thickness greater than the thickness of the extension portion in each interconnect layer. [13] The circuit of claim 10, wherein the insulating portions and the via holes are substantially coplanar. [14] A circuit according to claim 10, wherein: at least some of the plurality of semiconductor devices are vertical semiconductor devices having vertical active regions extending in a direction substantially perpendicular to the surface of the substrate (1001) at positions of at least some of the points in the two-dimensional grid, or at least a portion of the plurality of semiconductor devices are planar semiconductor devices or a fin field effect transistor having horizontal active regions or fins extending in the row or column direction. [15] The circuit of claim 10, further comprising: contact plugs disposed at a portion of points in the two-dimensional grid on the interconnect structure. [16] The circuit of claim 10, further comprising: contact parts arranged at positions of at least a portion of the points in the two-dimensional grid on the plurality of semiconductor devices, the contact parts extending downwards to contact source / drain regions (1005, 1009) or the contact plugs of corresponding semiconductor devices, wherein at least some of the plurality of semiconductor devices are vertical semiconductor devices having vertical active regions extending in a direction substantially perpendicular to the surface of the substrate (1001) at positions of at least some of the points in the two-dimensional grid, and the contact plugs and the vertical active regions are substantially coplanar, or wherein at least some of the plurality of semiconductor devices are planar semiconductor devices or fin field-effect transistors having horizontal active regions or fins extending in the row or column direction, and the contact plugs and the source / drain regions (1005, 1009) in the horizontal active regions or fins are substantially coplanar, wherein at least a portion of the contact plugs are in contact with the uppermost via holes, wherein at least a portion of the plurality of semiconductor devices are vertical semiconductor devices having vertical active regions extending in a direction substantially perpendicular to the surface of the substrate (1001) at positions of at least a portion of the points in the two-dimensional grid, and wherein each vertical semiconductor device comprises a gate electrode (1069, 1073) formed around a channel region in a vertical active region, and at least a portion of the contact plugs are in contact with the gate electrodes (1069, 1073) of the adjacent vertical semiconductor devices, wherein the via hole contains a metal silicide, the main body part and the extension part in the interconnect layer contain a metal silicide, and the contact plug contains a metal silicide. [17] The circuit of claim 14, wherein a horizontal active region of each planar semiconductor device or a fin of each fin field effect transistor comprises a channel region disposed between adjacent points in the two-dimensional lattice and source / drain regions disposed on either side of the channel region. [18] The circuit of claim 17, wherein each planar semiconductor device or fin field effect transistor comprises a gate electrode (1069, 1073) extending in a direction crossing an extension direction of a corresponding horizontal active region or fin or overlapping a corresponding channel region in a vertical direction. [19] The circuit of claim 10, further comprising: a hard mask layer (1011, 1013, 1025, 1027, 1041, 1043, 2011, 2013, 2107) disposed over the active region, the hard mask layer having a grid pattern defined by the rows and columns, wherein the active region comprises a single-crystal semiconductor material, wherein the channel region of the semiconductor device comprises a single-crystal semiconductor material. [20] An electronic device comprising the connection structure according to any one of claims 1 to 9 or the circuit according to any one of claims 10 to 19.

Images