Semiconductor element, current transformer device and methods for manufacturing semiconductor components

Abstract

Semiconductor device (10) comprising the following: a base plate (1); a substrate (2) arranged on the base plate (1); a semiconductor element (3) that is electrically connected to the substrate (2); a housing (4) arranged on the base plate (1) such that it covers the substrate (2) and the semiconductor element (3); and a wiring connection (5) which is electrically connected to the semiconductor element (3), wherein the housing (4) comprises a first housing unit (41) and a second housing unit (42) which is separate from the first housing unit (41), the wiring connection (5) includes a first wiring unit (51), wherein the first wiring unit (51) is arranged such that it projects from an inside of the housing (4) to an outside and is connected to at least one, the semiconductor element (3) and / or the substrate (2), and a second wiring unit (52) which is bent with respect to the first wiring unit (51) and is arranged outside the housing (4), wherein the first housing unit (41) and the second housing unit (42) are arranged to enclose the first wiring unit (51), the first wiring unit (51) being sandwiched between the first housing unit (41) and the second housing unit (42), wherein the first housing unit (41) and the second housing unit (42) are arranged such that they are in contact with the base plate (1).

Description

TECHNICAL AREA

[0001] The present invention relates to a semiconductor device, a current transformer device, and a method for manufacturing the semiconductor device. STATE OF THE ART

[0002] Known semiconductor devices have a wiring terminal that connects the semiconductor device to an external device. A portion of the wiring terminal is open to the outside of a package through a through-hole in the semiconductor device's housing. For example, in a semiconductor device described in Japanese Patent JP 7-58 282 (Patent Document 1), a semiconductor element is attached through an insulating substrate to a metal plate mounted on a substrate. An electrode terminal (wiring terminal) is glued to the metal plate. After the housing is glued to the mounting substrate, the portion of the electrode terminal (wiring terminal) that protrudes through the through-hole in the housing to the outside of the housing is bent.US Patent 2012 / 0074542A1 (Patent Document 2) describes a semiconductor device in which a control board can be mounted outside a casing and a power semiconductor element can be placed inside the casing. The device comprises a metal step holder, a shielding plate, and a metal ring. The holder includes a base section implanted in the casing, a connecting section extending from one end of the base section, and a step section formed at a boundary between the base section and the connecting section. The shielding plate is positioned over the step section such that the connecting section of the holder penetrates the shielding plate. One end of the metal ring projects from one end of the connecting section beyond the shielding plate.The semiconductor device is designed so that the control board is mounted above the protruding end of the metal ring and attached to the connecting section by an engagement element. STATE OF THE ART Patent document 1: Japanese patent JP 7-58 282 Patent document 2: US Patent US 2012 / 0 074 542 A1 BRIEF DESCRIPTION OF THE INVENTION Problems to be solved with the invention

[0003] In the semiconductor device described in patent document 1, after the housing is glued to the base plate, the area of ​​the electrode terminal (wiring terminal) exposed to the outside of the housing through the through-hole formed in the housing is bent. When the electrode terminal (wiring terminal) is bent, a mechanical force is exerted on a bonding unit between the electrode terminal (wiring terminal) and the metal plate, so that the electrode terminal (wiring terminal) is sometimes peeled away from the metal plate.

[0004] The present invention was made with regard to the problems mentioned above, and one objective of the present invention is to provide a semiconductor device, a current transformer device and a method for manufacturing the semiconductor device which is capable of preventing the detachment of the wiring connection. Means of solving the problems

[0005] A semiconductor device according to the invention comprises a base plate, a substrate, a semiconductor element, a housing, and a wiring connection. The substrate is arranged on the base plate. The semiconductor element is electrically connected to the substrate. The housing is arranged on the base plate such that it covers the substrate and the semiconductor element. The wiring connection is electrically connected to the semiconductor element. The housing comprises a first housing unit and a second housing unit, which is separate from the first housing unit. The wiring connection comprises a first wiring unit and a second wiring unit. The first wiring unit is arranged such that it projects from the inside of the housing to the outside and is connected to at least one of the two elements, the semiconductor element and / or the substrate.The second wiring unit is bent relative to the first wiring unit and is located outside the housing. The first housing unit and the second housing unit are arranged to enclose the first wiring unit. Effect of the invention

[0006] In the semiconductor device according to the present invention, the second wiring unit is bent relative to the first wiring unit and arranged outside the housing. The first housing unit and the second housing unit are arranged such that the first wiring unit lies between them. This prevents mechanical forces from bending the wiring connection while the first wiring unit is bonded to at least one of the semiconductor elements and the substrate. Consequently, detachment of the wiring connection from at least one of the semiconductor elements and / or the substrate is prevented. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a sectional view that schematically shows a first configuration of a semiconductor device according to a first embodiment of the present invention; Fig. Figure 2 is a top view schematically showing the first configuration of the semiconductor device according to the first embodiment of the present invention; Fig. Figure 3 is a sectional view that schematically shows a second configuration of the semiconductor device according to the first embodiment of the present invention; Fig. Figure 4 is a top view schematically showing the second configuration of the semiconductor device according to the first embodiment of the present invention; Fig. Figure 5 is a flowchart showing a method for manufacturing the semiconductor device according to the first embodiment of the present invention; Fig. Figure 6 is a sectional view that schematically shows a first process of the method for manufacturing the semiconductor device according to the first embodiment of the present invention; Fig. Figure 7 is a sectional view that schematically shows a second process of the method for manufacturing the semiconductor device according to the first embodiment of the present invention; Fig. Figure 8 is a sectional view that schematically shows a third process of the method for manufacturing the semiconductor device according to the first embodiment of the present invention; Fig. Figure 9 is a sectional view schematically showing a fourth process of the method for manufacturing the semiconductor device according to the first embodiment of the present invention; Fig. 10 is a sectional view that schematically shows a configuration of a semiconductor device according to a second embodiment of the present invention; Fig. Figure 11 is a top view schematically showing the configuration of the semiconductor device according to the second embodiment of the present invention; Fig. 12 is a side view which schematically shows a first configuration of a semiconductor device according to a third embodiment of the present invention; Fig. Figure 13 is a top view schematically showing a second configuration of the semiconductor device according to the third embodiment of the present invention; Fig. 14 is a sectional view which schematically shows a third configuration of the semiconductor device according to the third embodiment of the present invention; Fig. 15 is a side view schematically showing a configuration of a semiconductor device according to a fourth embodiment of the present invention; Fig. 16 is a sectional view schematically showing a first configuration of a semiconductor device according to a fifth embodiment of the present invention; Fig. 17 is a sectional view schematically showing a second configuration of the semiconductor device according to the fifth embodiment of the present invention, and Fig. Figure 18 is a block diagram showing a configuration of an energy converter system according to a sixth embodiment of the present invention. DESCRIPTION OF THE EXECUTION FORMS

[0007] With reference to the drawings, embodiments of the present invention are described below. In the following description, identical or corresponding parts are designated by the same reference numerals, and redundant descriptions are not repeated. Design 1

[0008] With reference to the Fig. 1 and Fig. 2 describes a first configuration of a semiconductor device 10 according to a first embodiment. Fig. Figure 1 is a sectional view that schematically shows a first configuration of the semiconductor device 10 according to the first embodiment. Fig. Figure 2 is a top view schematically showing the first embodiment of the semiconductor device 10 according to the first embodiment.

[0009] The semiconductor element 10 comprises a base plate 1, a substrate 2, a semiconductor element 3, a housing 4, and a wiring connection 5. The semiconductor component 10 is a power semiconductor device for electrical energy.

[0010] The base plate 1 is a socket for the semiconductor device 10. The base plate 1 is primarily flat. It is primarily made of copper (Cu), aluminum (Al), or a similar material. The base plate 1 may be primarily made of a material other than those described above, or it may be a composite material consisting of the material described above and another material. The material and shape of the base plate 1 are not restricted, as long as the function of the semiconductor device 10 is not affected. Furthermore, the structure of the base plate 1 may be appropriately defined, as long as the function of the semiconductor device 10 is not affected.

[0011] Substrate 2 is arranged on base plate 1. Substrate 2 comprises an insulating layer and a metal layer. The structure of substrate 2 is, for example, a structure in which metal layers are formed on both surfaces of the insulating layer. This structure connects substrate 2 to base plate 1 and semiconductor element 3. Furthermore, this structure enables excitation between substrate 2 and base plate 1, as well as between substrate 2 and semiconductor element 3. The insulating layer is, for example, a ceramic plate or an insulating film containing an organic component. The material of the ceramic plate is, for example, aluminum oxide (Al₂O₃), silicon nitride (Si₃N₄), or aluminum nitride (AlN). The material of the metal layer is, for example, gold (Au) or copper (Cu).The structure of the metal layer can be a single-layer structure, in which only one type of these metals is used, or a laminated structure, in which several types of metals are used. The material and structure of the substrate 2 are not restricted, as long as the function of the semiconductor device 10 is not impaired. Furthermore, the shape of the substrate 2 can be determined in a suitable manner, as long as the function of the semiconductor device 10 is not impaired.

[0012] The semiconductor element 3 is electrically connected to the substrate 2. The material of the semiconductor element 3 is silicon (Si), silicon carbide (SiC), or the like. In addition to the materials described above, the material of the semiconductor element 3 can also be gallium nitride (GaN). The structure of the semiconductor element 3 is a bipolar insulated-gate transistor (IGBT), a metal-oxide-semiconductor field-effect transistor (MOSFET), or similar. The thickness of the semiconductor element 3 can be selected according to the design. For example, the thickness of the semiconductor element 3 is greater than or equal to 50 µm and less than or equal to 500 µm.

[0013] The semiconductor element 3 comprises an electrode and a metal layer (not shown) on a front and a back side. The electrode and metal layer material is primarily aluminum (Al), copper (Cu), nickel (Ni), or similar. The electrode material is not limited to these. The material, structure, shape, and other features of the semiconductor element 3 are not limited to those described above; rather, the material, structure, shape, and other features of the semiconductor element 3 can be determined in a suitable manner, provided that the function of the semiconductor device 10 is not impaired and the electrode can be formed.

[0014] The semiconductor element 3 can further include an adhesive layer, a barrier layer, and an antioxidant layer. The materials of the adhesive layer, the barrier layer, and the antioxidant layer are gold (Au), titanium (Ti), titanium nitride (TiN), tungsten (W), or the like. The structure of the semiconductor element 3 can be a laminated structure of two or more layers in which the metal layer, the adhesive layer, the barrier layer, and the antioxidant layer are appropriately combined. The materials and configurations of the metal layer, the adhesive layer, the barrier layer, and the antioxidant layer are not limited to these. The thickness of the metal layer, the adhesive layer, the barrier layer, and the antioxidant layer can be specified according to the design. For example, the thickness of the metal layer, the adhesive layer, the barrier layer, and the antioxidant layer can be 5 nm or more and 50 µm or less, respectively.The process for forming the metal layer, the adhesion layer, the barrier layer, and the antioxidant layer is primarily plating, sputtering, or similar methods. However, the process for forming these layers is not limited to these methods and can be appropriately selected as needed.

[0015] The housing 4 is arranged on the base plate 1 such that it covers the substrate 2 and the semiconductor element 3. The housing 4 contacts the base plate 1 on one or more sides. In particular, the housing 4 is shaped to cover a side surface of the substrate 2 and a top surface of the semiconductor element 3. The housing 4 has a side wall. The side wall is frame-shaped so that it surrounds the side surface of the substrate 2. An area where the housing 4 covers the substrate 2 and the semiconductor element 3 is defined as the inside. An area outside the housing 4 is referred to as the outside.

[0016] The housing 4 comprises a first housing unit 41 and a second housing unit 42, which is separate from the first housing unit 41. The housing 4 is divided into the first housing unit 41 and the second housing unit 42. The housing 4 is a separate structure that is divided into two or more. The first housing unit 41 and the second housing unit 42 are arranged such that they enclose a first wiring unit 51 of the wiring terminal 5 described later. The first housing unit 41 and the second housing unit 42 are in contact with the base plate 1.

[0017] The package 4 includes a split area. The first package unit 41 and the second package unit 42 are configured to be split at the split area. The split area has a contact point with the base plate 1. The angle formed by the split area and the base plate 1 is greater than 0 degrees and less than 360 degrees. The position, number, and shape of the package 4 to be split can be appropriately determined according to the design of the semiconductor device 10.

[0018] The second housing unit 42 comprises a cover 421 and a base body 422. The cover 421 is positioned opposite the base plate 1. The main body 422 forms an outer circumference of the housing 4. An opening is provided in an upper area of ​​the housing 4. The cover 421 covers this opening.

[0019] To ensure the insulation of the semiconductor device 10, the material of the housing 4 is insulating. The material of the housing 4 is, for example, a polyphenylene sulfide resin (PPS resin). The structure, material, and shape of the housing 4 can be suitably determined as long as the function of the semiconductor device 10 and the function and effect of the first embodiment are not impaired.

[0020] The wiring terminal 5 is electrically connected to the semiconductor element 3. The wiring terminal 5 comprises a first wiring unit 51 and a second wiring unit 52. The first wiring unit 51 is arranged so that it projects from the inside of the housing 4 to the outside. The first wiring unit 51 is bonded to the semiconductor element 3. The second wiring unit 52 is arranged outside the housing 4. The second wiring unit 52 is bent relative to the first wiring unit 51.

[0021] Before bonding the wiring terminal 5, operations such as bending or cutting are performed on the wiring terminal 5, and the wiring terminal 5 is bent at least once in the middle. In this way, the first wiring unit 51 and the second wiring unit 52 are formed within the wiring terminal 5. For this reason, the second wiring unit 52 is not in a straight line with the first wiring unit 51. The first wiring unit 51 and the semiconductor element 3 are connected to each other via a bonding unit 53. The bonding unit 53 may contain a conductive bonding material, which will be described later.

[0022] The material of the wiring terminal 5 is, for example, aluminum (Al) or copper (Cu). The wiring terminal 5 can contain a so-called dissimilar material, such as other metals and organic components, and its surface can be coated with the dissimilar material. The form of the wiring terminal 5 is, for example, a plate, a foil, or a wire. The structure, material, and form of the wiring terminal 5 can be appropriately determined as long as the function of the semiconductor device 10 and the function and effect of the first embodiment are not impaired. To maintain the function and effect of the first embodiment, the form of the wiring terminal 5 must be the form it has at the time of product use, when the wiring terminal 5 is connected to the substrate 2.

[0023] The bonding unit 53 may also contain an intermediate layer. For example, the thickness of the bonding unit 53, including the intermediate layer, is greater than or equal to 0.1 µm and less than or equal to 2000 µm. The intermediate layer contains, for example, a stress-buffer layer that buffers the stress. This allows the stress exerted on the bonding unit 53 to be relieved during a reliability test. The material of the stress-buffer layer is, for example, inert steel (Invar), molybdenum (Mo), tungsten (W), or an alloy containing these materials. The structure of the stress-buffer layer is either a single-layer structure using a single material type or a laminated structure using a variety of material types. If the stress-buffer structure is laminated, the ratio of the individual laminated layers can be any ratio.The material, shape and structure of the intermediate layer can be determined in a suitable manner, as long as the function and effect of the first embodiment are not impaired.

[0024] A bonding material (not shown) is used when required to connect / bond a component of the semiconductor device 10 to another component. The bonding material may be either insulating or conductive.

[0025] The insulating bonding material is used to join the first housing unit 41 and the second housing unit 42, as well as the base plate 1 and the housing 4. The insulating bonding material has insulating properties. For example, the insulating bonding material is a silicone adhesive. The first housing unit 41 and the second housing unit 42, as well as the base plate 1 and the housing 4, are bonded together without gaps by the insulating bonding material.

[0026] The conductive bonding material is used to connect base plate 1 and substrate 2, substrate 2 and semiconductor element 3, substrate 2 and wiring terminal 5, and semiconductor element 3 and wiring terminal 5. The conductive bonding material is conductive. Examples of conductive bonding materials include solder, a sintered metal body, or a liquid-phase diffusion bonding material. Solders include both lead-based and lead-free solders. Furthermore, various bonding methods exist using solder, such as a method in which the solder is melted in a reducing atmosphere or a method in which the temperature of the solder is increased in an inert gas. The solder bonding method is not limited to these methods, as long as the function and effect of the first embodiment are not impaired.Furthermore, even in the case of bonding using a sintered body or a liquid phase diffusion bonding material, the bonding method can be appropriately determined as long as there are no problems with the use of the product.

[0027] Examples of environments in which bonding is performed using the bonding material include a pressureless environment, an environment at atmospheric pressure, a pressurized environment, and an environment with a reducing atmosphere of hydrogen or formic acid. The environment in which the bonding is performed using the bonding material can be determined appropriately.

[0028] An insulating sealing material can be provided inside the housing 4. The insulating sealing material is a gel-like material or a resin insulating material such as epoxy. This can improve the insulation of the semiconductor device 10.

[0029] With reference to the Fig. 3 and Fig. Section 4 below describes a second configuration of the semiconductor device 10 of the first embodiment. Fig. Figure 3 is a sectional view that schematically shows a second configuration of the semiconductor device 10 according to the first embodiment. Fig. Figure 4 is a top view in which the second configuration of the semiconductor device 10 according to the first embodiment is schematically shown.

[0030] In the second embodiment of the first embodiment, the first wiring unit 51 of the wiring connection 5 is connected to the substrate 2, such that a bonding unit 53 is formed between the first wiring unit 51 and the substrate 2. Which of the two elements, the semiconductor element 3 and the substrate 2, is connected to the first wiring unit 51 can be determined according to the design of the semiconductor component 10.

[0031] With reference to the Fig. In sections 5 to 9, a method for manufacturing the semiconductor device 10 according to the first embodiment is described below. Fig. Figure 5 is a flowchart illustrating the process for manufacturing the semiconductor device 10 according to the first embodiment. The process for manufacturing the semiconductor device 10 of the first embodiment includes a joining process S11 and an assembly process S12. The joining process S11 includes a first process, a second process, and a third process. The assembly process S12 includes a fourth process and a fifth process. Fig. Figure 6 is a sectional view showing the first process. Fig. Figure 7 is a cross-sectional view of the second process. Fig. Figure 8 is a cross-sectional view of the third process. Fig. Figure 9 is a cross-sectional view of the fourth process.

[0032] In connection process S11, the substrate 2 is positioned on the base plate 1. The semiconductor element 3 is electrically connected to the substrate 2. The first wiring unit 51 of the wiring terminal 5 is electrically connected to the semiconductor element 3. The wiring terminal 5 comprises a first wiring unit 51 and a second wiring unit 52. The second wiring unit 52 is bent relative to the first wiring unit 51.

[0033] In the first process, substrate 2 is bonded to base plate 1. In the second process, semiconductor element 3 is bonded to substrate 2. In the third process, the first wiring unit 51 is bonded to either substrate 2 or semiconductor element 3. The wiring connector 5, bonded to substrate 2 in the third process, retains its final shape upon product use. Consequently, no further processing of the wiring connector 5 is performed in connection process S11. The order of the first, second, and third processes is arbitrary.

[0034] A conductive bonding material is used to connect base plate 1 and substrate 2, and to connect substrate 2 and semiconductor element 3. A conductive bonding material, heat, ultrasonic energy, or similar means is also used to connect semiconductor element 3 and first wiring unit 51, and to connect substrate 2 and first wiring unit 51. In the case of bonding using heat, the heat source is a laser, electrical heat, or the like. In the case of bonding using ultrasonic waves, the energy of the ultrasonic waves is determined according to the material used for the wiring connection 5.

[0035] The bonding unit 53 is formed between the semiconductor element 3 and the first wiring unit 51 or between the substrate 2 and the first wiring unit 51. A suitable method for forming the bonding unit 53 can be determined. The bonding unit 53 can be formed using a conductive bonding material. Alternatively, the bonding unit 53 can be formed on the surface of the semiconductor element 3 by a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process.

[0036] Chemical vapor deposition is one example of a coating process. Types of coating include electroless coating and electrolytic coating. The type of coating, the forming process, the technique, and the forming conditions can be appropriately determined as long as the intended bonding unit 53 can be formed. In both electroless and electrolytic deposition, it is necessary to form a base layer and, if applicable, an adhesive layer on the surface of the insulating oxide layer to enable the deposition of the layer. Methods for forming the base layer and the adhesive layer include the chemical vapor deposition process described later and the physical vapor deposition process.The method for forming the base layer and the adhesive layer can be either chemical or physical vapor deposition, as long as the method does not impair the formation of the coating and yields a target coating. Considering the design of the semiconductor device 10 and the thicknesses of the nucleation layer and the base layer required for the formation of the adhesive layer, it is particularly desirable that the base layer and the adhesive layer be formed by means of the sputtering layer formation described later.

[0037] The physical deposition process is, for example, sputtering. Many methods exist for sputtering, such as magnetron sputtering, evaporation, and ion beam sputtering. A direct current (DC) or alternating current (AC) source is used as the power supply for sputtering. Many conditions govern sputtering, such as the presence or absence of heating, the presence or absence of a supported layer formation process, the input power, and the flow rate. The sputtering process, power supply, and conditions can be appropriately determined as long as the intended bond unit 53 can be formed.

[0038] If the bonding unit 53 also contains an intermediate layer, the method for forming the intermediate layer can be appropriately determined according to the purpose of the intermediate layer.

[0039] During process S12, the housing 4 is arranged to cover the substrate 2 and the semiconductor element 3, which are mounted on the base plate 1. The housing 4 comprises a first housing unit 41 and a second housing unit 42, which is separate from the first housing unit 41. In process S12, the first wiring unit 51 extends further outward from the inside of the housing 4. The second wiring unit 52 is located outside the housing 4. The first wiring unit 51 is sandwiched between the first housing unit 41 and the second housing unit 42.

[0040] The second wiring unit 52 is bent relative to the first wiring unit 51. Therefore, the wiring connection 5 is bent outside the housing 4. In the fourth step, the first housing unit 41 and the main body 422 of the second housing unit 42 are connected to the base plate 1 to form the housing 4 with the opening. The second wiring unit 52 can be supported by the first housing unit 41. In the fifth step, the cover 421 is glued to the main body 422 and the opening is closed, thus forming the housing 4.

[0041] In the final process S12, the first housing unit 41 and the second housing unit 42 are bonded as desired, and a procedure is carried out in which no tension is applied to the wiring terminal 5, and the housing 4 is formed. For example, the first housing unit 41 and the second housing unit 42 slide from the side of the substrate 2 and the semiconductor element 3, respectively, so that they clamp the first wiring unit 51 and are connected to each other. In this way, the housing 4 is formed on the base plate 1 so that it covers the substrate 2 and the semiconductor element 3. The housing 4 is thus formed without exerting any tension on the wiring terminal 5, which is bent outside the housing 4 and the bonding unit 53.

[0042] The advantageous effect of the first embodiment is described below.

[0043] The semiconductor element 10 according to the first embodiment includes a housing 4 in which the wiring connector 5 is formed such that it is enclosed on both sides by the first housing unit 41 and the second housing unit 42. Therefore, the wiring connector 5 can be used in a form that is already in place at the time of product use. Accordingly, it is not necessary to bend the wiring connector 5 after the housing 4 has been bonded. Consequently, no mechanical force is exerted on the bonding unit 53 between the wiring connector 5 and the substrate 2 or the semiconductor element 3 to bend the wiring connector 5, thus preventing the wiring connector 5 from detaching.

[0044] In the first embodiment, the housing 4 can also be formed in a frame-like shape in the state in which the previously bent wiring connector 5 is bonded. Accordingly, it is not necessary to machine the wiring connector 5 after the housing 4 has been formed, so that the stresses acting on the wiring connector 5 and the bonding unit 53 can be reduced. Consequently, the long-term reliability of the semiconductor device 10 is improved.

[0045] The housing 4 consists of at least two areas: the first housing unit 41 and the second housing unit 42. Accordingly, the degree of freedom in the design and arrangement of the housing 4 is greater than that of the integrated housing. Thus, the housing 4 can be formed with the optimal shape and structure according to the design and operating conditions of the semiconductor device 10 and the shape and position of the wiring connection 5.

[0046] In the method for manufacturing the semiconductor device 10 according to the first embodiment, the housing 4 can be arranged such that it embeds the wiring terminal 5, which has its shape at the time of product use, in the assembly process S12. Thus, it is not necessary to bend the wiring terminal 5 after the connection process S11 or after executing process S12. Accordingly, during the manufacturing of the semiconductor device 10, the transfer of voltage to the wiring terminal 5 and the bonding unit 53 is prevented. Therefore, a semiconductor device 10 with high long-term reliability can be manufactured. Design 2

[0047] A second embodiment has the same configuration, operation, and effect as the first embodiment described above, unless otherwise specified. Consequently, the same components as in the first embodiment are designated with the same reference numerals, and their description is not repeated.

[0048] With reference to the Fig. 10 and Fig. 11 below schematically illustrates a configuration of the semiconductor device 10 according to the second embodiment. Fig. Figure 10 is a sectional view that schematically shows the structure of the semiconductor device 10 according to the second embodiment. Fig. Figure 11 is a top view schematically showing the structure of the semiconductor device 10 according to the second embodiment.

[0049] The housing 4 includes an engagement unit 43. The semiconductor device 10 further comprises an engagement unit 44. The second wiring unit 52 is attached to the engagement unit 43 by the engagement unit 44. The semiconductor device 10 according to the second embodiment differs from the semiconductor device 10 according to the first embodiment in that the housing 4 also includes the engagement unit 43 and that the semiconductor device 10 also includes the engagement unit 44.

[0050] In particular, the engagement unit 43 is a nut, an area in which a screw hole is formed, or the like. Specifically, the structure of the engagement unit 43 is a structure in which a nut receiving a screw is embedded in the upper surface of the housing 4, a structure in which the cutting of the screw is carried out on the upper surface of the housing 4, or the like. Specifically, the engagement unit 44 is a screw, a threaded rod, or the like. The semiconductor device 10 further comprises external wiring 6. The external wiring 6 is electrically connected to an external device of the semiconductor device 10. The external wiring 6 is electrically connected to the second wiring unit 52 on the engagement unit 43. The engagement unit 43 and the engagement unit 44 function as a so-called terminal block that connects the second wiring unit 52 and the external wiring 6.

[0051] When the second wiring unit 52 and the external wiring 6 are connected, the engagement unit 43 and the engagement unit 44 are engaged, thus improving the fastening relationship between the second wiring unit 52 and the external wiring 6. This firmly connects the second wiring unit 52 and the external wiring 6. An engagement unit 43 can be provided on the top of the housing 4. In this housing, the engagement unit 43 supports the second wiring unit 52. The engagement unit 43 can also cover an area of ​​the semiconductor element 3.

[0052] The advantageous effect of the first embodiment is described below.

[0053] In the semiconductor device 10 according to the second embodiment, the engagement unit 43 and the engagement unit 44 are engaged, thus achieving a fastening effect in the engagement unit 43. Accordingly, the second wiring unit 52 and the external wiring 6 can be firmly attached to the housing 4 by the engagement unit 44 within the engagement unit 43. This improves the long-term reliability of the semiconductor device 10.

[0054] The housing 4 can support the second wiring unit 52 by positioning the engagement unit 43 on its top surface. The stress exerted on the second wiring unit 52 from the top of the housing 4, when the second wiring unit 52 and the external wiring 6 are attached, can be relieved by the support provided by the engagement unit 43. This prevents deformation of the second wiring unit 52 and thus improves the long-term reliability of the semiconductor device 10. embodiment 3

[0055] A third embodiment has the same configuration, operation, and effect as the first embodiment described above, unless otherwise specified. Consequently, the same components as in the first embodiment are designated with the same reference numerals, and their description is not repeated.

[0056] With reference to Fig. 12 In the following, a first configuration of the semiconductor device 10 according to the third embodiment is shown schematically. Fig. Figure 12 is a side view that schematically shows the first configuration of the semiconductor device 10 according to the third embodiment.

[0057] The first housing unit 41 according to the third embodiment includes a first recess 41c. The second housing unit 42 according to the third embodiment includes a first projection 42c. The first recess 41c is designed to be attached to the first projection 42c. The semiconductor device 10 according to the third embodiment differs from the semiconductor device 10 according to the first embodiment in that the first housing unit 41 includes a first recess 41c and the second housing unit 42 includes a first projection 42c.

[0058] In particular, the first recess 41c and the first projection 42c have an uneven or stepped shape. The unevenness or step of the first recess 41c and the first projection 42c are joined by bonding material so that they are combined in the divided area. The shapes, the number of steps, the arrangement, and the depth of the first recess 41c and the first projection 42c can be suitably determined, provided that the shapes achieve the function and effect of the third embodiment.

[0059] The creepage distance and adhesive area in the housing where the first housing unit 41 and the second housing unit 42 are connected by the first recess 41c and the first projection 42c are larger than the creepage distance and adhesive area in the housing where the first housing unit 41 and the second housing unit 42 are connected by a vertical plane. As the creepage distance and adhesive area increase, the application distance and application area where the insulating bonding material is applied to the housing 4 also increase.

[0060] Fig. Figure 13 schematically shows a second configuration of the semiconductor device 10 according to the third embodiment. Fig. Figure 13 is a top view showing the second configuration of the semiconductor device 10 according to the third embodiment. In the second configuration of the embodiment, the first recess 41c and the first projection 42c are formed in a direction from the inside to the outside of the housing 4.

[0061] Fig. Figure 14 schematically shows a third embodiment of the semiconductor device 10 according to the third embodiment. Fig. Figure 14 is a top view showing the third configuration of the semiconductor device 10 according to the third embodiment. In the third configuration of the third embodiment, the first housing unit 41 and the second housing unit 42 include a second recess 4a. The first housing unit 41 and the second housing unit 42 include a second projection 4b. The second recess 4a is designed to be attached to the second projection 4b. The second recess 4a and the second projection 4b extend in a direction from the base plate 1 to the cover 421. In particular, the first housing unit 41 includes a first main housing unit 41A and a first sub-housing unit 41B, and the second housing unit 42 includes a second main housing unit 42A and a second sub-housing unit 42B. The first main housing unit 41A and the second main housing unit 42A include a second recess 4a.The lower first housing unit 41B and the lower second housing unit 42B contain a second projection 4b.

[0062] The advantageous effect of the embodiment is described below.

[0063] In the semiconductor device 10 according to the third embodiment, the connection area in which the first housing unit 41 and the second housing unit 42 are connected is large, thus increasing the connection strength and strengthening the bond between the first housing unit 41 and the second housing unit 42. Furthermore, the first recess 41c and the first projection 42c, which provide irregularities in the thickness direction of the housing 4, enlarge the application area in which the insulating bonding material is applied to the housing 4, thereby increasing the insulation of the housing 4.

[0064] In the third embodiment of the semiconductor device 10, the first housing unit 41 and the second housing unit 42 are connected to each other by the second recess 4a and the second projection 4b, in addition to the first recess 41c and the first projection 42c. This further increases the bond strength and insulation of the housing 4. Design 4

[0065] A fourth embodiment has the same configuration, operation, and effect as the first embodiment described above, unless otherwise specified. Consequently, the same components as in the first embodiment are designated with the same reference numerals, and their description is not repeated.

[0066] With reference to Fig. 15 below schematically illustrates a configuration of the semiconductor device 10 according to the fourth embodiment. Fig. Figure 15 is a side view that schematically shows the structure of the semiconductor device 10 according to the fourth embodiment.

[0067] The first housing unit 41 according to the fourth embodiment includes a first inclined unit 41i. The second housing unit 42 according to the fourth embodiment includes a second inclined unit 42i. The first inclined unit 41i is inclined along the second inclined unit 42i. The semiconductor device 10 according to the fourth embodiment differs from the semiconductor device 10 according to the first embodiment in that the first housing unit 41 includes a first inclined unit 41i and that the second housing unit 42 includes a second inclined unit 42i.

[0068] The first inclined unit 41i and the second inclined unit 42i are inclined with respect to the direction in which the base plate 1 and the housing 4 overlap. The first inclined unit 41i and the second inclined unit 42i are configured such that their inclined surfaces are in contact. With this configuration, the first inclined unit 41i and the second inclined unit 42i are fitted into the split area.

[0069] The positions of the first inclined unit 41i and the second inclined unit 42i, the length of the inclination, the angle of inclination, the direction of inclination, and the like can be appropriately determined according to the performance of the intended semiconductor device 10. To achieve the effect of the fourth embodiment, it is desirable that the first inclined unit 41i and the second inclined unit 42i face the top of the base plate 1 and are arranged so that they have no dead angle or blind spot.

[0070] In the housing where there is no blind spot from the top of the base plate 1, all areas of either the first inclined unit 41i or the second inclined unit 42i facing the top are projected onto the base plate 1 when the divided area is projected onto the base plate 1 from the vertical direction with respect to the base plate 1. Furthermore, even if the inclined surface is a curved surface, all areas of the curved surface can be projected when the divided area is projected onto the base plate 1 from the vertical direction. Therefore, the first inclined unit 41i and the second inclined unit 42i are not limited to an inclined surface consisting solely of a flat surface in order to achieve the function and effect of the fourth embodiment. For example, the first inclined unit 41i and the second inclined unit 42i can have curved surfaces.

[0071] The advantageous effect of this embodiment is described below. When bonding the first housing unit 41 and the second housing unit 42, the adhesive material is applied from the top of the base plate 1 to the split area. As in the third embodiment, if there is an unevenness or step between the first housing unit 41 and the second housing unit 42, a blind spot may be created in the split area from the top of the base plate 1. Furthermore, if the unevenness or step is present between the first housing unit 41 and the second housing unit 42, as in the third embodiment, the unevenness or step may create insufficient space for application.For these reasons, the bonding material cannot be applied evenly between the first housing unit 41 and the second housing unit 42, and there is a possibility that the adhesive strength and insulation will be reduced.

[0072] In the fourth embodiment, the first inclined unit 41i and the second inclined unit 42i are inclined relative to the top surface of the base plate 1. Therefore, neither the first inclined unit 41i nor the second inclined unit 42i has a dead angle with respect to the top surface of the housing 4. Consequently, the bonding material can be applied uniformly between the first housing unit 41 and the second housing unit 42. This increases the bond strength and the insulation of the housing 4, thus improving the long-term reliability of the semiconductor device 10.

[0073] In the fourth embodiment, the first housing unit 41 can additionally have a first recess 41c and the second housing unit 42 can additionally have a first projection 42c. In this housing, the position, orientation, number, and other features where the inclination is provided can be appropriately adjusted according to the intended performance. In particular, the first recess 41c and the first projection 42c are designed such that no dead angle is created from the top of the housing 4. This increases the long-term reliability of the semiconductor device 10 and improves the adhesion and insulation of the housing 4. Design 5

[0074] The fifth embodiment has the same configuration, operation, and effect as the first embodiment described above, unless otherwise specified. Consequently, the same components as in the first embodiment are designated with the same reference numerals, and their description is not repeated.

[0075] With reference to the Fig. 16 and Fig. 17 below schematically illustrates a configuration of the semiconductor device 10 according to the fifth embodiment. Fig. Figure 16 is a sectional view that schematically shows a first embodiment of the semiconductor device 10 according to the fifth embodiment. Fig. Figure 17 is a sectional view that schematically shows a second configuration of the semiconductor device 10 according to the fifth embodiment.

[0076] The first housing unit 41 according to the embodiment comprises a first cover 411 and a first main body 412. The first cover 411 has a first upper recess. The first main body 412 comprises a first upper projection and a first lower projection. The base plate 1 includes a first lower recess. The first upper recess and the first upper projection are mate-fit. The first lower recess and the first lower projection are mate-fit.

[0077] The cover 421 of the second housing unit 42 includes a second upper recess. The main body 422 of the second housing unit 42 includes a second upper projection and a second lower projection. The base plate 1 includes a second lower recess. The second upper recess and the second upper projection are fitted together. The second lower recess and the second lower projection are fitted together.

[0078] The advantageous effect of the first embodiment is described below.

[0079] In the semiconductor device 10 according to the fifth embodiment, the distance and the area in which the housing 4 and the base plate 1 are bonded are large, thus increasing the adhesive force to bond the housing 4 and the base plate 1 more firmly. Furthermore, the creepage distance and the bonding area are increased by enlarging the distance and the area in which the housing 4 and the base plate 1 are bonded, thereby increasing the insulation. Design 6

[0080] In a sixth embodiment, the semiconductor device according to one of the first to fifth embodiments described above is used in a current transformer device. Although the present invention is not limited to a specific current transformer device, the housing in which the present invention is applied to a three-phase inverter is described below as the sixth embodiment.

[0081] Fig. Figure 18 is a block diagram showing the configuration of a current transformer system in which the current transformer device is used according to the sixth embodiment.

[0082] The current transformer system in Fig. Figure 18 includes a power supply 100, a current transformer 200, and a load 300. The power supply 100 is a DC power supply and provides the current transformer 200 with direct current. The power supply 100 can be represented by various components. For example, the power supply 100 can be constructed from a DC system, a solar cell, and a battery, or from a rectifier circuit connected to an AC system or an AC / DC converter. The power supply 100 can be designed with a DC-to-voltage converter that converts the DC power supplied by the DC system into a predetermined power output.

[0083] The current transformer 200 is a three-phase inverter that is connected between the power supply 100 and the load 300. It converts the direct current power supplied by the power supply 100 into alternating current power and delivers the alternating current power to the load 300. As shown in Fig. As shown in Figure 18, the current transformer device 200 includes a main transformer circuit 201, which converts the direct current into alternating current in order to output the alternating current, and a control circuit 203, which outputs a control signal to the main transformer circuit 201 for controlling the main transformer circuit 201.

[0084] The Last 300 is a three-phase motor driven by the alternating current supplied by the current transformer 200. The Last 300 is not limited to a specific application but is a motor that can be used in various electrical devices. For example, the Last 300 is used in hybrid cars, electric cars, rail vehicles, elevators, or as a motor for an air conditioner.

[0085] The current transformer device 200 is described in detail below. The main converter circuit 201 contains a switching element and a reverse-flow diode (not shown), converts the DC voltage supplied by the power supply 100 into AC voltage by switching the switching element, and supplies the AC voltage to the load 300. Although there are various specific circuit configurations of the main converter circuit 201, the main converter circuit 201 according to the sixth embodiment is a two-stage, three-phase full-bridge circuit that can be configured by six switching elements and six reverse-flow diodes connected antiparallel to the respective switching elements. Each switching element and each reverse-flow diode of the main converter circuit 201 is formed by the semiconductor module 202, which corresponds to one of the first to fifth embodiments described above.Six switching elements are connected in series in pairs to form upper and lower branches, and each of the upper and lower branches forms each phase (U-phase, V-phase, W-phase) of the full bridge circuit. One output terminal of each of the upper and lower branches, i.e., three output terminals of the main converter circuit 201, are connected to the load 300.

[0086] Furthermore, the main converter circuit 201 includes a control circuit (not shown) that controls each switching element. The control circuit may be integrated into the semiconductor module 202 or may be a separate control circuit from the semiconductor module 202. The control circuit generates a control signal that drives the switching element of the main converter circuit 201 and delivers the control signal to the control electrode of the switching element of the main converter circuit 201. In particular, the control signal to turn on the switching element and the control signal to turn off the switching element are output to the control electrode of each switching element in accordance with the control signal from the control circuit 203 (described later).The control signal is a voltage signal (on signal) that is greater than or equal to a threshold voltage of the switching element when the switching element is held in an on state, and the control signal is a voltage signal (off signal) that is less than or equal to the threshold voltage of the switching element when the switching element is held in an off state.

[0087] The control circuit 203 controls the switching elements of the main converter circuit 201 so that the desired power is delivered to the load 300. Specifically, the time (on-time) for which each switching element of the main converter circuit 201 is to be switched on is calculated based on the power to be delivered to the load 300. For example, the main converter circuit 201 can be controlled by a PWM controller, which modulates the on-time of the switching element according to the output voltage. A control command (control signal) is output to the control circuit contained in the main converter circuit 201, so that the "on" signal is output to the switching element to be switched on at any given time, and the "off" signal is output to the switching element to be switched off at any given time. The control circuit outputs the "on" signal or the "off" signal as a control signal to the control electrode of each switching element according to the control signal.

[0088] In the current transformer device according to the sixth embodiment, the semiconductor module according to one of the first to fifth embodiments is used as a switching element and backflow diode of the main transformer circuit 201, so that the reliability of the current transformer device can be realized.

[0089] Although the example in which the present invention is applied to a two-stage three-phase inverter is described in the sixth embodiment, the present invention is not limited to the sixth embodiment but can be applied to various current transformer devices. In the sixth embodiment, the two-stage current transformer device is used. However, a three-stage or multi-stage current transformer device can also be used, or the present invention can be applied to a single-phase inverter when the current is supplied to a single-phase load. Furthermore, the present invention can also be applied to a DC / DC converter or an AC / DC converter when the current is supplied to a DC load or the like.

[0090] Furthermore, the current transformer device to which the present invention is applied is not limited to the case where the load described above is an electric motor, but can also be used, for example, as a power supply device for an electrical discharge machine, a laser beam machine, an induction heating stove or a contactless power supply system, and can also be used as a power conditioner for a solar power generation system and a power storage system.

[0091] It should be noted that the described embodiments are in every respect exemplary and not limiting. The scope of the present invention is not limited by the above description, and it is intended that all modifications and their equivalents are included in the present invention. Reference symbol list 1 Base plate 2 Substrat 3 Semiconductor element 4 cases 5 Wiring connection 10 Semiconductor components 41 first housing unit 42 second housing unit 51 first wiring unit 52 second wiring unit 100 Power supply 200 current transformer device 201 Main converter circuit 202 Semiconductor module 203 Control circuit 300 Last

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