SiC semiconductor component and method for manufacturing the same

Abstract

Method for manufacturing a SiC semiconductor component, comprising: a step of providing a SiC wafer that has a main surface and is composed of a SiC monocrystal; a step of the formation process, namely in the main area, a multitude of alignment patterns that define a planned cutting line, that delineates a multitude of chip regions, that include a first chip region in which a functional component is formed, and that include a second chip region in which a monitor pattern is formed; a step of forming a plurality of main surface electrodes on the main surface, each covering the chip regions, such that the planned cutting line is exposed, and each forming a section of the functional component or a section of the monitor pattern; a step of forming on the main surface a plurality of insulating layers, each partially covering the main surface electrodes and defining a dicing road that exposes the planned cutting line in a region between those chip regions that are adjacent to each other; a step of emitting laser light onto the planned cutting line exposed opposite the main surface electrodes and the insulating layers, through the dicing road (91), and forming a modified region that is modified to have a property different from that of the SiC monocrystal in the SiC wafer; and a step of separating the SiC wafer, using the modified region as a starting point.

Description

Technical field

[0001] The present invention relates to a method for manufacturing a SiC semiconductor component. State of the art

[0002] A method for manufacturing a SiC semiconductor device has become known in recent years, employing a laser irradiation cleaving method. In this method, laser light is directed onto a SiC wafer, and the wafer is subsequently cleaved along the section exposed to the laser light. This method allows the SiC wafer to be easily separated or cut, thus reducing manufacturing time.

[0003] In a process for manufacturing a SiC semiconductor device, a monitor pattern, also known as a PCM (process control monitor), is formed in an arbitrary region of a SiC wafer. The monitor pattern allows the suitability of each step performed on the SiC wafer to be indirectly evaluated based on its physical and electrical characteristics. The physical characteristics include, for example, the dimensions of a structure formed within the monitor pattern. The electrical characteristics include, for example, the resistance and capacitance values ​​of a semiconductor region formed within the monitor pattern.

[0004] Patent literature 1 discloses a method for manufacturing a SiC semiconductor component using a SiC wafer that includes auxiliary patterns (monitor patterns) arranged concentrically at positions that overlap laser irradiation regions (planned cutting lines). List of citations from patent literature

[0005] Patent literature 1: Japanese publication JP 2016 - 134 427 A

[0006] Other semiconductor components are known from documents US 2009 / 0121337 A1, JP 2012-146876 A, US 2014 / 131876 A, JP H09-153603 A, JP S52-90275 A, JP 2011-222607 A and US 6 555 925 B1. Overview of the invention Technical problem

[0007] In the SiC wafer according to patent literature 1, laser light is blocked by the monitor patterns, and consequently, unmodified sections, in which modified regions are not present, are formed in regions that are hidden or concealed by the monitor patterns. During a cleaving step of the SiC wafer, a force that maintains an atomic arrangement (a crystal structure of SiC) acts on the unmodified sections directly beneath the monitor patterns. As a result, meanderings are formed in cleaved sections of the SiC wafer, with the monitor patterns as their starting points.

[0008] A preferred embodiment of the present invention provides a method for fabricating a SiC semiconductor device in which shape defects due to a monitor pattern can be suppressed. A preferred embodiment of the present invention provides a SiC semiconductor device with a structure in which shape defects due to an auxiliary pattern are suppressed. Solution to the problem

[0009] The above problem is solved by a method for manufacturing a SiC semiconductor component according to claim 1.

[0010] In general, such a process includes a preparation step of a SiC wafer, which has a main surface and is built up from a SiC monocrystal; a setting step on the main surface, a planned cutting line that demarcates a plurality of chip regions, including a first chip region in which a functional device is formed and a second chip region in which a monitor pattern is formed for process control of the first chip region; a forming step on the main surface, a plurality of main surface electrodes, each covering the chip regions such that the planned cutting line is exposed, and each forming a section of the functional device or a section of the monitor pattern; and an irradiation step.Radiating laser light onto the planned cutting line exposed to the main surface electrodes, and forming a modified region that is modified to have a property different from the SiC monocrystal, and a step of splitting or separating the SiC wafer, with the modified region as a starting point.

[0011] According to this method for fabricating the SiC semiconductor device, shape defects due to the monitor pattern can be suppressed. Furthermore, according to this method for fabricating the SiC semiconductor device, a SiC semiconductor device with a structure in which shape defects due to the monitor pattern are suppressed can be fabricated and provided.

[0012] Furthermore, an example of a SiC semiconductor device is disclosed, comprising a SiC chip having a first principal surface and a second principal surface, each formed in a top view as a four-sided shape, and having four side surfaces, each connecting the first principal surface and the second principal surface and each composed of cleavage surfaces, with a modified region formed in the respective side surfaces and modified to have a property different from that of a SiC monocrystal, with an alignment pattern as an auxiliary pattern formed in a circumferential boundary section of the first principal surface with inward spacing from the respective side surfaces, in a top view, with a principal surface electrode formed on the first principal surface with inward spacing from the respective side surfaces and exposing the alignment pattern.namely in plan view, and with an insulating layer formed on the first main surface at inward distances from the respective side surfaces, which partially covers the main surface electrode and which, together with the side surfaces, defines a dicing road that exposes the alignment pattern, namely in plan view, and wherein no auxiliary pattern other than the alignment pattern is formed in the circumferential edge section of the first main surface which, in plan view, is positioned within the dicing road.

[0013] According to this structure, the SiC semiconductor component can be provided with a structure in which shape defects due to the auxiliary pattern are suppressed.

[0014] The above-mentioned as well as further tasks, features and effects of the present invention will become clearer from the following description of the preferred embodiments with reference to the accompanying drawings. Brief description of the drawings Fig. Figure 1 is a diagram of a unit cell of a 4H-SiC monocrystal. Fig. Figure 2 is a top view of a silicon plane of the unit cell, which is in Fig. 1 is shown. Fig. Figure 3 is a perspective view of a SiC semiconductor component. Fig. Figure 4 is a perspective view from a different direction of the SiC semiconductor component, which is in Fig. 3 is shown. Fig. Figure 5 is a top view of the SiC semiconductor component, which is located in Fig. 3 is shown. Fig. 6 is a sectional view along a line VI-VI, which is in Fig. 3 is shown, or along a line VV, which is in Fig. 5 is shown. Fig. 7 is an enlarged view of Region VII, which is located in Fig. 3 or in Fig. 5 is shown. Fig. 8 is a sectional view along a line VIII-VIII, which is in Fig. 7 is shown. Fig. Figure 9 is a diagram of a SiC wafer used to fabricate the SiC semiconductor device that is used in Fig. 3 is shown. Fig. Figure 10A is a sectional view of a region of a section of the SiC wafer and shows an example of a method for fabricating the SiC semiconductor device, which is described in Fig. 3 is shown. Fig. 10B is a sectional view of a step that corresponds to that of the Fig. 10A follows. Fig. 10C is a sectional view of a step that corresponds to that of the Fig. 10B follows. Fig. 10D is a sectional view of a step that corresponds to that of the Fig. 10C follows. Fig. 10E is a sectional view of a step that corresponds to that of the Fig. 10D follows. Fig. 10F is a sectional view of a step that corresponds to that of the Fig. 10E follows. Fig. 10G is a cross-sectional view of a step similar to that of the Fig. 10F follows. Fig. 10H is a sectional view of a step that corresponds to that of the Fig. 10G follows. Fig. 10I is a sectional view of a step that corresponds to that of the Fig. 10H follows. Fig. 10J is a sectional view of a step that corresponds to that of the Fig. 10I follows. Fig. 10K is a cross-sectional view of a step that corresponds to that of the Fig. 10J follows. Fig. 10L is a sectional view of a step similar to that of the Fig. 10K to follow. Fig. 10M is a sectional view of a step that corresponds to that of the Fig. 10L follows. Fig. 10N is a sectional view of a step that corresponds to that of the Fig. 10M follows. Fig. 10O is a sectional view of a step that corresponds to that of the Fig. 10N follows. Fig. 10P is a sectional view of a step that corresponds to that of the Fig. 100 follows. Fig. Figure 11A is a top view of a region of a section of the SiC wafer and shows an example of the process for fabricating the SiC semiconductor device described in Fig. 3 is shown. Fig. 11B is a top view of a step corresponding to that of the Fig. 11A follows. Fig. 11C is a top view of a step corresponding to that of the Fig. 11B follows. Fig. 11D is a top view of a step that corresponds to that of the Fig. 11C follows. Fig. 11E is a top view of a step corresponding to that of the Fig. 11D follows. Fig. 11F is a top view of a step corresponding to that of the Fig. 11E follows. Fig. 11G is a top view of a step similar to that of the Fig. 11F follows. Fig. 11H is a top view of a step that corresponds to that of the Fig. 11G follows. Fig. 11I is a top view of a step that corresponds to that of the Fig. 11H follows. Fig. 11J is a top view of a step similar to that of the Fig. 11I follows. Fig. 11K is a top view of a step that corresponds to that of the Fig. 11J follows. Fig. 11L is a top view of a step similar to that of the Fig. 11K follows. Fig. 11M is a top view of a step similar to that of the Fig. 11L follows. Fig. 11N is a top view of a step corresponding to that of the Fig. 11M follows. Fig. 11O is a top view of a step that corresponds to that of the Fig. 11N follows. Fig. 11P is a top view of a step that corresponds to that of the Fig. 11O follows. Fig. Figure 12 is an enlarged top view of a slit section or split section of a SiC wafer according to a reference example. Fig. Figure 13 is a top view of another SiC semiconductor component. Fig. 14 is an enlarged top view of an internal structure of Region XIV, which is located in Fig. 13 is shown. [ Fig. 15] Fig. 15 is a sectional view along a line XV-XV, which is in Fig. 14 is shown. Description of embodiments

[0015] Fig. Figure 1 is a diagram of a unit cell of a 4H-SiC monocrystal (hereinafter referred to simply as the "unit cell"). Fig. Figure 2 is a top view of a silicon plane of the unit cell, which is in Fig. 1 is shown.

[0016] In preferred embodiments of the present invention, examples are described in which a 4H-SiC monocrystal is used as an example of a SiC monocrystal built from a hexagonal crystal. The SiC monocrystal built from the hexagonal crystal has a plurality of polytypes, including a 2H (hexagonal)-SiC monocrystal, the 4H-SiC monocrystal, and a 6H-SiC monocrystal, according to the cycle of the atomic arrangement. The preferred embodiments of the present invention are not intended to exclude polytypes that differ from the 4H-SiC monocrystal.

[0017] With reference to Fig. 1 and Fig. 2. The unit cell comprises tetrahedral structures in which four carbon atoms are bonded to a single silicon atom in a tetrahedral arrangement. The unit cell has an atomic arrangement in which the tetrahedral structures are stacked on top of each other in a four-period arrangement. The unit cell has a hexagonal prism structure with a hexagonal silicon plane, a hexagonal carbon plane, and six side planes connecting the silicon and carbon planes.

[0018] The silicon plane is a terminal plane enclosed by silicon atoms. In the silicon plane, a single silicon atom is positioned at each of the six corners of a hexagon, and a single silicon atom is positioned at the center of the hexagon. The carbon plane is a terminal plane enclosed by carbon atoms. In the carbon plane, a single carbon atom is positioned at each of the six corners of a hexagon, and a single carbon atom is positioned at the center of the hexagon.

[0019] The crystal planes of the unit cell are defined by four coordinate axes (a1, a2, a3, and c), including an a1-axis, an a2-axis, an a3-axis, and a c-axis. Of the four coordinate axes, a3 takes on a value of -(a1+a2). The structure of the 4H-SiC monocrystal is described below based on the silicon plane.

[0020] In a top-down view of the silicon plane from the c-axis, the a1-axis, the a2-axis, and the a3-axis are each aligned along directions of the arrangement of the nearest neighboring Si atoms (hereinafter referred to simply as the "nearest neighbor directions"), based on the Si atoms positioned at the center. The a1-axis, the a2-axis, and the a3-axis are each offset by 120° in accordance with the arrangement of the Si atoms.

[0021] The c-axis is oriented perpendicular to the silicon plane based on the Si atoms located at the center. The silicon plane is a (0001) plane. The carbon plane is a (000-1) plane. The side planes of the hexagonal prism contain six crystal planes oriented along the nearest neighbor directions, as seen from a top view of the silicon plane from the c-axis. More precisely, the side planes of the hexagonal prism contain the six crystal planes, each containing a multitude of nearest neighbor Si atoms.

[0022] In the top view when viewing the silicon plane from the c-axis, the side planes of the unit cell include a (1-100) plane, a (0-110) plane, a (-1010) plane, a (-1100) plane, a (01-10) plane and a (10-10) plane, in a clockwise direction starting from a tip of the a1-axis.

[0023] Diagonal planes of the unit cell that do not pass through the center comprise six crystal planes oriented along intersection directions that cross the nearest neighbor directions, as seen from the c-axis when viewing the silicon plane from above. Viewed from the perspective of the Si atoms positioned at the center, the directions that cross the nearest neighbor directions are orthogonal to those directions. More precisely, the diagonal planes of the hexagonal prism that do not pass through the center comprise the six crystal planes, each containing a multitude of Si atoms that are not nearest neighbors.

[0024] In the top view when viewing the silicon plane from the c-axis, the diagonal planes of the unit cell that do not pass through the center include a (11-20) plane, a (1-210) plane, a (-2110) plane, a (-1-120) plane, a (-12-10) plane and a (2-1-10) plane.

[0025] The crystal directions of the unit cell are defined by directions perpendicular to the crystal planes. A normal direction to the (1-100) plane is a [1-100] direction. A normal direction to the (0-110) plane is a [0-110] direction. A normal direction to the (-1010) plane is a [-1010] direction. A normal direction to the (-1100) plane is a [-1100] direction. A normal direction to the (01-10) plane is a [01-10] direction. A normal direction to the (10-10) plane is a [10-10] direction.

[0026] A normal direction to the (11-20) plane is a [11-20] direction. A normal direction to the (1-210) plane is a [1-210] direction. A normal direction to the (-2110) plane is a [-2110] direction. A normal direction to the (-1-120) plane is a [-1-120] direction. A normal direction to the (-12-10) plane is a [-12-10] direction. A normal direction to the (2-1-10) plane is a [2-1-10] direction.

[0027] The hexagonal crystal is sixfold symmetrical and has equivalent crystal planes and crystal directions every 60°. For example, the (1-100) plane, the (0-110) plane, the (-1010) plane, the (-1100) plane, the (01-10) plane, and the (10-10) plane are equivalent crystal planes. Furthermore, the (11-20) plane, the (1-210) plane, the (-2110) plane, the (-1-120) plane, the (-12-10) plane, and the (2-1-10) plane are equivalent crystal planes.

[0028] Furthermore, the [1-100] direction, the [0-110] direction, the [-1010] direction, the [-1100] direction, the [01-10] direction, and the [10-10] direction are equivalent crystal directions. The [11-20] direction, the [1-210] direction, the [-2110] direction, the [-1-120] direction, the [-12-10] direction, and the [2-1-10] direction are also equivalent crystal directions.

[0029] The

[0001] direction and the [000-1] direction are referred to as the c-axis. The (0001) plane and the (000-1) plane are referred to as the c-planes. The [11-20] direction and the [-1-120] direction are referred to as an a-axis. The (11-20) plane and the (-1-120) plane are referred to as the a-planes. The [1-100] direction and the [-1100] direction are referred to as an m-axis. The (1-100) plane and the (-1100) plane are referred to as the m-planes.

[0030] Fig. Figure 3 is a perspective view of a SiC semiconductor component 1. Fig. Figure 4 is a perspective view from a different direction of the SiC semiconductor component 1, which is located in Fig. 3 is shown. Fig. Figure 5 is a top view of the SiC semiconductor component 1, which is located in Fig. 3 is shown. Fig. 6 is a sectional view along a line VI-VI, which is in Fig. 3 is shown, or along a line VV which is in Fig. 5 is shown. Fig. 7 is an enlarged view of Region VII, which is located in Fig. 3 or Fig. 5 is shown. Fig. 8 is a sectional view along a line VIII-VIII, which is in Fig. 7 is shown.

[0031] With reference to Fig. 3 to Fig. Figure 8 of the SiC semiconductor component 1 includes a SiC chip 2, which is constructed from a 4H-SiC monocrystal. The SiC chip 2 is formed in a rectangular parallelepiped shape. The SiC chip 2 can have a thickness TC of not less than 40 µm and not more than 300 µm. The thickness TC can be not less than 40 µm and not greater than 100 µm, not less than 100 µm and not greater than 150 µm, not less than 150 µm and not greater than 200 µm, not less than 200 µm and not greater than 250 µm, or not less than 250 µm and not greater than 300 µm. The thickness TC is preferably not less than 60 µm and not greater than 150 µm.

[0032] The SiC chip 2 has a first principal surface 3 on one side, a second principal surface 4 on the other side, and four side surfaces 5A, 5B, 5C, and 5D connecting the first principal surface 3 and the second principal surface 4. The side surfaces 5A to 5D include a first side surface 5A, a second side surface 5B, a third side surface 5C, and a fourth side surface 5D. The first principal surface 3 and the second principal surface 4 are each formed as four-sided shapes in a top view when viewed in a normal direction Z to the surfaces (hereinafter simply referred to as the "top view"). The first principal surface 3 and the second principal surface 4 can also be formed as rectangular shapes in a top view.

[0033] The first principal surface 3 and the second principal surface 4 face the c-planes of the SiC monocrystal and are opposite the c-planes of the SiC monocrystal, respectively. The first principal surface 3 faces the silicon plane of the SiC monocrystal. The second principal surface 4 faces the carbon plane of the SiC monocrystal. The first principal surface 3 and the second principal surface 4 may have an off angle, inclined at a predetermined angle in an off direction with respect to the c-planes. The off direction is preferably the a-axis direction of the SiC monocrystal. If an off angle is present, the c-axis of the SiC monocrystal is inclined by exactly the off angle with respect to the normal direction Z. The off angle may exceed 0° and may not be greater than 10°.

[0034] The off-angle cannot be less than 0° and not greater than 6°. The off-angle cannot be less than 0° and not greater than 2°, less than 2° and not greater than 4°, or less than 4° and not greater than 6°. The off-angle preferably exceeds 0° and is not greater than 4.5°. The off-angle cannot be less than 3° and not greater than 4.5°. In this case, the off-angle is preferably not less than 3° and not greater than 3.5°, or less than 3.5° and not greater than 4°. The off-angle cannot be less than 1.5° and not greater than 3°. In this case, the off-angle is preferably not less than 1.5° and not greater than 2°, or less than 2° and not greater than 2.5°.

[0035] The second main surface 4 can be composed of a rough surface having grinding marks and / or annealing marks (in particular, laser irradiation marks). The annealing marks can contain amorphized SiC and / or SiC (more precisely, Si) silicidalized (alloyed) with a metal. The second main surface 4 is preferably composed of an ohmic surface having at least annealing marks.

[0036] Faces 5A to 5D each consist of a cleavage surface. The first face, 5A, and the second face, 5B, extend in a first direction X and are opposite each other in a second direction Y, which intersects the first direction X. The third face, 5C, and the fourth face, 5D, extend in the second direction Y and are opposite each other in the first direction X. More precisely, the second direction Y is orthogonal to the first direction X. The first direction X is the m-axis direction. The second direction Y is the a-axis direction. Therefore, the first face, 5A, and the second face, 5B, are formed by the a-planes of the SiC monocrystal. Furthermore, the third face, 5C, and the fourth face, 5D, are formed by the m-planes of the SiC monocrystal.

[0037] The first face 5A and the second face 5B can form inclined surfaces inclined relative to the c-axis of the SiC monocrystal based on the normal direction Z. The first face 5A and the second face 5B can also be inclined at an angle known as the "off angle" relative to the normal direction Z when the normal direction Z is set to 0°. The angle known as the "off angle" can be equal to the "off angle" or it can be an angle greater than 0° but smaller than the "off angle". Furthermore, the third face 5C and the fourth face 5D extend as planes in the second direction Y (the a-axis direction) and the normal direction Z. More precisely, the third face 5C and the fourth face 5D are essentially perpendicular to the first principal face 3 and the second principal face 4, respectively.

[0038] The length of each of the face surfaces 5A to 5D cannot be less than 0.1 mm and cannot be greater than 15 mm. The length of each of the face surfaces 5A to 5D cannot be less than 0.1 mm and cannot be greater than 1 mm, less than 1 mm and cannot be greater than 5 mm, less than 5 mm and cannot be greater than 10 mm, or less than 10 mm and cannot be greater than 15 mm. The maximum meander width (absolute value) of each of the face surfaces 5A to 5D is not greater than 10 µm. More precisely, the maximum meander width of each of the face surfaces 5A to 5D is not greater than 5 µm. The maximum meander shape width of each of the side faces 5A to 5D is defined as a distance in a normal direction to each of the side faces 5A to 5D between a location that is most raised towards an outer side of the SiC chip 2 and a location that is most recessed towards an inner side of the SiC chip 2, in a top view.

[0039] In this embodiment, the SiC chip 2 has a laminated structure that separates a SiC substrate 6 from the n + The substrate comprises a SiC substrate 6 and an n-type SiC epitaxial layer 7, laminated from the side of the second main surface 4 towards the side of the first main surface 3 in that order. The SiC substrate 6 forms the second main surface 4 and sections of the side surfaces 5A to 5D. The SiC epitaxial layer 7 forms the first main surface 3 and sections of the side surfaces 5A to 5D.

[0040] The n-type impurity concentration of the SiC substrate 6 cannot be less than 1.0×10 18 cm -3 and not larger than 1.0×10 21 cm -3The SiC substrate 6 can have a thickness of not less than 40 µm and not more than 250 µm. The thickness of the SiC substrate 6 can be not less than 40 µm and not greater than 100 µm, not less than 100 µm and not greater than 150 µm, not less than 150 µm and not greater than 200 µm, or not less than 200 µm and not greater than 250 µm. Preferably, the thickness of the SiC substrate 6 is not less than 40 µm and not greater than 150 µm. By thinning the SiC substrate 6, its resistance value can be reduced.

[0041] The SiC epitaxial layer 7 has an n-type impurity concentration that is lower than the n-type impurity concentration of the SiC substrate 6. The n-type impurity concentration of the SiC epitaxial layer 7 cannot be less than 1.0 × 10 15 cm -3 and not larger than 1.0×10 18 cm -3The SiC epitaxial layer 7 can have a thickness that is less than the thickness of the SiC substrate 6. The thickness of the SiC epitaxial layer 7 cannot be less than 1 µm and cannot be greater than 50 µm. The thickness of the SiC epitaxial layer 7 cannot be less than 1 µm and cannot be greater than 5 µm, less than 5 µm and cannot be greater than 10 µm, less than 10 µm and cannot be greater than 15 µm, less than 15 µm and cannot be greater than 20 µm, less than 20 µm and cannot be greater than 30 µm, less than 30 µm and cannot be greater than 40 µm, or less than 40 µm and cannot be greater than 50 µm. The thickness of the SiC epitaxial layer 7 is preferably not less than 5 µm and not greater than 15 µm.

[0042] With reference to Fig. 3 and Fig. 4. The SiC semiconductor component 1 includes a plurality of modified regions 8A, 8B, 8C, and 8D, each formed on the side faces 5A to 5D. The plurality of modified regions 8A to 8D includes first modified regions 8A, second modified regions 8B, third modified regions 8C, and fourth modified regions 8D.

[0043] The modified regions 8A to 8D are regions in which sections of the SiC monocrystal forming the face surfaces 5A to 5D are modified such that they possess a property different from that of the SiC monocrystal. The modified regions 8A to 8D are regions that are modified to exhibit a property differing from that of the SiC monocrystal with respect to density, refractive index, mechanical strength (crystal strength), or other physical characteristics.

[0044] The modified regions 8A to 8D can contain at least one layer consisting of a remelted-and-resolidified layer, a defect layer, a dielectric breakdown layer, and a refractive index change layer. The remelted-and-resolidified layer is a layer in which a section of the SiC monocrystal has been remelted and subsequently resolidified. The defect layer is a layer containing a hole, fissure, etc., formed in the SiC monocrystal. The dielectric breakdown layer is a layer in which a section of the SiC monocrystal has undergone dielectric breakdown. The refractive index change layer is a layer in which a section of the SiC monocrystal has changed to a refractive index different from that of the SiC monocrystal.

[0045] The multitude of modified regions 8A to 8D are formed at intervals from the first main surface 3 to the side of the second main surface 4 on the respective side surfaces 5A to 5D. The multitude of modified regions 8A to 8D are formed at intervals from the second main surface 4 to the side of the first main surface 3 on the respective side surfaces 5A to 5D.

[0046] The multitude of modified regions 8A to 8D are preferably formed in the SiC substrate 6. Even more preferably, the multitude of modified regions 8A to 8D are formed in the SiC substrate 6 at distances from the SiC epitaxial layer 7 towards the side of the second main surface 4. Variations in the physical and electrical properties of the SiC epitaxial layer 7 due to the multitude of modified regions 8A to 8D can thus be suppressed. That is, a functional component can be suitably formed in the SiC epitaxial layer 7.

[0047] In this embodiment, the first to fourth modified regions 8A to 8D are each formed in a plurality of levels on the side faces 5A to 5D (four levels in this embodiment). The number of levels of the first to fourth modified regions 8A to 8D is the number of the first to fourth modified regions 8A to 8D that are present in the normal direction Z on the side faces 5A to 5D.

[0048] The number of levels in the first to fourth modified regions 8A to 8D is adjusted according to the thickness TC of the SiC chip 2. Specifically, for SiC chip 2 with a thickness TC of no more than 150 µm, the cleavage thickness can be reduced, and therefore the number of levels in the first to fourth modified regions 8A to 8D can be decreased. In this case, the workload can be reduced, and therefore productivity can be increased. Reducing the thickness TC of SiC chip 2 also effectively reduces the resistance of SiC chip 2.

[0049] The first modified regions 8A are formed with spacing in the normal direction Z and are each formed as bands extending along the first face 5A in the first direction X (m-axis direction). The first modified regions 8A each extend from a corner section on the side of the third face 5C to a corner section on the side of the fourth face 5D.

[0050] Each first modified region 8A comprises a plurality of first modified sections 9A. Each first modified section 9A is a laser irradiation mark formed by irradiation with laser light. The first modified sections 9A are each formed as lines extending in the normal direction Z and are spaced apart in the first direction X (m-axis direction). The first modified sections 9A can instead each be formed as points. The single first modified region 8A is formed by a band-shaped region connecting the first modified sections 9A in the first direction X (m-axis direction). In this embodiment, the first modified sections 9A are formed in a matrix spaced apart in the first direction X (m-axis direction) and in the normal direction Z, and are opposite each other in the first direction X (m-axis direction) and in the normal direction Z.

[0051] The second modified regions 8B are formed with spacing in the normal direction Z and are each formed as bands extending in the first direction X (m-axis direction) along the second face 5B. The second modified regions 8B each extend from a corner section on the side of the third face 5C to a corner section on the side of the fourth face 5D.

[0052] Every second modified region 8B contains a plurality of second modified sections 9B. Every second modified section 9B is a laser irradiation mark formed by irradiation with laser light. The second modified sections 9B are each formed as lines extending in the normal direction Z and are spaced apart in the first direction X (m-axis direction). The second modified sections 9B can each instead be formed as points. The single second modified region 8A is formed by a band-shaped region connecting the second modified sections 9B in the first direction X (m-axis direction). In this embodiment, the second modified sections 9B are formed in a matrix spaced apart in the first direction X (m-axis direction) and in the normal direction Z, and are opposite each other in the first direction X (m-axis direction) and in the normal direction Z.

[0053] The third modified regions 8C are formed with spacing in the normal direction Z and are each formed as bands extending in the second direction Y (a-axis direction) along the third face 5C. The third modified regions 8C each extend from a corner section on the side of the first face 5A to a corner section on the side of the second face 5B.

[0054] The respective third modified regions 8C can be formed continuously or continuously with the respective first modified regions 8A at the corner section connecting the first side surface 5A and the third side surface 5C. The respective third modified regions 8C can be formed at intervals from the respective first modified regions 8A at the corner section connecting the first side surface 5A and the third side surface 5C. The respective third modified regions 8C can be formed continuously with the respective second modified regions 8B at the corner section connecting the second side surface 5B and the third side surface 5C. The respective third modified regions 8C can be formed at intervals from the respective second modified regions 8B at the corner section connecting the second side surface 5B and the third side surface 5C.

[0055] Each third modified region 8C contains a plurality of third modified sections 9C. Each third modified section 9C is a laser irradiation mark formed by irradiation with laser light. The third modified sections 9C are each formed as lines extending in the normal direction Z and are spaced apart in the second direction Y (a-axis direction). The third modified sections 9C can instead each be formed as points. The individual third modified region 8C is formed by a band-shaped region connecting the third modified sections 9C in the second direction Y (a-axis direction). In this embodiment, the third modified sections 9C are formed in a matrix spaced apart in the second direction Y (a-axis direction) and the normal direction Z, and are opposite each other in the second direction Y (a-axis direction) and the normal direction Z.

[0056] The fourth modified regions 8D are formed with spacing in the normal direction Z and are each formed as bands extending in the second direction Y (a-axis direction) along the fourth face 5D. The fourth modified regions 8D each extend from a corner section on the side of the first face 5A to a corner section on the side of the second face 5B.

[0057] The respective fourth modified regions 8D can be formed continuously with the respective first modified regions 8A at the corner section connecting the first face 5A and the fourth face 5D. The respective fourth modified regions 8D can be formed at intervals from the respective first modified regions 8A at the corner section connecting the first face 5A and the fourth face 5D. The respective fourth modified regions 8D can be formed continuously with the respective second modified regions 8B at the corner section connecting the second face 5B and the fourth face 5D. The respective fourth modified regions 8D can be formed at intervals from the respective second modified regions 8B at the corner section connecting the second face 5B and the fourth face 5D.

[0058] Each fourth modified region 8D contains a plurality of fourth modified sections 9D. Each fourth modified section 9D is a laser irradiation mark formed by irradiation with laser light. The fourth modified sections 9D are each formed as lines extending in the normal direction Z and are spaced apart in the second direction Y (a-axis direction). The fourth modified sections 9D can instead each be formed as points. The single fourth modified region 8D is formed by a band-shaped region connecting the fourth modified sections 9D in the second direction Y (a-axis direction). In this embodiment, the fourth modified sections 9D are formed in a matrix spaced apart in the second direction Y (a-axis direction) and in the normal direction Z, and are opposite each other in the second direction Y (a-axis direction) and in the normal direction Z.

[0059] The first to fourth modified regions 8A to 8D can be formed at the same depth or at different depths. The first to fourth modified regions 8A to 8D can each be formed as a single ring extending continuously along the side faces 5A to 5D by being continuously formed at the corner sections of the SiC chip 2.

[0060] The modification ratios of the face surfaces 5A to 5D do not necessarily have to be matched. The modification ratios of the face surfaces 5A to 5D can be the same or different. The modification ratios of the face surfaces 5A to 5D can be set by the total values, total areas, etc., of the first to fourth modified regions 8A to 8D (first to fourth modified sections 9A to 9D).

[0061] The third face 5C (fourth face 5D), which is composed of the m-plane of the SiC monocrystal, extends along a nearest neighbor direction of Si and therefore has the property of being more easily cleaved than the first face 5A (second face 5B), which is composed of the a-plane of the Si monocrystal or SiC monocrystal. The modification ratio of the third face 5C (fourth face 5D) can therefore be smaller than the modification ratio of the first face 5A (second face 5B).

[0062] The distance between adjacent third-modified regions 8C (fourth-modified regions 8D) on the third face 5C (fourth-face 5D) can be smaller than the distance between adjacent first-modified regions 8A (second-modified regions 8B) on the first face 5A (second-face 5B). The number of levels of the third-modified regions 8C (fourth-modified regions 8D) on the third face 5C (fourth-face 5D) can be smaller than the number of levels of the first-modified regions 8A (second-modified regions 8B) on the first face 5A (second-face 5B). The thickness (width) of the third modified regions 8C (fourth modified regions 8D) of the third face 5C (fourth face 5D) can be smaller than the thickness (width) of the first modified regions 8A (second modified regions 8B) of the first face 5A (second face 5B).

[0063] The SiC chip 2 includes an active region 10 and an outer region 11. The active region 10 is a region that contains, as an example of the functional component, an SBD (Schottky diode or Schottky barrier diode) 12. In a top view, the active region 10 is formed in a central section of the SiC chip 2, with inward distances from the side faces 5A to 5D. In a top view, the active region 10 is formed in a four-sided shape, with four sides that are parallel to the side faces 5A to 5D.

[0064] The outer region 11 is a region on an outer side of the active region 10. The outer region 11 is formed in a region between the side faces 5A to 5D and the active region 10. The outer region 11 is formed in a ring shape (in particular, a continuous shape) that surrounds the active region 10 in plan view.

[0065] With reference to Fig. Section 6 of the SiC semiconductor device 1 includes an n-type diode region 13, which is formed in a surface layer section of the first main surface 3, specifically in the active region 10. The diode region 13 is formed in a central section of the first main surface 3. The plane shape of the diode region 13 is arbitrary. The diode region 13 can be formed in a four-sided shape, with four sides parallel to the side surfaces 5A to 5D in the top view.

[0066] In this embodiment, the diode region 13 is formed using a section of the SiC epitaxial layer 7. The n-type impurity concentration of the diode region 13 is equal to the n-type impurity concentration of the SiC epitaxial layer 7. The n-type impurity concentration of the diode region 13 can exceed the n-type impurity concentration of the SiC epitaxial layer 7. In this case, the diode region 13 is formed by introducing an n-type impurity into a planar section of the SiC epitaxial layer 7.

[0067] A protection region 14, containing a p-type impurity, is formed in a surface layer section of the first main surface 3, specifically in the outer region 11. The p-type impurity of protection region 14 need not be activated, or it may be. Protection region 14 is formed as a band extending along the diode region 13 in plan view. More precisely, protection region 14 is formed in a ring shape (more precisely, in a continuous shape) that surrounds the diode region 13 in plan view. Protection region 14 is thus formed as a protection ring region.

[0068] The active region 10 (diode region 13) is defined by the protection region 14. The plane shape of the active region 10 (diode region 13) is determined by the plane shape of the protection region 14. The protection region 14 can be formed as a polygonal ring shape or as a circular ring shape, as seen from the top view.

[0069] With reference to Fig. 5, Fig. 7 and Fig. 8 The SiC semiconductor component 1 includes a plurality of alignment patterns 20 as accessory patterns, which are formed in a circumferential edge section of the first main surface 3, in plan view at distances inwards from the side surfaces 5A to 5D. An accessory pattern refers to an ornamental structure that is electrically independent of the functional component (the SBD 12 in this embodiment) and which includes a metallic material (metal pattern) and / or an insulating material (insulating pattern) that does not contribute to the electrical properties of the SiC semiconductor component 1.

[0070] The alignment patterns 20 are each formed in the first main surface 3, specifically at the outer region 11. In plan view, the alignment patterns 20 are formed such that one is located at each of the four corners of the first main surface 3. The alignment patterns 20 are each formed on diagonals of the first main surface 3 at the four corners of the first main surface 3. The alignment patterns 20 are not formed in any regions other than the four corners of the first main surface 3.

[0071] Each orientation pattern 20 is formed in a shape that differs from a circular shape in plan view. Each orientation pattern 20 comprises a first section 21 and a second section 22, each extending in different directions. In this embodiment, each orientation pattern 20 is formed in an L-shape, comprising the first section 21 and the second section 22. The first section 21 extends along the m-axis direction of the SiC monocrystal. The second section 22 extends along the a-axis direction of the SiC monocrystal. Each orientation pattern 20 also serves as an orientation marker, indicating a crystal orientation of the SiC monocrystal.

[0072] An inner corner section 23 of each orientation pattern 20 is opposite the active region 10 in the plan view. An outer corner section 24 of each orientation pattern 20 is opposite a corner section of the first principal surface 3 in the plan view. Each orientation pattern 20 defines an L-shaped passage 25 at the corner section of the first principal surface 3 in the plan view.

[0073] The alignment patterns 20 are formed at each of the four corners of the first main surface 3 such that the first sections 21 are positioned on the same straight line and that the second sections 22 are positioned on the same straight line. No auxiliary pattern other than the alignment patterns 20 is formed on extension lines of the first sections 21 of the alignment patterns 20 at the outer region 11. No auxiliary pattern other than the alignment patterns 20 is formed on extension lines of the second sections 22 of the alignment patterns 20 at the outer region 11.

[0074] Each alignment pattern 20 is formed from a material other than a metal. More precisely, each alignment pattern 20 has an alignment trench structure comprising an alignment trench 26 and an insulator 27. The alignment trench 26 is formed by trenching into the first main surface 3 in the direction of the second main surface 4. The alignment trench 26 has side walls and a bottom wall. The side walls and the bottom wall of the alignment trench 26 are positioned within the SiC epiaxial layer 7.

[0075] The side walls of the alignment trench 26 can extend in the normal direction Z. The angle formed by the side walls of the alignment trench 26 with the first principal surface 3 within the SiC epitaxial layer 7 cannot be less than 90° and cannot be greater than 95° (for example, not less than 91° and not greater than 93°). The side walls of the alignment trench 26 can be formed substantially perpendicular to the first principal surface 3. The alignment trench 26 can be formed in a converging shape, with the opening width narrowing or tapering from the first principal surface 3 towards the bottom wall.

[0076] The bottom wall of the alignment trench 26 points towards the c-plane of the SiC monocrystal. The bottom wall of the alignment trench 26 has an off angle that is inclined in the a-axis direction with respect to the c-plane of the SiC monocrystal. The bottom wall of the alignment trench 26 can be formed parallel to the first principal surface 3. The bottom wall of the alignment trench 26 can be formed in a shape that is curved towards the second principal surface 4.

[0077] The depth DT of the alignment trench 26 cannot be less than 0.01 µm and cannot be greater than 10 µm. The depth DT cannot be less than 0.01 µm and cannot be greater than 1 µm, less than 1 µm and cannot be greater than 2 µm, less than 2 µm and cannot be greater than 4 µm, less than 4 µm and cannot be greater than 6 µm, less than 6 µm and cannot be greater than 8 µm, or less than 8 µm and cannot be greater than 10 µm.

[0078] The width WT of the alignment trench 26 cannot be less than 1 µm and cannot be greater than 100 µm. The width WT is a width in a direction perpendicular to the direction in which the alignment trench 26 extends. The width WT cannot be less than 1 µm and cannot be greater than 20 µm, less than 20 µm and cannot be greater than 40 µm, less than 40 µm and cannot be greater than 60 µm, less than 60 µm and cannot be greater than 80 µm, or less than 80 µm and cannot be greater than 100 µm.

[0079] The width WL of the L-shaped passage 25 can exceed 0 µm and not exceed 200 µm. The width WL is a width in a direction perpendicular to the direction in which the L-shaped passage 25 extends. The width WL can exceed 0 µm and not exceed 10 µm, not exceed 10 µm and not exceed 20 µm, not exceed 20 µm and not exceed 50 µm, not exceed 50 µm and not exceed 100 µm, not exceed 100 µm and not exceed 150 µm, or not exceed 150 µm and not exceed 200 µm.

[0080] The insulator 27 is embedded as an integral or one-piece object in the alignment trench 26. The insulator 27 is made of a transparent insulating material. The insulator 27 comprises at least one of silicon oxide, silicon nitride, aluminum oxide, zirconium oxide, and tantalum oxide. In this embodiment, the insulator 27 is made of silicon oxide.

[0081] The SiC semiconductor component 1 includes an interlayer insulating layer 30 formed on the first main surface 3. The interlayer insulating layer 30 is composed of a transparent insulating material. The interlayer insulating layer 30 can have a laminated structure comprising a silicon oxide layer and a silicon nitride layer. Alternatively, the interlayer insulating layer 30 can have a single-layer structure consisting of either a silicon oxide layer or a silicon nitride layer. In this embodiment, the interlayer insulating layer 30 consists of a silicon oxide layer.

[0082] The intermediate insulating layer 30 includes a contact opening 31 that exposes the diode region 13 in the active region 10. The contact opening 31 also exposes inner circumferential edges of the protected region 14. The contact opening 31 can be planar. It can also be formed as a four-sided shape, with four sides parallel to the side surfaces 5A to 5D in the top view.

[0083] The intermediate insulating layer 30 covers the alignment patterns 20 at the outer region 11. The circumferential edges of the intermediate insulating layer 30 are exposed at the side surfaces 5A to 5D. In this embodiment, the circumferential edges of the intermediate insulating layer 30 are continuous with the side surfaces 5A to 5D. The circumferential edges of the intermediate insulating layer 30 can be formed with inward-facing gaps from the side surfaces 5A to 5D. In this case, the circumferential edges of the intermediate insulating layer 30 can expose the alignment patterns 20 at the first main surface 3.

[0084] The thickness of the intermediate insulating layer 30 cannot be less than 0.1 µm and not greater than 10 µm. The thickness of the intermediate insulating layer 30 cannot be less than 0.1 µm and not greater than 1 µm, not less than 1 µm and not greater than 2 µm, not less than 2 µm and not greater than 4 µm, not less than 4 µm and not greater than 6 µm, not less than 6 µm and not greater than 8 µm, or not less than 8 µm and not greater than 10 µm. The thickness of the intermediate insulating layer 30 is preferably not less than 0.5 µm and not greater than 5 µm.

[0085] The SiC semiconductor component 1 includes a first main surface electrode 32, which is formed on the first main surface 3. The first main surface electrode 32 is connected to the diode region 13 and the protection region 14 within the contact opening 31. The first main surface electrode 32 extends from the contact opening 31 to the intermediate insulating layer 30.

[0086] The circumferential edges of the first main surface electrode 32 are formed on the intermediate insulating layer 30, with inward distances from the side surfaces 5A to 5D. The circumferential edges of the first main surface electrode 32 expose the alignment pattern 20 in a top view. In this embodiment, the circumferential edges of the first main surface electrode 32 expose the alignment pattern 20 across the intermediate insulating layer 30.

[0087] The first main surface electrode 32 has a laminated structure, including a barrier layer 33 and a main body layer 34, which are laminated or stacked on top of each other in that order, starting from the side of the first main surface 3. The barrier layer 33 is formed as a film along the first main surface 3 and the intermediate insulating layer 30. The barrier layer 33 forms a Schottky junction with the diode region 13. The SBD 12, which has the first main surface electrode 32 as an anode and the diode region 13 as a cathode, is thus formed. That is, the first main surface electrode 32 is an anode electrode of the SBD 12.

[0088] The barrier layer 33 can comprise at least one Ti layer, one Pd layer, one Cr layer, one V layer, one Mo layer, one W layer, one Pt layer, and one Ni layer. The thickness of the barrier layer 33 cannot be less than 0.01 µm and not greater than 5 µm. The thickness of the barrier layer 33 can be less than 0.01 µm and not greater than 0.1 µm, less than 0.1 µm and not greater than 1 µm, less than 1 µm and not greater than 2 µm, less than 2 µm and not greater than 3 µm, less than 3 µm and not greater than 4 µm, or less than 4 µm and not greater than 5 µm.

[0089] The main body layer 34 is formed on the barrier layer 33. The main body layer 34 is formed as a film along the barrier layer 33. The main body layer 34 covers an entire area of ​​a main surface of the barrier layer 33. The circumferential edges of the first main surface electrode 32 are formed by the barrier layer 33 and the main body layer 34. The main body layer 34 comprises at least one layer of pure Al (referring to an Al layer composed of Al with a purity of at least 99%), one AlSi alloy layer, one AlCu alloy layer, and one AlSiCu alloy layer.

[0090] The thickness of the main body layer 34 exceeds the thickness of the barrier layer 33. The thickness of the main body layer 34 cannot be less than 0.05 µm and cannot be greater than 10 µm. The thickness of the main body layer 34 cannot be less than 0.05 µm and cannot be greater than 0.1 µm, less than 0.1 µm and cannot be greater than 1 µm, less than 1 µm and cannot be greater than 2 µm, less than 2 µm and cannot be greater than 4 µm, less than 4 µm and cannot be greater than 6 µm, less than 6 µm and cannot be greater than 8 µm, or less than 8 µm and cannot be greater than 10 µm. The thickness of the main body layer 34 is preferably not less than 1 µm and not greater than 8 µm.

[0091] The SiC semiconductor component 1 includes an insulating layer 40 that covers the first main surface electrode 32, specifically over the first main surface 3. Fig. In Figure 5, the insulating layer 40 is shown by hatching. More precisely, the insulating layer 40 is formed on top of the intermediate insulating layer 30.

[0092] The insulating layer 40 has a pad opening 41 that exposes the first main surface electrode 32. In this embodiment, the pad opening 41 exposes the first main surface electrode 32 within a region surrounded by the contact opening 31, as seen from the top view. Alternatively, the pad opening 41 can surround the contact opening 31 in a region outside of the contact opening 31, as seen from the top view. The shape of the pad opening 41 can be planar. The pad opening 41 can be formed in a four-sided shape, with four sides parallel to the side surfaces 5A to 5D, as seen from the top view.

[0093] The inner walls of the pad opening 41 have inclined surfaces 42 that are inclined downwards or obliquely oriented from a main surface of the insulating layer 40 towards the intermediate insulating layer 30. The inclined surfaces 42 can be formed in curved shapes that are recessed or set back towards the side of the first main surface 3.

[0094] An angle θ1 from each inclined surface 42 cannot be less than 30° and cannot be greater than 60°. The angle θ1 is an acute angle formed by a straight line connecting a starting point and an end point of the inclined surface 42 with the first principal surface 3. The angle θ1 cannot be less than 30° and cannot be greater than 35°, less than 35° and cannot be greater than 40°, less than 40° and cannot be greater than 45°, less than 45° and cannot be greater than 50°, less than 50° and cannot be greater than 55°, or less than 55° and cannot be greater than 60°. The angle θ1 is preferably not less than 40° and cannot be greater than 50°.

[0095] The circumferential edges of the insulating layer 40 are formed at inward distances from the side surfaces 5A to 5D. The circumferential edges of the insulating layer 40 expose the alignment patterns 20 in the top view. In this embodiment, the insulating layer 40 exposes the alignment patterns 20 over the intermediate insulating layer 30 in the top view.

[0096] The perimeter edges of the insulating layer 40, together with the side surfaces 5A to 5D, define dicing roads 43. The first section 21 and the second section 22 of each alignment pattern 20 are also road markings indicating the directions in which the dicing roads 43 extend. No auxiliary pattern other than the alignment patterns 20 is formed in sections exposed at the dicing roads 43. That is, no auxiliary pattern is formed in sections on the intermediate insulating layer 30 that are exposed at the dicing roads 43.

[0097] The width WD of each dicing road 43 cannot be less than 1 µm and cannot be greater than 50 µm. The width WD is a width in a direction orthogonal (perpendicular) to the direction in which the dicing road 43 extends. The width WD cannot be less than 1 µm and cannot be greater than 10 µm, less than 10 µm and cannot be greater than 20 µm, less than 20 µm and cannot be greater than 30 µm, less than 30 µm and cannot be greater than 40 µm, or less than 40 µm and cannot be greater than 50 µm.

[0098] The width WD is preferably not less than 5% and not greater than 25% of the thickness TC of the SiC chip 2. The width WD can be not less than 5% and not greater than 7.5%, not less than 7.5% and not greater than 10%, not less than 10% and not greater than 12.5%, not less than 12.5% ​​and not greater than 15%, not less than 15% and not greater than 17.5%, not less than 17.5% and not greater than 20%, not less than 20% and not greater than 22.5%, or not less than 22.5% and not greater than 25% of the thickness TC. The width WD is preferably less than 5% and not greater than 15% of the thickness TC.

[0099] The circumferential edges of the insulating layer 40 have inclined surfaces 44, which slope downwards from the main surface of the insulating layer 40 towards the intermediate insulating layer 30. The inclined surfaces 44 can be formed in curved shapes that are recessed or set back towards the side of the first main surface 3.

[0100] An angle 92 from each inclined surface 44 cannot be less than 30° and cannot be greater than 60°. The angle θ2 is an acute angle formed by a straight line connecting a starting point and an end point of the inclined surface 44 with the first principal surface 3. The angle θ2 cannot be less than 30° and cannot be greater than 35°, less than 35° and cannot be greater than 40°, less than 40° and cannot be greater than 45°, less than 45° and cannot be greater than 50°, less than 50° and cannot be greater than 55°, or less than 55° and cannot be greater than 60°. The angle 82 is preferably not less than 40° and cannot be greater than 50°.

[0101] The angle θ2 of the inclined surfaces 44 can be greater than or less than the angle θ1 of the inclined surfaces 42. The angle θ2 of the inclined surfaces 44 can be equal to the angle θ1 of the inclined surfaces 42. The fact that the angle θ2 is equal to the angle θ1 means that the angle θ2 lies within a range of ±1° of the angle θ1, or within a range of ±1° of the angle θ1.

[0102] In the insulating layer 40, which has the inclined surfaces 44, interference of laser light through the insulating layer 40 can be suppressed when the laser light is emitted onto an inner surface of the SiC chip 2 (more precisely, a SiC wafer 62, which is described below). In particular, by ensuring that the angle θ2 is not less than 30° and not greater than 60°, the interference of laser light through the insulating layer 40 can be suitably suppressed. This prevents unwanted refraction of the laser light due to a difference in the refractive indices of the insulating layer 40 and air, and the laser light can be focused onto a suitable region in the SiC chip 2 (SiC wafer 62). Accordingly, the SiC chip 2 can be formed, which has the first to fourth modified regions 8A to 8D, suitably formed on the side surfaces 5A to 5D.

[0103] The width WD of the dicing roads 43 extending in the a-axis direction can be equal to or different from the width WD of dicing roads 43 extending in the m-axis direction. For example, the width WD of the dicing roads 43 extending in the a-axis direction can be smaller than the width WD of dicing roads 43 extending in the m-axis direction. In this case, the modification ratio of the third side face 5C (fourth side face 5D) extending in the a-axis direction can be smaller than the modification ratio of the first side face 5A (second side face 5B) extending in the m-axis direction.

[0104] The first to fourth modified regions 8A to 8D (first to fourth modified sections 9A to 9D) are formed by laser irradiation marking, as mentioned above. The width WD is set taking into account the refractive indices of laser light incident on the SiC chip 2 and the intermediate insulating layer 30. If the first to fourth modified regions 8A to 8D (first to fourth modified sections 9A to 9D) are formed at the same depth positions, the dicing roads 43 are preferably formed such that they have a uniform width WD.

[0105] If the third modified regions 8C (fourth modified regions 8D) are not to be formed at positions that are deep compared with the first modified regions 8A (second modified regions 8B), the width WD of the dicing roads 43 extending in the a-axis direction can be narrower than the width WD of dicing roads 43 extending in the m-axis direction.

[0106] In this embodiment, the insulating layer 40 has a laminated structure comprising a passivation layer 45 and a resin layer 46, which are laminated in that order starting from the side of the first main surface 3. The passivation layer 45 can comprise at least one silicon oxide layer and one silicon nitride layer. The passivation layer 45 can have a laminated structure comprising a silicon oxide layer and a silicon nitride layer. The passivation layer 45 can have a single-layer structure consisting of either a silicon oxide layer or a silicon nitride layer.

[0107] The passivation layer 45 preferably comprises an insulating material that differs from that of the intermediate insulating layer 30. In this embodiment, the passivation layer 45 is composed of a silicon nitride layer. The passivation layer 45 is formed as a film along the intermediate insulating layer 30 and the first main surface electrode 32. The passivation layer 45 has a first opening 47 that exposes a section of the first main surface electrode 32. The first opening 47 can be planar. The first opening 47 can be formed in a four-sided shape, with four sides parallel to the side surfaces 5A to 5D in a top view.

[0108] The thickness of the passivation layer 45 cannot be less than 0.1 µm and not greater than 20 µm. The thickness of the passivation layer 45 cannot be less than 0.1 µm and not greater than 1 µm, not less than 1 µm and not greater than 5 µm, not less than 5 µm and not greater than 10 µm, not less than 10 µm and not greater than 15 µm, or not less than 15 µm and not greater than 20 µm.

[0109] The resin layer 46 is formed as a film along a major surface of the passivation layer 45. The resin layer 46 can contain a photosensitive resin. The photosensitive resin can be of a negative or positive type. The resin layer 46 can contain at least one polyimide, one polyamide, and one polybenzoxazole. In this embodiment, the resin layer 46 contains polybenzoxazole.

[0110] In this embodiment, the circumferential edges of the resin layer 46 expose the circumferential edges of the passivation layer 45. The circumferential edges of the insulating layer 40 are formed by the resin layer 46 and the passivation layer 45. The resin layer 46 can cover the circumferential edges of the passivation layer 45. In this case, the circumferential edges of the insulating layer 40 are formed by the resin layer 46.

[0111] The resin layer 46 has a second opening 48 that exposes a section of the first main surface electrode 32. The shape of the second opening 48 is arbitrary. The second opening 48 can be formed in a four-sided shape, with four sides parallel to the side surfaces 5A to 5D in the top view. The second opening 48 communicates with the first opening 47 of the passivation layer 45 and forms a single pad opening 41 with the first opening 47.

[0112] The inner walls of the second opening 48 can be flush with the inner walls of the first opening 47. The inner walls of the second opening 48 can be positioned on the sides of the side faces 5A to 5D relative to the inner walls of the first opening 47. The inner walls of the second opening 48 can also be positioned on the inner sides of the SiC chip 2 relative to the inner walls of the first opening 47. That is, the resin layer 46 can cover the inner walls of the first opening 47. In this case, the pad opening 41 is formed by the resin layer 46 (second opening 48).

[0113] The thickness of the resin layer 46 cannot be less than 1 µm and not greater than 50 µm. The thickness of the resin layer 46 cannot be less than 1 µm and not greater than 10 µm, not less than 10 µm and not greater than 20 µm, not less than 20 µm and not greater than 30 µm, not less than 30 µm and not greater than 40 µm, or not less than 40 µm and not greater than 50 µm.

[0114] The SiC semiconductor component 1 has a pad electrode 49 formed on the first main surface electrode 32. The pad electrode 49 is located within the pad opening 41 on the first main surface electrode 32. The pad electrode 49 is electrically connected to the first main surface electrode 32. The pad electrode 49 covers the inclined surfaces 42 of the pad opening 41. The pad electrode 49 has a terminal surface or connection surface 50, which is externally connected to a connecting wire (for example, a bond wire).

[0115] The terminal surface 50 is positioned on the side of the first main surface electrode 32 with respect to the main surface of the insulating layer 40 (resin layer 46). The terminal surface 50 may project higher than the main surface of the insulating layer 40 (resin layer 46). The terminal surface 50 may have an overlapping section that covers the inclined surfaces 42 of the pad opening 41 and the main surface of the insulating layer 40 (resin layer 46).

[0116] The pad electrode 49 comprises a metallic material that differs from that of the first main surface electrode 32. The pad electrode 49 comprises at least one Ni layer, one Pd layer, and one Au layer. The pad electrode 49 can have a laminated structure in which at least two Ni layers, one Pd layer, and one Au layer are laminated on top of each other in any sequence. The pad electrode 49 can have a single-layer structure composed of one Ni layer, one Pd layer, or one Au layer.

[0117] The pad electrode 49 preferably has a terminal surface 50 formed by an Au layer. The pad electrode 49 can have a laminated structure comprising a Ni layer, a Pd layer, and an Au layer, laminated in that order starting from the side of the first main surface electrode 32. In this embodiment, the pad electrode 49 has a laminated structure comprising a Ni layer and an Au layer, laminated in that order starting from the side of the first main surface electrode 32.

[0118] The SiC semiconductor device 1 includes a second main surface electrode 51, which is formed on the second main surface 4. The second main surface electrode 51 is formed as a cathode electrode of the SBD 12. The second main surface electrode 51 forms an ohmic contact with the second main surface 4. The second main surface electrode 51 includes at least one Ti layer, one Ni layer, one Pd layer, one Au layer, and one Ag layer.

[0119] The second main surface electrode 51 can have a laminated structure in which at least two layers of a Ti layer, a Ni layer, a Pd layer, an Au layer, and an Ag layer are laminated in any order. The second main surface electrode 51 can also have a single-layer structure consisting of a Ti layer, a Ni layer, a Pd layer, an Au layer, or an Ag layer. The second main surface electrode 51 preferably includes a Ti layer as an ohmic electrode. In this embodiment, the second main surface electrode 51 has a laminated structure comprising a Ti layer, a Ni layer, a Pd layer, an Au layer, and an Ag layer, laminated in that order starting from the side of the second main surface 4.

[0120] As described above, the SiC semiconductor component 1 includes the SiC chip 2, the first to fourth modified regions 8A to 8D, the alignment patterns 20, the first main surface electrode 32, and the insulating layer 40. The SiC chip 2 has the first main surface 3 and the second main surface 4, each formed in four-sided shapes in the top view, and has the side surfaces 5A to 5D, which are composed of gap surfaces.

[0121] The first to fourth modified regions 8A to 8D are each formed on the side surfaces 5A to 5D. The alignment patterns 20 are formed in the circumferential boundary section (outer region 11) of the first main surface 3, in plan view with inward distances from the side surfaces 5A to 5D. The first main surface electrode 32 is formed on the first main surface 3, in plan view with inward distances from the side surfaces 5A to 5D, and exposes the alignment patterns 20.

[0122] The insulating layer 40 partially covers the first main surface electrode 32 in plan view. The insulating layer 40 delineates the dicing or separating lines 43 formed on the first main surface electrode 32, in plan view, with inward distances from the side surfaces 5A to 5D, and exposes the alignment patterns 20, also with respect to the side surfaces 5A to 5D. In the circumferential boundary section of the first main surface 3, which is positioned within the dicing lines 43, in plan view, no auxiliary pattern other than the alignment patterns 20 is formed.

[0123] With such a structure, the flatness of the side faces 5A to 5D can be prevented from decreasing due to an auxiliary pattern. The SiC semiconductor device 1 with a structure in which shape defects are suppressed due to an auxiliary pattern can thus be provided.

[0124] This also ensures that, at the dicing lines 43, it is not necessary to physically cut the insulating layer 40 when the SiC semiconductor component 1 is separated or cut out of the SiC wafer 62. The SiC semiconductor component 1 can thus be easily cut out of the SiC wafer 62. Furthermore, fractures of the SiC chip 2 due to peeling and degradation of the insulating layer 40 can be prevented. Consequently, shape defects of the SiC chip 2 caused by the insulating layer 40 can be suppressed.

[0125] Fig. Figure 9 is a diagram of the SiC wafer 62 used to fabricate the SiC semiconductor device 1, which is in Fig. 3 is shown.

[0126] With reference to Fig. In a process for manufacturing the SiC semiconductor component 1, the SiC wafer 62, which has a plate shape (disk shape in this embodiment) and is composed of the 4H-SiC monocrystal, is used. The SiC wafer 62 forms a base for the SiC chip 2. The SiC wafer 62 has a laminated structure comprising the SiC substrate 6 and the SiC epitaxial layer 7. The SiC epitaxial layer 7 is formed by epitaxially growing SiC starting from the SiC substrate 6.

[0127] The SiC wafer 62 has a first wafer main surface 63 on one side, a second wafer main surface 64 on another side, and a wafer side surface 65 that connects the first wafer main surface 63 and the second wafer main surface 64. The first wafer main surface 63 and the second wafer main surface 64 have an off-angle that corresponds to the off-angle of the SiC chip 2.

[0128] An orientation flat or orientation recess 66 is formed in the wafer side face 65 as an example of a marker indicating the crystal orientation. The orientation flat 66 is a notched or recessed section formed in the wafer side face 65. In this embodiment, the orientation flat 66 extends in a straight line along the a-axis direction of the SiC monocrystal.

[0129] An orientation plane 66 extending in the m-axis direction of the SiC monocrystal and an orientation plane 66 extending in the a-axis direction of the SiC monocrystal can instead be formed in the wafer side face 65. An orientation notch, formed from a notched section recessed or removed towards a central section of the SiC wafer 62, can instead be formed in the wafer side face 65 instead of the orientation plane 66.

[0130] The SiC wafer 62 comprises a first wafer corner section or edge section 67 and a second wafer corner section or edge section 68. The first wafer corner section 67 connects the first wafer main face 63 and the wafer side face 65. The second wafer corner section 68 connects the second wafer main face 64 and the wafer side face 65.

[0131] The first wafer corner section 67 has a first chamfered portion 69, which slopes downwards from the first main wafer face 63 towards the wafer side face 65. The first chamfered portion 69 may be curved. The second wafer corner section 68 has a second chamfered portion 70, which slopes downwards from the second main wafer face 64 towards the wafer side face 65. The second chamfered portion 70 may also be curved.

[0132] The SiC wafer 62 has a thickness TW that exceeds the thickness TC of the SiC chip 2. The thickness TW cannot be less than 100 µm and cannot be greater than 1000 µm. The thickness TW cannot be less than 100 µm and cannot be greater than 200 µm, less than 200 µm and cannot be greater than 400 µm, less than 400 µm and cannot be greater than 600 µm, less than 600 µm and cannot be greater than 800 µm, or less than 800 µm and cannot be greater than 1000 µm.

[0133] Planned cutting lines 72, which delineate a plurality of chip regions 71 in a subsequent step, are set or provided on the first main wafer surface 63. The planned cutting lines 72 are set or placed in a grid that extends along the m-axis and a-axis directions of the SiC monocrystal.

[0134] More precisely, the planned cutting lines 72 comprise a plurality of first planned cutting lines 72A and a plurality of second planned cutting lines 72B. The first planned cutting lines 72A each extend along the m-axis direction of the SiC monocrystal. The second planned cutting lines 72B each extend along the a-axis direction of the SiC monocrystal.

[0135] The chip regions 71 are set in a matrix along the m-axis and a-axis directions of the SiC monocrystal by the planned cutting lines 72. Each chip region 71 has one side oriented along the m-axis direction and one side oriented along the a-axis direction of the SiC monocrystal. The chip regions 71 include a plurality of first chip regions 71A and a second chip region 71B, or a plurality of second chip regions 71B. Fig. The second chip regions 71B are shown by a solid hatching or entirely in black.

[0136] The first chip regions 71A are regions in which the functional component (the SBD 12 in this embodiment) is formed. The second chip regions 71B are dummy chip regions and are regions in which a monitor pattern 73 is formed for performing process control of the first chip regions 71A. The monitor pattern 73 is also referred to as a PCM (process control monitor). The monitor patterns 73 are formed only in the second chip regions 71B. The monitor pattern 73 is not formed in the first chip region 71A or on the planned cutting line 72.

[0137] Each monitor pattern 73 includes various structures necessary to perform process control of the first chip regions 71A and is not limited to a specific embodiment. The monitor pattern 73 can include at least one of a bipolar transistor, a MISFET (metal-insulator-semiconductor field-effect transistor), a pn junction diode, an SBD, a MIS capacitor, an insulating film, a wiring film, a trench, and a via electrode.

[0138] The suitability of each step performed on the first chip regions 71A is evaluated indirectly at any given time from the physical and electrical characteristics of the structures formed in the monitor patterns 73. The physical characteristics include, for example, the dimensions of the structure formed in each monitor pattern 73. The electrical characteristics include, for example, the resistance and capacitance values ​​of a semiconductor region, etc., formed in each monitor pattern 73. By performing each step while maintaining the physical and electrical characteristics of the monitor patterns 73 at certain levels, the functional components can be suitably formed in the first chip regions 71A.

[0139] The number of first chip regions 71A cannot be less than 100 regions and cannot be greater than 10,000 regions. The number of first chip regions 71A cannot be less than 100 regions and cannot be greater than 1,000 regions, less than 1,000 regions and cannot be greater than 2,500 regions, less than 2,500 regions and cannot be greater than 5,000 regions, less than 5,000 regions and cannot be greater than 7,500 regions, or less than 7,500 regions and cannot be greater than 10,000 regions.

[0140] The number of second chip regions 71B is less than the number of first chip regions 71A. The number of second chip regions 71B is not less than 1 region and not greater than 20 regions. The number of second chip regions 71B can be not less than 1 region and not greater than 5 regions, not less than 5 regions and not greater than 10 regions, not less than 10 regions and not greater than 15 regions, or not less than 15 regions and not greater than 20 regions.

[0141] The region ratio of the number of second chip regions 71B to the number of first chip regions 71A cannot be less than 0.001 and cannot be greater than 0.01. The region ratio cannot be less than 0.001 and cannot be greater than 0.002, less than 0.002 and cannot be greater than 0.004, less than 0.004 and cannot be greater than 0.006, less than 0.006 and cannot be greater than 0.008, or less than 0.008 and cannot be greater than 0.01.

[0142] The planar area of ​​every second chip region 71B is equal to the planar area of ​​every first chip region 71A. The fact that the planar area of ​​every second chip region 71B is equal to the planar area of ​​every first chip region 71A means that the planar area of ​​every second chip region 71B lies within a range of ±1% of the planar area of ​​every first chip region 71A.

[0143] The chip regions 71 preferably include a plurality of the second chip regions 71B. Each step performed on the first chip regions 71A can thereby be suitably evaluated. The chip regions 71 preferably include a single second chip region 71B that is positioned at the central section of the SiC wafer 62. The chip regions 71 preferably include one or a plurality of second chip regions 71B that are positioned at intervals from a second chip region 71B located at the center to the peripheral edge faces (wafer side face 65) of the SiC wafer 62. Process errors at the central section and at the peripheral edge faces of a single SiC wafer 62 can thereby be suitably evaluated.

[0144] The chip regions 71 preferably include an odd number of second chip regions 71B. In this embodiment, the chip regions 71 include nine second chip regions 71B. It is understood that the chip regions 71 can instead contain an even number of second chip regions 71B.

[0145] The second chip regions 71B are oriented opposite each other in the a-axis direction of the SiC monocrystal, across one or a plurality (a plurality in this embodiment) of the first chip regions 71A. The second chip regions 71B are oriented opposite each other in the m-axis direction of the SiC monocrystal, across one or a plurality (a plurality in this embodiment) of the first chip regions 71A. In this embodiment, the second chip regions 71B are arranged in a matrix with spacing in the a-axis and m-axis directions of the SiC monocrystal.

[0146] After predetermined structures are formed in the chip regions 71, the SiC wafer 62 is cut along the planned cutting lines 72. This cuts out the first chip regions 71A as the SiC semiconductor components 1, and the second chip regions 71B are cut out as dummy SiC semiconductor components. The dummy SiC semiconductor components can be discarded.

[0147] Fig. 10A to Fig. Figure 10P are sectional views of a region of a section of the SiC wafer 62 and show an example of a method for fabricating the SiC semiconductor devices 1, which are in Fig. 3 are shown. Fig. 11A to Fig. Figure 11P are top views of a region of a section of the SiC wafer 62 and show an example of the method for manufacturing the SiC semiconductor components 1, which are in Fig. 3 are shown. In each of the Fig. 11A to Fig. Figure 11P shows a top view of a region containing three first chip regions 71A and one second chip region 71B.

[0148] With reference to Fig. 10A and Fig. In step 11A, the SiC wafer 62 is prepared. Next, a plurality of alignment trenches 26 are formed in the first main wafer face 63. In this step, a hard mask (not shown), which has a predetermined pattern, is first formed on the first main wafer face 63. The hard mask is composed of silicon dioxide.

[0149] The hard mask can be formed by a thermal oxidation treatment process or a CVD (chemical vapor deposition) process. The hard mask has a multitude of openings that expose regions where the alignment trenches 26 are to be formed. The openings are each formed in an L-shape in a top view. The openings are formed by an etching process. The etching process can be a wet etching process and / or a dry etching process.

[0150] Next, unnecessary sections of the SiC wafer 62 are removed by an etching process over or through the hard mask. The etching process can be a wet etching process and / or a dry etching process. The etching process is preferably a dry etching process. The alignment grooves 26, each of which is L-shaped in plan view, are thereby formed in the first main wafer face 63.

[0151] The planned cutting lines 72 are defined by the alignment trenches 26. More precisely, the alignment trenches 26 form a plurality of intersection pattern groups or cutting pattern groups 83, each of which shows an intersection of the planned cutting lines 72. The intersection pattern groups 83 are formed in a matrix with spacing in the a-axis direction and the m-axis direction of the SiC monocrystal.

[0152] Each intersection pattern group 83 includes four nearest-adjacent alignment trenches 26. The four nearest-adjacent alignment trenches 26 are spaced apart in the a-axis and m-axis directions of the SiC monocrystal. On the first wafer main face 63, the four nearest-adjacent alignment trenches 26 define an intersection 84 extending in the a-axis and m-axis directions of the SiC monocrystal through the outer corner sections 24. By subdividing the intersection 84 into four parts, the intersection 84 becomes the L-shaped passages 25 of the SiC chips 2.

[0153] The width of each intersection 84 can exceed 0 µm and not exceed 400 µm. The width of intersection 84 can exceed 0 µm and not exceed 20 µm, not exceed 20 µm and not exceed 40 µm, not exceed 40 µm and not exceed 100 µm, not exceed 100 µm and not exceed 200 µm, not exceed 200 µm and not exceed 300 µm, or not exceed 300 µm and not exceed 400 µm.

[0154] The grid-like planned cutting lines 72, which pass through the intersections 84 of the respective intersection pattern groups 83 in plan view, are defined hereby. Furthermore, the first chip regions 71A, each of which has an alignment trench 26 at each of four corners in plan view, are delimited by the planned cutting lines 72. The second chip regions 71B, each of which has an alignment trench 26 at each of four corners in plan view, are also delimited by the planned cutting lines 72.

[0155] Next, with reference to Fig. 10B and Fig. 11B A base insulating layer 85, which is to become a base for the insulators 27, is formed on the first wafer main face 63. The base insulating layer 85 fills the alignment trenches 26 and covers the first wafer main face 63. The base insulating layer 85 is formed by a thermal oxidation treatment process and / or a CVD process.

[0156] Next, a section of the base insulating layer 85, covering the first main wafer surface 63, is removed by an etching process. The etching process can be a wet etching process and / or a dry etching process. This creates the alignment patterns 20, which include the alignment trenches 26 and the insulators 27.

[0157] Next, with reference to Fig. 10C and Fig. 11C Main sections of the SBDs 12 (here, the diode regions 13 and the protection regions 14) are formed in the first chip regions 71A, and semiconductor sections (for example, semiconductor sections, etc., of SBDs or MISFETs) of the monitor patterns 73 are formed in the second chip regions 71B. This step may include a step of selectively introducing an n-type and / or a p-type impurity into the first chip regions 71A and the second chip regions 71B. The n-type and / or the p-type impurity may be introduced into the SiC wafer 62 by an ion implantation process using an ion implantation mask (not shown).

[0158] Next, with reference to Fig. 10D and Fig. 11D The interlayer insulating layer 30 is formed on the first main wafer surface 63. The interlayer insulating layer 30 covers the first chip regions 71A and the second chip regions 71B. The interlayer insulating layer 30 contains silicon oxide. The interlayer insulating layer 30 is formed by a thermal oxidation treatment process or a CVD process.

[0159] Next, with reference to Fig. 10E and Fig. 11E a plurality of contact openings 31 and a plurality of monitor contact openings 86 are formed in the interlayer insulating layer 30. The contact openings 31 are each formed in sections of the interlayer insulating layer 30 that cover the first chip regions 71A. The monitor contact openings 86 are each formed in sections of the interlayer insulating layer 30 that cover the second chip regions 71B. The number of monitor contact openings 86 in each second chip region 71B is arbitrary and is set according to the monitor pattern 73 formed in the second chip region 71B.

[0160] The contact openings 31 and the monitor contact openings 86 are formed by removing unnecessary sections of the intermediate insulating layer 30 by an etching process over a resist mask (not shown). The etching process can be a wet etching process and / or a dry etching process.

[0161] Next, with reference to Fig. 10F and Fig. 11F a first base main surface electrode 87 is formed on the first wafer main surface 63. The first base main surface electrode 87 has a laminated structure comprising the barrier layer 33 and the main body layer 34. The barrier layer 33 and the main body layer 34 can each be formed by a sputtering process and / or a vapor deposition process.

[0162] Next, with reference to Fig. 10G and Fig. Non-essential sections of the first base main surface electrode 87 are removed, and a plurality of first main surface electrodes 32 are formed in the chip regions 71. The first main surface electrodes 32 formed in the second chip regions 71B are referred to as monitor main surface electrodes 88. The non-essential sections of the first base main surface electrode 87 can be removed by an etching process over a resist mask (not shown). The etching process can be a wet etching process and / or a dry etching process.

[0163] The first main surface electrodes 32 cover the first chip regions 71A in such a way that the planned cutting lines 72 are exposed. The first main surface electrodes 32 also expose the alignment trenches 26 (intersection pattern groups 83). The first main surface electrodes 32 are electrically connected to the diode regions 13 and the protection regions 14 in the corresponding first chip regions 71A.

[0164] The main monitor surface electrodes 88 cover the second chip regions 71B such that the planned cutting lines 72 are exposed. The main monitor surface electrodes 88 also expose the alignment trenches 26 (intersection pattern groups 83). The main monitor surface electrodes 88 are electrically connected to the semiconductor regions, etc., in the corresponding second chip regions 71B. The number of main monitor surface electrodes 88 in each second chip region 71B is arbitrary and is set according to the monitor pattern 73 formed in the second chip region 71B.

[0165] Next, with reference to Fig. 10H and Fig. In 11H, a base insulating layer 89, which is to become the base of the insulating layers 40, is formed on the first main wafer surface 63. The insulating layers 40 each have the laminated structure that includes the passivation layer 45 and the resin layer 46. The passivation layer 45 contains silicon nitride. The passivation layer 45 can be formed by a CVD process. The resin layer 46 contains a photosensitive resin (polybenzoxazole in this embodiment). The resin layer 46 can be formed by coating the photosensitive resin onto the passivation layer 45.

[0166] Next, with reference to Fig. 10I and Fig. 11I a plurality of pad openings 41, a plurality of monitor pad openings 90 and dicing roads 91 are formed in the base insulating layer 89, and at the same time the base insulating layer 89 is subdivided into a plurality of insulating layers 40.

[0167] In this step, the resin layer 46 is first selectively exposed and then developed. This creates the second openings 48 and the dicing lines 91 in the resin layer 46. Next, sections of the passivation layer 45 exposed at the resin layer 46 are removed by an etching process. The etching process can be a wet etching process and / or a dry etching process. This creates the first openings 47 and the dicing lines 91 in the passivation layer 45. The base insulating layer 89 is also subdivided into the insulating layers 40.

[0168] The pad openings 41 are each formed by a first opening 47 and a second opening 48. The pad openings 41 expose the corresponding first main surface electrodes 32. The monitor pad openings 90 are each formed by a first opening 47 and a second opening 48. The monitor pad openings 90 expose the corresponding monitor main surface electrodes 88. The number of monitor pad openings 90 is arbitrary and is set according to the monitor pattern 73 (monitor main surface electrode 88) formed in the second chip region 71B.

[0169] The dicing roads 91 are delimited by the circumferential edges of the insulating layers 40 and are formed into a grid that extends in plan view along the planned cutting lines 72. The dicing roads 91 expose the planned cutting lines 72 in plan view. Furthermore, the dicing roads 91 expose the alignment trenches 26 (intersection pattern groups 83) in plan view.

[0170] In sections of the first wafer main surface 63 exposed by the dicing roads 91, no auxiliary pattern other than the alignment trenches 26 (intersection pattern groups 83) is formed. Furthermore, no auxiliary pattern is formed in a section of the interlayer insulating layer 30 exposed by the dicing roads 91.

[0171] The width WD2 of the Dicing Roads 91 cannot be less than 2 µm and cannot be greater than 100 µm. The width WD2 is a width orthogonal (perpendicular) to the direction in which each Dicing Road 91 extends. The width WD2 cannot be less than 2 µm and not greater than 20 µm, less than 20 µm and not greater than 40 µm, less than 40 µm and not greater than 60 µm, less than 60 µm and not greater than 80 µm, or less than 80 µm and not greater than 100 µm.

[0172] The width WD2 is preferably not less than 10% and not greater than 50% of the final thickness TW of the SiC wafer 62. The width WD2 can be not less than 10% and not greater than 15%, not less than 15% and not greater than 20%, not less than 20% and not greater than 25%, not less than 25% and not greater than 30%, not less than 30% and not greater than 35%, not less than 35% and not greater than 40%, not less than 40% and not greater than 45%, or not less than 45% and not greater than 50% of the final thickness TW of the SiC wafer 62. The width WD2 is preferably not less than 10% and not greater than 30% of the final thickness TW of the SiC wafer 62.

[0173] The dicing lines 91 suppress the interference of laser light by or due to the insulating layers 40 when the laser light is emitted onto the interior of the SiC wafer 62. By ensuring that the width WD2 of the dicing lines 91 is no less than 10% and no greater than 50% of the final thickness TW of the SiC wafer 62, the interference of laser light by the insulating layers 40 can be adequately suppressed. This suppresses the unwanted refraction of the laser light due to the difference in the refractive indices of the insulating layers 40 and air, and the laser light can be focused onto the appropriate region in the SiC wafer 62. Consequently, the first to fourth modified regions 8A to 8D can be appropriately formed in a subsequent step.

[0174] The circumferential edges of each insulating layer 40 have inclined surfaces 44 that slope downwards from the main surface of the insulating layer 40 towards the intermediate insulating layer 30. The inclined surfaces 44 can be formed in curved shapes that are recessed or recessed towards the side of the SiC wafer 62. The angle θ2 of each inclined surface 44 cannot be less than 30° and cannot be greater than 60°. The angle θ2 is the angle within the insulating layer 40 formed by the straight line connecting the starting and ending points of the inclined surface 44 with the first main surface 3.

[0175] The angle θ2 cannot be less than 30° and not greater than 35°, less than 35° and not greater than 40°, less than 40° and not greater than 45°, less than 45° and not greater than 50°, less than 50° and not greater than 55°, or less than 55° and not greater than 60°. The angle θ2 is preferably not less than 40° and not greater than 50°.

[0176] By making the circumferential edges of the insulating layers 40 inclined surfaces 44, the interference of laser light through the insulating layers 40 can be suppressed when the laser light is emitted onto the interior of the SiC wafer 62. In particular, by ensuring that the angle θ2 of the insulating layer 40 is no less than 30° and no greater than 60°, the interference of laser light through the insulating layers 40 can be suitably suppressed. This suppresses the unwanted refraction of the laser light due to the difference in the refractive indices of the insulating layers 40 and air, and the laser light can be focused onto the appropriate region in the SiC wafer 62. Consequently, the first to fourth modified regions 8A to 8D can be suitably formed in the subsequent step.

[0177] The width WD2 of the dicing streets 91 extending in the a-axis direction can be equal to or different from the width WD2 of dicing streets 91 extending in the m-axis direction. For example, the width WD2 of the dicing streets 91 extending in the a-axis direction can be smaller than the width WD2 of dicing streets 91 extending in the m-axis direction. In this case, the total number of chip regions 71 can be increased.

[0178] Next, with reference to Fig. 10 years and Fig. 11J A plurality of pad electrodes 49 are formed on the corresponding first main surface electrodes 32, and a plurality of monitor pad electrodes 92 are each formed on the corresponding monitor main surface electrodes 88. The pad electrodes 49 and the monitor pad electrodes 92 can each be formed by a plating process.

[0179] Next, with reference to Fig. 10K and Fig. 11K, the second main wafer surface 64, was ground. The second main wafer surface 64 can be ground using a CMP process (chemical mechanical polishing). This thins the SiC wafer 62 until it reaches the desired thickness.

[0180] Next, with reference to Fig. 10L and Fig. 11L, the second main surface electrode 51 is formed on the second wafer main surface 64. The second main surface electrode 51 can be formed by a sputtering process, a vapor deposition process, and / or a plating process. Before or during the formation of the second main surface electrode 51, heat treatment ("annealing treatment") can be performed on the second wafer main surface 64. The heat treatment on the second wafer main surface 64 can be performed by a laser irradiation process.

[0181] Next, with reference to Fig. 10M and Fig. 11M an elastic carrier tape 93 attached or glued to the second main wafer surface 64.

[0182] Next, with reference to Fig. 10N and Fig. 11N laser light is emitted onto the planned cutting lines 72 of the SiC wafer 62. A multitude of modified regions 94, which are intended to form the basis of the first to fourth modified regions 8A to 8D, are thereby created in the SiC wafer 62.

[0183] The laser light is emitted onto the SiC wafer 62 from the side of the first main wafer surface 63 and across the intermediate insulating layer 30, which is exposed at the dicing lines 91. The thickness of the intermediate insulating layer 30 is extremely small compared to the thickness TW of the SiC wafer 62, and therefore the intermediate insulating layer 30 does not obstruct the laser light incident on the SiC wafer 62. Furthermore, the dicing lines 91 are delimited by the inclined surfaces 44 of the insulating layers 40. By delimiting the dicing lines 91 with the inclined surfaces 44 of the insulating layers 40, blockage of the laser light by the insulating layers 40 can be suppressed.

[0184] A focal point of the laser light, a laser energy, a laser pulse rate, a laser irradiation velocity, etc., are each set to arbitrary values ​​according to the number (number of levels), positions, sizes, shapes, thicknesses, etc., of the modified regions 94 to be formed. Furthermore, a modification ratio of the SiC wafer 62 is set according to the number, positions, sizes, shapes, thicknesses, etc., of the modified regions 94.

[0185] In this step, the laser light is emitted in multiple stages (four stages in this step) at different depth positions of the SiC wafer 62, at a single irradiation position on a planned cutting line 72. When the laser irradiation ends with respect to the single irradiation position, the irradiation position is moved to another position on the planned cutting line 72, and the laser light is emitted again in multiple stages. The levels (four levels in this step) of the modified regions 94 are thereby formed at intervals in the normal direction Z within the interior of the SiC wafer 62.

[0186] The modified regions 94 are each formed in the interior of the SiC wafer 62 at distances from the first main wafer surface 63 towards the side of the second main wafer surface 64.

[0187] The second main wafer surface, or the modified regions 94, are preferably formed in the SiC substrate 6. Even more preferably, the modified regions 94 are formed in the SiC substrate 6 at distances from the SiC epitaxial layer 7 towards the side of the second main wafer surface 64. Variations in the physical and electrical properties of the SiC epitaxial layer 7 due to the modified regions 94 can thus be suppressed. This means that the functional components can be suitably formed in the SiC epitaxial layer 7.

[0188] Because the second planned cutting lines 72B extend along the a-axis direction of the SiC monocrystal, the second planned cutting lines 72B have a property that they are easier to cleave than the first planned cutting lines 72A, which extend along the m-axis direction of the SiC monocrystal.

[0189] A modification ratio of the second planned cutting lines 72B can therefore be smaller than a modification ratio of the first planned cutting lines 72A. For example, if the modified regions 94 on the second planned cutting lines 72B are not formed at positions that are deep compared to the first planned cutting lines 72A, the width WD2 of the dicing roads 91 extending in the a-axis direction can be made narrower than the width WD2 of the dicing roads 91 extending in the m-axis direction.

[0190] The modified regions 94 along the second planned cutting line 72B can be formed after the modified regions 94 along the first planned cutting line 72A have been formed. The modified regions 94 along the first planned cutting line 72A can be formed after the modified regions 94 along the second planned cutting line 72B have been formed. The modified regions 94 along the first planned cutting line 72A and the modified regions 94 along the second planned cutting line 72B can be formed alternately.

[0191] Next, with reference to Fig. 10O and Fig. 11O of the SiC wafer 62 is cleaved along the planned cutting lines 72, with the modified regions 94 as the starting points. The SiC wafer 62 is cleaved together with the interlayer insulating layer 30. The interlayer insulating layer 30 has an extremely small thickness and therefore does not impede the cleavage.

[0192] The SiC wafer 62 can be cleaved by a breaking method of a shear type, a 3-point bend type, a folding type, and / or a roll-to-roll contact type. A breaking method of a 3-point bend type is shown as an example in Fig. 10O shown.

[0193] In the fracture process of a 3-point bending type, for example, two support elements 95 are used, which support the SiC wafer 62 on the side of the second wafer main surface 64, and a single blade element 96 is used, which exerts a splitting force on the SiC wafer 62, originating from the side of the first wafer main surface 63. The two support elements 95 are arranged such that they are opposite each other in plan view over a planned cutting line 72, which is to be split. The blade element 96 exerts the splitting force on the planned cutting line 72, which is to be split.

[0194] This splits the SiC wafer 62 along the planned cutting lines 72, with the first chip regions 71A becoming a plurality of SiC semiconductor devices 1, and the second chip regions 71B becoming a plurality of dummy SiC semiconductor devices 97. Furthermore, the intersections 84 of the SiC wafer 62 become the L-shaped passes 25 of the SiC semiconductor devices 1. The dicing paths 91 of the SiC wafer 62 also become the dicing paths 43 of the SiC semiconductor devices 1.

[0195] This step described an example where the splitting force was applied to the SiC wafer 62 starting from the side of the first wafer main surface 63. However, the splitting force can instead be applied to the SiC wafer 62 starting from the side of the second wafer main surface 64. In this case, the carrier tape 93 can be attached to the side of the first wafer main surface 63.

[0196] The SiC wafer 62 can be cleaved along the second planned cutting line 72B after it has been cleaved along the first planned cutting line 72A. That is, the SiC wafer 62 can be cleaved in the nearest adjacent directions after it has been cleaved in directions that intersect or cross the nearest adjacent directions. Although the SiC wafer 62 is cleaved in the directions that intersect or cross the nearest adjacent directions during the cleavage step of the first planned cutting line 72A, the load or stress applied to the SiC wafer 62 is continuously maintained, such that the formation of meanderings on cleaved sections is suppressed.

[0197] In the step of splitting the second planned cutting line 72B, the SiC wafer 62 is split along the m-axis direction, and therefore the load applied to the SiC wafer 62 becomes discontinuous. However, the formation of meander shapes at the split sections is suppressed because the load is applied along the nearest adjacent directions. In particular, the formation of meander shapes that have a connecting section of a split section along a first planned cutting line 72A and a split section along a second planned cutting line 72B as a starting point can be suppressed. The formation of meander shapes can thus also be suppressed by exploiting physical properties of the SiC wafer 62.

[0198] Next, with reference to Fig. 10P and Fig. 11P stretches ("expands") and fixes the carrier tape 93 in directions away from a center towards the circumferential edges of the SiC wafer 62. This maintains constant distances between the SiC semiconductor components 1. Distances between the SiC semiconductor components 1 and the dummy SiC semiconductor components 97 are also maintained constant. This suppresses breaks in the SiC semiconductor components 1 due to collisions during handling. The suppression of shape defects in the SiC semiconductor components 1, etc., is also effective in preventing unwanted collisions.

[0199] Fig. Figure 12 is an enlarged top view of a split section of a SiC wafer 98 according to a reference example. Structures of the SiC wafer 98 that correspond to those of the SiC wafer 62 are designated with the same reference symbols, and a description thereof is omitted.

[0200] The SiC wafer 98 contains a monitor pattern 73, which is formed in the dicing line 91 in the first wafer main area 63. Fig. In Figure 12, the monitor pattern 73 is shown by a hatching. The monitor pattern 73 is formed on the planned cutting line 72. In the SiC wafer 98, during the step of forming the modified regions 94, laser light is blocked by the monitor pattern 73.

[0201] Therefore, in a region of the SiC wafer 98 blocked by the monitor pattern 73, an unmodified section is formed in which the modified region 94 is absent. During the splitting of the SiC wafer 98, a force that maintains an atomic arrangement acts on the unmodified section directly beneath the monitor pattern 73. Specifically, the SiC monocrystal has a physical property of being strong with respect to the force that maintains the atomic arrangement, compared to a Si monocrystal, etc. A meandering shape 99 with the monitor pattern 73 as a starting point is therefore formed in the split section of the SiC wafer 98. The maximum meander width (absolute value) of the meandering shape 99 exceeds 10 µm in the top view.

[0202] Such a problem can be solved by forming the first chip region 71A, which contains the monitor pattern 73. In this case, however, the planar area of ​​the first chip region 71A increases, and consequently, the number of SiC semiconductor devices 1 that can be obtained from a single SiC wafer 62 decreases. Furthermore, as a result of the SiC semiconductor device 1 becoming larger due to the increase in the planar area of ​​the first chip region 71A, the requirement to reduce or refine the SiC semiconductor device 1 cannot be met. If a monitor pattern (auxiliary pattern) is built from a metal pattern, there is also a possibility that the electrical characteristics (properties) of the SiC semiconductor device 1 will vary due to the monitor pattern.

[0203] In contrast, on SiC wafer 62, the monitor pattern 73 is not formed in a region other than the second chip regions 71B. This means that on SiC wafer 62, the second chip regions 71B are specifically designated for the monitor pattern 73. Therefore, a monitor pattern 73 does not become a blocking object for laser light.

[0204] Alignment patterns 20 are also formed in the first main wafer face 63 in the top view at intervals from the dicing roads 91. Furthermore, the alignment patterns 20 are formed from a material other than a metal. In particular, each alignment pattern 20 has the alignment trench structure, which includes the alignment trench 26 and the insulator 27. Moreover, no other auxiliary pattern besides the alignment patterns 20 is formed in the first main wafer face 63, which is positioned within the dicing roads 91. Therefore, no auxiliary pattern becomes a blocking object with respect to laser light.

[0205] Furthermore, the first main surface electrodes 32 and the monitor main surface electrodes 88 are formed in the first wafer main surface 63 at distances from the dicing lines 91, as seen in the top view. Therefore, the first main surface electrodes 32 and the monitor main surface electrodes 88 do not form any blocking objects with respect to the laser light.

[0206] Furthermore, the modified regions 94 are formed along the planned cutting lines 72 at intervals from the alignment patterns 20. The alignment patterns 20 therefore do not impede the splitting of the SiC wafer 62. The modified regions 94 can thus be suitably formed on the planned cutting lines 72, and at the same time the splitting force can be suitably applied to the planned cutting lines 72.

[0207] Shape defects of the split sections due to the first main surface electrodes 32, the monitor main surface electrodes 88, the alignment patterns 20, and the monitor patterns 73 can therefore be suppressed, and consequently, meander shapes or serpentine shapes of the split sections of the SiC wafer 62 can be suitably suppressed. A maximum meander shape width (absolute value) of the split sections of the SiC wafer 62 can therefore be suppressed to no greater than 10 µm (in particular, to no greater than 5 µm).

[0208] Furthermore, by suppressing meander shapes of the split sections, the margin or tolerance that accommodates the meander shapes can be reduced, and consequently, the chip regions 71 can be reduced or made smaller. The chip regions 71 can also be reduced or made smaller because there is no need to form the monitor patterns 73 in the first chip regions 71A. A requirement to manufacture the SiC semiconductor device 1 compactly can therefore be met, and at the same time, the number of SiC semiconductor devices 1 that can be obtained from a single SiC wafer 62 can be increased.

[0209] Furthermore, the insulating layers 40 of the SiC wafer 62 do not need to be physically cut or separated. This allows the SiC wafer 62 to be easily cleaved, while simultaneously suppressing peeling and degradation of the insulating layers 40. Consequently, shape defects in the cleaved sections of the SiC wafer 62 caused by the insulating layers 40 can be suppressed.

[0210] Fig. Figure 13 is a top view of another SiC semiconductor component 101. Fig. 14 is an enlarged top view of an internal structure of Region XIV, which is located in Fig. 13 is shown. Fig. 15 is a sectional view along a line XV-XV, which is in Fig. Figure 14 is shown. Below, structures corresponding to those described with respect to the SiC semiconductor device 1 are designated with the same reference symbols, and a description thereof is omitted.

[0211] With reference to Fig. 13 to Fig. In section 15, the SiC semiconductor device 101 is a switching device that includes a MISFET (metal-insulator-semiconductor field-effect transistor) 102, which is formed as an example of a functional component in place of the SBD 12 in the active region 10. That is, the SiC semiconductor devices 101 are manufactured by forming the MISFETs 102 in the first chip regions 71A of the SiC wafer 62.

[0212] The SiC semiconductor component 101 includes the SiC chip 2, the first to fourth modified regions 8A to 8D (first to fourth modified sections 9A to 9D), the alignment patterns 20, the interlayer insulating layer 30, the first main surface electrode 32, the insulating layer 40, the pad electrode 49, and the second main surface electrode 51. Fig. In Figure 13, the insulating layer 40 is shown by hatching.

[0213] The SiC substrate 6 is formed as a drain region of the MISFET 102. The SiC epitaxial layer 7 is formed as a drift region of the MISFET 102. The second main surface electrode 51 is formed as a drain electrode of the MISFET 102.

[0214] In this embodiment, the SiC epitaxial layer 7 has different n-type impurity concentrations along the normal direction Z. In particular, the SiC epitaxial layer 7 includes a high-concentration region 103 with a high n-type impurity concentration and a low-concentration region 104 with a lower n-type impurity concentration than the high-concentration region 103.

[0215] The high-concentration region 103 is formed in a region on the side of the first main surface 3. The low-concentration region 104 is formed in a region on the side of the second main surface 4, relative to the high-concentration region 103. The thickness of the high-concentration region 103 is less than the thickness of the low-concentration region 104. The thickness of the high-concentration region 103 is less than half the total thickness of the SiC epitaxial layer 7.

[0216] A peak value of the n-type impurity concentration in the high-concentration region 103 cannot be less than 1.0×10 16 cm -3 and not larger than 1.0×10 18 cm -3 A peak value of the n-type impurity concentration in the low-concentration region 104 cannot be less than 1.0 × 10 15 cm -3 and not larger than 1.0×10 16 cm -3It is understood that the n-type impurity concentration of the SiC epitaxial layer 7 can have a concentration gradient with which the n-type impurity concentration gradually increases within a range of not less than 1.0 × 10 15 cm -3 and not larger than 1.0×10 18 cm -3 decreases, starting from the SiC substrate 6 towards the first main surface 3.

[0217] The SiC semiconductor device 101 incorporates a multitude of trench-gate structures 111 formed in the first main surface 3 in the active region 10. The trench-gate structures 111 are each formed as bands extending in the first direction X and spaced apart in the second direction Y. In plan view, the trench-gate structures 111 as a whole are formed as strips extending in the first direction X.

[0218] In this embodiment, the trench-gate structures 111 extend as bands from a circumferential edge section on one side (the side of the third side surface 5C) to a circumferential edge section on another side (the side of the fourth side surface 5D) of the active region 10. The trench-gate structures 111 cross an intermediate section of the active region 10 between the circumferential edge section on one side and the circumferential edge section on the other side.

[0219] The length of each trench-gate structure 111 cannot be less than 1 mm and cannot be greater than 10 mm. The length of each trench-gate structure 111 cannot be less than 1 mm and cannot be greater than 2 mm, less than 2 mm and cannot be greater than 4 mm, less than 4 mm and cannot be greater than 6 mm, less than 6 mm and cannot be greater than 8 mm, or less than 8 mm and cannot be greater than 10 mm. The length of each trench-gate structure 111 is preferably not less than 2 mm and not greater than 6 mm. The total extension per unit area of ​​a single trench-gate structure 111 cannot be less than 0.5 µm / µm 2 and not larger than 0.75 µm / µm 2 .

[0220] Each trench-gate structure 111 includes a gate trench 112, a gate insulating layer 113, and a gate electrode 114. In Fig. Figure 14 shows the gate insulating layers 113 and the gate electrodes 114 by hatching.

[0221] Each gate trench 112 is formed in the SiC epitaxial layer 7. The gate trench 112 comprises sidewalls and a bottom wall. The sidewalls, which form the long sides of the gate trench 112, are formed by the a-planes of the SiC monocrystal. The sidewalls, which form the short sides of the gate trench 112, are formed by the m-planes of the SiC monocrystal.

[0222] The side walls of the gate trench 112 can extend along the normal direction Z. Angles formed by the side walls of the gate trench 112 with respect to the first principal surface 3 within the SiC chip 2 can be no less than 90° and no greater than 95° (for example, no less than 91° and no greater than 93°). The side walls of the gate trench 112 can be formed substantially perpendicular to the first principal surface 3. The gate trench 112 can be formed in a converging shape, with an opening width that tapers or narrows from the first principal surface 3 towards the bottom wall.

[0223] The bottom wall of gate trench 112 is positioned in the high-concentration region 103. The bottom wall of gate trench 112 points towards the c-plane of the SiC monocrystal. The bottom wall of gate trench 112 has an off angle, inclined in the a-axis direction with respect to the c-plane of the SiC monocrystal. The bottom wall of gate trench 112 can be formed parallel to the first principal surface 3. The bottom wall of gate trench 112 can be formed in a shape that is curved towards the second principal surface 4.

[0224] Gate Trench 112 has a first depth D1. The first depth D1 cannot be less than 0.5 µm and cannot be greater than 3 µm. The first depth D1 cannot be less than 0.5 µm and cannot be greater than 1 µm, not less than 1 µm and cannot be greater than 1.5 µm, not less than 1.5 µm and cannot be greater than 2 µm, not less than 2 µm and cannot be greater than 2.5 µm, or not less than 2.5 µm and cannot be greater than 3 µm.

[0225] The width of the gate trench 112 along the second direction Y cannot be less than 0.1 µm and not greater than 2 µm. The width of the gate trench 112 cannot be less than 0.1 µm and not greater than 0.5 µm, less than 0.5 µm and not greater than 1 µm, less than 1 µm and not greater than 1.5 µm, or less than 1.5 µm and not greater than 2 µm.

[0226] An opening edge section of the gate trench 112 includes an inclined section that slopes downwards from the first principal surface 3 towards an inner side of the gate trench 112. The opening edge section of the gate trench 112 is a section that connects the first principal surface 3 and the side walls of the gate trench 112. The inclined section of the gate trench 112 is formed in a shape that curves towards an inner side of the SiC chip 2. The inclined section of the gate trench 112 can be formed in a shape that curves towards the inner side of the gate trench 112. The inclined section of the gate trench 112 relaxes a concentration of an electric field with respect to the opening edge section of the gate trench 112.

[0227] The gate insulating layer 113 comprises at least one of silicon dioxide, silicon nitride, aluminum oxide, zirconium oxide, and tantalum oxide. The gate insulating layer 113 can have a laminated structure in which a silicon dioxide layer and a silicon nitride layer are laminated in any sequence. The gate insulating layer 113 can have a single-layer structure consisting of either a silicon dioxide layer or a silicon nitride layer. In this embodiment, the gate insulating layer 113 has a single-layer structure consisting of a silicon dioxide layer.

[0228] The gate insulation layer 113 is formed as a film along the inner walls of each gate trench 112 and delineates a recessed space within the gate trench 112. The gate insulation layer 113 comprises a first region 115, a second region 116, and a third region 117. The first region 115 is formed along the side walls of the gate trench 112. The second region 116 is formed along the bottom wall of the gate trench 112. The third region 117 is formed along the first main surface 3.

[0229] The thickness of the first region 115 is less than the thickness of the second region 116 and less than the thickness of the third region 117. The thickness of the first region 115 cannot be less than 0.01 µm and cannot be greater than 0.2 µm. The thickness of the second region 116 cannot be less than 0.05 µm and cannot be greater than 0.5 µm. The thickness of the third region 117 cannot be less than 0.05 µm and cannot be greater than 0.5 µm.

[0230] The gate insulation layer 113 includes a bulging section 118 that projects towards the interior of the gate trench 112 at the opening edge section. The bulging section 118 is formed at a connecting section between the first region 115 and the third region 117 of the gate insulation layer 113. The bulging section 118 is formed in a shape that curves towards the inner side of the gate trench 112. The bulging section 118 narrows an opening of the gate trench 112 at the opening edge section. A gate insulation layer 113 that does not have the bulging section 118 can be formed instead. A gate insulation layer 113 that has a uniform thickness can be formed instead.

[0231] Each gate electrode 114 is embedded in the corresponding gate groove 112, specifically via the gate insulating layer 113. More precisely, the gate electrode 114 is embedded in the recessed space within the gate groove 112, which is delimited by the gate insulating layer 113. The gate electrode 114 has an electrode surface that is exposed at the opening of the gate groove 112. The electrode surface of the gate electrode 114 is curved and recessed towards the bottom wall of the gate groove 112. The electrode surface of the gate electrode 114 is narrowed by the curved section 118 of the gate insulating layer 113.

[0232] The gate electrode 114 is made of a conductive material other than a metal. The gate electrode 114 is preferably made of conductive polysilicon. In this embodiment, the gate electrode 114 comprises p-type polysilicon doped with a p-type impurity.

[0233] The p-type impurity concentration of the gate electrode 114 cannot be less than 1.0×10 18 cm -3 and not larger than 1.0×10 22 cm -3 The p-type impurity of the gate electrode 114 can contain at least one of boron, aluminum, indium, and gallium. The sheet resistance of the gate electrode 114 cannot be less than 10 Ω / □ and cannot be greater than 500 Ω / □ (approximately 200 Ω / □ in this embodiment). The thickness of the gate electrode 114 cannot be less than 0.5 µm and cannot be greater than 3 µm.

[0234] The SiC semiconductor device 101 includes a first low-resistance layer 119 that covers the gate electrodes 114. The first low-resistance layer 119 covers the gate electrodes 114 within the gate trenches 112. The first low-resistance layer 119 forms a section of each trench-gate structure 111.

[0235] The first low-resistance layer 119 comprises a conductive material having a layer resistance that is lower than the layer resistance of the gate electrodes 114. The layer resistance of the first low-resistance layer 119 cannot be less than 0.01 Ω / □ and cannot be greater than 10 Ω / □. The thickness of the first low-resistance layer 119 in the normal direction Z is preferably less than the thickness of the gate electrodes 114. The thickness of the first low-resistance layer 119 cannot be less than 0.01 µm and cannot be greater than 3 µm.

[0236] More precisely, the first low-resistance layer 119 comprises a polycide layer. The polycide layer is formed by siliciding surface areas of the gate electrodes 114 with a metallic material. That is, the electrode surfaces of the gate electrodes 114 are formed by the first low-resistance layer 119. More precisely, the polycide layer is composed of a p-type polycide layer containing a p-type impurity doped into the gate electrodes 114. The polycide layer preferably has a specific resistance of not less than 10 µΩ·cm and not greater than 110 µΩ·cm.

[0237] The layer resistance inside the gate grooves 112, in which the gate electrodes 114 and the first low-resistance layer 119 are embedded, is no greater than the layer resistance of the gate electrodes 114 alone. The layer resistance inside the gate grooves 112 is preferably no greater than the layer resistance of n-type polysilicon doped with an n-type impurity. The layer resistance inside the gate grooves 112 is approximately the layer resistance of the first low-resistance layer 119. The layer resistance inside the gate grooves 112 cannot be less than 0.01 Ω / □ and cannot be greater than 10 Ω / □. The layer resistance inside the gate grooves 112 is preferably less than 10 Ω / □.

[0238] The first low-resistance layer 119 can contain at least one of TiSi, TiSi2, NiSi, CoSi, CoSi2, MoSi2, and WSi2. Of these materials, NiSi, CoSi2, and TiSi2 are particularly suitable as the polycid layer forming the first low-resistance layer 119 because they have a comparatively low resistivity and a comparatively low temperature dependence. The first low-resistance layer 119 is preferably composed of CoSi2, which has the property of exhibiting low diffusion to other regions.

[0239] The first low-resistance layer 119 includes contact sections in contact with the gate insulating layers 113. In particular, the contact sections of the first low-resistance layer 119 contact the third regions 117 (curved sections 118) of the gate insulating layers 113. This suppresses a current path between the first low-resistance layer 119 and the SiC epitaxial layer 7. In particular, a design in which the contact sections of the first low-resistance layer 119 are connected to relatively thick corner sections of the gate insulating layers 113 is effective in reducing the risk of a current path.

[0240] By embedding p-type polysilicon, which has a work function different from that of n-type polysilicon, in the gate grooves 112, the gate threshold voltage Vth can be increased by about 1 V. However, p-type polysilicon has a sheet resistance that is several tens of times (about 20 times) higher than that of n-type polysilicon. Therefore, when p-type polysilicon is used as the material for the gate electrodes 114, energy loss increases along with an increase in parasitic resistance within the gate grooves 112 (hereinafter referred to simply as the "gate resistance").

[0241] Accordingly, in the SiC semiconductor component 101, the first low-resistance layer 119 (p-type polysilicon) is formed on the gate electrodes 114 (p-type polysilicon). This first low-resistance layer 119 reduces the layer resistance inside the gate grooves 112 while allowing an increase in the gate threshold voltage Vth.

[0242] For example, in the structure having the first low-resistance layer 119, the layer resistance can be reduced to no more than 1 / 100 compared to a structure lacking the first low-resistance layer 119. Similarly, in the structure having the first low-resistance layer 119, the layer resistance can be reduced to no more than 1 / 5 compared to the gate electrodes 114 containing n-type polysilicon.

[0243] This reduces the gate resistance, allowing current to be efficiently diffused along the trench-gate structures 111. That is, the first low-resistance layer 119 acts as a current diffusion layer, diffusing or distributing the current within the gate trenches 112. In particular, despite the fact that current transmission is required for the gate trenches 112, which have a length on the order of millimeters (not less than 1 mm), a switching delay can be effectively suppressed by the low-resistance layer 119 or low-resistance electrode layer 119.

[0244] Furthermore, in the structure featuring the first low-resistance layer 119, the p-type impurity concentration inside the SiC epitaxial layer 7 does not need to be increased to raise the gate threshold voltage Vth. The gate threshold voltage Vth can thus be appropriately increased while suppressing an increase in channel resistance.

[0245] The SiC semiconductor component 101 comprises a plurality of trench-source structures 121, each formed in regions between adjacent trench-gate structures 111. The trench-source structures 121 are spaced apart in the second direction Y, in an embodiment where a single trench-gate structure 111 is sandwiched together.

[0246] The trench-source structures 121 are each formed as a band extending in the first direction X. In a plan view, the trench-source structures 121 are collectively formed as strips extending in the first direction X.

[0247] A distance or division (“pitch”) PS in the second direction Y, between the central sections of adjacent trench-source structures 121, cannot be less than 1 µm and cannot be greater than 5 µm. The distance PS cannot be less than 1 µm and cannot be greater than 2 µm, less than 2 µm and cannot be greater than 3 µm, less than 3 µm and cannot be greater than 4 µm, or less than 4 µm and cannot be greater than 5 µm. The distance PS is preferably not less than 1.5 µm and not greater than 3 µm.

[0248] Each trench-source structure 121 includes a source trench 122, a source insulating layer 123, and a source electrode 124. In Fig.Figure 14 shows the source electrodes 124 by hatching. Each source trench 122 is formed in the SiC epitaxial layer 7. The source trench 122 includes sidewalls and a bottom wall. The sidewalls forming the long sides of the source trench 122 are formed by the a-planes of the SiC monocrystal. The sidewalls forming the short sides of the source trench 122 are formed by the m-planes of the SiC monocrystal.

[0249] The bottom walls of Source Trenches 122 are positioned in High Concentration Region 103. The bottom walls of Source Trenches 122 are positioned relative to the bottom walls of Gate Trenches 112 in regions on the side of the second main surface 4. The bottom walls of Source Trenches 122 are positioned in the normal direction Z in regions between the bottom walls of Gate Trenches 112 and Low Concentration Region 104.

[0250] The bottom walls of the source trenches 122 are arranged along the c-plane of the SiC monocrystal. The bottom walls of the source trenches 122 have an off-angle inclined in the a-axis direction with respect to the c-plane of the SiC monocrystal. The bottom walls of the source trenches 122 can be formed parallel to the first principal surface 3. The bottom walls of the source trenches 122 can each be formed in a shape curved towards the second principal surface 4.

[0251] The source trenches 122 have a second depth D2 that exceeds the first depth D1 of the gate trenches 112. Provided that the source trenches 122 are positioned in the high-concentration region 103, the DS / DG or D2 / D1 ratio of the second depth D2 with respect to the first depth D1 cannot be less than 1.5. The DS / DG or D2 / D1 ratio is preferably not less than 2.

[0252] The second depth D2 cannot be less than 0.5 µm and not greater than 10 µm. Alternatively, the second depth D2 cannot be less than 0.5 µm and not greater than 1 µm, less than 1 µm and not greater than 2 µm, less than 2 µm and not greater than 4 µm, less than 4 µm and not greater than 6 µm, less than 6 µm and not greater than 8 µm, or less than 8 µm and not greater than 10 µm. Instead, the Source Trenches 122 can be formed with the second depth D2 being essentially the same as the first depth D1.

[0253] Each source trench 122 comprises a first trench section 125 and a second trench section 126. The first trench section 125 is formed at one opening side of the source trench 122. The first trench section 125 has a first width W1 in the second direction Y. The first trench section 125 can have a converging shape, in which the first width W1 narrows or becomes narrower from the first main surface 3 towards the side of the bottom wall.

[0254] The first trench section 125 can be formed, which traverses the bottom walls of the gate trenches 112 in the normal direction Z. That is, a depth of the first trench section 125 can exceed the first depth D1 of the gate trenches 112.

[0255] The first trench section 125 is preferably formed in a region on the side of the first main surface 3 with respect to the bottom walls of the gate trenches 112. That is, the depth of the first trench section 125 is preferably less than the first depth D1 of the gate trenches 112. The depth of the first trench section 125 cannot be less than 0.1 µm and not greater than 2 µm. The depth of the first trench section 125 cannot be less than 0.1 µm and not greater than 0.5 µm, not less than 0.5 µm and not greater than 1 µm, not less than 1 µm and not greater than 1.5 µm, or not less than 1.5 µm and not greater than 2 µm.

[0256] The first width W1 of the first trench section 125 cannot be less than the width of the gate trenches 112, or it can be less than the width of the gate trenches 112. The first width W1 preferably exceeds the width of the gate trenches 112. The first width W1 cannot be less than 0.1 µm and not greater than 2 µm. The first width W1 cannot be less than 0.1 µm and not greater than 0.5 µm, not less than 0.5 µm and not greater than 1 µm, not less than 1 µm and not greater than 1.5 µm, or not less than 1.5 µm and not greater than 2 µm.

[0257] The second trench section 126 is formed on the side of the bottom wall of the source trench 122. In the normal direction Z, the second trench section 126 is formed in a region between the first trench section 125 and a bottom section of the SiC epiaxial layer 7 and traverses or runs alongside the bottom walls of the gate trenches 112. In the normal direction Z, a depth of the second trench section 126 based on the first trench section 125 preferably exceeds the first depth D1 of the gate trenches 112.

[0258] The second trench section 126 has a second width W2 that is smaller than the first width W1 in the second direction Y. Given that the second width W2 is smaller than the first width W1, the second width W2 cannot be smaller than the width of the gate trenches 112, or it can be smaller than the width of the gate trenches 112.

[0259] The second width W2 cannot be less than 0.1 pm and less than 2 µm. The second width W2 cannot be less than 0.1 µm and less than 2 µm. The second width W2 cannot be less than 0.1 µm and greater than 0.5 µm, less than 0.5 µm and less than 1 µm, less than 1 µm and less than 1.5 µm, or less than 1.5 µm and less than 2 µm. It is understood that instead, the second trench section 126 can be formed with the second width W2 being essentially equal to the first width W1.

[0260] The total opening width of the source trench 122 is preferably designed such that it is approximately equal to the opening width of the gate trenches 112. The fact that the opening width of the source trench 122 is approximately the same as the opening width of the gate trenches 112 refers to the fact that the opening width of the source trench 122 falls within a range of ±20% of the opening width of the gate trenches 112, or within a range of ±20% of the opening width of the gate trenches 112.

[0261] The side walls of the second trench section 126 can extend along the normal direction Z. Angles formed by the side walls of the second trench section 126 with respect to the first principal surface 3 within the SiC chip 2 can be no less than 90° and no greater than 95° (for example, no less than 91° and no greater than 93°). The side walls of the second trench section 126 can be formed substantially perpendicular to the first principal surface 3. The second trench section 126 can be formed in a converging shape, where the second width W2 narrows from the first trench section 125 towards the side of the bottom wall.

[0262] Each source insulating layer 123 comprises at least one of silicon dioxide, silicon nitride, aluminum oxide, zirconium oxide, or tantalum oxide. The source insulating layer 123 can have a laminated structure in which a silicon dioxide layer and a silicon nitride layer are laminated in any sequence. The source insulating layer 123 can have a single-layer structure composed of either a silicon dioxide layer or a silicon nitride layer. In this embodiment, the source insulating layer 123 has a single-layer structure composed of a silicon dioxide layer.

[0263] The source insulating layer 123 is formed as a film along the inner walls of the corresponding source trench 122 and delineates a recess within the source trench 122. More precisely, the source insulating layer 123 is formed as a film along the inner walls of the source trench 122 in such a way as to expose the first trench section 125 and to cover the second trench section 126.

[0264] The source insulation layer 123 thus delineates the excavation space within the second trench section 126 of the source trench 122. The source insulation layer 123 also has a side wall window section 127, which exposes the first trench section 125 of the source trench 122.

[0265] The source insulating layer 123 comprises a first region 128 and a second region 129. The first region 128 is formed along the side walls of the source trench 122. The second region 129 is formed along the bottom wall of the source trench 122. The thickness of the first region 128 is less than the thickness of the second region 129. The thickness of the first region 128 cannot be less than 0.01 µm and cannot be greater than 0.2 µm. The thickness of the second region 129 cannot be less than 0.05 µm and cannot be greater than 0.5 µm.

[0266] The thickness of the first region 128 can be essentially equal to the thickness of the first region 128 of the gate insulating layers 113. The thickness of the second region 129 can be essentially equal to the thickness of the second region 129 or 116 of the gate insulating layers 113. The source insulating layers 123, each having a uniform thickness, can be formed instead.

[0267] Each source electrode 124 is embedded in the corresponding source trench 122, via the source insulating layer 123. More precisely, the source electrode 124 is embedded in the first trench section 125 and the second trench section 126 of the source trench 122, via the source insulating layer 123.

[0268] The source electrode 124 is embedded in the recess space delimited by the second trench section 126, on the side of the bottom wall of the source trench 122. The source electrode 124 has a side wall contact section 130 that is in contact with side walls of the first trench section 125, which are exposed on the opening side of the source trench 122 at the side wall window section 127.

[0269] The source electrode 124 has an electrode surface that is exposed at the opening of the source trench 122. The electrode surface of the source electrode 124 is formed in a curved shape that is recessed or set back towards the bottom wall of the source trench 122. The electrode surface of the source electrode 124 can be formed parallel to the first main surface 3.

[0270] The thickness of the source electrode 124 in the normal direction Z cannot be less than 0.5 µm and not greater than 10 µm. The thickness of the source electrode 124 cannot be less than 0.5 µm and not greater than 1 µm, less than 1 µm and not greater than 2 µm, less than 2 µm and not greater than 4 µm, less than 4 µm and not greater than 6 µm, less than 6 µm and not greater than 8 µm, or less than 8 µm and not greater than 10 µm.

[0271] The source electrode 124 is made of a conductive material other than a metal. The source electrode 124 is preferably made of conductive polysilicon. In this embodiment, the source electrode 124 comprises p-type polysilicon doped with a p-type impurity.

[0272] The p-type impurity concentration of the source electrode 124 cannot be less than 1×10 13 cm -3 and not larger than 1×10 22 cm -3 The p-type impurity concentration of the source electrode 124 is preferably equal to the p-type impurity concentration of the gate electrode 114. The p-type impurity of the source electrode 124 may contain at least one of boron, aluminum, indium, and gallium.

[0273] The SiC semiconductor device 101 comprises second low-resistance layers 131, each covering a source electrode 124. Each second low-resistance layer 131 covers the source electrode 124 within the respective source trench 122. The second low-resistance layer 131 forms a section of the corresponding trench-source structure 121. The second low-resistance layers 131 have the same structure as the first low-resistance layers 119. The description relating to the first low-resistance layers 119 can be applied to the description relating to the second low-resistance layers 131.

[0274] The SiC semiconductor device 101 includes a p-type body region 141, which is formed in a surface layer section of the first principal surface 3 in the active region 10. The body region 141 defines the active region 10. The p-type impurity concentration of the body region 141 is lower than the p-type impurity concentration of the gate electrodes 114. The p-type impurity concentration of the body region 141 is lower than the p-type impurity concentration of the source electrodes 124. A peak value of the p-type impurity concentration of the body region 141 cannot be less than 1.0 × 10⁻⁶. 17 cm -3 and not larger than 1.0×10 19 cm -3 .

[0275] In the surface layer section of the first main surface 3, body region 141 covers the side walls of the gate trenches 112 and the side walls of the source trenches 122. Body region 141 is formed in a region on the side of the first main surface 3 with respect to the bottom walls of the gate trenches 112. Body region 141 lies opposite the gate electrodes 114 via the gate insulating layers 113.

[0276] Body region 141 is furthermore formed in relation to the second trench sections 126 of the source trenches 122 in regions on the side of the first trench section 125. Body region 141 covers the first trench sections 125 of the source trenches 122.

[0277] Body region 141 is connected to the sidewall contact sections 130 of the source electrodes 124, which are exposed at the first trench sections 125 of the source trenches 122. Body region 141 is thus source-grounded within the SiC chip 2. Body region 141 can cover sections of the second trench sections 126. In this case, body region 141 can be located opposite the source electrodes 124 via sections of the source insulating layers 123.

[0278] The SiC semiconductor component 101 includes source regions 142 of n +-type, which are formed in surface layer sections of body region 141. The source regions 142 are formed along the gate trenches 112. A peak value of an n-type contaminant concentration of the source regions 142 exceeds the peak value of the n-type contaminant concentration of the high concentration region 103. The peak value of the n-type contaminant concentration of the source regions 142 cannot be less than 1.0 × 10 18 cm -3 and not larger than 1.0×10 21 cm -3 .

[0279] In the surface layer sections of body region 141, the source regions 142 cover the side walls of the gate grooves 112 and the side walls of the source grooves 122. The source regions 142 are located opposite the gate electrodes 114 via the gate insulating layers 113. The source regions 142 are preferably located opposite the first low-resistance layers 119 via the gate insulating layers 113.

[0280] The source regions 142 are further formed in regions on the side of the first trench sections 125 with respect to the second trench sections 126 of the source trenches 122. The source regions 142 cover the first trench sections 125 of the source trenches 122. The source regions 142 are connected to the sidewall contact sections 130 of the source electrodes 124, which are exposed at the first trench sections 125 of the source trenches 122. The source regions 142 are thus source-grounded within the SiC chip 2.

[0281] Sections of the source regions 142, oriented along the side walls of the gate grooves 112, define the channels of the MISFET 102, together with the high concentration region 103 within the body region 141. Switching the channels on and off (“ON / OFF”) is controlled by the gate electrodes 114.

[0282] The SiC semiconductor component 101 includes a multitude of contact regions 143 from p +-type, which are formed in surface layer sections of the first main surface 3 in the active region 10. A peak value of a p-type contamination concentration from each contact region 143 exceeds the peak value of the p-type contamination concentration of body region 141. The peak value of the p-type contamination concentration from each contact region 143 cannot be less than 1.0 × 10 18 cm -3 and not larger than 1.0×10 21 cm -3 .

[0283] The contact regions 143 are each formed in regions along the source trenches 122. More precisely, a multitude of contact regions 143 are formed in a some-to-one correspondence with respect to a corresponding single source trench 122. The contact regions 143 are each formed at intervals along the corresponding single source trench 122. The contact regions 143 are each formed at intervals from the gate trenches 112.

[0284] Each contact region 143 covers the first trench section 125 of the corresponding source trench 122. Each contact region 143 is located between the side-wall contact section 130 of the source electrode 124 and the source regions 142 at the first trench section 125 of the corresponding source trench 122. Furthermore, each contact region 143 is located between the side-wall contact section 130 of the source electrode 124 and the body region 141 at the first trench section 125 of the corresponding source trench 122.

[0285] Each contact region 143 is thereby electrically connected to the source electrode 124, the body region 141 and the source regions 142. Furthermore, each contact region 143 is source-grounded within the SiC chip 2.

[0286] Sections of each contact region 143 covering the first trench section 125 are led out towards the gate trenches 112. The sections of each contact region 143 covering the first trench section 125 of the source trench 122 are formed in relation to a soil section of body region 141 in regions on the side of the first main surface 3. The sections of each contact region 143 covering the first trench section 125 may extend to intermediate regions between the gate trenches 112 and the source trench 122.

[0287] Each contact region 143 further covers the second trench section 126 of the corresponding source trench 122. At the second trench section 126 of the corresponding source trench 122, each contact region 143 of the source electrode 124 lies opposite the source insulating layer 123.

[0288] Each contact region 143 further covers the bottom wall of the corresponding source trench 122. Each contact region 143 lies opposite the source electrode 124 via the bottom wall of the corresponding source trench 122. A bottom section of each contact region 143 can be formed parallel to the bottom wall of the corresponding source trench 122.

[0289] The SiC semiconductor device 101 includes a multitude of p-type deep-well regions 144 formed in surface layer sections of the first main surface 3 in the active region 10. A peak p-type impurity concentration from each deep-well region 144 is lower than the peak p-type impurity concentration of the contact regions 143.

[0290] The peak p-type impurity concentration of each deep-well region 144 cannot be less than the peak p-type impurity concentration of body region 141, or less than the peak p-type impurity concentration of body region 141. The peak p-type impurity concentration of each deep-well region 144 cannot be less than 1.0 × 10 17 cm -3 and not larger than 1.0×10 19 cm -3 .

[0291] The deep basin regions 144 are formed in a one-to-one correspondence to the source trenches 122. Each deep basin region 144 is formed as a band extending along the corresponding source trench 122 in plan view.

[0292] Each deep basin region 144 is formed within the high concentration region 103. Each deep basin region 144 is formed in relation to body region 141 in a region on the side of the second main surface 4. Each deep basin region 144 transitions continuously into body region 141.

[0293] Each deep basin region 144 includes a section that covers the second trench section 126 of the corresponding source trench 122. Each deep basin region 144 includes sections that cover the second trench section 126 of the corresponding source trench 122 across the contact regions 143.

[0294] Each deep basin region 144 further includes a section that covers the bottom wall of the corresponding source trench 122. Each deep basin region 144 includes sections that cover the bottom wall of the corresponding source trench 122 across the contact regions 143.

[0295] Each deep basin region 144 has a bottom section positioned on the side of the second main surface 4 with respect to the bottom walls of the gate trenches 112. The bottom section of each deep basin region 144 can be formed parallel to the bottom wall of each source trench 122. The deep basin regions 144 are preferably formed such that they have a constant depth.

[0296] Each deep basin region 144 forms a pn transition zone with the high concentration region 103. Depletion layers extend from the pn transition zones towards the gate trenches 112. The depletion layers may overlap with the bottom walls of the gate trenches 112.

[0297] In a SiC semiconductor device 101, which contains only a pn junction diode, the problem of electric field concentration inside the SiC chip 2 does not frequently occur due to the structure, which does not include trenches. The respective deep-well regions 144 cause the MISFET 102 of the trench-gate type to approximate the structure of a pn junction diode.

[0298] The electric field within the SiC chip 2 can thereby be relaxed in the trench-gate type MISFET 102. Furthermore, the concentration of an electric field relative to the gate trenches 112 can be suitably relaxed by means of the depletion layers in the deep-well regions 144, whose bottom sections are arranged on the side of the second main surface 4 with respect to the bottom walls of the gate trenches 112. Narrowing the distance PS between adjacent source trenches 122 (deep-well regions 144) is effective in relaxing the concentration of the electric field and improving the withstand voltage.

[0299] The deep-well regions 144 are preferably formed such that they have a constant depth. The respective deep-well regions 144 prevent the withstand voltage (for example, electrostatic breakdown strength) of the SiC chip 2 from being restricted, and therefore an improvement in the withstand voltage can be suitably achieved.

[0300] By using the source trenches 122, the deep-well regions 144 can be suitably formed in comparatively deep regions of the SiC chip 2. The deep-well regions 144 can also be formed along the source trenches 122, and therefore the occurrence of a variation in the depth of the deep-well regions 144 can be suitably suppressed.

[0301] In this embodiment, sections of the high-concentration region 103 are also arranged in regions between adjacent deep-well regions 144. This allows a JFET (junction field effect transistor) resistance to be reduced in the regions between adjacent deep-well regions 144.

[0302] Furthermore, in this embodiment, the bottom sections of the respective deep-well regions 144 are positioned in the high-concentration region 103. This allows current paths to be formed in lateral directions parallel to the first main surface 3 in regions of the high-concentration region 103 directly below the respective deep-well regions 144. Consequently, current spreading resistance can be reduced. The low-concentration region 104 increases the withstand voltage of the SiC chip 2 in such a structure.

[0303] In this embodiment, the intermediate insulating layer 30 covers the source regions 142 and the contact regions 143 in the active region 10. More precisely, the intermediate insulating layer 30 covers entire areas of the source regions 142 and entire areas of the contact regions 143 in the active region 10, as seen in a sectional view along the second direction Y. Furthermore, the intermediate insulating layer 30 covers entire areas of the source regions 142 and entire areas of the contact regions 143 in a top view.

[0304] More precisely, in the active region 10, the interlayer insulating layer 30 crosses the first trench sections 125 of the source trenches 122 and covers the source electrodes 124. On the first main surface 3, the interlayer insulating layer 30 covers the sidewall contact sections 130 of the source electrodes 124.

[0305] The intermediate insulating layer 30 contains source holes 151. The source holes 151 expose the source electrodes 124 in the active region 10. The source holes 151 can be formed as bands extending along the trench-source structures 121. More precisely, the source holes 151 are formed within regions that, in plan view, are surrounded by the side walls of the source trenches 122 (first trench sections 125).

[0306] The source holes 151 expose the source electrodes 124 at intervals extending from the side walls of the source trenches 122 (first trench sections 125) towards the inner sides of the source trenches 122. The source holes 151 expose only the source electrodes 124. An opening edge section of each source hole 151 is formed in a shape that curves towards the interior of the source hole 151.

[0307] In the electrode surfaces of the source electrodes 124, recesses 152 are formed, which are cut out or set back towards the bottom walls of the source trenches 122. The recesses 152 can be formed as bands extending along the trench-source structures 121. The recesses 152 are formed inside the regions surrounded by the side walls of the source trenches 122 (first trench sections 125), as seen from above.

[0308] The recesses 152 are formed at intervals extending from the side walls of the source trenches 122 (first trench sections 125) towards the inner sides of the source trenches 122. The recesses 152 expose the second low-resistance layers 131. The recesses 152 can penetrate or enter the second low-resistance layers 131. The source holes 151 communicate with the recesses 152 of the source electrodes 124.

[0309] In this embodiment, the first main surface electrode 32 has a laminated structure comprising a barrier layer 153 and a main body layer 154, which are laminated in this order starting from the side of the SiC chip 2.

[0310] The barrier layer 153 preferably comprises at least one Ti layer and one TiN layer. The barrier layer 153 preferably has a laminated structure comprising a Ti layer and a TiN layer laminated in that order, starting from the side of the SiC chip 2. Alternatively, the barrier layer 153 can have a single-layer structure consisting of either a Ti layer or a TiN layer.

[0311] The thickness of barrier layer 153 cannot be less than 0.01 µm and not greater than 6 µm. The thickness of barrier layer 153 cannot be less than 0.01 µm and not greater than 0.1 µm, less than 0.1 µm and not greater than 2 µm, less than 2 µm and not greater than 4 µm, or less than 4 µm and not greater than 6 µm.

[0312] The main body layer 154 has a resistance value that is lower than the resistance value of the barrier layer 153. The main body layer 154 includes at least one of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer.

[0313] The thickness of the main body layer 154 exceeds the thickness of the barrier layer 153. The thickness of the main body layer 154 cannot be less than 0.05 µm and cannot be greater than 10 µm. The thickness of the main body layer 154 cannot be less than 0.05 µm and cannot be greater than 0.1 µm, less than 0.1 µm and cannot be greater than 1 µm, less than 1 µm and cannot be greater than 2 µm, less than 2 µm and cannot be greater than 4 µm, less than 4 µm and cannot be greater than 6 µm, less than 6 µm and cannot be greater than 8 µm, or less than 8 µm and cannot be greater than 10 µm.

[0314] The first main surface electrode 32 includes a gate main surface electrode 155 and a source main surface electrode 156. A gate voltage is applied to the gate main surface electrode 155. The gate voltage cannot be less than 10 V and cannot be greater than 50 V (for example, approximately 30 V). A source voltage is applied to the source main surface electrode 156. The source voltage can be a reference voltage (for example, a ground voltage).

[0315] The main gate surface electrode 155 is formed in the active region 10. The main gate surface electrode 155 includes a gate pad 157 and a gate finger or arm 158. The gate pad 157 is formed in a region on the side of the first side surface 5A, as seen from the top view.

[0316] More precisely, the Gate-Pad 157 is formed along a region along a central section of the first side face 5A, as seen from the top view. The Gate-Pad 157 can be formed in a region along a corner section connecting any two of the side faces 5A to 5D, as seen from the top view. The Gate-Pad 157 can be formed into a four-sided shape as seen from the top view.

[0317] The gate finger 158 extends from the gate pad 157 and stretches as a band along the circumferential edges of the active region 10. In this embodiment, the gate finger 158 extends along the first side surface 5A, the third side surface 5C and the fourth side surface 5D and delimits an inner side of the active region 10 from three directions.

[0318] The gate finger 158 is electrically connected to the gate electrodes 114 via the intermediate insulating layer 30. An electrical signal from the gate pad 157 is transmitted to the gate electrodes 114 via the gate finger 158.

[0319] The source main surface electrode 156 is formed in the active region 10 at intervals from the gate main surface electrode 155. In plan view, the source main surface electrode 156 is formed in a C-shape such that it covers a region of a C-shape that is delimited by the gate main surface electrode 155.

[0320] The source main surface electrode 156 is electrically connected to the source electrodes 124 via the source holes 151. That is, in this embodiment, the source main surface electrode 156, which is made of a metallic material, is electrically connected to the source electrodes 124, which are made of conductive polysilicon.

[0321] In this embodiment, the insulating layer 40 selectively covers the gate main surface electrode 155 and the source main surface electrode 156. The pad opening 41 of the insulating layer 40 includes a gate pad opening 159 and a source pad opening 160. The gate pad opening 159 and the source pad opening 160 are each formed by the first opening 47 of the passivation layer 45 and the second opening 48 of the resin layer 46.

[0322] The gate pad opening 159 exposes the gate pad 157 of the main gate surface electrode 155. The plane shape of the gate pad opening 159 is arbitrary. The source pad opening 160 exposes the main source surface electrode 156. The plane shape of the source pad opening 160 is arbitrary.

[0323] In this embodiment, the pad electrode 49 comprises a gate pad electrode 161 and a source pad electrode 162. The gate pad electrode 161 is formed within the gate pad opening 159 on the main gate surface electrode 155. The gate pad electrode 161 is electrically connected to the main gate surface electrode 155. The gate pad electrode 161 has a gate terminal surface 163, which is externally connected to a connecting wire.

[0324] The gate terminal surface 163 is positioned on the side of the gate main surface electrode 155 with respect to the main surface of the insulating layer 40 (resin layer 46). The gate terminal surface 163 may project higher than the main surface of the insulating layer 40 (resin layer 46). The gate terminal surface 163 may have an overlapping section that covers the main surface of the insulating layer 40 (resin layer 46).

[0325] The source pad electrode 162 is formed within the source pad opening 160 on the source main surface electrode 156. The source pad electrode 162 is electrically connected to the source main surface electrode 156. The source pad electrode 162 has a source terminal surface 164 which is externally connected to a connecting wire.

[0326] The source-terminal surface 164 is positioned on the side of the source main surface electrode 156 with respect to the main surface of the insulating layer 40 (resin layer 46). The source-terminal surface 164 may project higher than the main surface of the insulating layer 40 (resin layer 46). The source-terminal surface 164 may have an overlapping section that covers the main surface of the insulating layer 40 (resin layer 46).

[0327] Even in a case where the SiC semiconductor component 101 is manufactured, incorporating the MISFET 102 instead of the SBD 12, the same effects as with the SiC semiconductor component 1 can be demonstrated. Although not explicitly stated in the description of the SiC semiconductor component 101, the same arrangements can be applied with regard to the thickness and the inclination angles θ1 and θ2 of the insulating layer 40, the width WD of the dicing tracks 43, the structure of the pad electrode 49, etc., as in the first preferred embodiment.

[0328] The present invention can be implemented in other embodiments.

[0329] In each of the preferred embodiments described above, an example has been described in which the insulating layer 40 has the laminated structure comprising the passivation layer 45 and the resin layer 46. However, the insulating layer 40 may instead have a single-layer structure composed of either the passivation layer 45 or the resin layer 46.

[0330] In the first preferred embodiment described above, an example was described in which the diode regions 13 are of the n-type. However, instead of the n-type diode regions 13, p-type diode regions 13 can be used. In this case, a diode with a pn junction can be provided instead of the SBD 12.

[0331] In the second preferred embodiment described above, an example was described in which the first low-resistance layers 119 and the second low-resistance layers 131 are formed. However, a structure can be used instead in which the first low-resistance layers 119 and / or the second low-resistance layers 131 are not formed.

[0332] In the second preferred embodiment described above, an example was described in which the gate electrodes 114 are formed containing p-type polysilicon doped with a p-type impurity. However, if an increase in the gate threshold voltage Vth is not a primary concern, the gate electrodes 114 can contain n-type polysilicon doped with an n-type impurity instead of p-type polysilicon.

[0333] In this case, the first low-resistance layer 119 can be formed by silicification of sections of the gate electrodes 114 (n-type polysilicon) using a metallic material, forming planar layer sections. That is, the first low-resistance layer 119 can contain an n-type polysilicon. With such a structure, the gate resistance can be reduced. It is understood that the first low-resistance layer 119 does not have to be formed.

[0334] In the second preferred embodiment described above, an example was described in which the source electrodes 124 are formed containing p-type polysilicon doped with a p-type impurity. However, instead of the p-type polysilicon, n-type polysilicon doped with an n-type impurity may be used.

[0335] In this case, the second low-resistance layers 131 can be formed by silicification of sections of the source electrodes 124 (n-type polysilicon) using a metallic material, forming surface layer sections. That is, the second low-resistance layers 131 can contain an n-type polysilicon. It is understood that the formation of the second low-resistance layers 131 is not mandatory.

[0336] In the second preferred embodiment described above, an example was described in which the MISFET 102 was formed. Instead of the drain region of n + However, the -type can be a collector region of p +-type can be applied. In this structure, an IGBT (Bipolar Transistor with Insulated Gate) can be provided instead of the MISFET 102. In this case, in each of the preferred embodiments described above, the "source" of the MISFET 102 is replaced by an "emitter" of the IGBT, and the "drain" of the MISFET 102 is replaced by a "collector" of the IGBT.

[0337] In each of the preferred embodiments described above, a structure can be used in which the conductivity types of the respective semiconductor sections are inverted. That is, a p-type section can be made into an n-type, and an n-type section can be made into a p-type.

[0338] In each of the preferred embodiments described above, an example was given in which the first direction X is the m-axis direction of the SiC monocrystal and in which the second direction Y is the a-axis direction of the SiC monocrystal. However, an embodiment can be used instead in which the first direction X is the a-axis direction of the SiC monocrystal and in which the second direction Y is the m-axis direction of the SiC monocrystal.

[0339] In each of the preferred embodiments described above, the width WD of the dicing lines 43 was set to not less than 5% and not greater than 25% of the thickness TC of the SiC chip 2 in order to suppress interference of laser light through the insulating layer 40 (resin layer 46). That is to say, the width WD2 of the dicing lines 91 was set to not less than 10% and not greater than 50% of the final thickness TW of the SiC wafer 62.

[0340] However, the width WD of the dicing lines 43 (width WD2 of the dicing lines 91) can be adjusted so that the laser light is emitted onto the SiC wafer 62 (SiC chip 2) via the insulating layer 40.

[0341] In this case, the width WD of the dicing lines 43 (width WD2 of the dicing lines 91) can be further reduced. For example, the maximum meander width (absolute value) of the split sections of the SiC wafer 62 is not greater than 10 µm (specifically, not greater than 5 µm), and therefore the width WD2 of the dicing lines 91 can be set to not less than 5 µm and not greater than 20 µm. That is, the width WD of the dicing lines 43 can be set to not less than 2.5 µm and not greater than 10 µm.

[0342] The chip regions 71, which occupy the SiC wafer 62, can thereby be enlarged, and therefore the number of obtained SiC semiconductor devices 1 that can be obtained from a single SiC wafer 62 can be increased.

[0343] In this case, however, the distance between adjacent first main surface electrodes 32 and adjacent chip regions 71 must be set to no less than 40% of the thickness TC of the SiC chip 2 (final thickness TW of the SiC wafer 62). That is, distances from the circumferential edges of the first main surface electrodes 32 to the side surfaces 5A to 5D must be set to no less than 20% of the thickness TC of the SiC chip 2 (final thickness TW of the SiC wafer 62).

[0344] A field plate (field electrode), an equipotential electrode, or another voltage-resistant structure, such as a metal layer, distinct from the first main surface electrode 32, may be formed at a section further towards an outer side than the first main surface electrode 32. In this case, the formation step of the metal layer of the field plate, the equipotential electrode, etc., in a region at an outer side of the first main surface electrode 32 in each chip region 71 should be performed during the formation step of the first main surface electrode 32, or before or after the formation step of the first main surface electrode 32.

[0345] In this case, the distance between adjacent metal layers of adjacent chip regions 71 must be set to no less than 40% of the thickness TC of the SiC chip 2 (final thickness TW of the SiC wafer 62). That is, the distances from the circumferential edges of the metal layers to the side faces 5A to 5D must be set to no less than 20% of the thickness TC of the SiC chip 2 (final thickness TW of the SiC wafer 62).

[0346] In this case, the insulating layer 40 preferably has a flat main surface. If a field plate, an equipotential electrode, or another voltage-resistant structure is formed at a section further towards an outer side than the first main surface electrode 32, a non-planar or uneven structure, which is a reflection of the intermediate insulating layer 30, the field plate, etc., is formed on the main surface of the insulating layer 40, and it is therefore likely to be difficult to focus the laser light to a desired position with good precision. Such a problem can be suppressed by flattening or forming the main surface of the insulating layer 40 flat.

[0347] Examples of features that can be derived or extracted from this description and the figures are given below.

[0348] [A1] Method for fabricating a SiC semiconductor device comprising a SiC semiconductor layer, a main area electrode formed on the SiC semiconductor layer, and an insulating layer partially covering the main area electrode on the SiC semiconductor layer, wherein the method for fabricating the SiC semiconductor device comprises: a step of providing a SiC wafer having a main area, a step of delineating, on the main area of ​​the SiC wafer, a plurality of chip regions comprising a main chip region and a dummy chip region, a step of forming the main area electrode in each chip region, a step of forming the insulating layer partially covering the respective main area electrodes and exposing outer circumferential areas of the respective chip regions as a dicing line, a step of emitting laser light along the dicing line and forming a modified region,which is oriented along the dicing line, namely into an interior of the SiC wafer, and a step of applying an external force to the SiC wafer and splitting the SiC wafer, with the modified region as a starting point, and wherein the main surface electrodes are formed in regions that avoid the dicing line.

[0349] According to this method for fabricating the SiC semiconductor device, interference from laser light due to the main surface electrodes can be suppressed. The modified region can thus be suitablely formed in a desired region within the SiC wafer. Consequently, the SiC wafer can be appropriately cleaved.

[0350] [A2] Method for manufacturing the SiC semiconductor component according to A1, further comprising a test step of evaluating in the dummy chip region the suitability of the respective steps carried out in the respective chip regions.

[0351] [A3] Method for producing the SiC semiconductor device according to A1 or A2, wherein in the step of forming the insulating layer the dicing road or line is exposed in which a metal pattern is not present.

[0352] [A4] Method for manufacturing the SiC semiconductor device according to any one of A1 to A3, wherein the step of delimiting the chip regions includes a step of delimiting the chip regions into a four-sided shape, each having an alignment pattern at four corners in a top view.

[0353] [A5] Method for manufacturing the SiC semiconductor device according to A4, wherein the alignment pattern is arranged such that it avoids a position of the dicing line onto which the laser light is emitted.

[0354] [A6] Method for producing the SiC semiconductor device according to A4 or A5, wherein the alignment pattern is formed by removing the main surface of the SiC wafer by means of an etching process.

[0355] [B1] A method for manufacturing a SiC semiconductor device comprising a SiC semiconductor layer, a main area electrode formed on the SiC semiconductor layer, and an insulating layer partially covering the main area electrode on the SiC semiconductor layer, wherein the method for manufacturing the SiC semiconductor device comprises: a step of providing a SiC wafer having a main area, a step of delineating, on the main area of ​​the SiC wafer, a plurality of chip regions comprising a main chip region and a dummy chip region, a step of forming the main area electrode in each chip region, and a step of forming the insulating layer such that it partially covers the respective main area electrodes and exposes outer circumferential areas of the respective chip regions as a dicing line.a step of emitting laser light along the dicing line and forming a modified region oriented along the dicing line within the interior of the SiC wafer, and a step of applying an external force to the SiC wafer and splitting the SiC wafer with the modified region as a starting point, wherein the step of forming the insulating layer includes a step of forming the insulating layer such that a circumferential edge of the insulating layer becomes an inclined surface.

[0356] According to this method for fabricating the SiC semiconductor device, interference from laser light due to the main surface electrodes can be suppressed. The modified region can thus be suitablely formed in a desired area of ​​the SiC wafer. Consequently, the SiC wafer can be appropriately cleaved.

[0357] [B2] Method for manufacturing the SiC semiconductor device according to B1, wherein the inclination angle of the inclined surface of the insulating layer with respect to the main surface of the SiC wafer is not less than 30° and not greater than 60°.

[0358] [B3] Method for manufacturing the SiC semiconductor device according to B1 or B2, wherein the inclination angle of the inclined surface of the insulating layer with respect to the main surface of the SiC wafer is not less than 40° and not greater than 50°.

[0359] [B4] Method for manufacturing the SiC semiconductor device according to any one of B1 to B3, wherein the inclined surface of the insulating layer is formed in a curved shape which is excluding towards the main surface of the SiC wafer.

[0360] [B5] Method for manufacturing the SiC semiconductor device according to any one of B1 to B4, wherein the dicing line is formed with a width of not less than 20% of the thickness of the SiC wafer.

[0361] [B6] Method for producing the SiC semiconductor device according to any one of B1 to B5, further comprising a step of forming a pad electrode which overlaps the inclined surface of the insulating layer on the main surface electrode.

[0362] [B7] Method for manufacturing the SiC semiconductor device according to one of B1 to B6, wherein the SiC wafer is provided with a thickness of not more than 200 µm. The thickness of the SiC wafer is to be understood as the thickness in or during the step of splitting the SiC wafer.

[0363] [C1] In a method for fabricating a SiC semiconductor device comprising a SiC semiconductor layer, a main area electrode formed on the SiC semiconductor layer, and an insulating layer partially covering the main area electrode on the SiC semiconductor layer, the method for fabricating the SiC semiconductor device includes: a step of providing a SiC wafer having a main area; a step of delineating, on the main area of ​​the SiC wafer, a plurality of chip regions comprising a main chip region and a dummy chip region; a step of forming the main area electrode in each chip region; a step of forming the insulating layer partially covering the respective main area electrodes and exposing the outer periphery of the respective chip regions as a dicing line; a step of emitting laser light along the dicing line and forming a modified region.which is oriented along the dicing line, namely in an interior of the SiC wafer, and a step of applying an external force to the SiC wafer and splitting the SiC wafer, with the modified region as a starting point, and wherein the step of forming the modified region includes a step of emitting laser light onto an interior of the SiC wafer via the insulating layer.

[0364] [C2] Method for producing the SiC semiconductor component according to C1, wherein the dicing line is formed with a width of not less than 5 µm and not greater than 20 µm.

[0365] [C3] Method for manufacturing the SiC semiconductor component according to C1 or C2, wherein the distance between adjacent main surface electrodes of adjacent chip regions is not less than 40% of the thickness of the SiC wafer.

[0366] [C4] Method for manufacturing the SiC semiconductor device according to any one of C1 to C3, further comprising a step of forming a metal layer on an outer side of the main surface electrode in each of the chip regions, wherein a distance between a plurality of mutually adjacent metal layers of or from mutually adjacent chip regions is not less than 40% of the thickness of the SiC wafer.

[0367] [C5] Method for fabricating the SiC semiconductor device according to any one of C1 to C4, wherein the SiC wafer is provided with a thickness of not more than 200 µm. The thickness of the SiC wafer is to be understood as the thickness in the step of splitting the SiC wafer.

[0368] [D1] Method for fabricating a SiC semiconductor device, comprising: a step of preparing or providing a SiC wafer having a main surface and composed of a SiC monocrystal; a step of setting or setting, on the main surface, a planned cutting line delineating a plurality of chip regions, which include a first chip region in which a functional device is formed, and which include a second chip region in which a monitor pattern for performing process control for the first chip region is formed; a step of forming on the main surface a plurality of main surface electrodes, each covering the chip regions such that the planned cutting line is exposed, and each forming a section of the functional device orforming a section of the monitor pattern; a step of emitting laser light onto the planned cutting line exposed opposite the main surface electrodes, and forming a modified region that is modified to have a property different from that of the SiC monocrystal; and a step of splitting or separating the SiC wafer, with the modified region as a starting point.

[0369] [D2] Method for fabricating the SiC semiconductor device according to D1, further comprising: a step of forming on the main surface a plurality of insulating layers, each partially covering the main surface electrodes and defining a dicing road that exposes the planned cutting line in a region between those chip regions that are adjacent to each other, prior to the step of forming the modified region; and wherein the laser light is emitted onto the planned cutting line exposed at the dicing road.

[0370] [D3] Method for manufacturing the SiC semiconductor device according to D2, wherein the insulating layers are each formed such that they have an inclined surface that delimits the dicing road.

[0371] [D4] Method for manufacturing the SiC semiconductor component according to D3, wherein the insulating layers each have the inclined surface which is recessed or set back in a curved shape.

[0372] [D5] Method for manufacturing the SiC semiconductor device according to any one of D2 to D4, wherein the dicing line has a width of not less than 10% and not more than 50% of the thickness of the SiC wafer.

[0373] [D6] Method for manufacturing the SiC semiconductor component according to any one of D2 to D5, wherein the insulating layers each include a resin layer.

[0374] [D7] Method for manufacturing the SiC semiconductor device according to any one of D1 to D6, wherein the step of setting or setting the planned cutting line includes a step of forming, in the main area, a plurality of orientation patterns that define the planned cutting line.

[0375] [D8] Method for manufacturing the SiC semiconductor device according to D7, wherein the planned cutting line is defined in a region between the alignment patterns that are adjacent, with distances from the alignment patterns.

[0376] [D9] Method for manufacturing the SiC semiconductor device according to D7 or D8, wherein the chip regions are each fitted with a circumferential edge section in which the alignment patterns are arranged, and wherein the SiC wafer is split such that the alignment patterns remain in the chip regions.

[0377] [D10] Method for manufacturing the SiC semiconductor device according to any one of D7 to D9, wherein the step of forming the alignment patterns includes a step of forming a trench in the main surface.

[0378] [D11] Method for manufacturing the SiC semiconductor device according to any one of D1 to D10, further comprising: a step of forming an intermediate insulating layer on the main surface, namely after the step of setting the planned cutting line and before the step of forming the main surface electrode; and wherein the main surface electrode is formed on the intermediate insulating layer.

[0379] [D12] Method for producing the SiC semiconductor device according to D11, wherein the interlayer insulating layer covering the planned cutting line is formed, wherein the laser light is emitted onto the SiC wafer via the interlayer insulating layer, and wherein the SiC wafer is split together with the interlayer insulating layer.

[0380] [D13] Method for manufacturing the SiC semiconductor component according to any one of D1 to D12, wherein the planned cutting line is set in a grid shape that delimits the chip regions in a matrix.

[0381] [D14] Method for manufacturing the SiC semiconductor device according to any one of D1 to D13, wherein the planned cutting line is set in a lattice shape extending in an a-axis direction and an m-axis direction of the SiC monocrystal and delineating the chip regions in a matrix oriented in the a-axis direction and the m-axis direction of the SiC monocrystal, and wherein the SiC wafer is cleaved in the a-axis direction and the m-axis direction of the SiC monocrystal.

[0382] [D15] Method for manufacturing the SiC semiconductor device according to D14, wherein a plurality of the second chip regions are included opposite each other in the a-axis direction of the SiC monocrystal, transversely across one or a plurality of the first chip regions.

[0383] [D16] Method for manufacturing the SiC semiconductor device according to D14 or D15, wherein a plurality of the second chip regions are included opposite each other in the m-axis direction of the SiC monocrystal, across one or a plurality of the first chip regions.

[0384] [D17] Method for manufacturing the SiC semiconductor device according to any one of D1 to D16, wherein the number of first chip regions is not less than 100 regions and not greater than 10000 regions, and wherein the number of second chip regions is not less than 1 region and not greater than 20 regions.

[0385] [D18] Method for manufacturing the SiC semiconductor device according to any one of D1 to D17, wherein the first chip regions do not have a monitor pattern.

[0386] [D19] Method for manufacturing the SiC semiconductor device according to any one of D1 to D18, wherein the SiC wafer is prepared which includes a SiC substrate and a SiC epitaxial layer and wherein the main area is constructed from the SiC epitaxial layer.

[0387] [D20] SiC semiconductor device comprising: a SiC chip having a first principal surface and a second principal surface, each formed in four-sided shapes in a plan view, and having four side surfaces, each connecting the first principal surface and the second principal surface, each composed of cleavage surfaces; a modified region formed in the respective side surfaces, modified to have a property different from that of a SiC monocrystal; an alignment pattern as an auxiliary pattern formed in a circumferential boundary section of the first principal surface, in plan view with inward spacing from the respective side surfaces; a principal surface electrode formed on the first principal surface with inward spacing from the respective side surfaces, exposing the alignment pattern in plan view;and an insulating layer formed on the first main surface with inward spacing from the respective side surfaces, partially covering the main surface electrode and defining a dicing road which, in plan view with the side surfaces, exposes the alignment pattern; and wherein no auxiliary pattern other than the alignment pattern is formed in the circumferential boundary section of the first main surface which, in plan view, is positioned within the dicing road.

[0388] [D21] SiC semiconductor device according to D20, wherein the alignment pattern is formed in a corner section of the first main surface, in the top view.

[0389] [D22] SiC semiconductor device according to D20 or D21, wherein the alignment pattern includes a trench formed in the first principal face.

[0390] [D23] SiC semiconductor device according to D22, wherein the alignment pattern includes an insulator embedded in the trench.

[0391] [D24] SiC semiconductor device according to any one of D20 to D23, further comprising: an interlayer insulating layer formed on the first main surface and covering the alignment pattern; and wherein the main surface electrode is formed on the interlayer insulating layer, and wherein the insulating layer is formed on the interlayer insulating layer. Reference symbol list 1 SiC semiconductor component 2 SiC chips 3 first main area 4 second main area 5A Side surface 5B Side surface 5C Side surface 5D side surface 7 SiC epiaxial layer 8A modified region 8B modified region 8C modified region 8D modified region 20 alignment patterns 26 alignment trench 27 Insulator 30 Intermediate layer insulating layer 32 first main surface electrode 41 Insulating layer 44 inclined surface 46 Resin layer 62 SiC wafers 63 first wafer main surface 71 Chip Region 71A first chip region 71B second chip region 72 planned cutting line 73 monitor patterns 90 Dicing Street 93 modified region 101 SiC semiconductor component

Claims

[1] Method for fabricating a SiC semiconductor device, comprising: a step of providing a SiC wafer that has a main surface and is composed of a SiC monocrystal; a step of the formation process, namely in the main area, a multitude of alignment patterns that define a planned cutting line, that delineates a multitude of chip regions, that include a first chip region in which a functional component is formed, and that include a second chip region in which a monitor pattern is formed; a step of forming a plurality of main surface electrodes on the main surface, each covering the chip regions, such that the planned cutting line is exposed, and each forming a section of the functional component or a section of the monitor pattern; a step of forming on the main surface a plurality of insulating layers, each partially covering the main surface electrodes and defining a dicing road that exposes the planned cutting line in a region between those chip regions that are adjacent to each other; a step of emitting laser light onto the planned cutting line exposed opposite the main surface electrodes and the insulating layers, through the dicing road (91), and forming a modified region that is modified to have a property different from that of the SiC monocrystal in the SiC wafer; and a step of separating the SiC wafer, using the modified region as a starting point. [2] Method for manufacturing the SiC semiconductor component according to claim 1, wherein the alignment patterns are formed from a material other than a metallic material. [3] Method for manufacturing the SiC semiconductor component according to claim 1 or 2, wherein The step of providing the SiC wafer includes the preparation of a SiC substrate and a SiC epitaxial layer on the SiC substrate, with the main surface being made up of the SiC epitaxial layer, and The step of forming the alignment patterns includes a step of formation in the main area of ​​an alignment trench structure, which has side walls and a bottom wall in the SiC epitaxial layer. [4] Method for manufacturing the SiC semiconductor component according to claim 3, wherein the step of forming the alignment patterns comprises a step of embedding a transparent insulating material in the alignment trench structure. [5] Method for producing the SiC semiconductor component according to claim 3 or 4, wherein the step of forming the modified region comprises illuminating the SiC substrate with laser light at a distance from the SiC epitaxial layer to form the modified region in the SiC substrate at a distance from the SiC epitaxial layer. [6] Method for manufacturing the SiC semiconductor component according to any one of claims 1 to 5, wherein the insulating layers are each formed such that they have an inclined surface that delimits the dicing road. [7] Method for manufacturing the SiC semiconductor component according to claim 6, wherein the insulating layers each have the inclined surface which is excluded in a curved shape. [8] Method for manufacturing the SiC semiconductor component according to any one of claims 1 to 7, wherein the dicing line has a width of not less than 10% and not more than 50% of the thickness of the SiC wafer. [9] Method for manufacturing the SiC semiconductor component according to any one of claims 1 to 8, wherein the insulating layers each comprise a resin layer. [10] Method for manufacturing the SiC semiconductor component according to any one of claims 1 to 9, wherein the planned cutting line is defined in a region between the alignment patterns that are adjacent, with distances from the alignment patterns. [11] Method for manufacturing the SiC semiconductor component according to any one of claims 1 to 10, wherein the chip regions are each provided with a circumferential edge section in which the alignment patterns are arranged, and wherein the SiC wafer is split such that the alignment patterns remain in the chip regions. [12] Method for manufacturing the SiC semiconductor component according to any one of claims 1 to 11, further comprising: a step of forming an intermediate insulating layer on the main surface, specifically after the step of forming the alignment patterns and before the step of forming the main surface electrode; and the main surface electrode is formed on the intermediate insulating layer. [13] Method for manufacturing the SiC semiconductor component according to claim 12, wherein the intermediate insulating layer that covers the planned cutting line and alignment patterns, the laser light is emitted onto the SiC wafer via the intermediate insulating layer, and the SiC wafer is split together with the interlayer insulating layer. [14] Method for manufacturing the SiC semiconductor component according to any one of claims 1 to 13, wherein the planned cutting line is set in a grid shape that delineates the chip regions in a matrix. [15] Method for manufacturing the SiC semiconductor component according to any one of claims 1 to 14, wherein the planned cutting line is set in a lattice shape that extends in an a-axis direction and an m-axis direction of the SiC monocrystal and delineates the chip regions in a matrix that is aligned in the a-axis direction and the m-axis direction of the SiC monocrystal, and the SiC wafer is cleaved in the a-axis direction and the m-axis direction of the SiC monocrystal. [16] Method for manufacturing the SiC semiconductor component according to claim 15, wherein a plurality of the second chip regions are included which are opposite each other in the a-axis direction of the SiC monocrystal, transversely across one or a plurality of the first chip regions. [17] Method for manufacturing the SiC semiconductor component according to claim 15 or 16, wherein a plurality of the second chip regions are included which are opposite each other in the m-axis direction of the SiC monocrystal, transversely across one or a plurality of the first chip regions. [18] Method for manufacturing the SiC semiconductor component according to any one of claims 1 to 17, wherein the number of first chip regions is not less than 100 regions and not greater than 10000 regions, and the number of second chip regions is not less than 1 region and not greater than 20 regions. [19] Method for manufacturing the SiC semiconductor component according to any one of claims 1 to 18, wherein the first chip regions do not have a monitor pattern.

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