Solid-body imaging element, imaging device and method for controlling a solid-body imaging element

Abstract

The image quality of a single frame is enhanced in a solid-state imaging device that processes the frame using metadata. A sample-and-hold circuit, which holds a pixel signal, is provided for each set of pixels. A signal processing unit generates a first digital signal by performing signal processing on each of the held pixel signals and generates a second digital signal by performing signal processing on each of the held pixel signals. A metadata extraction unit extracts predefined metadata from the first digital signal. An image processing unit performs predefined image processing on the second digital signal using the metadata.

Description

TECHNICAL FIELD

[0001] The present technology relates to a solid-state imaging element. More specifically, the present technology relates to a solid-state imaging element that performs exposure using a global shutter method, an imaging device, and a method for controlling a solid-state imaging element. BACKGROUND

[0002] Conventionally, in imaging devices and the like, a global shutter method for simultaneously exposing all pixels has been widely used to avoid rolling shutter distortion. For example, a solid-state imaging element has been proposed that performs object detection on image data (in other words, individual images) acquired using a global shutter method and generates metadata indicating the result (see, for example, Patent Document 1). CITATION LISTPATENT DOCUMENT

[0003] Patent Document 1: Japanese Patent Application Publication No. 2020-054007 SUMMARY OF THE INVENTION PROBLEMS TO BE SOLVED BY THE INVENTION

[0004] By using the related technique described above, the solid-state imaging element can process the next frame F2 using metadata generated from a certain frame F1. However, if the subject to be recognized is a moving body, the position of the subject may change between frame F1 and frame F2, and if the metadata of frame F1 is used, there is a possibility that appropriate image processing based on a recognition result cannot be performed.

[0005] The present technology was developed in consideration of such a situation, and an objective of the present technology is to perform appropriate image processing in a solid-state imaging element that processes individual images using metadata. SOLVING THE PROBLEMS

[0006] The present technology was developed to solve the problems described above, and a first aspect thereof relates to a solid-state imaging element and a method for controlling the same, the solid-state imaging element including: a plurality of pixels each provided with a sample-and-hold circuit that holds a pixel signal; an analog-to-digital conversion unit that generates a first digital signal by performing analog-to-digital conversion processing on each of the held pixel signals and generates a second digital signal by performing the analog-to-digital conversion processing on each of the held pixel signals; a metadata extraction unit that extracts predetermined metadata from the first digital signal; and an image processing unit that performs predetermined image processing on the second digital signal using the metadata.This results in an effect that appropriate image processing is carried out.

[0007] Furthermore, in the first aspect, the metadata extraction unit may perform recognition processing for recognizing a predetermined object in a frame in which the first digital signals are arranged, and generate data indicating a result of the recognition processing as the metadata. This brings about an effect of executing appropriate image processing based on the recognized result.

[0008] Furthermore, in the first aspect, the metadata may specify a predetermined area, and the image processing unit may perform processing to replace a color in the area with a specific color. This produces an effect of hiding a predetermined object.

[0009] Furthermore, in the first aspect, the metadata may specify a predetermined region, and the image processing unit may perform mosaic processing on the region. This results in an effect of hiding a predetermined object.

[0010] Furthermore, in the first aspect, the metadata may indicate a predetermined region, and the image processing unit may extract the region as a region of interest from a single image in which the second digital signals are arranged. This results in an effect of performing predetermined processing on the region of interest.

[0011] Furthermore, in the first aspect, each of the plurality of pixels may include: a pre-stage circuit that generates a pixel signal; a sample-and-hold circuit that holds the pixel signal; and a post-stage circuit that reads the pixel signal from the sample-and-hold circuit and outputs the read pixel signal. This achieves an effect of holding pixel signals for each pixel.

[0012] Furthermore, in the first aspect, the sample-and-hold circuit may include: first and second capacitor elements; and a selection circuit that sequentially performs control for connecting the first and second capacitor elements to a predetermined post-stage node and control for connecting another one of the first and second capacitor elements to the post-stage node. This achieves an effect of holding the reset level and signal level.

[0013] Furthermore, in the first aspect, the selection circuit may sequentially perform control for connecting one of the first and second capacitor elements to a predetermined post-stage node, control for disconnecting both the first and second capacitor elements from the post-stage node, and control for connecting another of the first and second capacitor elements to the post-stage node. This achieves a noise reduction effect.

[0014] Furthermore, in the first aspect, each of the plurality of pixels may further include a post-stage reset transistor that initializes a level of the post-stage node when both the first and second capacitor elements are disconnected from the post-stage node. This provides a noise-reducing effect.

[0015] Furthermore, a second aspect of the present technology relates to an imaging device including: a plurality of pixels each provided with a sample-and-hold circuit that holds a pixel signal; a signal processing unit that generates a first digital signal by performing signal processing on each of the held pixel signals and generates a second digital signal by performing the signal processing on each of the held pixel signals; a metadata extraction unit that extracts predetermined metadata from the first digital signal; an image processing unit that performs predetermined image processing on the second digital signal using the metadata; and a recording unit that records a frame in which the second digital signals subjected to the processing are arranged.This brings about an effect that appropriate image processing is performed based on the single image captured by the imaging device. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram illustrating a configuration example of an imaging apparatus according to a first embodiment of the present technology. Fig. 2 is a block diagram illustrating a configuration example of a solid-state imaging element according to the first embodiment of the present technology. Fig. 3 is a circuit diagram illustrating a configuration example of a pixel according to the first embodiment of the present technology. Fig. 4 is a block diagram illustrating a configuration example of a load MOS (Metal Oxide Semiconductor) circuit block and a column signal processing circuit according to the first embodiment of the present technology. Fig. 5 is a circuit diagram illustrating a configuration example of a pixel provided with two systems of post-stage circuits according to the first embodiment of the present technology. Fig. 6 is a circuit diagram illustrating another example of the pixel according to the first embodiment of the present technology. Fig. 7 is a circuit diagram illustrating a configuration example of a pixel in which the number of transistors in a sample-and-hold circuit is reduced in the first embodiment of the present technology. Fig. 8 is a circuit diagram illustrating a configuration example of a pixel in a charge domain method according to the first embodiment of the present technology. Fig. 9 is a block diagram illustrating a configuration example of a logic circuit according to the first embodiment of the present technology. Fig. 10 is a timing chart illustrating an example of an operation of the solid-state imaging element according to the first embodiment of the present technology. Fig. 11 is a timing chart illustrating an example of an operation of a solid-state imaging element in a comparative example. Fig. 12 is a diagram illustrating an example of a first frame and a recognition result according to the first embodiment of the present technology. Fig. 13 is a diagram illustrating an example of a second frame and a processed frame according to the first embodiment of the present technology. Fig. 14 is a flowchart illustrating an example of an operation of the solid-state imaging element according to the first embodiment of the present technology. Fig. 15 is a diagram illustrating an example of a second frame and a processed frame according to a first modification example of the first embodiment of the present technology. Fig. 16 is a diagram illustrating an example of a second frame and a region of interest according to a second modification example of the first embodiment of the present technology. Fig. 17 is a circuit diagram illustrating a configuration example of a pixel according to a second embodiment of the present technology. Fig. 18 is a timing diagram illustrating an example of a global shutter operation according to the second embodiment of the present technology. Fig. 19 is a timing chart illustrating an example of a read operation according to the second embodiment of the present technology. Fig. 20 is a timing chart illustrating another example of the read operation according to the second embodiment of the present technology. Fig. 21 is a circuit diagram illustrating a configuration example of a pixel according to a first modification example of the second embodiment of the present technology. Fig. 22 is a timing chart illustrating an example of a global shutter operation according to the first modification example of the second embodiment of the present technology. Fig. 23 is a timing chart illustrating an example of a read operation according to the first modification example of the second embodiment of the present technology. Fig. 24 is a view illustrating an example of a stacked structure of a solid-state imaging element according to a second modification example of the second embodiment of the present technology. Fig. 25 is a circuit diagram illustrating a configuration example of a pixel according to the second modification example of the second embodiment of the present technology. Fig. 26 is a view illustrating an example of a stacked structure of a solid-state imaging element according to a third modification example of the second embodiment of the present technology. Fig. 27 is a circuit diagram illustrating a configuration example of a pixel according to a third embodiment of the present technology. Fig. 28 is a timing diagram illustrating an example of a global shutter operation according to a fourth embodiment of the present technology. Fig. 29 is a circuit diagram illustrating a configuration example of a pixel according to the fourth embodiment of the present technology. Fig. 30 is a diagram for describing a reset execution according to the fourth embodiment of the present technology. Fig. 31 is a diagram for describing level variations caused by a reset execution according to the fourth embodiment of the present technology. Fig. 32 is a timing chart illustrating an example of voltage control according to the fourth embodiment of the present technology. Fig. 33 is a timing diagram illustrating an example of a global shutter operation for odd frames according to a fifth embodiment of the present technology. Fig. 34 is a timing chart illustrating an example of an odd-frame read operation according to the fifth embodiment of the present technology. Fig. 35 is a timing diagram illustrating an example of a global shutter operation for even frames according to the fifth embodiment of the present technology. Fig. 36 is a timing chart illustrating an example of an even frame read operation according to the fifth embodiment of the present technology. Fig. 37 is a circuit diagram illustrating a configuration example of a column signal processing circuit according to a sixth embodiment of the present technology. Fig. 38 is a timing diagram illustrating an example of a global shutter operation according to the sixth embodiment of the present technology. Fig. 39 is a timing chart illustrating an example of a read operation according to the sixth embodiment of the present technology. Fig. 40 is a timing diagram illustrating an example of a rolling shutter operation according to a seventh embodiment of the present technology. Fig. 41 is a block diagram illustrating a configuration example of a solid-state imaging element according to an eighth embodiment of the present technology. Fig. 42 is a circuit diagram illustrating a configuration example of a dummy pixel, a regulator, and a switching unit according to the eighth embodiment of the present technology. Fig. 43 is a timing chart illustrating an example of an operation of the dummy pixel and the controller according to the eighth embodiment of the present technology. Fig. 44 is a circuit diagram illustrating a configuration example of an effective pixel according to the eighth embodiment of the present technology. Fig. 45 is a timing diagram illustrating an example of a global shutter operation according to the eighth embodiment of the present technology. Fig. 46 is a timing chart illustrating an example of a read operation according to the eighth embodiment of the present technology. Fig. 47 is a diagram for describing effects according to the eighth embodiment of the present technology. Fig. 48 is a block diagram illustrating a schematic configuration example of a vehicle control system. Fig. 49 is an explanatory view illustrating an example of an installation position of an imaging section. METHOD FOR CARRYING OUT THE INVENTION

[0016] Modes for implementing the present technology (hereinafter referred to as embodiments) are described below. The description will be given in the following order. 1. First Embodiment (Example of holding a pixel signal and performing signal processing twice) 2. Second Embodiment (Example of adding a post-stage reset transistor, holding a pixel signal, and performing signal processing twice) 3. Third Embodiment (Example of adding a discharge transistor, holding a pixel signal, and performing signal processing twice) 4. Fourth Embodiment (Example of Holding a Pixel Signal and Performing Signal Processing Twice to Control a Reset Power Supply Voltage) 5. Fifth Embodiment (Example of Holding a Pixel Signal and Performing Signal Processing Twice to Switch Levels to Be Held for Each Frame) 6. Sixth Embodiment (Example of Holding a Pixel Signal and Performing Signal Processing Twice to Suppress a Black Spot Phenomenon) 7. Seventh Embodiment (Example of Holding a Pixel Signal and Performing Signal Processing Twice and Performing a Rolling Shutter Operation) 8. Eighth Embodiment (Example of Turning Off the Pre-stage Source Follower During Reading, Holding the Pixel Signal and Performing Signal Processing Twice) 9. Application example for mobile bodies <1. First Embodiment>[Configuration Example of the Imaging Device]

[0017] Fig. 1 is a block diagram illustrating a configuration example of an imaging device 100 according to a first embodiment of the present technology. The imaging device 100 is a device that acquires image data and includes an imaging lens 110, a solid-state imaging element 200, a recording unit 120, and an imaging control unit 130. The imaging device 100 is assumed to be a digital camera or an electronic device (a smartphone, a PC, or the like) with an imaging function.

[0018] The solid-state imaging element 200 acquires image data (frames) under the control of the imaging control unit 130. The solid-state imaging element 200 supplies frame images to the recording unit 120 via a signal line 209.

[0019] The imaging lens 110 focuses light and directs the light to the solid-state imaging element 200. The imaging control unit 130 controls the solid-state imaging element 200 to capture individual images. For example, the imaging control unit 130 supplies an imaging control signal including a vertical synchronization signal XVS to the solid-state imaging element 200 via a signal line 139. The recording unit 120 records individual images.

[0020] Here, the vertical synchronization signal XVS is a signal indicating imaging timing, and a periodic signal having a constant frequency (60 Hertz or the like) is used as the vertical synchronization signal XVS.

[0021] Note that although the imaging device 100 records individual images, the individual images may be transmitted outside the imaging device 100. In this case, an external interface for transmitting individual images is further provided. Alternatively, the imaging device 100 may further display individual images. In this case, a display section is further provided. [Configuration example of the solid-state imaging element]

[0022] Fig. 2 is a block diagram illustrating a configuration example of the solid-state imaging element 200 according to the first embodiment of the present technology. The solid-state imaging element 200 includes a vertical scanning circuit 211, a pixel array unit 220, a timing control circuit 212, a digital-to-analog converter (DAC) 213, a load MOS circuit block 250, and a column signal processing circuit 260. In the pixel array unit 220, a plurality of pixels 300 are arranged in a two-dimensional grid pattern. Furthermore, each circuit in the solid-state imaging element 200 is provided in, for example, a single semiconductor chip.

[0023] Hereinafter, a set of pixels 300 arranged in a horizontal direction is referred to as a “row” and a set of pixels 300 arranged in a direction perpendicular to the row is referred to as a “column”.

[0024] The timing control circuit 212 controls operation timings of each of the vertical scanning circuit 211, the DAC 213, and the column signal processing circuit 260 in synchronization with the vertical synchronization signal XVS from the imaging control unit 130.

[0025] The DAC 213 generates a sawtooth-shaped ramp signal through digital-to-analog (DA) conversion. The DAC 213 supplies the generated ramp signal to the column signal processing circuit 260.

[0026] The vertical scanning circuit 211 sequentially selects rows and controls them to output analog pixel signals. The pixel 300 photoelectrically converts incident light to generate the analog pixel signal. The pixel 300 supplies a pixel signal to the column signal processing circuit 260 via the load MOS circuit block 250.

[0027] In the load MOS circuit block 250, a MOS transistor providing a constant current is provided for each column.

[0028] The column signal processing circuit 260 performs signal processing, such as AD conversion processing or CDS processing, on the pixel signal for each column. The column signal processing circuit 260 supplies image data (frame) including the processed signals to the recording unit 120. [Pixel configuration example]

[0029] Fig. 3 is a circuit diagram illustrating a configuration example of pixel 300 according to the first embodiment of the present technology. Pixel 300 includes a pre-stage circuit 310, a sample-and-hold circuit 320, and a post-stage circuit 350. In pixel array unit 220, a vertical signal line 309 is wired for each column.

[0030] The pre-stage circuit 310 includes a photoelectric conversion element 311, a transfer transistor 312, a floating diffusion (FD) reset transistor 313, an FD 314, a pre-stage amplification transistor 315, and a current source transistor 316.

[0031] The photoelectric conversion element 311 generates charges through photoelectric conversion. The transfer transistor 312 transfers the charges from the photoelectric conversion element 311 to the FD 314 according to a transfer signal trg from the vertical scanning circuit 211.

[0032] The FD reset transistor 313 extracts charges from the FD 314 to initialize the FD 314 according to an FD reset signal rst from the vertical scanning circuit 211. The FD 314 accumulates charges and generates a voltage corresponding to a charge amount. The pre-stage amplification transistor 315 amplifies a voltage level of the FD 314 and outputs the amplified voltage to a pre-stage node 319.

[0033] Furthermore, the FD reset transistor 313 and the pre-stage amplification transistor 315 have their respective sources connected to a power supply voltage VDD. The current source transistor 316 is connected to a drain of the pre-stage amplification transistor 315. A predetermined bias voltage BIAS is supplied to a gate of this current source transistor 316.

[0034] The sample-and-hold circuit 320 includes capacitor elements 321 and 322 and a selection circuit 330. The capacitor elements 321 and 322 have their respective one ends connected in common to the pre-stage node 319 and have their respective other ends connected to the selection circuit 330. Note that the capacitor elements 321 and 322 are examples of first and second capacitor elements described in the claims.

[0035] The selection circuit 330 includes a selection transistor 331 and a selection transistor 332. The selection transistor 331 opens and closes a path between the capacitor element 321 and a post-stage node 340 according to a selection signal Φr from the vertical scanning circuit 211. The selection transistor 332 opens and closes a path between the capacitor element 322 and the post-stage node 340 according to a selection signal Φs from the vertical scanning circuit 211.

[0036] The post-stage circuit 350 includes a post-stage amplification transistor 351 and a post-stage selection transistor 352. The post-stage amplification transistor 351 amplifies the level of the post-stage node 340. The post-stage selection transistor 352 outputs a signal having the level amplified by the post-stage amplification transistor 351 to a vertical signal line 309 as a pixel signal according to a post-stage selection signal selb from the vertical scanning circuit 211.

[0037] It is noted that, for example, n-channel metal oxide semiconductor (nMOS) transistors are used as various transistors (transfer transistor 312 and the like) in the pixel 300.

[0038] The vertical scanning circuit 211 supplies a high-level FD reset signal rst and a high-level transfer signal trg to all pixels at the start of an exposure. Accordingly, the photoelectric conversion element 311 is initialized. Hereinafter, this control is referred to as "PD reset."

[0039] Then, the vertical scanning circuit 211 provides a high-level FD reset signal rst for one pulse period, while setting the selection signal Φr to the high level for all pixels immediately before the end of an exposure. Accordingly, the FD 314 is initialized, and a level corresponding to the level of the FD 314 at that time is held in the capacitor element 321. This control is hereinafter referred to as "FD reset."

[0040] The level of the FD 314 at the time of FD reset and a level corresponding to the level of the FD 314 (the level held in the capacitor element 321 and the level of the vertical signal line 309) are hereinafter collectively referred to as “P-phase” or “reset level”.

[0041] At the end of the exposure, the vertical scanning circuit 211 provides a high-level transfer signal trg throughout the pulse period, while the selection signal Φs is set to the high level for all pixels. Accordingly, signal charges corresponding to the exposure amount are transferred to the FD 314, and a level corresponding to the level of the FD 314 at that time is held in the capacitor element 322.

[0042] The level of the FD 314 during a signal charge transfer and a level corresponding to the level of the FD 314 (the level held in the capacitor element 322 and the level of the vertical signal line 309) are hereinafter collectively referred to as "D-phase" or "signal level".

[0043] The exposure control of simultaneously starting and ending exposure for all pixels in this way is called a global shutter method. Through this exposure control, the pre-stage circuit 310 generates pixel signals (reset level and signal level) for all pixels. The reset level of the pixel signal is held in capacitor element 321, and the signal level is held in capacitor element 322.

[0044] After the end of the exposure, the vertical scanning circuit 211 sequentially selects a line and sequentially outputs the reset level and the signal level of the line. If the reset level is output, the vertical scanning circuit 211 provides a high-level selection signal Φr for a predetermined period, while the FD reset signal rst and the post-stage selection signal selb of the selected line are set to the high level. Accordingly, the capacitor element 321 is connected to the post-stage node 340, and the reset level is read.

[0045] After reading the reset level, the vertical scanning circuit 211 provides a high-level selection signal Φs for a predetermined period while maintaining the FD reset signal rst and the post-stage selection signal selb of the selected row at a high level. Accordingly, the capacitor element 322 is connected to the post-stage node 340, and the signal level is read.

[0046] Through the above-described read control, the selected row selection circuit 330 sequentially performs control for connecting the capacitor element 321 to the post-stage node 340 and control for connecting the capacitor element 322 to the post-stage node 340. Furthermore, the post-stage circuit 350 of the selected row sequentially reads the pixel signal (reset level and signal level) from the sample-and-hold circuit 320 via the post-stage node 340 and outputs the pixel signal to the vertical signal line 309. [Configuration example of the column signal processing circuit]

[0047] Fig. 4 is a block diagram illustrating a configuration example of the load MOS circuit block 250 and the column signal processing circuit 260 according to the first embodiment of the present technology.

[0048] In the load MOS circuit block 250, the vertical signal line 309 is wired for each column. If the number of columns is I (I is an integer), I vertical signal lines 309 are wired. Furthermore, a load MOS transistor 251, which provides a constant current id2, is connected to each of the vertical signal lines 309.

[0049] A signal processing unit 261, a logic circuit 400, and a high-speed interface 410 are arranged in the column signal processing circuit 260. The signal processing unit 261 includes a plurality of ADCs 262. The ADC 262 is arranged for each column. If the number of columns is 1, 1 ADCs 262 are arranged.

[0050] The ADC 262 converts an analog pixel signal from the corresponding column into a digital signal using a ramp signal Rmp from the DAC 213. The ADC 262 supplies a digital signal to the logic circuit 400. For example, a single-slope ADC including a comparator and a counter is arranged as the ADC 262. For example, the counter in the ADC 262 performs a downcount when the reset level is AD-converted and performs an upcount when the signal level is AD-converted. Accordingly, correlated double sampling (CDS) processing is performed to obtain a difference between the reset level and the signal level. It is noted that a CDS circuit may be added in the signal processing unit 261, the ADC 262 may perform only AD conversion processing, and the CDS circuit may perform CDS processing.In this way, the signal processing unit 261 performs signal processing including AD conversion processing and CDS processing.

[0051] Logic circuit 400 performs various types of signal processing other than CDS processing on each of the digital signals for each column. Logic circuit 400 supplies a frame containing the processed digital signal to high-speed interface 410. High-speed interface 410 outputs the frame to recording unit 120.

[0052] It is noted that the circuit configuration of the pixel 300 is not limited to those shown in Fig. 3, as long as the pixel signal can be generated and sampled and held.

[0053] For example, as in Fig. 5, two systems of post-stage circuits are provided for each pixel. In this case, it is sufficient for the selection transistor 331 to open and close the path between the capacitor element 321 and the post-stage circuit 350-1, and the selection transistor 332 to open and close the path between the capacitor element 322 and the post-stage circuit 350-2. The post-stage circuit 350-1 includes a post-stage amplification transistor 351-1 and a post-stage selection transistor 352-1, and the post-stage circuit 350-2 includes a post-stage amplification transistor 351-2 and a post-stage selection transistor 352-2. Furthermore, two vertical signal lines are wired for each column, the post-stage circuit 350-1 outputs a pixel signal to a vertical signal line 309-1, and the post-stage circuit 350-2 outputs a pixel signal to a vertical signal line 309-2.

[0054] Furthermore, as in Fig. 6 illustrates that the selection transistors 331 and 332 are connected in series between the pre-stage circuit 310 and the post-stage circuit 350. In this case, the capacitor element 322 is connected to a connection node between the selection transistors 331 and 332, and the capacitor element 321 is connected to a connection node between the selection transistor 331 and the post-stage circuit 350. The control method for this sample-and-hold circuit 320 is described in, for example, "Chen Xu et al., A Stacked Global-Shutter CMOS Imager with SC-Type Hybrid-GS Pixel and Self-Knee Point Calibration Single-Frame HDR and On-Chip Binarization Algorithm for Smart Vision Applications, ISSCC2019."

[0055] Furthermore, as in Fig. As illustrated in Figure 7, a sampling transistor 333 and the capacitor element 321 may be inserted in series between the pre-stage circuit 310 and the post-stage circuit 350, and the capacitor element 322 may also be connected to their connection node. In this case, a post-stage reset transistor 341 that initializes the post-stage node 340 is further provided. The control method for this circuit is described in, for example, "Jae-kyu Lee, et al., A 2.1e-Temporal Noise and -105dB Parasitic Light Sensitivity Backside-Illuminated 2.3 um-Pixel Voltage-Domain Global Shutter CMOS Image Sensor Using High-Capacity DRAM Capacitor Technology, ISSCC 2020."

[0056] Each of the sample-and-hold circuits 320 in Fig. 3, Fig. 5, Fig. 6 and Fig. 7, which were previously described, is a circuit in a voltage domain method that holds a voltage, but a circuit in a charge domain method that holds a charge can also be used, as in Fig. 8 is illustrated.

[0057] In the charge domain method from Fig. 8, for example, selection transistors 331-1 and 331-2 are inserted in series between pre-stage circuit 310 and post-stage circuit 350. Furthermore, selection transistors 332-1 and 332-2, which are connected in series, are inserted in parallel to the circuit including selection transistors 331-1 and 331-2. Capacitor element 321 is connected to a connection node between selection transistors 331-1 and 331-2, and capacitor element 322 is connected to a connection node between selection transistors 332-1 and 332-2. [Logic circuit configuration example]

[0058] Fig. Figure 9 is a block diagram illustrating a configuration example of the logic circuit 400 according to the first embodiment of the present technology. The logic circuit 400 includes a column interface 401, an image processing unit 402, an image signal processor (ISP) circuit 403, a metadata extraction unit 404, and a memory 405.

[0059] Here, each of the previously described pixels 300 maintains a pixel signal in synchronization with the vertical synchronization signal XVS. The signal processing unit 261 performs signal processing (AD conversion processing and CDS processing) for converting a pixel signal into a digital signal after CDS processing for each pixel twice in synchronization with the vertical synchronization signal XVS. Since each of the signal processing includes AD conversion processing for the reset level and AD conversion processing and CDS processing for the signal level, four AD conversion processing and two CDS processing are performed in two times the signal processing.

[0060] The column interface 401 receives digital signals from the signal processing unit 261 and supplies image data (frames) in which the digital signals are arranged to the image processing unit 402. Since the signal processing is performed twice for each pixel in synchronization with the vertical synchronization signal XVS, two frames are generated for each period of the vertical synchronization signal XVS. These frames are the same data, but subsequently, a first frame is referred to as „ F1" and a second frame is called "F2" to distinguish them.

[0061] The image processing unit 402 performs various types of processing, such as defective pixel correction and dark correction, on the frame from the column interface 401. The image processing unit 402 processes the first frame F1 and supplies the frame F1 to the ISP circuit 403.

[0062] The ISP circuit 403 performs processing to reduce the amount of data on the frame F1 as needed. If the processing load of the metadata extraction unit 404 is large, the ISP circuit 403 reduces the amount of data. For example, downscaling and tone reduction are performed. Furthermore, if the image from the signal processing unit 261 is a Bayer array image and the format of the input image to the metadata extraction unit 404 is a color image composed of three colors of R, G, and B for each pixel, the ISP circuit 403 performs demosaic processing to convert the Bayer array into a color image. The ISP circuit 403 supplies the processed frame F1 to the metadata extraction unit 404.

[0063] The metadata extraction unit 404 extracts predetermined metadata from the image frame F1. For example, the metadata extraction unit 404 performs recognition processing for recognizing a predetermined object on the image frame F1 and generates data indicating the processing result as metadata. The metadata includes, for example, information about whether the recognition target was recognized, information about the type, name, and attribute of the recognized object, information indicating the area of ​​the object, and the like. The attributes include, for example, gender, age, and the like. The metadata extraction unit 404 provides the extracted metadata to the image processing unit 402.

[0064] The working memory 405 holds data used in recognition processing. For example, recognition processing is performed by a neural network, and intermediate data exchanged between layers in the neural network is temporarily held in the working memory 405. Furthermore, weights used in the neural network are stored in advance in the working memory 405.

[0065] The image processing unit 402 performs predetermined processing on the second frame F2 using the metadata extracted from the first frame F1. For example, processing for replacing the color of the area of ​​the object indicated by the metadata with a specific color (black or the like) is performed on the frame F2. The image processing unit 402 delivers the processed frame as F2' to the high-speed interface 410.

[0066] As described above, each of the pixels 300 is provided with a sample-and-hold circuit that holds a pixel signal. In synchronization with the vertical synchronization signal XVS, the signal processing unit 261 performs processing for generating a digital signal after CDS processing twice by signal processing (AD conversion processing and CDS processing) for each of the pixel signals held in the pixel 300. The frame in which the first digital signals are arranged is F1, and the frame in which the second digital signals are arranged is F2. Note that the first digital signal is an example of a first digital signal described in the claims, and the second digital signal is an example of a second digital signal described in the claims.

[0067] The metadata extraction unit 404 extracts metadata from the frame F1 and supplies the metadata to the image processing unit 402. The image processing unit 402 performs predetermined processing on the frame F2 using the metadata of the frame F1. [Operation example of the solid-state imaging element]

[0068] Fig. 10 is a timing chart illustrating an example of an operation of the solid-state imaging element 200 according to the first embodiment of the present technology.

[0069] The vertical scanning circuit 211 exposes all pixels in the pixel array unit 220 over an exposure period from time T0 to time T1. Furthermore, the vertical synchronization signal XVS falls at time T1.

[0070] Over a period from time T1 to time T2, the signal processing unit 261 sequentially reads the held pixel signals line by line and performs signal processing (AD conversion processing and CDS processing) to generate a frame F1. Furthermore, the image processing unit 402 performs image processing, such as defective pixel correction, on the frame F1 and supplies the processed frame F1 to the metadata extraction unit 404 via the ISP circuit 403 (not illustrated).

[0071] During a period from time T2 to time T3, the metadata extraction unit 404 extracts metadata from the frame F1 and supplies the metadata to the image processing unit 402.

[0072] Over a period from time T3 to immediately before time T4, the signal processing unit 261 sequentially reads the held pixel signals line by line and performs signal processing to generate a frame F2. Since the signal processing is performed on the same pixel as the first time, the frame F2 becomes the same data as the frame F1. The image processing unit 402 performs predetermined processing on the frame F2 using the metadata and supplies the processed frame F2' to the high-speed interface 410. The high-speed interface 410 outputs the frame F2' to the outside. Also, at time T4, the vertical synchronization signal XVS falls.It is noted that if multiple frames are captured in synchronization with the vertical synchronization signal XVS, all pixels are exposed within one exposure period from the predetermined time point to time T4, and the next pixel signal is generated.

[0073] Here, a configuration in which the sample-and-hold circuit 320 is not arranged in the pixel is assumed as a comparative example.

[0074] Fig. 11 is a timing diagram illustrating an example of an operation of the solid-state imaging element 200 in the comparative example. The vertical scanning circuit 211 exposes all pixels in the pixel array unit 220 over the exposure period from time T0 to time T1.

[0075] Over the period from time T1 to time T2, the signal processing unit 261 sequentially reads the pixel signals line by line and performs signal processing (AD conversion processing and CDS processing) to generate a frame F1. Furthermore, the image processing unit 402 performs image processing, such as defective pixel correction, on the frame F1 and supplies the processed frame F1 to the metadata extraction unit 404 via the ISP circuit 403 (not illustrated).

[0076] The vertical scanning circuit 211 exposes all pixels in the pixel array unit 220 over the exposure period from time T2 to time T3. The vertical synchronization signal XVS falls at time T3. Furthermore, the metadata extraction unit 404 extracts metadata from the frame F1 within the exposure period and supplies the metadata to the image processing unit 402.

[0077] Over a predetermined period from time T3, the signal processing unit 261 sequentially reads the pixel signals line by line and performs signal processing to generate a frame F2. The pixel signals generated by the exposure at time T0 to time T1 are destroyed by the exposure at times T2 to T3. Therefore, if a moving body is imaged, the frame F2 becomes data different from the frame F1.

[0078] Over a predetermined period from time T3, the image processing unit 402 performs predetermined processing on the frame F2 using the metadata and supplies the processed frame F2' to the high-speed interface 410. The high-speed interface 410 outputs the frame F2' to the outside.

[0079] As illustrated in the drawing, in the comparative example in which the sample-and-hold circuit 320 is not arranged for each pixel, a pixel signal is not held, and signal processing cannot be performed twice on the same pixel signal. Therefore, if the frame F2 is processed using the metadata of the frame F1, the object detected in the frame F1 may move and change its position in the frame F2. As a result, the processing using the metadata is not performed on an appropriate area, and there is a possibility that appropriate image processing without positional deviation cannot be performed on the frame F2'.

[0080] On the other hand, if the sample-and-hold circuit 320 is arranged for each pixel, signal processing can be performed twice on the same pixel signal, as in Fig. 10. Therefore, the position of the object is the same in each of the frame F1 and the frame F2. Therefore, the image processing unit 402 can perform processing using the metadata on an appropriate area and can perform appropriate image processing on the frame F2'.

[0081] Fig. 12 is a diagram illustrating an example of a first frame and a recognition result according to the first embodiment of the present technology. In the drawing, a is an example of a first frame 500, and b is a diagram illustrating an example of a recognition result.

[0082] As illustrated in a of the drawing, the frame 500 includes subjects such as a human 501 and a building 502. In the recognition processing, it is assumed that the recognition target is a human. In this case, as illustrated in b of the drawing, the human 501 is recognized, and information indicating a rectangular area 510 including the object is generated as metadata. In the drawing, the rectangular area 510 indicated by a bold dotted line corresponds to an area indicated by metadata.

[0083] Fig. 13 is a diagram illustrating an example of a second frame and a processed frame according to the first embodiment of the present technology. In the drawing, a is an example of a second frame 510, and b is an example of a frame 520 processed using metadata.

[0084] As illustrated in a of the drawing, the same frame 510 as the first frame 500 is generated by the second signal processing. Then, as illustrated in b of the drawing, the area 521 specified by the metadata is filled with a specific color (black or the like).

[0085] Fig. 14 is a flowchart illustrating an example of an operation of the solid-state imaging element 200 according to the first embodiment of the present technology. This operation is initiated, for example, when a predetermined application for capturing a single image is executed. The vertical scanning circuit 211 in the solid-state imaging element 200 exposes all pixels simultaneously (step S901). For each pixel, the sample-and-hold circuit 320 in the pixel samples and holds the pixel signal (step S902).

[0086] The signal processing unit 261 performs signal processing (AD conversion processing and CDS processing) on ​​each of the held pixel signals to generate a first frame (step S903). The image processing unit 402 performs image processing on the frame (step S904), and the metadata extraction unit 404 extracts metadata from the processed frame (step S905).

[0087] Further, the signal processing unit 261 performs signal processing on each of the held pixel signals to generate a second frame image (step S906). The image processing unit 402 references the metadata and determines whether the target object has been detected or not (step S907). If the target object has been detected (step S907: Yes), the image processing unit 402 performs image processing, such as filling, using the metadata (step S908). On the other hand, if the target object has not been detected (step S907: No), the image processing unit 402 performs normal image processing, such as defective pixel correction, without using the metadata (step S909). After step S908 or S909, the solid-state imaging element 200 ends the frame image acquisition operation.

[0088] It is noted that if a plurality of frames are captured in synchronization with the vertical synchronization signal XVS, the processing of steps S901 to S909 is repeatedly executed in synchronization with the vertical synchronization signal XVS.

[0089] In this way, according to the first embodiment of the present technology, since the pixel signal is held for each pixel and the second frame, which is the same as the first frame, is processed using the metadata extracted from the first frame, it is possible to perform appropriate image processing compared with the comparative example in which the pixel signal is not held. [First modification example]

[0090] In the first embodiment described above, the image processing unit 402 performs processing to fill the area specified by the metadata with a specific color (such as black) for the frame F2. However, the processing performed using the metadata is not limited to the processing to fill with black or the like. A solid-state imaging element 200 according to a first modification example of the first embodiment differs from the solid-state imaging element 200 of the first embodiment in that mosaic processing is performed on an area specified by metadata.

[0091] Fig. 15 is a diagram illustrating an example of a second frame and a processed frame according to the first modification example of the first embodiment of the present technology. In the drawing, a is an example of a second frame 510, and b is an example of a frame 520 processed using metadata.

[0092] As illustrated in b of the drawing, the image processing unit 402 performs mosaic processing on an area 522 specified by the metadata.

[0093] In this way, according to the first modification example of the first embodiment of the present technology, since mosaic processing is performed on the area 522 indicated by the metadata, the recognized object can be hidden by mosaic. [Second modification example]

[0094] In the first embodiment described above, the image processing unit 402 performs processing to fill the area specified by the metadata with a specific color (such as black) for the frame F2. However, the processing performed using the metadata is not limited to the processing to fill with black or the like. A solid-state imaging element 200 according to a second modification example of the first embodiment differs from the solid-state imaging element 200 of the first embodiment in that an area specified by metadata is extracted as a region of interest (ROI).

[0095] Fig. 16 is a diagram illustrating an example of a second frame and a region of interest according to the second modification example of the first embodiment of the present technology. In the drawing, a is an example of a second frame 510, and b is an example of a region of interest 530.

[0096] As illustrated in b of the drawing, the image processing unit 402 extracts an area specified by the metadata as the area of ​​interest 530 from the single image 510. For example, a detection result of suspicious behavior, possession of a dangerous object, or the presence or absence of a suspicious object is used as the metadata. The image processing unit 402 then performs various types of image processing, such as defective pixel correction, on the area of ​​interest 530.

[0097] It is noted that in Fig. 13, Fig. 15 and Fig. 16 The entire person is a detection target, but only the face can also be a detection target. Furthermore, an object other than a person, such as a vehicle's license plate number, can be set as a detection target.

[0098] In this way, according to the second modification example of the first embodiment of the present technology, since the area indicated by the metadata is extracted as an area of ​​interest (ROI), the ROI can be set based on the detection result (metadata) of the presence or absence of a suspicious behavior or the like. <2. Second Embodiment>

[0099] In the first embodiment described above, the selection circuit 330 sequentially connects the capacitor elements 321 and 322 to the post-stage node 340, but with this configuration, there is a possibility that noise may not be sufficiently suppressed. A pixel 300 of this second embodiment differs from the pixel 300 of the first embodiment in that the post-stage node 340 is initialized when the selection circuit 330 disconnects the capacitor elements 321 and 322 from the post-stage circuit 340.

[0100] Fig. 17 is a circuit diagram illustrating a configuration example of the pixel 300 according to the second embodiment of the present technology. The pixel 300 of the second embodiment differs from the pixel 300 of the first embodiment in that a post-stage reset transistor 341 is further provided.

[0101] The post-stage reset transistor 341 initializes a level of the post-stage node 340 to a predetermined potential Vreg according to a post-stage reset signal rstb from the vertical scanning circuit 211. A potential different from the power supply potential VDD (for example, a potential lower than VDD) is set as the potential Vreg.

[0102] After reading the reset level, the vertical scanning circuit 211 provides a high-level post-stage reset signal rstb throughout the pulse period, while maintaining the FD reset signal rst and the post-stage select signal selb of the selected row at the high level. Accordingly, the level of the post-stage node 340 is initialized. At this time, both the select transistor 331 and the select transistor 332 are in an open state, and the capacitor elements 321 and 322 are disconnected from the post-stage node 340.

[0103] After initializing the post-stage node 340, the vertical scanning circuit 211 provides a high-level selection signal Φs for a predetermined period while maintaining the FD reset signal rst and the post-stage selection signal selb of the selected row at a high level. Accordingly, the capacitor element 322 is connected to the post-stage node 340, and the signal level is read.

[0104] Through the read control described above, the selected row selection circuit 330 sequentially performs control for connecting the capacitor element 321 to the post-stage node 340, control for disconnecting the capacitor elements 321 and 322 from the post-stage node 340, and control for connecting the capacitor element 322 to the post-stage node 340. Furthermore, when the capacitor elements 321 and 322 are disconnected from the post-stage node 340, the post-stage reset transistor 341 of the selected row initializes the level of the post-stage node 340. Furthermore, the post-stage circuit 350 of the selected row sequentially reads the reset level and the signal level from the capacitor elements 321 and 322 via the post-stage node 340 and outputs the reset level and the signal level to the vertical signal line 309.

[0105] Fig. 18 is a timing diagram illustrating an example of a global shutter operation according to the second embodiment of the present technology. The vertical scanning circuit 211 supplies a high-level FD reset signal rst and the high-level transfer signal trg to all rows (in other words, all pixels) over a period from a time T0 immediately before the start of an exposure to a time T1 after the pulse period has elapsed. Accordingly, all pixels are Pd-reset, and exposure begins simultaneously in all rows.

[0106] Here, rst_[n] and trg_[n] in the figure indicate signals to pixels in the nth row among N rows. N is an integer indicating the total number of rows, and n is an integer from 1 to N.

[0107] Then, at a time T2 immediately before the end of the exposure period, the vertical scanning circuit 211 provides a high-level FD reset signal rst throughout the pulse period, while setting the post-stage reset signal rstb and the selection signal Φr to high levels for all pixels. Accordingly, all pixels are FD reset, and the reset level is sampled and held. Here, rstb_[n] and Φr_[n] in the figure indicate signals to pixels in the nth row.

[0108] At a time T3 after the time T2, the vertical scanning circuit 211 returns the selection signal Φr to the low level.

[0109] At a time T4 at the end of the exposure, the vertical scanning circuit 211 provides a high-level transfer signal trg over the pulse period, while the post-stage reset signal rstb and the select signal Φs are set to the high level for all pixels. Accordingly, the signal level is sampled and held. Furthermore, the level of the pre-stage node 319 decreases from the reset level (VDD - Vgs) to the signal level (VDD - Vgs - Vsig). Here, VDD is a power supply voltage, and Vsig is a net signal level obtained by the CDS processing. Vgs indicates a gate-source voltage of the pre-stage amplification transistor 315. Furthermore, Φs_[n] in the drawing indicates signals to pixels in the nth row.

[0110] At a time T5 after the time T4, the vertical scanning circuit 211 returns the selection signal Φs to the low level.

[0111] Furthermore, the vertical scanning circuit 211 drives the current source transistors 316 of all rows (all pixels) to supply a current id1. Here, id1_[n] in the drawing indicates a current of pixels in the nth row. The larger the current id, the greater the IR drop, so the current id1 is required to be on the order of a few nanoamperes (nA) to several tens of nanoamperes (nA). On the other hand, the load MOS transistors 251 of all columns are in the off state, and the current id2 is not supplied to the vertical signal line 309.

[0112] Fig. 19 is a timing chart illustrating an example of a read operation according to the second embodiment of the present technology. During a read period of the n-th row from time T10 to time T17, the vertical scanning circuit 211 sets the FD reset signal rst and the post-stage selection signal selb of the n-th row to the high level. Furthermore, during the reset period, the post-stage reset signal rstb of all rows is driven to the low level. Here, selb_[n] in the drawing indicates signals to pixels in the n-th row.

[0113] The vertical scanning circuit 211 supplies a high-level selection signal Φr to the n-th row for a period from a time T11 immediately after the time T10 to a time T13. The potential of the post-stage node 340 becomes a reset level Vrst.

[0114] The DAC 213 gradually increases the ramp signal Rmp over a period from time T12 after time T11 to time T13. The ADC 262 compares the ramp signal Rmp with the level Vrst' of the vertical signal line 309 and counts a count value over a period until the comparison result is inverted. Accordingly, the P-phase level (reset level) is read.

[0115] The vertical scanning circuit 211 supplies a high-level post-stage reset signal rstb to the n-th row over the pulse period from a time T14 immediately after the time T13. Accordingly, if a parasitic capacitance is present in the post-stage node 340, the history of the previous signal held in the parasitic capacitance can be erased.

[0116] The vertical scanning circuit 211 supplies a high-level selection signal Φs to the n-th row over a period from a time T15 immediately after the initialization of the post-stage node 340 to a time T17. The potential of the post-stage node 340 becomes a signal level Vsig. During exposure, the signal level is lower than the reset level, but during reading, the signal level is higher than the reset level because the post-stage node 340 is used as a reference. A difference between the reset level Vrst and the signal level Vsig corresponds to a net signal level from which reset noise and FD offset noise have been removed.

[0117] The DAC 213 gradually increases the ramp signal Rmp over a period from time T16 after time T15 to time T17. The ADC 262 compares the ramp signal Rmp with the level Vrst' of the vertical signal line 309 and counts a count value over a period until the comparison result is inverted. Accordingly, the D-phase level (signal level) is read.

[0118] Furthermore, the vertical scanning circuit 211 controls the current source transistor 316 of the nth row to be read over the period from time T10 to time T17 to provide the current id1. Furthermore, the timing control circuit 212 controls the load MOS transistors 251 of all columns to provide the current id2 within the read period of all rows.

[0119] It is noted that the solid-state imaging element 200 reads the signal level after the reset level, but is not limited to this order. Alternatively, as shown in Fig. As illustrated in Figure 20, the solid-state imaging element 200 reads the reset level after the signal level. In this case, as illustrated in the drawing, the vertical scanning circuit 211 provides a high-level selection signal Φr after the high-level selection signal Φs. Furthermore, in this case, it is necessary to reverse the slope of the ramp signal.

[0120] Furthermore, any of the first and second modification examples of the first embodiment can be applied to the second embodiment.

[0121] In this way, according to the second embodiment of the present technology, the post-stage reset transistor 341 initializes the post-stage node 340 when the selection circuit 330 disconnects the capacitor elements 321 and 322 from the post-stage circuit 340. Since the capacitor elements 321 and 322 are disconnected, the level of reset noise generated by the drive becomes a level corresponding to a parasitic capacitance smaller than the capacitances of the capacitor elements 321 and 322. By reducing this noise, the image quality of image data can be improved. [First modification example]

[0122] In the second embodiment described above, the pre-stage circuit 310 reads a signal, and the pre-stage circuit 310 is connected to the pre-stage node 319, but this configuration cannot block noise from the pre-stage circuit 319 during reading. A pixel 300 of a first modification example of the second embodiment differs from the pixel 300 of the second embodiment in that a transistor is inserted between the pre-stage circuit 310 and the pre-stage node 319.

[0123] Fig. 21 is a circuit diagram illustrating a configuration example of the pixel 300 according to the first modification example of the second embodiment of the present technology. The pixel 300 of the first modification example of the second embodiment differs from the pixel 300 of the second embodiment in that a pre-stage reset transistor 323 and a pre-stage selection transistor 324 are further provided. Furthermore, the power supply voltage of the pre-stage circuit 310 and the post-stage circuit 350 of the first modification example of the second embodiment is denoted as VDD1.

[0124] The post-stage reset transistor 323 initializes the level of the pre-stage node 319 with a power supply voltage VDD2. It is desirable that the power supply voltage VDD2 be set to a value that satisfies the following expression. VDD2 = VDD1 - Vgs

[0125] In the above expression, Vgs is a gate-source voltage of the pre-stage amplification transistor 315.

[0126] Setting the value that satisfies Expression 1 enables a reduction in the potential variations between the pre-stage node 319 and the post-stage node 340 in the dark. This makes it possible to improve photoresponse non-uniformity (PRNU).

[0127] The pre-stage selection transistor 324 opens and closes a path between the pre-stage circuit 310 and the pre-stage node 319 according to a pre-stage selection signal sel from the vertical scanning circuit 211.

[0128] Fig. 22 is a timing chart illustrating an example of a global shutter operation according to the first modification example of the second embodiment of the present technology. The timing chart of the first modification example of the second embodiment differs from the timing chart of the first embodiment in that the vertical scanning circuit 211 further provides a pre-stage reset signal rsta and the pre-stage selection signal sel. In the drawings, rsta_[n] and sel_[n] indicate signals to pixels in the nth row.

[0129] The vertical scanning circuit 211 supplies a high-level pre-stage selection signal sel to all pixels over a period from time T2 immediately before the end of an exposure to time T5. The pre-stage reset signal rsta is driven to the low level.

[0130] Fig. 23 is a timing diagram illustrating an example of a read operation according to the first modification example of the second embodiment of the present technology. During the reading of each line, the pre-stage selection signal sel is driven to a low level. With this control, the pre-stage selection transistor 324 becomes open, and the pre-stage node 319 is disconnected from the pre-stage circuit 310. This allows noise from the pre-stage node 319 to be blocked during reading.

[0131] Furthermore, the vertical scanning circuit 211 supplies a high-level pre-stage reset signal rsta to the n-th line during the read period of the n-th line from a time T10 to a time T17.

[0132] Furthermore, during reading, the vertical scanning circuit 211 controls the current source transistors 316 of all pixels to stop supplying current id1. Current id2 is supplied in a manner similar to the second embodiment. Thus, the control of current id1 is simplified compared to the second embodiment.

[0133] In this way, according to the first modification example of the second embodiment of the present technology, it is possible to block noise from the pre-stage circuit 310 because the pre-stage selection transistor 324 turns into the open state during reading to disconnect the pre-stage circuit 310 from the pre-stage node 319. [Second modification example]

[0134] In the second embodiment described above, the circuits in the solid-state imaging element 200 are provided in a single semiconductor chip, but there is a possibility that this configuration may prevent the elements from fitting into the semiconductor chip if the pixel 300 is miniaturized. A solid-state imaging element 200 of a second modification example of the second embodiment differs from the solid-state imaging element 200 of the second embodiment in that the circuits in the solid-state imaging element 200 are distributed among two semiconductor chips.

[0135] Fig. 24 is a view illustrating an example of a stacked structure of the solid-state imaging element 200 according to the second modification example of the second embodiment of the present technology. The solid-state imaging element 200 of the second modification example of the second embodiment includes a lower pixel chip 202 and an upper pixel chip 201 stacked on the lower pixel chip 202. These chips are electrically connected by, for example, Cu-Cu bonding. Note that the connection may be performed using a via or a bump in addition to the Cu-Cu bonding.

[0136] An upper pixel array unit 221 is arranged in the upper pixel chip 201. A lower pixel array unit 222 and a column signal processing circuit 260 are arranged in the lower pixel chip 202. For each pixel in the pixel array unit 220, a portion of the pixel is arranged in the upper pixel array unit 221, and the remainder is arranged in the lower pixel array unit 222.

[0137] Furthermore, a vertical scanning circuit 211, a timing control circuit 212, a DAC 213, and a load MOS circuit block 250 are also arranged in the lower pixel chip 202. These circuits are omitted from the drawing.

[0138] Furthermore, the upper pixel chip 201 is manufactured, for example, by a pixel-dedicated process, and the lower pixel chip 202 is manufactured, for example, by a complementary MOS (CMOS) process.

[0139] Fig. 25 is a circuit diagram illustrating a configuration example of a pixel 300 according to the second modification example of the second embodiment of the present technology. In the pixel 300, the pre-stage circuit 310 is arranged in the upper pixel chip 201, and the other circuits and elements (such as the capacitor elements 321 and 322) are arranged in the lower pixel chip 202. Note that the current source transistor 316 may be further arranged in the lower pixel chip 202. As illustrated in the drawing, dispersing the elements in the pixel 300 in the upper pixel chip 201 and the lower pixel chip 202, which are stacked on top of each other, allows for a reduction in the pixel area, thereby enabling pixel miniaturization.

[0140] In this way, according to the second modification example of the second embodiment of the present technology, pixel miniaturization is enabled because the circuits and elements in the pixel 300 are distributed in the two semiconductor chips. [Third modification example]

[0141] In the second modification example of the second embodiment described above, a part of the pixel 300 and the peripheral circuits (such as the column signal processing circuit 260) are provided in the lower pixel chip 202 on the lower side. However, with this configuration, the arrangement area of ​​the circuits and elements on the lower pixel chip 202 side due to the peripheral circuit is larger than the arrangement area of ​​the upper pixel chip 201, and there is a possibility that unnecessary space without circuits and elements is generated in the upper pixel chip 201. A solid-state imaging element 200 of a third modification example of the second embodiment differs from the solid-state imaging element 200 of the second modification example of the second embodiment in that the circuits in the solid-state imaging element 200 are distributed among three semiconductor chips.

[0142] Fig. 26 is a view illustrating an example of a stacked structure of the solid-state imaging element 200 according to the third modification example of the second embodiment of the present technology. The solid-state imaging element 200 of the third modification example of the second embodiment includes the upper pixel chip 201, the lower pixel chip 202, and a circuit chip 203. These chips are stacked and electrically connected by, for example, Cu-Cu bonding. Note that the connection may be performed using a via or a bump in addition to the Cu-Cu bonding.

[0143] An upper pixel array unit 221 is arranged in the upper pixel chip 201. The lower pixel array unit 222 is arranged in the lower pixel chip 202. For each pixel in the pixel array unit 220, a portion of the pixel is arranged in the upper pixel array unit 221, and the remainder is arranged in the lower pixel array unit 222.

[0144] Furthermore, the column signal processing circuit 260, the vertical scanning circuit 211, the timing control circuit 212, the DAC 213, and the load MOS circuit block 250 are arranged in the circuit chip 203. Circuits other than the column signal processing circuit 260 are omitted from the drawing.

[0145] Using the three-layer configuration, as illustrated in the drawing, enables a reduction in unused space and further pixel miniaturization compared to the two-layer configuration. Furthermore, the lower pixel chip 202, which is the second layer, can be manufactured using a dedicated process for the capacitor and switch.

[0146] In this way, in the third modification example of the second embodiment of the present technology, since the circuits in the solid-state imaging element 200 are distributed in the three semiconductor chips, the pixel can be further miniaturized compared to a case where the circuits are distributed in the two semiconductor chips. <3. Third Embodiment>

[0147] In the second embodiment described above, the reset level is sampled and held during the exposure period, but this configuration prevents the exposure period from being shorter than the sample-and-hold period of the reset level. A solid-state imaging element 200 of this third embodiment differs from the solid-state imaging element 200 of the second embodiment in that a transistor that discharges charges from a photoelectric conversion element is added to shorten the exposure period.

[0148] Fig. 27 is a circuit diagram illustrating a configuration example of a pixel 300 according to the third embodiment of the present technology. The pixel 300 of the third embodiment differs from the pixel 300 of the second embodiment in that a discharge transistor 317 is further provided in the pre-stage circuit 310.

[0149] The discharge transistor 317 functions as an overflow drain that discharges charges from the photoelectric conversion element 311 according to a discharge signal ofg from the vertical scanning circuit 211. For example, nMOS transistors are used as the discharge transistor 317.

[0150] In a configuration where the discharge transistor 317 is not provided, as in the second embodiment, blooming may occur when charges are transferred from the photoelectric conversion element 311 for all pixels to the FD 314. Then, at the time of FD reset, the potential of the FD 314 and the potential of the pre-stage node 319 drop. In response to the potential drop, charge and discharge currents of the capacitor elements 321 and 322 continue to occur, and an IR drop of the power supply or ground changes from a steady state without blooming.

[0151] On the other hand, at the time of sampling and holding the signal levels of all pixels, after the signal charges are transferred, the photoelectric conversion element 311 has no charge, so blooming does not occur. An IR drop from the power supply or ground will enter the steady state without blooming. Stripe noise occurs due to a difference in the IR drop between the reset level and the signal level at the time of sampling and holding.

[0152] On the other hand, in the third embodiment, in which the discharge transistor 317 is provided, the charges in the photoelectric conversion element 311 are discharged to the overflow drain. Therefore, IR drops at the time of sampling and holding the reset level and the signal level become almost identical, so it is possible to suppress streaking noise.

[0153] Fig. 28 is a timing chart illustrating an example of a global shutter operation according to the third embodiment of the present technology. At a time T0 before the start of an exposure, the vertical scanning circuit 211 supplies a high-level FD reset signal rst to all pixels for the pulse period, while setting the discharge signal ofg to the high level for all pixels. Accordingly, PD reset and FD reset are performed for all pixels. Further, the reset level is sampled and held. Here, ofg_[n] in the drawing indicates signals to pixels in the nth row of the N rows.

[0154] Then, at time T1, which is the start of an exposure, the vertical scanning circuit 211 returns the discharge signal ofg for all pixels to the low level. Then, the vertical scanning circuit 211 supplies a high-level transfer signal trg to all pixels for a period from time T2 immediately before the end of an exposure to time T3 at the end of the exposure. Accordingly, the signal level is sampled and held.

[0155] In a configuration where the discharge transistor 317 is not provided, as in the second embodiment, both the transfer transistor 312 and the FD reset transistor 313 must be turned on at the beginning of an exposure (i.e., at the time of PD reset). With this control, at the time of PD reset, the FD 314 must also be reset at the same time. Therefore, it is necessary to perform the FD reset again within the exposure period and sample and hold the reset level, and the exposure period cannot be made shorter than the sample and hold period of the reset level. When sampling and holding the reset levels of all pixels, a certain waiting time is required until the voltage or current stabilizes, and a sample and hold period of, for example, several microseconds (µs) to several tens of microseconds (µs) is required.

[0156] On the other hand, in the third embodiment, in which the discharge transistor 317 is provided, the PD reset and the FD reset can be performed separately. Therefore, as illustrated in the drawing, it is possible to sample and hold the reset level by performing the FD reset before the PD reset is canceled (the start of an exposure). This allows the exposure period to be made shorter than the reset level holding period.

[0157] It is noted that the first to third modification examples of the second embodiment can also be applied to the third embodiment.

[0158] In this way, according to the third embodiment of the present technology, it is possible to sample and hold the reset level by performing FD reset before the start of an exposure because the discharge transistor 317 that discharges charges from the photoelectric conversion element 311 is provided. This allows the exposure period to be made shorter than the holding period of the reset level. <4. Fourth Embodiment>

[0159] In the second embodiment described above, the FD 314 is initialized with the power supply voltage VDD, but there is a possibility that this configuration may cause photoresponse non-uniformity (PRNU) deterioration due to variations in the capacitor elements 321 and 322 or parasitic capacitance. A solid-state imaging element 200 of this fourth embodiment differs from the solid-state imaging element 200 of the second embodiment in that the PRNU is improved by reducing the power supply to the FD reset transistor 313 during reading.

[0160] Fig. 29 is a circuit diagram illustrating a configuration example of a pixel 300 according to the fourth embodiment of the present technology. The pixel 300 of the fourth embodiment differs from the pixel 300 of the second embodiment in that the power supply of the FD reset transistor 313 is separated from the power supply voltage VDD of the pixel 300.

[0161] The FD reset transistor 313 of the fourth embodiment has a drain connected to a reset power supply voltage VRST. The reset power supply voltage VRST is controlled by, for example, the timing control circuit 212.

[0162] Here, deterioration of the PRNU in the pixel 300 of the second embodiment will be described with reference to Fig. 30 and Fig. 31. In the second embodiment, as shown in Fig. As illustrated in Figure 30, at a time T0 immediately before the start of an exposure, the potential of the FD 314 decreases due to a reset operation of the FD reset transistor 313. This variation is referred to as Vft.

[0163] In the second embodiment, since the power supply voltage of the FD reset transistor 313 is VDD, the potential of the FD 314 at time T0 varies from VDD to VDD - Vft. Furthermore, the potential of the pre-stage node 319 during one exposure becomes VDD - Vft - Vsig.

[0164] Furthermore, in the second embodiment, as in Fig. As illustrated in Figure 31, the FD reset transistor 313 enters the on state during reading to fix the FD 314 to the power supply voltage VDD. The potential of the pre-stage node 319 and the potential of the post-stage node 340 during reading are shifted upward by approximately the variation Vft of the FD 314. However, due to variations in the capacitance values ​​of the capacitor elements 321 and 322 or parasitic capacitance, the amount of shift voltage varies for each pixel, causing degradation of the PRNU.

[0165] The transition amount of the post-stage node 340, if the pre-stage node 319 transitions by Vft, is expressed by, for example, the following expression. {(Cs+δCs) / (Cs+δCs+Cp)} * Vft

[0166] In the above expression, Cs is a capacitance value of the capacitor element 322 on the signal level side, and δCs is a variation of Cs. Cp is a capacitance value of the parasitic capacitance of the post-stage node 340.

[0167] Expression 2 can be approximated by the following expression. {1−(δCs / Cs)*(Cp / Cs)} *Vft

[0168] From Expression 3, the variations of the post-stage node 340 can be expressed by the following expression. {(δCs / Cs)*(Cp / Cs)} *Vft

[0169] If (δCs / Cs) is set to 10 -2 is set, (Cp / Cs) to 10 -1 and Vft is set to 400 millivolts (mV), PRNU according to Expression 4 is 400 µVrms, which is a relatively large value.

[0170] In particular, to reduce kTC noise during sample-and-hold of an input conversion capacitance, it is necessary to increase the charge-to-voltage conversion efficiency of the FD 314. To increase the charge-to-voltage conversion efficiency, it is necessary to increase the capacitance of the FD 314, but the smaller the capacitance of the FD 314, the larger the variation Vft, which may be several hundred millivolts (mV). In this case, a PRNU influence according to Expression 6 may not be negligible.

[0171] Fig. 32 is a timing chart illustrating an example of voltage control according to the fourth embodiment of the present technology.

[0172] The timing control circuit 212 performs control to cause the reset power supply voltage VRST for the row-by-row read period after a time T9 to be different from the reset power supply voltage VRST for the exposure period.

[0173] For example, during the exposure period, the timing control circuit 212 sets the reset power supply voltage VRST to be identical to the power supply voltage VDD. On the other hand, during the read period, the timing control circuit 212 decreases the reset power supply voltage VRST to VDD - Vft. That is, during the read period, the timing control circuit 212 decreases the reset power supply voltage VRST by an amount approximately equal to the variation in Vft caused by a reset execution. Through this control, the reset level of the FD 314 can be made the same during exposure and during read.

[0174] Controlling the reset power supply voltage VRST, as illustrated in the drawing, enables reduction of variations in the voltage of the FD 314 and the pre-stage node 319. Therefore, it is possible to suppress variations in the capacitor elements 321 and 322 and deterioration of the PRNU due to parasitic capacitance.

[0175] It is noted that the first to third modification examples of the second embodiment or the third embodiment can also be applied to the fourth embodiment.

[0176] In this way, according to the fourth embodiment of the present technology, since the timing control circuit 212 reduces the reset power supply voltage VRST by the variation Vft caused by a reset during reading, it is possible to make the reset level during exposure and the reset level during reading identical. Therefore, it is possible to suppress deterioration of photoresponse non-uniformity (PRNU). <5. Fifth Embodiment>

[0177] In the second embodiment described above, the reset level and the signal level are read in this order for each frame, but there is a possibility that this configuration may cause deterioration of photoresponse unevenness (PRNU) due to variations in capacitor elements 321 and 322 or parasitic capacitance. A solid-state imaging element 200 of this fifth embodiment differs from the solid-state imaging element 200 of the second embodiment in that the PRNU is improved by switching between the level held in capacitor element 321 and the level held in capacitor element 322 for each frame.

[0178] The solid-state imaging element 200 of the fifth embodiment continuously captures multiple frames in synchronization with the vertical synchronization signal. An odd-numbered frame is referred to as an "odd frame," and an even-numbered frame is referred to as an "even frame."

[0179] Fig. 33 is a timing chart illustrating an example of a global shutter operation for odd frames according to the fifth embodiment. The pre-stage circuit 310 in the solid-state imaging element 200 sets the selection signal Φr and the selection signal Φs to the high level in this order within the exposure period of the odd frame, causing the capacitor element 321 to hold the reset level, and then causing the capacitor element 322 to hold the signal level.

[0180] Fig. 34 is a timing diagram illustrating an example of an odd-frame read operation according to the fifth embodiment of the present technology. The post-stage circuit 350 in the solid-state imaging element 200 sets the select signal Φr and the select signal Φs to the high level in this order to read the reset level and the signal level in this order within the odd-frame read period.

[0181] Fig. 35 is a timing chart illustrating an example of a global shutter operation for even frames according to the fifth embodiment. The pre-stage circuit 310 in the solid-state imaging element 200 sets the selection signal Φs and the selection signal Φr to the high level in this order within the exposure period of the even frame, causing the capacitor element 322 to hold the reset level, and then causing the capacitor element 321 to hold the signal level.

[0182] Fig. 36 is a timing diagram illustrating an example of an even-frame read operation according to the fifth embodiment of the present technology. The post-stage circuit 350 in the solid-state imaging element 200 sets the selection signal Φs and the selection signal Φr to the high level in this order to read the reset level and the signal level in this order within the even-frame read period.

[0183] As in Fig. 33 and Fig. As illustrated in Figure 35, the levels held in capacitor elements 321 and 322 are reversed between the even frame and the odd frame. Accordingly, the polarity of the PRNU is also reversed between even and odd frames. The column signal processing circuit 260 in the subsequent stage obtains an arithmetic mean of the odd frame and the even frame. Accordingly, it is possible to cancel PRNUs with opposite polarities.

[0184] This control is effective for capturing a moving image or summing individual images. Furthermore, it does not require adding an element to pixel 300 and can be achieved by simply changing a control system.

[0185] It is noted that the first to third modification examples of the second embodiment or the third and fourth embodiments can also be applied to the fifth embodiment.

[0186] In this way, according to the fifth embodiment of the present technology, since the level held in capacitor element 321 and the level held in capacitor element 322 are reversed between the odd frame and the even frame, the polarity of the PRNU can be reversed between the odd frame and the even frame. The column signal processing circuit 260 adds the odd frame and the even frame, making it possible to suppress PRNU degradation. <6. Sixth Embodiment>

[0187] In the second embodiment described above, the column signal processing circuit 260 obtains a difference between the reset level and the signal level for each column. However, this configuration may suffer from a block spot (black spot) phenomenon when very high-intensity light is incident on the pixel, in which a luminance increases due to overflow of charges from the photoelectric conversion element 311 and becomes black. A solid-state imaging element 200 of this sixth embodiment differs from the solid-state imaging element 200 of the second embodiment in that it is determined for each pixel whether the black spot phenomenon has occurred.

[0188] Fig. 37 is a circuit diagram illustrating a configuration example of a column signal processing circuit 260 according to the sixth embodiment of the present technology. In the column signal processing circuit 260 of the sixth embodiment, a plurality of ADCs 270 and a logic circuit 400 are arranged. Furthermore, a plurality of CDS processing units 291 and a plurality of selectors 292 are arranged in the logic circuit 400. The ADC 270, the CDS processing unit 291, and the selector 292 are provided for each column. Note that other circuits (the metadata extraction unit 404 and the like) in the logic circuit 400 are omitted from the drawing.

[0189] ADC 270 further includes a comparator 280 and a counter 271. Comparator 280 compares the level of vertical signal line 309 with the ramp signal Rmp from DAC 213 and outputs a comparison result VCO. The comparison result VCO is provided to counter 271 and timing control circuit 212. Comparator 280 includes a selector 281, capacitor elements 282 and 283, autozero switches 284 and 286, and a comparator element 285.

[0190] The selector 281 connects either the vertical signal line 309 of the corresponding column or a node of a predetermined reference voltage VREF via the capacitor element 282 to a non-inverting input terminal (+) of the comparator element 285 according to an input side selection signal selin. The input side selection signal selin is provided by the timing control circuit 212. Note that the selector 281 is an example of an input side selector described in the claims.

[0191] The comparator element 285 compares a level of the non-inverting input terminal (+) with a level of an inverting input terminal (-) and outputs the comparison result VCO to the counter 271. The ramp signal Rmp is input to the inverting input terminal (-) via the capacitor element 283.

[0192] The autozero switch 284 shorts the non-inverting input terminal (+) and an output terminal of the comparison result VCO according to an autozero signal Az from the timing control circuit 212. The autozero switch 286 shorts the inverting input terminal (-) and the output terminal of the comparison result VCO according to the autozero signal Az.

[0193] The counter 271 counts a count value over one period until the comparison result VCO is inverted and outputs a digital signal CNT_out indicating the count value to the CDS processing unit 291.

[0194] The CDS processing unit 291 performs CDS processing on the digital signal CNT_out. The CDS processing unit 291 calculates a difference between the digital signal CNT_out corresponding to the reset level and the digital signal CNT_out corresponding to the signal level and outputs the difference as CDS_out to the selector 292.

[0195] Selector 292 outputs either the digital signal CDS_out that has undergone CDS processing or a digital full code signal FULL as pixel data of the corresponding column, in accordance with an output page selection signal selout from timing control circuit 212. Note that selector 292 is an example of an output page selector described in the claims.

[0196] Fig. 38 is a timing diagram illustrating an example of a global shutter operation according to the sixth embodiment of the present technology. A method for controlling transistors at the time of a global shutter in the sixth embodiment is similar to the method in the second embodiment.

[0197] Here, it is assumed that very high-intensity light is incident on the pixel 300. In this case, the photoelectric conversion element 311 becomes full of charges, and the charges overflow from the photoelectric conversion element 311 to the FD 314, causing a decrease in the potential of the FD 314, which undergoes FD reset. A long-short-dashed line in the drawing indicates variations in the potential of the FD 314 when weak sunlight is incident, causing a relatively small amount of charges to overflow. A dotted line in the drawing indicates variations in the potential of the FD 314 when strong sunlight is incident, causing a relatively large amount of charges to overflow.

[0198] When weak sunlight is incident, the reset level drops at a time T3 when the FD reset is completed, but the level does not drop completely at this time.

[0199] On the other hand, when strong sunlight is incident, the reset level drops completely at time T3. In this case, the signal level becomes equal to the reset level, and the potential difference between the signal level and the reset level becomes "0," so the digital signal that has undergone CDS processing becomes like a digital signal in a dark state and fades to black. Thus, a phenomenon in which the pixel turns black despite very high-intensity light is called a black spot phenomenon or blooming.

[0200] Furthermore, if the level of the FD 314 of the pixel where the black spot phenomenon has occurred is too low, the operating point of the pre-stage circuit 310 cannot be ensured, and the current id1 of the current source transistor 316 varies accordingly. Since the current source transistor 316 of each pixel is connected to a common power supply or ground, when a certain pixel experiences current variations, variations in the IR drop in that pixel affect the sampling level of another pixel. A pixel experiencing the black spot phenomenon becomes an aggressor, and a pixel whose sampling level fluctuates due to the pixel becomes a victim. As a result, streaking noise occurs.

[0201] Note that if the discharge transistor 317 is provided as in the third embodiment, in a pixel experiencing a blooming, overflow charges are discharged to the discharge transistor 317, so the black spot phenomenon is less likely to occur. However, if the discharge transistor 317 is provided, some charges may flow to the FD 314, and the black spot phenomenon may be difficult to completely eliminate. Furthermore, there is also a drawback that a ratio of the effective area / charge amount for each pixel decreases due to the addition of the discharge transistor 317. Therefore, it is desirable to suppress the black spot phenomenon without using the discharge transistor 317.

[0202] As a method for suppressing the black spot phenomenon without using the discharge transistor 317, there are two possible methods. The first is to adjust a clipping level of the FD 314. The second is to determine whether the black spot phenomenon has occurred during reading, and if the black spot phenomenon has occurred, the output is replaced with the full code.

[0203] Regarding the first method, the high level of the FD reset signal rst (in other words, the gate of the FD reset transistor 313) in the drawing corresponds to the power supply voltage VDD, and the low level corresponds to the clipping level of the FD 314. In the first embodiment, a difference between the high level and the low level (i.e., the amplitude) is set to a value corresponding to a dynamic range. In contrast, in the sixth embodiment, the value is adjusted to a value that further adds a margin to this value. Here, the value corresponding to the dynamic range corresponds to a difference between the power supply voltage VDD and the potential of the FD 314 when the digital signal becomes the full code.

[0204] Decreasing the gate voltage (the low level of the FD reset signal rst) when the FD reset transistor 313 is off makes it possible to prevent the FD 314 from being excessively decreased due to blooming and the operating point of the pre-stage amplification transistor 315 from being lost.

[0205] Note that the dynamic range varies depending on the analog gain of the ADC. When the analog gain is low, a large dynamic range is required; conversely, when the analog gain is high, a small dynamic range is required. Therefore, it is possible to change the gate voltage when the FD reset transistor 313 is off according to the analog gain.

[0206] Fig. 39 is a timing chart illustrating an example of a read operation according to the sixth embodiment of the present technology. When the selection signal Φr becomes high at a time T11 immediately after a time T10, which is the start of reading, the potential of the vertical signal line 309 varies in the pixel to which sunlight is incident. A long-short dashed line in the drawing indicates variations in the potential of the vertical signal line 309 when weak sunlight is incident. A dotted line in the drawing indicates variations in the potential of the vertical signal line 309 when strong sunlight is incident.

[0207] For example, in an auto-zero period from time T10 to time T12, the timing control circuit 212 provides the input side selection signal selin of "0" to connect the comparator element 285 to the vertical signal line 309. Within this auto-zero period, the timing control circuit 212 performs auto-zeroing using the auto-zero signal Az.

[0208] Regarding the second method, for example, the timing control circuit 212 provides the input side selection signal selin of "1" within a determination period from time T12 to time T13. The input side selection signal selin disconnects the comparator element 285 from the vertical signal line 309 and connects the comparator element 285 to the reference voltage node VREF. The reference voltage VREF is set to an expected value of the level of the vertical signal line 309 when no blooming occurs. For example, if the gate-source voltage of the post-stage amplification transistor 351 is designated as Vgs2, Vrst corresponds to Vreg - Vgs2. Furthermore, the DAC 213 decreases the level of the ramp signal Rmp from Vrmp_az to Vrmp_sun within the determination period.

[0209] Furthermore, if blooming does not occur within the determination period, the reset level Vrst of the vertical signal line 309 is almost equal to the reference voltage VREF and is not much different from when the potential of the inverting input terminal (+) of the comparator element 285 is autozero. On the other hand, since the non-inverting input terminal (-) is lowered from Vrmp_az to Vrmp_sun, the comparison result VCO becomes high.

[0210] In contrast, if blooming occurs, the reset level Vrst becomes sufficiently higher than the reference voltage VREF, and the comparison result VCO becomes the low level when the following expression is satisfied. Vrst - VREF > Vrmp_az - Vrmp_sun

[0211] That is, the timing control circuit 212 can determine whether blooming has occurred or not based on whether or not the comparison result VCO becomes the low level within the determination period.

[0212] It is noted that it is necessary to ensure a certain large margin for sun determination (the right side of Expression 5) so as to prevent erroneous determination due to variations in the threshold voltage of the post-stage amplification transistor 351, IR drop differences of the in-plane Vreg, or the like.

[0213] After a time T13, after the determination period has elapsed, the timing control circuit 212 connects the comparator element 285 to the vertical signal line 309. Further, after a P-phase settling period from time T13 to time T14 has elapsed, the P-phase is read within a period from time T14 to time T15. After a D-phase settling period from time T15 to time T19 has elapsed, the D-phase is read within a period from time T19 to time T20.

[0214] If it is determined that no blooming has occurred during the determination period, the timing control circuit 212 controls the selector 292 according to the output side selection signal selout to output the digital signal CDS_out that has undergone the CDS processing as it is.

[0215] On the other hand, if it is determined that blooming has occurred during the determination period, the timing control circuit 212 controls the selector 292 according to the output page selection signal selout to output the full code FULL instead of the digital signal CDS_out that has undergone CDS processing. Therefore, it is possible to suppress the black spot phenomenon.

[0216] It is noted that the first to third modification examples of the second embodiment or the third to fifth embodiments can also be applied to the sixth embodiment.

[0217] In this way, according to the sixth embodiment of the present technology, it is possible to suppress the black spot phenomenon because the timing control circuit 212 determines whether the black spot phenomenon has occurred or not based on the comparison result VCO and outputs the full code when the black spot phenomenon has occurred. <7. Seventh Embodiment>

[0218] In the second embodiment described above, the vertical scanning circuit 211 performs control for simultaneously exposing all lines (all pixels) (i.e., the global shutter operation). However, if simultaneity of exposure is not required but low noise is required, such as during a test or analysis, it is desirable to perform a rolling shutter operation. A solid-state imaging element 200 of this seventh embodiment differs from the solid-state imaging element 200 of the second embodiment in that the rolling shutter operation is performed during a test or the like.

[0219] Fig. Figure 40 is a timing chart illustrating an example of a rolling shutter operation according to the seventh embodiment of the present technology. The vertical scanning circuit 211 performs control to sequentially select multiple lines and start exposure. This drawing illustrates exposure control of the nth line.

[0220] During the period from time T0 to time T2, the vertical scanning circuit 211 supplies a high-level post-stage selection signal selb, the high-level selection signal Φr, and the high-level selection signal Φs to the n-th line. Furthermore, at time T0, which is the start of an exposure, the vertical scanning circuit 211 supplies a high-level FD reset signal rst and the high-level post-stage reset signal rstb to the n-th line over the pulse period. The vertical scanning circuit 211 supplies the transfer signal trg to the n-th line at time T1 at the end of the exposure. The rolling shutter operation in the drawing enables the imaging element 200 to generate low-noise image data. It is noted that it is assumed that the two times of AD conversion and metadata extraction described in the first embodiment are not performed in the rolling shutter operation of the drawing.

[0221] It is noted that during normal imaging, the solid-state imaging element 200 of the seventh embodiment performs the global shutter operation in a manner similar to the second embodiment.

[0222] Furthermore, the first to third modification examples of the second embodiment or the third to sixth embodiments can also be applied to the seventh embodiment.

[0223] In this way, according to the seventh embodiment of the present technology, it is possible to generate low-noise image data because the vertical scanning circuit 211 performs control for sequentially selecting a plurality of lines and starting an exposure (i.e., the rolling shutter operation). <8. Eighth Embodiment>

[0224] In the second embodiment described above, the source of the pre-stage source follower (pre-stage amplification transistor 315 and current source transistor 316) is connected to the power supply voltage VDD, and row-by-row reading is performed with the source follower in the on state. However, there is a possibility that this driving method causes circuit noise of the pre-stage source follower to propagate to the subsequent stages during row-by-row reading, and random noise increases accordingly. A solid-state imaging element 200 of this eighth embodiment differs from the solid-state imaging element 200 of the first embodiment in that the pre-stage source follower is turned off during reading to reduce noise.

[0225] Fig. 41 is a block diagram illustrating a configuration example of the solid-state imaging element 200 according to the eighth embodiment of the present technology. The solid-state imaging element 200 of the eighth embodiment differs from the solid-state imaging element 200 of the second embodiment in that a regulator 420 and a switching unit 440 are further provided. Furthermore, in the pixel array unit 220 of the eighth embodiment, a plurality of effective pixels 301 and a predetermined number of dummy pixels 430 are arranged. The dummy pixels 430 are arranged around an area where the effective pixels 301 are arranged.

[0226] Furthermore, the power supply voltage VDD is supplied to each of the dummy pixels 430, and the power supply voltage VDD and a source voltage Vs are supplied to each of the effective pixels 301. A signal line through which the power supply voltage VDD is supplied to the effective pixels 301 is omitted from the drawing. Furthermore, the power supply voltage VDD is supplied from a pad 415 located outside the solid-state imaging element 200.

[0227] The regulator 420 generates a constant voltage V gen based on an input potential Vi from the dummy pixel 430 and provides the generated voltage V gen to the switching unit 440. The switching unit 440 selects either the power supply voltage VDD from the pad 415 or the generated voltage V genfrom the regulator 420 and supplies the selected voltage as the source voltage Vs to each of the columns of the effective pixels 301.

[0228] Fig. 42 is a circuit diagram illustrating a configuration example of the dummy pixel 430, the regulator 420, and the switching unit 440 according to the eighth embodiment of the present technology. In the drawing, a indicates a circuit diagram of the dummy pixel 430 and the regulator 420, and b indicates a circuit diagram of the switching unit 440.

[0229] As illustrated in a of the drawing, the dummy pixel 430 includes a reset transistor 431, an FD 432, an amplification transistor 433, and a current source transistor 434. The reset transistor 431 initializes the FD 432 according to a reset signal RST from the vertical scanning circuit 211. The FD 432 accumulates charges and generates a voltage corresponding to an amount of charge. The amplification transistor 433 amplifies a voltage level of the FD 432 and supplies the amplified voltage as the input voltage Vi to the regulator 420.

[0230] Furthermore, reset transistor 431 and amplification transistor 433 have their respective sources connected to the power supply voltage VDD. Current source transistor 434 is connected to a drain of amplification transistor 433. Current source transistor 434 provides current id1 under the control of vertical scanning circuit 211.

[0231] The regulator 420 includes a low-pass filter 421, a buffer amplifier 422, and a capacitor element 423. The low-pass filter 421 passes, as an output voltage Vj, a component in a low-frequency band below a predetermined frequency from a signal of the input voltage Vi.

[0232] The output voltage Vj is input to a non-inverting input terminal (+) of the buffer amplifier 422. An inverting input terminal (-) of the buffer amplifier 422 is connected to an output terminal of the buffer amplifier 422. The capacitor element 423 holds a voltage of the output terminal of the buffer amplifier 422 as V gen . This V gen is supplied to the switching unit 440.

[0233] As illustrated in b of the drawing, the switching unit 440 includes an inverter 441 and a plurality of switching circuits 442. The switching circuits 442 are each arranged for a corresponding one of the columns of the effective pixels 301.

[0234] The inverter 441 inverts a switching signal SW sent from the timing control circuit 212. The inverter 441 supplies the inverted signal to each of the switching circuits 442.

[0235] The switching circuit 442 selects either the power supply voltage VDD or the generated voltage V genand supplies the selected voltage as the source voltage Vs to the corresponding column in the pixel array unit 220. The switching circuit 442 includes switches 443 and 444. The switch 443 opens and closes a path between the node of the power supply voltage VDD and the corresponding column according to the switching signal SW. The switch 444 opens and closes a path between the node of the generated voltage V gen and the corresponding column according to the inverted signal of the switching signal SW.

[0236] Fig. 43 is a timing diagram illustrating an example of how the dummy pixel 430 and the regulator 420 operate according to the eighth embodiment of the present technology. At a time T10 immediately before reading a certain line, the vertical scanning circuit 211 supplies a high-level reset signal RST (here, the power supply voltage VDD) to each of the dummy pixels 430. A potential Vfd of the FD 432 in the dummy pixel 430 is initialized to the power supply voltage VDD. When the reset signal RST becomes low, then a reset execution causes a change to VDD - Vft.

[0237] Furthermore, the input voltage Vi decreases to VDD - Vgs - Vsig after the reset. By passing through the low-pass filter 421, Vj and V gen to approximately constant voltages.

[0238] After a time T20 immediately before reading the next line, a similar control is performed for each line and the constant generated voltage V gen is provided.

[0239] Fig. 44 is a circuit diagram illustrating a configuration example of the effective pixel 301 according to the eighth embodiment of the present technology. The effective pixel 301 is similar in circuit configuration to the pixel 300 of the second embodiment, except that the source voltage Vs is supplied from the switching unit 440 to the source of the pre-stage amplification transistor 315.

[0240] Fig. 45 is a timing diagram illustrating an example of a global shutter operation according to the eighth embodiment of the present technology. In the eighth embodiment, when all pixels are exposed simultaneously, the switching unit 440 selects the power supply voltage VDD and provides the power supply voltage VDD as the source voltage Vs. Further, at time T4, the voltage of the pre-stage node decreases from VDD - Vgs - Vth to VDD - Vgs - Vsig. Here, Vth represents a threshold voltage of the transfer transistor 312.

[0241] Fig. Fig. 46 is a timing diagram illustrating an example of a read operation according to the eighth embodiment of the present technology. In the eighth embodiment, the switching unit 440 selects the generated voltage V during reading. gen and sets the generated voltage V genthan the source voltage Vs. The generated voltage V gen is adjusted to VDD - Vgs - Vft. Furthermore, in the eighth embodiment, the vertical scanning circuit 211 controls the current source transistors 316 of all rows (all pixels) to stop supplying the current id1.

[0242] Fig. 47 is a diagram for describing effects according to the eighth embodiment of the present technology. In the first embodiment, the source follower (pre-stage amplification transistor 315 and current source transistor 316) of the pixel 300 to be read is turned on during row-by-row reading. However, there is a possibility that this driving method causes circuit noise of the pre-stage source follower to propagate to the subsequent stages (capacitor element and post-stage source follower and ADC), and read noise increases accordingly.

[0243] For example, in the second embodiment, as illustrated in the drawing, kTC noise generated in one pixel during the global shutter operation is 450 (µVrms). Furthermore, noise generated in the pre-stage source follower (the pre-stage amplification transistor 315 and the current source transistor 316) during row-by-row reading is 380 (µVrms). Noise generated in the post-stage source follower and subsequent stages is 160 (µVrms). Therefore, the total noise is 610 (µVrms). Thus, in the second embodiment, a proportion of the pre-stage source follower noise to the total noise becomes relatively large.

[0244] To reduce the noise of the pre-stage source follower in the eighth embodiment, the adjustable voltage (Vs) is supplied to the source of the pre-stage source follower, as described above. During the global shutter (exposure) operation, the switching unit 440 selects the power supply voltage VDD and provides the selected power supply voltage as the source voltage Vs. Then, after the end of the exposure, the switching unit 440 switches the source voltage Vs to VDD - Vgs - Vft. Furthermore, the timing control circuit 212 turns on the pre-stage current source transistor 316 during the global shutter (exposure) operation and turns off the pre-stage current source transistor 316 after the end of the exposure.

[0245] As in Fig. 45 and Fig. As illustrated in Figure 46, the previously described control makes the potential of the pre-stage node identical during the global shutter operation and the potential during row-by-row reading, thus enabling an improvement in the PRNU. Furthermore, since the pre-stage source follower is in the off state during row-by-row reading, no source follower circuit noise occurs and becomes zero (µVrms), as shown in Fig. 47. Note that in the pre-stage source follower, the pre-stage amplification transistor 315 is in the on state.

[0246] In this way, according to the eighth embodiment of the present technology, noise generated in the source follower can be reduced because the pre-stage source follower is brought into the off state during reading. <9. Application example for a mobile body>

[0247] The technology according to the present disclosure (the present technology) is applicable to various products. For example, the technology according to the present disclosure can also be implemented as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an aircraft, a drone, a ship, and a robot.

[0248] Fig. 48 is a block diagram illustrating a schematic configuration example of a vehicle control system, which is an example of a mobile body control system to which the technology according to the present disclosure can be applied.

[0249] The vehicle control system 12000 includes several electronic control units that are interconnected via a communication network 12001. In the Fig. 48, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, a vehicle exterior information detection unit 12030, a vehicle interior information detection unit 12040, and an integrated control unit 12050. Further, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound / image output section 12052, and an in-vehicle network interface (SST) 12053 are illustrated.

[0250] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various types of programs. For example, the drive system control unit 12010 functions as a control device for a driving force generating device for generating the driving force of the vehicle, such as an internal combustion engine, a drive motor, or the like, a driving force transmitting mechanism for transmitting the driving force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating the braking force of the vehicle, and the like.

[0251] The body system control unit 12020 controls the operation of various types of devices provided for a vehicle body according to various types of programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various types of lights such as a headlight, a reversing light, a brake light, a turn signal, a fog light, or the like. In this case, radio waves transmitted from a mobile device as an alternative to a key or signals from various types of switches can be input to the body system control unit 12020.The body system control unit 12020 receives these input radio waves or signals and controls a door locking device, the power window device, the lights or the like of the vehicle.

[0252] The vehicle exterior information detection unit 12030 detects information about the exterior of the vehicle, including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to an imaging section 12031. The vehicle exterior information detection unit 12030 causes the imaging section 12031 to capture an image of the exterior of the vehicle and receives the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can perform processing for detecting an object such as a person, a vehicle, an obstacle, a sign, a symbol on a road surface, or the like, or processing for detecting a distance thereto.

[0253] The imaging section 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging section 12031 can output the electrical signal as an image or can output the electrical signal as information about a measured distance. Furthermore, the light received by the imaging section 12031 can be visible light or can be non-visible light, such as infrared rays or the like.

[0254] The vehicle interior information detection unit 12040 detects information about the interior of the vehicle. The vehicle interior information detection unit 12040 is connected, for example, to a driver state detection section 12041 that detects the state of a driver. The driver state detection section 12041 includes, for example, a camera that records the driver. Based on detection information input from the driver state detection section 12041, the vehicle interior information detection unit 12040 can calculate a driver's fatigue level or a driver's concentration level, or can determine whether the driver is dozing.

[0255] The microcomputer 12051 may calculate a control target value for the driving force generating device, the steering mechanism, or the braking device based on the information about the interior or exterior of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output a control command to the drive system control unit 12010.For example, the microcomputer 12051 may perform cooperative control to implement functions of an Advanced Driver Assistance System (ADAS), which functions include collision avoidance or impact mitigation for the vehicle, following travel based on a following distance, speed maintenance travel, warning of a collision of the vehicle, warning of the vehicle leaving a lane, or the like.

[0256] In addition, the microcomputer 12051 can perform cooperative control intended for automated driving, which makes the vehicle drive automatically without depending on the driver's operation or the like, by controlling the driving force generating device, the steering mechanism, the braking device, or the like based on the information about the exterior or interior of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040.

[0257] Furthermore, the microcomputer 12051 may output a control command to the body system control unit 12020 based on the vehicle exterior information detected by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 may perform cooperative control to prevent glare by controlling the headlight to switch from, for example, a high beam to a low beam according to the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 12030.

[0258] The audio / video output section 12052 transmits an audio and / or video output signal to an output device capable of visually or acoustically communicating information to a vehicle occupant or the vehicle exterior. In the example of Fig. 48 illustrates an audio speaker 12061, a display section 12062, and a dashboard 12063 as the output device. The display section 12062 may include, for example, an onboard display and / or a head-up display.

[0259] Fig. 49 is a diagram illustrating an example of the installation position of the imaging section 12031.

[0260] In Fig. 49, the imaging section 12031 includes imaging sections 12101, 12102, 12103, 12104 and 12105.

[0261] The imaging sections 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions on a front nose, side mirrors, a rear bumper, and a rear door of the vehicle 12100, as well as a position on an upper part of a windshield within the interior of the vehicle. The imaging section 12101 provided at the front nose and the imaging section 12105 provided at the upper part of the windshield within the interior of the vehicle mainly obtain an image of the front of the vehicle 12100. The imaging sections 12102 and 12103 provided at the side mirrors mainly obtain an image of the sides of the vehicle 12100. The imaging section 12104 provided at the rear bumper or rear door mainly obtains an image of the rear of the vehicle 12100.The imaging section 12105 provided on the upper part of the windshield within the interior of the vehicle is mainly used for detecting a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.

[0262] It is noted that Fig. 49 illustrates an example of imaging areas of the imaging sections 12101 to 12104. An imaging area 12111 represents the imaging area of ​​the imaging section 12101 provided at the front nose. Imaging areas 12112 and 12113 represent the imaging areas of the imaging sections 12102 and 12103 provided at the side mirrors, respectively. An imaging area 12114 represents the imaging area of ​​the imaging section 12104 provided at the rear bumper or the tailgate. A bird's-eye view image of the vehicle 12100 as viewed from above is obtained, for example, by superimposing image data obtained by the imaging sections 12101 to 12104.

[0263] At least one of the imaging sections 12101 to 12104 may have a function for obtaining distance information. For example, at least one of the imaging sections 12101 to 12104 may be a stereo camera consisting of multiple imaging elements, or may be an imaging element with pixels for phase difference detection.

[0264] For example, the microcomputer 12051 may determine a distance to each three-dimensional object within the imaging areas 12111 to 12114 and a temporal change of the distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging sections 12101 to 12104, and thereby extract, as a preceding vehicle, specifically, a next three-dimensional object that exists in a moving path of the vehicle 12100 and that moves in substantially the same direction as the vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km / h).Furthermore, the microcomputer 12051 can set a following distance to be kept with a preceding vehicle in advance and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), or the like. Accordingly, it is possible to perform cooperative control intended for automated driving, which allows the vehicle to travel automatically without depending on the driver's operation or the like.

[0265] For example, the microcomputer 12051 can classify three-dimensional object data about three-dimensional objects into three-dimensional object data of a two-wheeled vehicle, a standard-size vehicle, a large-size vehicle, a pedestrian, a utility pole, and other three-dimensional objects based on the distance information obtained from the imaging sections 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data to automatically avoid an obstacle. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can visually recognize and obstacles that are difficult for the driver of the vehicle 12100 to visually recognize. Then, the microcomputer 12051 determines a collision risk that indicates a risk of collision with each obstacle.In a situation where the collision risk is equal to or higher than a set value and accordingly there is a possibility of a collision, the microcomputer 12051 issues a warning to the driver through the audio speaker 12061 or the display section 12062 and performs forced deceleration or evasive steering through the drive system control unit 12010. The microcomputer 12051 can thereby assist driving to avoid a collision.

[0266] At least one of the imaging sections 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may detect a pedestrian by determining whether or not there is a pedestrian in captured images of the imaging sections 12101 to 12104. Such detection of a pedestrian is performed, for example, by a process for extracting characteristic points in the captured images of the imaging sections 12101 to 12104 as infrared cameras and a process for determining whether or not the pedestrian exists by performing pattern matching processing on a series of characteristic points representing the outline of the object.When the microcomputer 12051 determines that there is a pedestrian in the captured images of the imaging sections 12101 to 12104 and accordingly detects the pedestrian, the audio / video output section 12052 controls the display section 12062 to display a square outline for highlighting, superimposed on the detected pedestrian. The audio / video output section 12052 can also control the display section 12062 to display an icon or the like representing the pedestrian at a desired position.

[0267] An example of the vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging section 12031 under the configurations described above. Specifically, for example, the imaging device 100 in Fig.1 to the imaging section 12031. By applying the technology according to the present disclosure to the imaging section 12031, it is possible to obtain a captured image that is easier to view, thereby making it possible to reduce driver fatigue.

[0268] It should be noted that the above-described embodiments are examples for implementing the present technology, and the items in the embodiments and the items used to specify the invention in the claims have a correspondence relationship. Likewise, there is a correspondence relationship between the items specifying the invention in the claims and the items in the embodiments of the present technology with the same names. However, the present technology is not limited to the embodiments and can be modified by applying various modifications to the embodiments without departing from the essence thereof.

[0269] It is noted that the effects described in this document are merely examples and are not limiting, and other effects may also be present.

[0270] It is noted that the present technology may also have the following configuration. (1) A solid-state imaging element comprising: a plurality of pixels, each provided with a sample-and-hold circuit that holds a pixel signal; a signal processing unit that generates a first digital signal by performing signal processing on each of the held pixel signals and generates a second digital signal by performing the signal processing on each of the held pixel signals; a metadata extraction unit that extracts predetermined metadata from the first digital signal; and an image processing unit that performs predetermined image processing on the second digital signal using the metadata. (2) The solid-state imaging element according to (1), wherein the metadata extraction unit performs recognition processing for recognizing a predetermined object in a frame in which the first digital signals are arranged, and generates data indicating a result of the recognition processing as the metadata. (3) The solid-state imaging element according to (1) or (2), wherein the metadata specifies a predetermined area, and the image processing unit performs processing for replacing a color in the area with a specific color. (4) The solid-state imaging element according to (1) or (2), wherein the metadata specifies a predetermined area, and the image processing unit performs mosaic processing on the area. (5) The solid-state imaging element according to (1) or (2), wherein the metadata indicates a predetermined area, and the image processing unit extracts the area as an area of ​​interest from a single image in which the second digital signals are arranged. (6) The solid-state imaging element according to any one of (1) to (5), wherein each of the plurality of pixels includes: a pre-stage circuit that generates a pixel signal; a sample-and-hold circuit that holds the pixel signal; and a post-stage circuit that reads the pixel signal from the sample-and-hold circuit and outputs the read pixel signal. (7) The solid-state imaging element according to (6), wherein the sample-and-hold circuit includes: a first and second capacitor element; and a selection circuit that sequentially performs control for connecting one of the first and second capacitor elements to a predetermined post-stage node and control for connecting another of the first and second capacitor elements to the post-stage node. (8) The solid-state imaging element according to (7), wherein the selection circuit sequentially performs control for connecting one of the first and second capacitor elements to a predetermined post-stage node, control for disconnecting both the first and second capacitor elements from the post-stage node, and control for connecting another of the first and second capacitor elements to the post-stage node. (9) The solid-state imaging element according to (8), wherein each of the plurality of pixels further includes a post-stage reset transistor that initializes a level of the post-stage node when both the first and second capacitor elements are disconnected from the post-stage node. (10) An imaging device comprising: a plurality of pixels, each provided with a sample-and-hold circuit that holds a pixel signal; a signal processing unit that generates a first digital signal by performing signal processing on each of the held pixel signals and generates a second digital signal by performing the signal processing on each of the held pixel signals; a metadata extraction unit that extracts predetermined metadata from the first digital signal; an image processing unit that performs predetermined image processing on the second digital signal using the metadata; and a recording unit that records a frame in which the second digital signals subjected to processing are arranged. (11) A method of controlling a solid-state imaging element, the method comprising: a signal processing procedure in which an analog-to-digital conversion unit generates a first digital signal by performing signal processing on a pixel signal held in each of a plurality of pixels each provided with a sample-and-hold circuit that holds the pixel signal, and generates a second digital signal by performing the signal processing on each of the held pixel signals; a metadata extraction procedure in which a metadata extraction unit extracts predetermined metadata from the first digital signal; and an image signal processing procedure in which an image processing unit performs predetermined image processing on the second digital signal using the metadata. LIST OF REFERENCE SYMBOLS 100 imaging device 110 imaging lens 120 recording unit 130 Imaging control unit 200 solid-state imaging elements 201 Upper pixel chip 202 Lower pixel chip 203 circuit chip 211 Vertical scan circuit 212 Timing control circuit 213 DAC 220 pixel array unit 221 Upper pixel array unit 222 Lower pixel array unit 250 load MOS circuit block 251 Load MOS transistor 260 column signal processing circuit 261 Signal processing unit 262, 270 ADC 271 counters 280 Comparator 281, 292 Selector 282, 283, 321, 322 capacitor element 284, 286 Autozero switch 285 Comparator element 291 CDS processing unit 300 pixels 301 Effective Pixels 310 Preamplifier circuit 311 Photoelectric conversion element 312 transfer transistor 313 FD reset transistor 314 FD 315 Preamplifier transistor 316 current source transistor 317 discharge transistor 320 Sample-and-hold circuit 323 Pre-stage reset transistor 324 Pre-stage selection transistor 330 selection circuit 331, 331-1, 331-2, 332, 332-1, 332-2 selection transistor 333 sampling transistor 341 Post-stage reset transistor 350, 350-1, 350-2 post-stage circuit 351, 351-1, 351-2 post-stage amplification transistor 352, 352-1, 352-2 post-stage selection transistor 400 logic circuit 401 column interface 402 Image processing unit 403 ISP circuit 404 Metadata Extraction Unit 405 RAM 410 high-speed interface 420 controllers 421 Low-pass filter 422 buffer amplifier 423 Capacitor element 430 dummy pixels 431 Reset transistor 432 FD 433 amplification transistor 434 Current source transistor 440 switching unit 441 Inverter 442 circuit 443, 444 switches 12031 Imaging Section QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2020-054007

[0003]

Claims

[1] Solid-state imaging element comprising: a plurality of pixels, each provided with a sample-and-hold circuit that holds a pixel signal; a signal processing unit that generates a first digital signal by performing signal processing on each of the held pixel signals and generates a second digital signal by performing the signal processing on each of the held pixel signals; a metadata extraction unit that extracts predetermined metadata from the first digital signal; and an image processing unit that performs predetermined image processing on the second digital signal using the metadata. [2] The solid-state imaging element according to claim 1, wherein the metadata extraction unit performs recognition processing for recognizing a predetermined object in a frame in which the first digital signals are arranged, and generates data indicating a result of the recognition processing as the metadata. [3] The solid-state imaging element according to claim 1, wherein the metadata indicates a predetermined area, and the image processing unit performs processing for replacing a color in the area with a specific color. [4] The solid-state imaging element according to claim 1, wherein the metadata indicates a predetermined region, and the image processing unit performs mosaic processing on the region. [5] The solid-state imaging element according to claim 1, wherein the metadata indicates a predetermined region, and the image processing unit extracts the region as a region of interest from a frame in which the second digital signals are arranged. [6] The solid-state imaging element of claim 1, wherein each of said plurality of pixels includes: a pre-stage circuit that generates a pixel signal; a sample-and-hold circuit that holds the pixel signal; and a post-stage circuit that reads the pixel signal from the sample-and-hold circuit and outputs the read pixel signal. [7] A solid-state imaging element according to claim 6, wherein the sample-and-hold circuit includes: a first and second capacitor element; and a selection circuit that sequentially performs control for connecting one of the first and second capacitor elements to a predetermined post-stage node and control for connecting another of the first and second capacitor elements to the post-stage node. [8] A solid-state imaging element according to claim 7, wherein the selection circuit sequentially performs control for connecting one of the first and second capacitor elements to a predetermined post-stage node, control for disconnecting both the first and second capacitor elements from the post-stage node, and control for connecting another of the first and second capacitor elements to the post-stage node. [9] The solid-state imaging element of claim 8, wherein each of the plurality of pixels further includes a post-stage reset transistor that initializes a level of the post-stage node when both the first and second capacitor elements are disconnected from the post-stage node. [10] Imaging device comprising: a plurality of pixels, each provided with a sample-and-hold circuit that holds a pixel signal; a signal processing unit that generates a first digital signal by performing signal processing on each of the held pixel signals and generates a second digital signal by performing the signal processing on each of the held pixel signals; a metadata extraction unit that extracts predetermined metadata from the first digital signal; an image processing unit that performs predetermined image processing on the second digital signal using the metadata; and a recording unit that records a frame in which the second digital signals subjected to processing are arranged. [11] A method of controlling a solid-state imaging element, the method comprising: an analog-to-digital conversion procedure in which an analog-to-digital conversion unit generates a first digital signal by performing signal processing on a pixel signal held in each of a plurality of pixels each provided with a sample-and-hold circuit that holds the pixel signal, and generates a second digital signal by performing the signal processing on each of the held pixel signals; a metadata extraction procedure in which a metadata extraction unit extracts predetermined metadata from the first digital signal; and an image signal processing procedure in which an image processing unit performs predetermined image processing on the second digital signal using the metadata.

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