SEMICONDUCTOR DEVICE AND MEMORY DEVICE

Abstract

According to one embodiment, a semiconductor device (160) includes: an operational amplifier (50) having a first input terminal (IT1), a second input terminal (IT2), and an output terminal (OT), the operational amplifier (50) outputting a first voltage (Vout) from the output terminal; a first resistor (51), one end of which is connected to the first input terminal and the other end of which is connected to the output terminal; a plurality of second resistors (55 <1> up to 55 <m>), one end of which is connected to the first input terminal, wherein the plurality of second resistors are connected in series; a plurality of switches (SW <1> to SW <m>), each having one end connected to a first node (NDc) between two adjacent resistors of the plurality of second resistors, and another end connected to a second node (NDd), the plurality of switches receiving a digital code (CD); and a current source circuit (59) connected between the second node and a third node (NDz), one of the plurality of switches being turned on based on the digital code, the current source circuit causing a first current (Ir) to flow from part or all of the plurality of second resistors to the third node via the switch in a turned-on state.< / m> < / m>

Description

AREA

[0001] The embodiments relate to a semiconductor device and a memory device. BACKGROUND

[0002] A digital-to-analog converter circuit and an analog-to-digital converter circuit are used in various semiconductor devices. CITATION LISTPATENT LITERATURE

[0003] Patent Literature 1: Japanese Patent No. JP 2002-76897 B SUMMARY

[0004] According to one embodiment, a semiconductor device includes: an operational amplifier having a first input terminal, a second input terminal, and an output terminal, the operational amplifier outputting a first voltage from the output terminal; a first resistor having one end connected to the first input terminal and the other end connected to the output terminal; a plurality of second resistors having one end connected to the first input terminal, the plurality of second resistors being connected in series; a plurality of switches, each having one end connected to a first node between two adjacent resistors of the plurality of second resistors and the other end connected to a second node, the plurality of switches receiving a digital code;and a current source circuit connected between the second node and a third node, wherein one of the plurality of switches is turned on based on the digital code, and the current source circuit causes a first current to flow from some or all of the plurality of second resistors to the third node via the switch in an on state; BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram illustrating a configuration example of a semiconductor device of a first embodiment. Fig. 2 is a circuit diagram illustrating a configuration example of a memory cell array of the semiconductor device of the first embodiment. Fig. 3 is a cross-sectional view illustrating a structural example of the semiconductor device of the first embodiment. Fig. 4 is a plan view illustrating a structural example of a memory cell of the semiconductor device of the first embodiment. Fig. 5 is a diagram for describing the relationship between a threshold voltage of the memory cell and data. Fig. 6 is a schematic diagram illustrating a configuration example of a digital-to-analog conversion circuit and a driving circuit of the semiconductor device of the first embodiment. Fig. 7 is a circuit diagram illustrating the configuration example of the digital-to-analog conversion circuit and the driving circuit of the semiconductor device of the first embodiment. Fig. 8 is a circuit diagram illustrating a configuration example of a specific circuit in the semiconductor device of the first embodiment. Fig. 9 is a circuit diagram illustrating the configuration example of a specific circuit in the semiconductor device of the first embodiment. Fig. 10 is a circuit diagram illustrating the configuration example of a specific circuit in the semiconductor device of the first embodiment. Fig. 11 is a diagram for describing an operation example of the semiconductor device of the first embodiment. Fig. 12 is a circuit diagram illustrating a configuration example of a digital-to-analog conversion circuit and a driving circuit of a semiconductor device of a second embodiment. Fig. 13 is a circuit diagram illustrating a configuration example of a digital-to-analog conversion circuit and a driving circuit of a semiconductor device of a third embodiment. Fig. 14 is a circuit diagram illustrating a configuration example of a digital-to-analog conversion circuit and a driving circuit of a semiconductor device of a fourth embodiment. Fig. 15 is a circuit diagram illustrating a configuration example of a specific circuit of the semiconductor device of the fourth embodiment. Fig. 16 is a block diagram illustrating a configuration example of a semiconductor device of a fifth embodiment. Fig. 17 is a block diagram illustrating a configuration example of a semiconductor device of a sixth embodiment. Fig. 18 is a block diagram illustrating a configuration example of a semiconductor device of a seventh embodiment. DETAILED DESCRIPTION

[0005] A semiconductor device of one embodiment is described with reference to the Fig. 1 to 18 described. (1) First embodiment

[0006] A semiconductor device of a first embodiment is described with reference to the Fig. 1 to 11 are described. ( a) Configuration example <gesamtkonfiguration>

[0007] An overall configuration of the semiconductor device of the first embodiment will be described with reference to FIG. Fig. 1 to 3.

[0008] Fig. 1 is a block diagram for describing a configuration example of a system SYS including the semiconductor device 1 of the present embodiment.

[0009] As in Fig. 1, the semiconductor device 1 of the present embodiment is a memory device 1.

[0010] The storage device 1 is provided in the storage system SYS.

[0011] The storage system SYS is connected to a host device 9 via a host bus. The storage system SYS can be requested by the host device 9 to write, read, and delete data.

[0012] The host device 9 is, for example, a personal computer, a server, or the like. The host bus is, for example, a bus based on an interface standard such as an SD interface (registered trademark), a Serial Attached Small Computer System Interface (SCSI) (SAS), a Serial Advanced Technology Attachment (ATA) (SATA), a Peripheral Component Interconnect Express (PCIe), or a Non-Volatile Memory Express (NVMe). Note that the storage system SYS may be connected to the host device 9 via wireless communication.

[0013] The storage system SYS includes the storage device 1 of the present embodiment and a storage controller 5.

[0014] The memory controller 5 is electrically connected to the memory device 1. The memory controller 5 sends a command CMD, an address ADD, and a plurality of control signals to the memory device 1.

[0015] The storage device 1 is a non-volatile semiconductor storage device. The storage device 1 of the present embodiment is, for example, a NAND flash memory 1.

[0016] The storage device 1 receives the command CMD, the address ADD, and the plurality of control signals. The data DT is transferred between the storage device 1 and the memory controller 5. Hereinafter, the data DT transferred from the memory controller 5 to the storage device 1 at the time of the write sequence is referred to as write data. Write data DT is written to the storage device 1. The data DT transferred from the storage device 1 to the memory controller 5 at the time of the read sequence is referred to as read data. The read data DT is read from the storage device 1.

[0017] The memory device 1 includes, for example, a memory cell array 110, a command register 120, an address register 130, a row control circuit 140, a sense amplifier circuit 150, a voltage generation circuit 160, a temperature sensor 170, an input / output circuit 180, and a sequencer 190.

[0018] The memory cell array 110 stores data. A plurality of bit lines and a plurality of word lines are provided in the memory cell array 110. The memory cell array 110 includes a plurality of BLK blocks. Each BLK block is a set of a plurality of memory cells. Each memory cell is connected to a bit line and a word line. The memory cell array 110 includes a plurality of select gate lines for selecting a control unit in the memory cell array 110.

[0019] An internal configuration of the memory cell array 110 will be described later.

[0020] The command register 120 temporarily stores the CMD command from the memory controller 5. The CMD command is, for example, a signal containing an order in which the sequencer 190 executes the read sequence, the write sequence, the erase sequence, and the like.

[0021] The address register 130 temporarily stores an address (select address) ADD from the memory controller 5. The ADD address includes, for example, a block address, a page address (word line address), a column address, and the like. For example, the block address, the page address, and the column address are used to select the BLK block, the word line, and the bit line (column), respectively. The block selected based on the block address is hereinafter referred to as the selected block. The word line selected based on the page address is referred to as the selected word line.

[0022] The row control circuit 140 controls an operation with respect to a row of the memory cell array 110. The row control circuit 140 selects a block BLK in the memory cell array 110 based on the block address. The row control circuit 140 transmits, for example, a voltage applied to an interconnection corresponding to the selected word line to the selected word line in the selected block BLK. The row control circuit 140 controls whether or not to select the selected gate line based on the address ADD. The row control circuit 140 includes a word line switch, a row decoder, and the like.

[0023] The sense amplifier circuit 150 controls an operation with respect to a column of the memory cell array 110. In the write sequence, the sense amplifier circuit 150 applies a voltage to each of the bit lines provided in the memory cell array 110 according to the write data DT from the memory controller 5. In the read sequence, the sense amplifier circuit 150 determines the data stored in the memory cell based on the presence or absence of current generation or potential fluctuation of the bit line. The sense amplifier circuit 150 transmits data based on a determination result as read data to the memory controller 5. The sense amplifier circuit 150 includes a sense amplifier unit, a data latch circuit, a cache circuit, and the like.

[0024] The voltage generation circuit 160 generates a variety of voltages for various operations of the memory device 1 in different operation sequences, such as the read sequence, the write sequence, and the erase sequence. The voltage generation circuit 160 outputs the generated voltage to each circuit. The voltage generation circuit 160 can apply a predetermined voltage to an interconnection corresponding to the word line, the bit line, and the like based on the address ADD. The voltage generation circuit 160 includes, for example, a charge pump circuit 161, a driver circuit 162, a digital-to-analog converter circuit 163, and the like.

[0025] The input / output circuit 180 functions as an interface circuit on the storage device 1 side between the storage device 1 and the memory controller 5. In a case where the storage device 1 is the NAND flash memory, the input / output circuit 180 communicates with the memory controller 5 based on a NAND interface standard such as an Open NAND Flash Interface (ONFi). A command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, a read enable signal REn, a ready / busy signal RBn, an input / output signal DQ, and the like are used for communication between the storage device 1 and the memory controller 5.

[0026] The command memory enable signal CLE is a signal indicating that the input / output signal DQ received by the memory device 1 is the command CMD. The address latch enable signal ALE is a signal indicating that the signal DQ received by the memory device 1 is the address ADD. The write enable signal WEn is a signal instructing the memory device 1 to input the input / output signal DQ. The read enable signal REn is a signal instructing the memory device 1 to output the input / output signal DQ.

[0027] The ready / busy signal RBn is a signal that notifies the memory controller 5 through the memory device 1 whether the memory device 1 is in a ready state in which a job is accepted from the memory controller 5 or in a busy state in which a job is not accepted.

[0028] For example, the input / output signal DQ is a signal set with a width of 8 bits. The input / output signal DQ can contain the command CMD, the address ADD, the data DT, and the like.

[0029] The temperature sensor 170 measures the temperature of a chip (or package) of the memory unit 1. The temperature sensor 170 transmits a temperature measurement result to the sequencer 190.

[0030] It should be noted that the temperature sensor 170 may be provided in the sequencer 190.

[0031] The sequencer 190 controls the operation of the entire memory unit 1. For example, the sequencer 190 controls each circuit based on the command CMD in the command register 120.

[0032] For example, the sequencer 190 generates a code (hereinafter also referred to as a digital code) CD based on the temperature measurement result. The code CD is indicated by a digital value of two or more bits. The sequencer 190 transmits the generated code CD to the voltage generation circuit 160. The voltage generation circuit 160 controls the magnitude of the voltage used to operate the memory device 1 based on the received code CD.

[0033] For example, the sequencer 190 includes a digital control circuit 191. The digital control circuit 191 generates various digital signals such as the code CD.

[0034] It should be noted that the code CD can be sent directly from the temperature sensor 170 to the voltage generation circuit 160.

[0035] Hereinafter, each of the circuits 120 to 190 except the memory cell array 110 or a set of circuits in the memory device 1 is referred to as CMOS circuit (or peripheral circuit) 200.

[0036] Fig. 2 is a circuit diagram showing a circuit configuration of a specific block BLK in the memory cell array 110.

[0037] As in Fig. As illustrated in Figure 2, a block BLK contains a plurality of (e.g., five) string units SU (SU0, SU1, SU2, SU3, and SU4). Each string unit SU contains a plurality of NAND strings NS. The number of blocks in the memory cell array 110, the number of string units in the block BLK, and the number of NAND strings in the string unit SU are optional.

[0038] Each NAND string NS includes a plurality of memory cells MT (MT0, MT1, MT2, ..., MTn-3, MTn-2, and MTn-1) and a plurality of selection transistors ST1 and ST2. n is a natural number not less than 2. The plurality of memory cells MT are connected in series between a source of the selection transistor ST1 and a drain of the selection transistor ST2.

[0039] The memory cell MT stores data in an essentially non-volatile manner.

[0040] The memory cell (also called memory cell transistor) MT is a field effect transistor with a control gate and a charge storage layer.

[0041] Gates of the selection transistors ST1 in each of the string units SU are each connected to a corresponding selection gate line SGD from a plurality of selection gate lines SGD (SGD0, SGD1, SGD2, SGD3 and SGD4).

[0042] The gates of the selection transistors ST2 in the respective string units SU are typically connected to a selection gate line SGS, for example. The gates of the selection transistors ST2 can be connected to different selection gate lines SGS for each string unit SU.

[0043] The control gates of the memory cells MT0, MT1, MT2, ..., MTn-3, MTn-2 and MTn-1 belonging to the same block BLK are each connected to a corresponding word line WL from the plurality of word lines WL (WL0, WL1, WL2, ..., WLn-3, WLn-2 and WLn-1).

[0044] Drains of the selection transistors ST1 of the NAND strings NS belonging to the same column in the memory cell array 110 are each connected to a corresponding bit line BL from the plurality of bit lines BL (BL0, BL1, ... and BLm-1). m is a natural number not less than 2.

[0045] The sources of a plurality of select transistors ST2 are typically connected to a source line SL. The string unit SU is an aggregate of NAND strings NS connected to different bit lines BL and to the same select gate line SGD.

[0046] The block BLK is an aggregate of the plurality of string units SU that share the plurality of word lines WL. The memory cell array 110 is an aggregate of the plurality of blocks BLK that share the plurality of bit lines BL.

[0047] In the following, a set of memory cells MT (memory cell group) that are commonly connected to the same word line WL in each string unit SU is also referred to as cell unit CU (or memory group).

[0048] Fig. 3 is a cross-sectional view showing a structural example of the memory cell array in a case where the semiconductor device 1 of the present embodiment is a NAND flash memory.

[0049] As in Fig. 3, the memory cell array 110 includes a semiconductor substrate (hereinafter also simply referred to as substrate) 20, conductive layers 21, 22 (22a, 22b and 22c) and 28, and insulating layers 31, 32, 34 and 38. The memory cell array 110 includes a structure (stacked interconnection 300) in which a plurality of conductive layers 22 (22a, 22b and 22c) are stacked in the Z direction.

[0050] The insulating layer 38 is located on an upper surface of the semiconductor substrate 20. The insulating layer 38 covers, for example, the CMOS circuit 200 such as the row control circuit 140 and the sense amplifier circuit 150 on the semiconductor substrate 20.

[0051] The conductive layer 21 is disposed on an upper surface of the insulating layer 38. The conductive layer 21 is, for example, a plate-shaped layer extending along an XY plane. The conductive layer 21 is used as a source line SL. The conductive layer 21 comprises, for example, phosphorus-doped silicon.

[0052] The insulating layer 31 is disposed on top of the conductive layer 21. The conductive layer 22a is provided on top of the insulating layer 31. The conductive layer 22a is, for example, a plate-shaped layer extending along the XY plane. The conductive layer 22a is used as a select gate line (SGS). The conductive layer 22a contains, for example, tungsten.

[0053] The insulating layer 32 and the conductive layer 22b are alternately stacked in the Z direction on an upper surface of the conductive layer 22a. The conductive layer 22b is, for example, a plate-shaped layer extending along the XY plane. A plurality of stacked conductive layers 22b are used as the word lines WL0, ..., and WLn-1 in this order from the semiconductor substrate 20 side. The conductive layer 22b contains, for example, tungsten.

[0054] The conductive layer 22c is disposed above an uppermost conductive layer 22b over the insulating layer 32. The conductive layer 22c is, for example, a plate-shaped layer extending along the XY plane. The conductive layer 22c is used as a select gate line SGD. The conductive layer 22c contains, for example, tungsten.

[0055] The insulating layer 34 is provided on top of the conductive layer 22c. The insulating layer 34 may include a plurality of insulating layers. The conductive layer 28 is arranged on top of the insulating layer 34. The conductive layer 28 is, for example, a linear layer extending in the Y direction. The conductive layer 28 is used as a bit line BL. In a region not shown, a plurality of conductive layers 28 are arranged in the X direction. The conductive layer 28 is made of, for example, copper.

[0056] Hereinafter, a structure including a plurality of stacked conductive layers 22 and a plurality of insulating layers 31 and 32 is referred to as a stacked interconnect 300.

[0057] Each of the memory columns MP is provided in the stacked interconnection 300 so as to extend in the Z direction. The memory column MP penetrates the insulating layers 32 and the conductive layers 22. A lower portion of the memory column MP is in contact with the conductive layer 21. A region where the memory column MP and the conductive layer 22a intersect functions as a selection transistor ST2. A region where the memory column MP and a conductive layer 22b cross functions as a memory cell MT. A region where the memory column MP and the conductive layer 22c cross functions as a selection transistor ST1.

[0058] Each of the memory columns MP includes, for example, a core element 24, a semiconductor layer 25, and a stacked film (also referred to as a memory layer) 26. The core element 24 is provided so as to extend in the Z direction. An upper end of the core element 24 is located, for example, above the conductive layer 22c. A lower end of the core element 24 reaches the conductive layer 21. The semiconductor layer 25 covers an edge of the core part 24. In a lower portion of the memory column MP, a part of the semiconductor layer 25 is in contact with the conductive layer 21. The stacked film 26 covers a side surface and a bottom surface of the semiconductor layer 25 except for a portion where the semiconductor layer 25 and the conductive layer 21 are in contact with each other. The core element 24 contains, for example, an insulator such as silicon oxide. The semiconductor layer 25 is made of, for example, silicon.

[0059] Fig. 4 is a plan view showing a structural example of the memory column of the NAND flash memory.

[0060] Fig. 4 is a cross-sectional view for describing a configuration of the storage column MP. Fig. 4 shows a cross section along the XY plane of the memory column MP at a location where the conductive layer 22b is arranged.

[0061] For example, the memory column MP has a circular (or elliptical) planar shape when viewed in the Z direction. The semiconductor layer 25 covers one side surface of a cylindrical core element 24. The stacked film 26 is located between the semiconductor layer 25 and the conductive layer 22b.

[0062] The stacked film 26 includes a tunnel insulating layer 261, a charge storage layer 262, and a block insulating layer 263. The tunnel insulating layer 261, the charge storage layer 262, and the block insulating layer 263 are stacked in a direction parallel to a surface (XY plane) of the semiconductor substrate 20.

[0063] The tunnel insulation layer 261 is provided between the semiconductor layer 25 and the charge storage layer 262. The tunnel insulation layer 261 acts as a tunnel barrier between the semiconductor layer 25 and the charge storage layer 262. When a voltage of a certain magnitude is applied between the conductive layer 22b and the semiconductor layer 25, a charge moves between the semiconductor layer 25 and the charge storage layer 262 due to a tunneling phenomenon. The tunnel insulation layer 261 includes, for example, silicon oxide.

[0064] The charge storage layer 262 is disposed between the tunnel insulation layer 261 and the block insulation layer 263. The charge storage layer 262 is, for example, a charge trap film capable of holding (trapping) charge. In this case, the charge storage layer 262 contains silicon nitride. Note that the charge storage layer 262 may be a floating gate electrode. The floating gate electrode is made of silicon.

[0065] The blocking insulating layer 263 is provided between the charge storage layer 262 and the conductive layer 22b. The blocking insulating layer 263 prevents the movement of charge between the charge storage layer 262 and the conductive layer 22b. The blocking insulating layer 263 comprises, for example, silicon oxide and / or aluminum oxide.

[0066] In the memory column MP, the semiconductor layer 25 is used as a channel region (current path) for the memory cells MT0, ..., and MTn-1 and the selection transistors ST1 and ST2. The memory device 1 can cause a current flow between the bit line BL and a contact LI (source line SL) via the memory column MP by turning on the memory cells MT0, ..., and MTn-1 and the selection transistors ST1 and ST2.

[0067] Returning to Fig. 3, a columnar contact CV is provided on top of the semiconductor layer 25 in the storage column MP. In the illustrated region, two contacts CV are shown, each corresponding to the two storage columns MP among the six storage columns MP. The contact CV is connected to the storage column MP that does not overlap a slot SHE and to which the contact CV is not connected, in a region not shown (e.g., a region in a depth direction or a front direction of the paper surface).

[0068] A conductive layer 28 (a bit line BL) is in contact with an upper surface of the contact CV. A contact CV is connected to a conductive layer 28 in each of the spaces divided by slots SLT and SHE. The memory column MP provided between the adjacent slots SLT and SHE and the memory column MP provided between the two adjacent slots SHE are electrically connected to each of the conductive layers 28.

[0069] The slot SLT includes, for example, a section along an XZ plane. The slot SLT divides the conductive layer 22. The contact LI in the slot SLT is provided along the slot SLT. A part of the upper end of the contact LI is in contact with the insulating layer 34. A lower end of the contact LI is in contact with the conductive layer 21. The contact LI is used, for example, as a part of the source line SL. A spacer SP is provided at least between the contact LI and the conductive layers 22a, 22b, and 22c. The contact LI is separated and insulated from the conductive layers 22a, 22b, and 22c by the spacer SP.

[0070] The slot SHE includes, for example, a section running along the XZ plane. The slot SHE divides at least the conductive layer 22c. An upper end of the slot SHE is in contact with the insulating layer 34. A lower end of the slot SHE is in contact with the insulating layer 32 between the uppermost conductive layer 22b and the conductive layer 22c. The slot SHE includes, for example, an insulator such as silicon oxide. The upper end of the slot SHE and the upper end of the slot SLT may or may not be aligned with each other. The upper end of the slot SHE and the upper end of the storage column MP may or may not be aligned with each other.

[0071] A plurality of elements TR and RES may be provided on the semiconductor substrate 20 below the memory cell array 110.

[0072] For example, a field-effect transistor TR is provided in a well region 27 of the semiconductor substrate 20. The well region 27 is a semiconductor area divided by an insulator 29a having a shallow trench isolation (STI) structure.

[0073] The field effect transistor comprises two sources / drains 41 (41a and 41b), a gate insulating layer 42 and a gate electrode 43.

[0074] The sources / drains 41a and 41b are located in the well region 27. Each of the sources / drains 41a and 41b is a diffusion layer (impurity semiconductor region). The gate insulating film 42 is located on the well region 27 between the two sources / drains 41a and 41b. The gate electrode 43 is located on the gate insulating film 42. A part of the well region 27 opposite the gate electrode 43 is a channel region of the field-effect transistor TR. The gate electrode 43 is composed, for example, of a single layer of polysilicon or a stack of polysilicon and silicide such as nickel silicide (NiSi), nickel-platinum silicide (NiPtSi), and cobalt silicide (CoSi). The gate electrode 43 includes, for example, a stack of silicon nitride (SiN) and polysilicon, tungsten (W), and tungsten silicide (WSi). The gate electrode 43 consists of, for example, aluminum (Al), titanium (Ti), and tantalum (Ta).The gate electrode 43 includes, for example, a stack of aluminum oxide (AlO), aluminum cobalt copper (AlCoCu), aluminum titanium nitride (AlTiN), aluminum titanium nitride (AlTiN), aluminum titanium oxynitride (AlTiON), tantalum nitride (TaN), and titanium nitride (TiN). The gate electrode 43 includes, for example, a stack of silicide such as nickel silicide (NiSi), nickel platinum silicide (NiPtSi), and cobalt silicide (CoSi), polysilicon, and titanium nitride (TiN). The gate electrode 43 includes, for example, a stack of tungsten (W), tungsten silicon nitride (WSiN), tungsten (W), titanium nitride (TiN), polysilicon, and titanium nitride (TiN). It should be noted that the stack described here does not necessarily include all of the layers, but may include only some of the layers.

[0075] A contact 46a is provided on the gate electrode 43. A contact 46b is provided on the source / drain electrode 41. Each of the plurality of contacts 46a and 46b is electrically connected to each of the plurality of interconnections (metal layers) 47a and 47b in the insulating layer (interlayer insulating film) 38.

[0076] For example, a resistor (resistive element) RES is provided on an insulator 29b in the semiconductor substrate 20. The resistor RES comprises a conductive layer (resistive layer) 45. The conductive layer 45 has a similar stack structure to the gate electrode 43. The conductive layer 45 comprises, for example, a single layer of polysilicon or a stack of polysilicon and silicide such as nickel silicide (NiSi), nickel platinum silicide (NiPtSi), and cobalt silicide (CoSi). The conductive layer 45 contains, for example, a stack of silicon nitride (SiN) and polysilicon, tungsten (W), and tungsten silicide (WSi). The conductive layer 45 consists, for example, of aluminum (Al), titanium (Ti), and / or tantalum (Ta). The conductive layer 45 comprises, for example, a stack of aluminum oxide (AlO), aluminum cobalt copper (AlCoCu), aluminum titanium nitride (AlTiN), aluminum titanium nitride (AlTiN), aluminum titanium oxynitride (AlTiON), tantalum nitride (TaN) and titanium nitride (TiN).The conductive layer 45 comprises, for example, a stack of silicide such as nickel silicide (NiSi), nickel platinum silicide (NiPtSi), and cobalt silicide (CoSi), polysilicon, and titanium nitride (TiN). The conductive layer 45 comprises, for example, a stack of tungsten (W), tungsten silicon nitride (WSiN), tungsten (W), titanium nitride (TiN), polysilicon, and titanium nitride (TiN). It should be noted that the stack described here does not necessarily include all of the layers, but may include only some of the layers.

[0077] A contact 46c is provided on top of the conductive layer 45. Contact 46c is connected to an interconnect 47c in the insulating layer 38.

[0078] The resistor RES can be mounted on a semiconductor region of the semiconductor substrate 20.

[0079] The resistor RES can be formed by a metal layer in the insulating layer 38.

[0080] The field-effect transistor TR and the resistor RES are electrically connected to other elements on the semiconductor substrate 20 via the interconnection lines 47a, 47b, and 47c, respectively. Consequently, the CMOS circuit 200, such as the row control circuit 140 and the voltage generation circuit 160, is formed on the semiconductor substrate 20 below the memory cell array 110.

[0081] It should be noted that the structure of the memory device 1 of the present embodiment is not limited to the structures in Fig. 3 and Fig. 4. For example, the memory cell array 110 and the CMOS circuit 200 may be formed on different chips (semiconductor substrates). In this case, the chip of the memory cell array 110 is stacked on the chip of the CMOS circuit 200 in the Z direction. The chip of the memory cell array 110 is connected to the chip of the CMOS circuit 200 via a conductive element.

[0082] Fig. 5 is a diagram for describing the relationship between the data stored in the memory cell MT and a threshold voltage of the memory cell MT.

[0083] As in Fig. As illustrated in Figure 5, the memory cell MT can assume a variety of states depending on the threshold voltage. The variety of memory cells exhibits different characteristics. Taking these different characteristics into account, the data is mapped to a voltage value distribution (hereinafter referred to as the threshold voltage distribution) 999 (999a, 999b, 999c, and 999d) centered on a voltage value of a specific threshold voltage.

[0084] The memory cell MT can assume an erase state and one or more program states.

[0085] In Fig. 5, an "Er" state corresponds to the erase state (a state in which data is erased), and the states "A", "B", ..., and "z" correspond to the program states (states in which data is programmed). Note that the "z" state conveniently indicates the program state corresponding to the highest threshold voltage (threshold voltage distribution) among a plurality of program states that can be assumed by the memory cell MT.

[0086] A single-level cell (SLC) consists of 1 bit / cell and can assume two states ("Er" and "A" states). A multi-level cell (MLC) consists of 2 bits / cell and can assume four states ("Er", "A", "B", and "C" states). A three-level cell (TLC) consists of 3 bits / cell and can assume eight states ("Er", "A", "B", ..., "F", and "G"). A quad-level cell (QLC) consists of 4 bits / cell and can assume 16 states ("0", "1", "2", ..., "E", and "F"). A penta-level cell (PLC) consists of 5 bits / cell and can assume 32 states ("0", "1", "2", ..., "U", and "V"). A hexa-level cell (HLC) consists of 6 bits / cell and can assume 64 states ("0", "1", "2", ..., "BA", and "BB"). A seven-level cell (7LC) consists of 7 bits / cell and can assume 128 states (states "0", "1", "2", ..., "DM" and "DN").

[0087] In an example in Fig. 5, the threshold voltage distribution 999a of the memory cell MT in the "Er" state is smaller than a voltage VAR. The threshold voltage distribution 999b of the memory cell MT in the "A" state is not smaller than the voltage VAR and is smaller than a voltage VBR (>VAR). The threshold voltage distribution 999c of the memory cell MT in the "B" state is not smaller than the voltage VBR and is smaller than a voltage VCR (>VBR). The threshold voltage distribution 999d of the memory cell MT in the "z" state is not smaller than a voltage VzR and is smaller than a voltage VREAD.

[0088] Each of the voltages (voltage values) VAR, VBR, ..., and VzR is a voltage used for reading data. Hereinafter, each of the voltages VAR, VBR, ..., and VzR is also referred to as a determination level or read level. The voltages VAR to VzR are also collectively referred to as a voltage (read voltage) VCGR. The voltage VREAD is, for example, a voltage applied to a word line (unselected word line) WL that does not contain a read target at the time of a read operation. When the voltage VREAD is applied to the memory cell MT, the memory cell MT is turned on regardless of the data stored in the memory cell MT. The data stored in the memory cell MT is determined based on an on / off result of the memory cell MT with respect to the applied read level.

[0089] To verify data writing, the voltages VAV, VBV, ..., and VzV are provided for each state. The voltage VAV is higher than the read level VAR and not higher than a lower limit of a desired threshold voltage distribution 999b of the "A" state. The voltage VBV is higher than the read level VBR and not higher than a lower limit of a desired threshold voltage distribution 999c of the "B" state. The voltage VzV is higher than the read level VzR and not higher than a lower limit of a desired threshold voltage distribution 999d of the "z" state.

[0090] To verify data erasure, a voltage VErV is provided between the threshold voltage distribution 999a of the "Er" state and the threshold voltage distribution 999b of the "A" state. The voltage VErV is, for example, lower than the voltage VAR and not lower than an upper limit of the desired threshold voltage distribution 999a of the "Er" state.

[0091] In the following, each of the voltages VErV, VAV, VBV, ..., and VzV is also referred to as verification level.

[0092] Regarding the verification of each state, in a case where the verification layer is applied to the memory cell MT, it is determined whether the verification of the state of each memory cell MT with respect to data writing or data erasure passes or fails (whether this is a failure or not) depending on whether the memory cell MT is turned on or not. Depending on whether the number of passes / fails in verifying the states of the plurality of memory cells is a value within an acceptable range, it is checked whether the executed operation sequence is successful.

[0093] The characteristics of the MT memory cell vary depending on the temperature of the chip (the package). Therefore, it is desirable that the voltage value of each read level and the voltage value of each verify level be adjusted depending on the chip temperature.

[0094] As described above Fig. 1, the memory device (semiconductor device) 1 of the present embodiment includes the digital-to-analog conversion circuit 163 in the voltage generation circuit 160.

[0095] Hereinafter, the digital-to-analog converter circuit 163 is referred to as a DA converter circuit 163.

[0096] The DA converter circuit 163 receives the code CD. The DA converter circuit 163 operates based on the code CD.

[0097] The driver circuit 162 outputs various voltages used for operating the memory cell array 110 to the row control circuit 140 and the sense amplifier circuit 150 using the voltage boosted by the charge pump circuit 161.

[0098] The driver circuit 162 outputs various adjusted voltages to each of the interconnections connected to the word line WL, the interconnections connected to the select gate lines SGD and SGS, and the interconnection connected to the source line SL according to a conversion result of the code CD by the DA converter circuit 163. For example, as the value of the code CD increases, an output voltage of the driver circuit 162 increases. Thus, in the present embodiment, the magnitude of the output voltage of the driver circuit 162 is controlled by the DA converter circuit 163 based on the code CD.

[0099] Fig. 6 is a circuit diagram showing a configuration example of the driver circuit 162 and the DA converter circuit 163 in the voltage generating circuit 160 in the memory device 1 of the present embodiment.

[0100] The driver circuit 162 includes a plurality of drivers DRV.

[0101] The DA converter circuit 163 includes a plurality of DA converters DAC.

[0102] A DAC is connected to a driver (DRV). A set of a DAC and a driver (DRV) can in some cases be considered a single circuit unit (DAC or driver).

[0103] Each DA converter DAC receives the code CD from the sequencer 190. As described above, the code CD is the digital signal (digital value) generated based on the measurement result of the temperature by the temperature sensor 170.

[0104] The DA converter DAC supplies an analog signal (e.g. voltage and / or current) based on the code CD to the driver DRV.

[0105] The driver DRV supplies an output voltage Vout, whose magnitude corresponds to the analog signal of the DA converter DAC, to the memory cell array 110 via the row control circuit 140. The output voltage Vout is applied to the word line WL, the select gate lines SGD and SGS, or the source line SL.

[0106] The output voltage Vout of the driver DRV is, for example, the verification level (verification voltage) used for the write sequence or the read level (read voltage) used for the read sequence.

[0107] The output voltage Vout of the driver DRV may include a program voltage, a non-selected voltage VREAD, voltages supplied to the select gate lines SGD and SGS, or the like.

[0108] In this way, the magnitude of the output voltage Vout of the driver DRV is controlled based on a result of the DA conversion processing of the DA converter DAC.

[0109] Note that the output signal Vout of the driver DRV can be supplied to the sense amplifier circuit 150.

[0110] Fig. 7 is a circuit diagram showing an internal configuration of the driver circuit 162 and the DA converter circuit 163 in the memory device (semiconductor device) 1 of the present embodiment.

[0111] In the driver circuit 162, the driver DRV contains an operational amplifier 50 and a resistor 51.

[0112] The operational amplifier 50 has two input terminals IT1 and IT2 and one output terminal OT. One input terminal IT1 is an inverting input terminal. The inverting input terminal IT1 is connected to a node ND1. The other input terminal IT2 is a non-inverting input terminal. The non-inverting input terminal IT2 is connected to a node ND2.

[0113] The output terminal OT is an output node of the driver DRV. The output terminal OT is electrically connected, for example, to the interconnect connected to the word line WL, to the interconnect connected to the select gate line SGD, to the interconnect connected to the select gate line SGS, or to the interconnect connected to the source line SL.

[0114] A voltage Vin of node ND1 is applied to the inverting input terminal IT1. The magnitude of the voltage Vin is controlled to be the same as the voltage (e.g., a voltage Vcenter) of the non-inverting input terminal IT2 by an operational amplification operation of operational amplifier 50. As a result, the current Iin flows through the inverting input terminal IT1 and node ND1. The voltage Vin does not depend on a resistance value of resistor 51 and a current value of the current Iin.

[0115] For example, the potential of node ND2 is set to a voltage Vcenter with a specific voltage value by voltage generation circuit 160. Voltage Vcenter is applied to node ND2, for example, via a voltage node NVA. Consequently, voltage Vcenter is supplied from node ND2 to non-inverting input terminal IT2.

[0116] The resistor 51 is connected to the operational amplifier 50. One end of the resistor 51 is connected to the inverting input terminal IT1 of the operational amplifier 50. The other end of the resistor 51 is connected to the output terminal OT of the operational amplifier 50. The resistor 51 has a resistance value R1. The resistor 51 is, for example, used in Fig. 3 formed.

[0117] Operational amplifier 50 and resistor 51 form an inverting amplifier circuit. Hereinafter, a set (driver) DRV containing operational amplifier 50 and resistor 51 is also referred to as a driver amplifier DRV.

[0118] For example, the operational amplifier 50 constituting the inverting amplifier circuit outputs the voltage Vout equal to the sum of the potential of the input terminal IT1 and the potential of the input terminal IT2 at the output terminal OT.

[0119] The DA converter DAC comprises a resistor chain (also called a resistor network or resistor circuit) RS, a plurality of switches SW and a current source circuit 59.

[0120] One end (input node) NDa of the resistor chain RS is connected via the node ND1 to the inverting input terminal IT1 of the operational amplifier 50.

[0121] The other end (output node) NDb of the resistor chain RS is connected via the node ND2 to the non-inverting input terminal IT2 of the operational amplifier 50.

[0122] The resistor chain RS comprises a plurality of resistors 55 connected in series. The resistor chain RS comprises, for example, M resistors 55. M is a natural number not less than 1. The resistance value of each resistor 55 is the same. Each resistor 55 has a resistance value R2. The resistor 55 is, for example, formed from the resistor RES in Fig. 3. The resistance value R2 of resistor 55 can, for example, assume a specific value in the range from 10 Ω to 10 kΩ. A more concrete example for the resistance value R2 is 1 kΩ.

[0123] A variety of switches SW (SW <1> , SW <2> , ..., SW <m-1>and SW <m>) is connected to the resistor chain RS. The number of switches SW is M. One switch SW is connected to a resistor 55.

[0124] Each switch SW is connected to a connection node NDc between the two resistors 55.

[0125] For each of the plurality of switches SW, one end of the switch SW is connected to the corresponding connection node NDc. The other end of each switch SW is connected to a node NDd. The connection node NDc is also referred to as a branch.

[0126] Between the resistor chain RS and the node NDd, the majority of switches SW are connected in parallel.

[0127] The switch SW is, for example, a metal oxide semiconductor switch (MOS) or a field effect transistor.

[0128] An input node NX1 of the current source circuit 59 is connected to the node NDd. A node NX2 of the current source circuit 59 is connected to a ground node NDz.

[0129] The current source circuit 59 draws a portion of the current (current Ir) flowing through the resistor chain RS through a switch SW in the on state. The current source circuit 59 causes the current Ir to flow from the node NDc, to which the switch SW is connected in the on state, to the ground node NDz. The magnitude of the current Ir can be determined depending on a driving force of the current source circuit 59.

[0130] In the DA converter DAC, each of the multiple switches SW is assigned a digital value identified by the code CD.

[0131] The number of bits in the CD code depends on the number of resistors (55) in the resistor chain (RS). For example, if the number of resistors (55) in the resistor chain (RS) is 256, the number of bits in the CD code is eight.

[0132] It should be noted that the number of resistors 55 is not limited to 256. The number of resistors 55 can be 512 (= 2 9 ) or 1024 (= 2 10 ) or more. In this case, the number of bits of the code CD is nine or ten or more. The number of resistors 55 can be 128 (= 2 7 ) or less. In this case, the number of bits of the CD code is seven or less.

[0133] Each switch SW is assigned a different 8-bit code, so that a switch SW can be selected from the multitude of switches SW. A switch SW is activated by an 8-bit digital value of the code CD.

[0134] When the DAC is operating, any one of the multiple switches SW is turned on based on the supplied code CD. Of the multiple switches SW, the remaining switches SW are turned off.

[0135] For example, the digital value of the code CD is assigned to each of the plurality of switches SW such that the digital value of the code CD increases in order from the side of a node NDb of the resistor chain RS (a non-inverting input terminal side IT2 of the operational amplifier 50) to the side of a node NDa of the resistor chain RS (an inverting input terminal side IT1 of the operational amplifier 50).

[0136] From the plurality of switches SW, the code CD of a first digital value is assigned to the switch SW <1> which is closest to the node NDb. Of the multitude of switches SW, the code CD of a last digital value is assigned to the switch SW <m>which is closest to the node NDa.

[0137] For example, in a case where the digital code CD is specified by an 8-bit digital value, the switch SW <1> in a first stage a first code (e.g. "00000000") CD. In a case where the digital code CD is specified by the 8-bit digital value, the switch SW<M(M=256)> in a final (256th) stage a 256th

[0138] As for the current path between the inverting input terminal IT and the current source circuit 59, the number of resistors 55 that must be in an effective state on the current path changes according to the value of the code CD.

[0139] For example, in a case where the value of the code CD is small, the number of resistors 55 in the effective state on the current path between the inverting input terminal IT1 and the current source circuit 59 (current path from node NDa to node NDc) is large. In contrast, in a case where the value of the code CD is large, the number of resistors 55 in the effective state on the current path between the inverting input terminal IT1 and the current source circuit 59 is smaller than in a case where the value of the code CD is small.

[0140] As a result, the current Iin flowing through the inverting input terminal IT1 of the operational amplifier 50 increases with increasing value of the digital value of the code CD.

[0141] In this way, in the DA converter circuit 163 of the memory device 1 of the present embodiment, a converted value from the digital value (code CD) to the analog value (current Iin) in the DA converter DAC changes relatively monotonously.

[0142] The current source circuit 59 is electrically connected to a connection node NDc in the resistor chain RS via a switch SW in the switched-on state.

[0143] For example, it depends on the temperature of the storage device 1 which of the several switches SW is selectively switched on. <stromquellen-schaltung>

[0144] A configuration example of the current source circuit 59 in the DA converter circuit 163 of the memory device 1 of the present embodiment will be described with reference to FIG. Fig. 8, Fig. 9 and Fig. 10 described.

[0145] Fig. Fig. 8 is a circuit diagram illustrating an example of a current source circuit 59A used in the DA converter DAC.

[0146] Current source circuit 59A is a current source with a circuit configuration (OP-Amp+Tr type) that includes an operational amplifier and a field-effect transistor. The OP-Amp+TR type current source circuit 59A can relatively stabilize current changes even when the output voltage changes.

[0147] The current source circuit 59A includes an operational amplifier 901, a field effect transistor 902 and a resistor 903.

[0148] The operational amplifier 901 includes an inverting input terminal IT1a, a non-inverting input terminal IT2a and an output terminal OTa.

[0149] Field-effect transistor 902 includes a gate and two source / drains (two nodes). Field-effect transistor 902 is, for example, an n-channel metal-oxide-semiconductor (MOS) transistor.

[0150] In the following, the field effect transistor is also simply referred to as a transistor.

[0151] The inverting input terminal IT1a of operational amplifier 901 is connected to one end of resistor 903 via node ND90a. The non-inverting input terminal IT2a of operational amplifier 901 is connected to a voltage node NV1, to which a voltage Vr is applied. The output terminal OTa of operational amplifier 901 is connected to the gate of field-effect transistor 902.

[0152] One source / drain electrode of field-effect transistor 902 is connected to a node ND90b. The other source / drain of field-effect transistor 902 is connected to one end of resistor 903. The other end of resistor 903 is connected to a ground node. Resistor 903 has a resistance Ra.

[0153] For example, node ND90b is connected to node NDd.

[0154] The operational amplifier 901 supplies an output voltage Vg to the gate of the field effect transistor 902 based on the operation processing using the voltage Vr and the potential of the node ND90a.

[0155] The field effect transistor 902 causes the current Ir to flow by a driving force corresponding to the output voltage Vg of the operational amplifier 901.

[0156] The magnitude of the current Ir in the current source circuit 59A in Fig. 8 has the following relationship. Ir=Vr / Ra

[0157] The current source circuit 59A can flow a current with one polarity.

[0158] In this way, the current source circuit 59A operates in Fig. 8 as a power source.

[0159] Fig. 9 is a circuit diagram illustrating an example of a current source circuit 59B different from that shown in Fig. 8 shown.

[0160] As in Fig. 9, the current source circuit 59B includes four field effect transistors 911, 912, 913, 914 and a current source element 915.

[0161] The current source circuit 59B is a current mirror type current source. The current mirror type current source circuit 59B has a relatively small circuit size. The current mirror type current source circuit 59B can handle a low supply voltage relatively easily.

[0162] The current source circuit 59B is a current mirror circuit with a cascade structure.

[0163] Each of transistors 911, 912, 913, and 914 has a gate and two source / drains (two nodes). Each of transistors 911, 912, 913, and 914 is an n-channel MOS transistor.

[0164] The gate of transistor 911 is connected to the gate of transistor 912.

[0165] One source / drain of transistor 911 is connected to a ground node. The other source / drain of transistor 911 is connected to a node ND91a.

[0166] One source / drain of transistor 912 is connected to the ground node. The other source / drain of transistor 912 is connected to a node ND91b.

[0167] The gate of transistor 913 is connected to the gate of transistor 914.

[0168] One source / drain of transistor 913 is connected to the other source / drain of transistor 911 via node ND91a.

[0169] One source / drain of transistor 914 is connected to the other source / drain of transistor 912 via node ND91b.

[0170] The other source / drain of transistor 913 is connected to the gates of transistors 911 and 912.

[0171] The gates of transistors 913 and 914 are connected to a voltage node NV2a. A bias voltage Vbias is applied to the gates of transistors 913 and 914 via the voltage node NV2a.

[0172] Element 915 is connected between the other source / drain of transistor 913 and a voltage node NV2b. A voltage V1, such as a supply voltage or a reference voltage, is applied to voltage node NV2b. Element 915 comprises a resistive element or a current source (e.g., the current source circuit in FIG. 10 described later). Fig. 8 or Fig. 10).

[0173] The other source / drain of transistor 914 is connected to a node ND91c. Node ND91c is connected to node NDd.

[0174] Transistors 913 and 914 operate with a driving force corresponding to the bias voltage Vbias.

[0175] Transistors 911 and 912 operate according to the potential of the other source / drain of transistor 913.

[0176] Through the current mirror circuit including the cascade-connected transistors 911, 912, 913 and 914, the current source circuit 59B can flow the current Ir with one polarity.

[0177] The circuit 59B in Fig. 9 can form the power source circuit 59 with a relatively small circuit area.

[0178] Fig. 10 is a circuit diagram showing an example of a current source circuit 59C different from that shown in Fig. 8 and Fig. 9 shown.

[0179] The current source circuit 59C in Fig. 10 is an operational amplifier (OP-Amp) type current source. The OP-Amp type current source circuit 59C can adjust the polarity of the output current in both negative and positive polarity directions.

[0180] The current source circuit 59C includes an operational amplifier 920 and a plurality of resistors 921, 922, 923, 924 and 925.

[0181] The operational amplifier 920 includes an inverting input terminal IT1c, a non-inverting input terminal IT2c, and an output terminal OTc. The inverting input terminal IT1c is connected to a node ND92a. The non-inverting input terminal IT2c is connected to a node ND92b. The output terminal OT2 is connected to a node ND92c.

[0182] One end of resistor 921 is connected to the inverting input terminal IT1c via node ND92a. The other end of resistor 921 is connected to a voltage node NV3a. A voltage Vrm is applied to the voltage node NV3a.

[0183] One end of resistor 922 is connected to the non-inverting input terminal IT2c via node ND92b. The other end of resistor 922 is connected to a voltage node NV3b. A voltage Vrp is applied to the voltage node NV3b.

[0184] One end of resistor 923 is connected to the inverting input terminal IT1c via node ND92a. The other end of resistor 923 is connected to the output terminal OTc via node ND92c.

[0185] One end of resistor 924 is connected to the output terminal OTc, and the other end of resistor 923 is connected via node ND92c. The other end of resistor 924 is connected to a node ND92d.

[0186] One end of resistor 925 is connected to the other end of resistor 924 via node ND92d. The other end of resistor 925 is connected to the non-inverting input terminal IT2c and one end of resistor 922 via node ND92b.

[0187] Each of resistors 921 and 922 has a resistance value Rb. Resistor 923 has a resistance value Rc. Resistor 924 has a resistance value Rd. Resistor 925 has a resistance value Re. The magnitude of the resistance value Re corresponds to the value "Rc-Rd".

[0188] Current source circuit 59C outputs current Ir from node ND92d. For example, node ND92d is connected to node NDd.

[0189] The magnitude of the current Ir in the current source circuit 59C in Fig. 10 has the following relationship. Ir=(Rc / Rb)×(Vrp−Vrm) / Rd

[0190] In this way, the current source circuit 59C functions as a current source through an arithmetic operation of the operational amplifier 920.

[0191] The current source circuit 59 can cause the current Ir to flow at the node ND92d in both positive and negative polarity.

[0192] It should be noted that the circuits 59A, 59B and 59C in the Fig. 8, Fig. 9 and Fig. 10 examples of the current source circuit 59 are shown. The current source circuit 59 of the DA converter DAC may have a different circuit configuration than that shown in Fig. 8, Fig. 9 and Fig. 10 shown. (b) Operational example

[0193] An operation example of the driver circuit 162 and the DA converter circuit 163 in the semiconductor device 1 of the present embodiment will be described with reference to Fig. 11 described.

[0194] In the memory device (e.g., the NAND flash memory) 1 as a semiconductor device of the present embodiment, the driver circuit 162 and the DA converter circuit 163 operate when supplying voltages to the word line WL, the select gate lines SGD and SGS, and the source line SL in the write sequence and the read sequence.

[0195] For example, the DA converter circuit 163 contributes to adjusting the voltage values of the test level and the read level depending on the temperature of the memory device 1.

[0196] In the memory device 1 of the present embodiment, the temperature sensor 170 measures the temperature of the chip (or package) at a specific time. The temperature sensor 170 transmits the temperature measurement result to the sequencer 190.

[0197] For example, the sequencer 190 receives the measurement result of the temperature sensor 170. In the sequencer 190, the digital control circuit 191 generates the code CD having a digital value corresponding to the measurement result and the command CMD based on the temperature measurement result and the command CMD in the command register 120. The sequencer 190 transmits the generated code CD to the voltage generation circuit 160.

[0198] The voltage generation circuit 160 receives the code CD. The voltage generation circuit 160 transmits the received code CD to the DA converter circuit 163.

[0199] The DA converter circuit 163 receives the code CD. In the DA converter circuit 163, each DA converter DAC controls the on / off switching of the plurality of switches SW based on the code CD. As a result, a switch SW corresponding to the code CD is turned on among the plurality of switches SW.

[0200] In the example in Fig. 11, a switch SW[CD:N] with the code CD of "N" is turned on. N is an integer not less than 0. For example, N is M or less. A possible maximum value of N is, for example, M-1. N also corresponds, for example, to the number of resistors 55 that are present on the current path from the node NDb at the other end of the resistor chain RS to a position of the switch SW in the on state.

[0201] The node (tap) NDc, which is connected to the switch SW[CD:N] in the on state, is electrically connected to the node NDd. As in this example, in a case where the switch SW[CD:N] with the code CD of "N" is in the on state, the MN resistors 55 are connected to the current source circuit 59 via the switch SW[CD:N] in the on state.

[0202] In this way, the number of resistors 55 that are put into the effective state as the current path of the current Iin is determined based on the number (address) of the switch SW in the on state specified by the code CD.

[0203] The current source circuit 59 causes the current Ir to flow from the connection node NDc to the ground node NDz via the switch SW[CD:N] in the on state.

[0204] The magnitude of the current Iin depends on the number (here: MN) of resistors 55 through which the current Iin flows.

[0205] The current Iin is divided at the connection node NDc to which the switch SW is connected in the on state.

[0206] A current Iz, which is the remaining part of the current Iin, flows from the non-inverting input terminal IT2 of the operational amplifier 50 through the switch SW[CD:N] in the on state toward the current source circuit 59.

[0207] The relationship between the current Iin and the current Ir is expressed by the following expression 1. Iin=(N / M)×Ir

[0208] Where "M" represents the number of resistors 55 in the resistor chain RS. M is a natural number not less than 1. "N" represents a value corresponding to the number assigned to the switch SW in the on state. For example, N is a natural number not less than 0 (zero). N and M can be binary numbers or decimal numbers.

[0209] For example, in a case where the number (M) of resistors 55 is 256, "N" has any value in the range of 0 to 255. When "N" is 0, the current Iin is 0 from the perspective of circuit design. It should be noted that the current Iin has a weak current value, which depends on a connection resistance included in the circuit and / or a variation in the characteristics between the elements of the circuit.

[0210] Note that the value "N" can be reformulated as the value indicating the number of resistors 55 present from the node NDb at the other end of the resistor chain RS to the position of the switch SW in the on state.

[0211] The value of "N" can also be expressed as a value corresponding to a position where the terminal node NDc in the resistor chain RS, among the plurality of terminal nodes (taps of the resistor 55) NDc in the resistor chain RS, is connected (short-circuited) to the input node NX1 (or the node NDd) of the power source circuit 59 via the switch SW in the on state.

[0212] Alternatively, the value "N" can also be reformulated as a value that indicates the number of resistors 55 that are not present between the switch SW in the on state and one end (input node) NDa of the resistor series NS from the plurality of (M) resistors 55 in the resistor chain RS.

[0213] As in Expression 1, the current Iin can be determined without depending on the magnitude of the resistance value R1 of the resistor 51 and the magnitude of the resistance value R2 of the resistor 55.

[0214] The current Iin, which is an analog value of a certain quantity, is determined by the DA converter DAC according to a digital value N, which is specified by the code CD.

[0215] For example, assume that the number of resistors is 55 256 and the code CD is an 8-bit digital value. In this case, when a first switch SW <0> is selectively switched on, the magnitude of the current Iin becomes essentially zero. When a 256th switch SW <256> is selectively switched on, the magnitude of the current Iin is approximately (255 / 256) x Ir.

[0216] The output voltage Vout of the driver DRV is expressed by the following expression: 2. Vout=Vcenter+R1×(N / M)×Ir

[0217] Here, "Vcenter" represents a voltage applied to the non-inverting input terminal IT2 of the operational amplifier 50. "R1" represents a resistance value of the resistor 51.

[0218] For example, "Vcenter", "M", and "Ir" in Expression 2 are design parameters set for the DA converter DAC and the driver DRV. As described above, "N" in Expression 2 is a variable corresponding to the digital code CD based on the temperature of the storage device 1 and the command CMD.

[0219] Therefore, in Expression 2, the magnitude of the output voltage Vout can be controlled according to the value of "N".

[0220] In this way, the magnitude of the output voltage Vout can be adjusted according to the code CD, the digital value.

[0221] As described above, in the voltage generation circuit 160 of the memory device 1 of the present embodiment, the DA converter DAC and the driver DRV operate.

[0222] As a result, in the present embodiment, the voltage having the set voltage value is supplied to the interconnection in the memory cell array 110. (c) Summary

[0223] In NAND flash memory, the allowable fluctuation range of the verify level and the read level with respect to each threshold voltage distribution decreases as the number of bits that can be stored in a memory cell increases.

[0224] The properties of the memory cell change depending on the temperature of the chip.

[0225] Therefore, it is desirable that the voltage value of the test level and the read level can be adjusted with higher accuracy.

[0226] In the memory device which is the semiconductor device of the present embodiment, the DA converter circuit 163 is used to control the magnitude of the voltage Vout output from the driver circuit 162.

[0227] In the DA converter circuit 163, the DA converter DAC includes the resistor chain RS and the plurality of switches SW. The resistor chain RS includes a plurality of series-connected resistors 55. Each of the plurality of switches SW is connected to one end of a corresponding resistor 55. The resistor chain RS is electrically connected to the power source circuit 59 via the plurality of switches SW.

[0228] When the voltage Vout is output from each driver DRV in the driver circuit 162, one of the multiple switches SW of each DA converter DAC is turned on based on the digital value of the code CD. This controls the number of resistors 55 through which the current from the driver DRV flows in the resistor chain RS. The magnitude of the current flowing in the resistor chain RS is determined.

[0229] As a result, in the memory device 1 as a semiconductor device of the present embodiment, the monotonicity of the DA conversion of the DA converter DAC is ensured.

[0230] For example, if a DA converter of a certain semiconductor device has a circuit configuration that uses a resistor-divided voltage with respect to the output voltage of a voltage source, the output impedance at the output node of the resistor changes according to the digital code. As a result, in a circuit that combines a resistor-divided voltage DA converter and an inverting amplifier circuit, the integral nonlinearity (INL) is degraded.

[0231] As in the semiconductor device of the present embodiment, in a case where the DA converter DAC has a circuit configuration that uses division of the current through the resistor string with respect to the output of the current source circuit 59, it is possible to substantially eliminate the change in the output impedance at the output node of the resistor string RS.

[0232] As a result, in the circuit in which the DA converter DAC in the present embodiment and the inverting amplifier circuit (driver) DRV are combined, the INL is not deteriorated.

[0233] Even if the resistance values R2 of the plurality of resistors 55 in the DA converter 205 vary during a manufacturing process, there is little influence on the current Iin and the output voltage Vout. Therefore, in the semiconductor device 1 of the present embodiment, even if the resolution of the DA converter DAC is, for example, a high bit of 8 bits or higher, the accuracy such as the differential nonlinearity (DNL) of the resistor chain RS and the DA converter circuit 163 is easily maintained high.

[0234] Note that the resistance value R2 of the resistor 55 can be any value because the output voltage Vout of the driver DRV increases with the value of the code. Therefore, the resistor 55 can have a resistance value that is easy to manufacture according to a manufacturing method or the like. That is, the resistance value R2 of the resistor 55 can be small. Therefore, the semiconductor device 1 of the present embodiment can implement the resistor chain RS and the DA conversion circuit 163 with a small area.

[0235] As represented by expressions 1 and 2 above, the current Iin and the output voltage Vout do not depend on the resistance value R2 of the resistor 55 in the resistor chain RS.

[0236] Therefore, the resistance value R2 of the resistor 55 can be set independently of the resistance value R1 of the resistor 51 used for the driver (inverting amplifier circuit) DRV. As a result, the semiconductor device 1 of the present embodiment can improve a degree of freedom in the design of the resistor chain RS and the DA converter circuit 163.

[0237] In the semiconductor device 1 of the present embodiment, the operational amplifier 50 of the driver DRV outputs the output voltage Vout through an inverting amplification process. Therefore, it is not necessary to supply a wide range of input voltages to the operational amplifier 50. As a result, the driver DRV in the semiconductor device 1 of the present embodiment is suitable for operation with a low supply voltage.

[0238] As described above, the semiconductor device of the present embodiment can improve the characteristics of the device. (2) Second embodiment

[0239] A semiconductor device of a second embodiment is described with reference to Fig. 12 described.

[0240] Fig. 12 is a diagram illustrating a configuration example of a DA converter DAC in a semiconductor device (e.g., a memory device) 1 of the present embodiment.

[0241] As in Fig. 12, in the present embodiment, a non-inverting input terminal IT2 of an operational amplifier 50 is separated from a resistor chain RS.

[0242] The non-inverting input terminal IT2 of the operational amplifier 50 is connected to a voltage node NZ1. A voltage generation circuit 160 applies a voltage Vc1 to the voltage node NZ1. As a result, the voltage Vc1 is applied to the non-inverting input terminal IT2 of the operational amplifier 50.

[0243] A node NDb of the resistor chain RS is connected to a voltage node NZ2. The voltage generation circuit 160 applies a voltage Vc2 to the voltage node NZ2.

[0244] As a result, the voltage Vc2 is applied to the node NDb of the resistor chain RS.

[0245] Each of the voltages Vc1 and Vc2 is a fixed voltage with a specific voltage value.

[0246] The magnitude of the output voltage Vout of the driver DRV can be changed by controlling a magnitude ratio between the voltages Vc1 and Vc2.

[0247] For example, if the voltage value of voltage Vc2 is smaller than the voltage value of voltage Vc1, the voltage value of output voltage Vout increases.

[0248] On the other hand, in a case where the voltage value of the voltage Vc2 is made larger than the voltage value of the voltage Vc1, the voltage value of the output voltage Vout decreases.

[0249] In the present embodiment, a current Iin is expressed by the following expression 3. Iin=(N / M)×Ir+(Vc1−Vc2) / (M×R2)

[0250] Where "Vc1" represents the voltage value of the voltage Vc1 applied to the non-inverting input terminal IT2 of the operational amplifier 50. "Vc2" represents the voltage value of the voltage Vc2 applied to the other end of the resistor chain RS.

[0251] The output voltage Vout of the driver DRV is expressed by the following expression: 4. Vout=Vc1+R1×(N / M)×Ir+(R1 / R2)×(Vc1−Vc2) / M

[0252] In this way, the magnitude of the output voltage Vout changes depending on the voltages Vc1 and Vc2 as well as the values "N" and "M" determined by the DA converter DAC.

[0253] With the above configuration, in the present embodiment, the monotonicity of DA conversion in the DA converter DAC is ensured.

[0254] In the present embodiment, the rise and fall of the output voltage Vout of the driver DRV can be controlled.

[0255] As described above, the semiconductor device of the present embodiment can improve the characteristics of the semiconductor device as in the first embodiment. (3) Third embodiment

[0256] A semiconductor device of a third embodiment will be described with reference to Fig. 13 described.

[0257] Fig. 13 is a diagram illustrating a configuration example of a DA converter DAC in a DA converter circuit in a semiconductor device (e.g., a memory device) 1 of the present embodiment.

[0258] As in Fig. 13, a resistor 56 is connected to a node NDx provided between a driver DRV and the DA converter DAC.

[0259] The node NDx is connected to an inverting input terminal IT1 of an operational amplifier 50, a node NDa at one end of a resistor chain RS and one end of a resistor 51.

[0260] One end of resistor 56 is connected to node NDx. The other end of resistor 56 is connected to a voltage node NZ3. Node NDx is provided between node ND1 and node NDa.

[0261] A voltage generation circuit 160 outputs a voltage Vr5 to a voltage node NZ3. Consequently, the voltage Vr5 is applied to the resistor 56.

[0262] The resistor 56 has a resistance value R3.

[0263] The level of the output voltage Vout of the driver DRV can be adjusted according to the level of the resistance value R3 of the resistor 56 and the level of the voltage Vr5.

[0264] In a case where the set value of the output voltage Vout is large, the resistance value R3 is made small. Conversely, in a case where the set value of the output voltage Vout is small, the resistance value R3 is made large. For example, in a case where the set value of the output voltage Vout can be a small value, the resistor 56 with a large resistance value R3 is used. In this case, for example, the resistance value R3 of the resistor 56 is larger than the resistance value R2 of the resistor 51.

[0265] For example, in a case where the setting value of the output voltage Vout is large, the resistance value R3 of the resistor 56 is made smaller than the resistance value R2 of the resistor 51.

[0266] In the present embodiment, a current Iin is expressed by the following Expression 5. Iin=(N / M)×Ir+(Vcenter−Vr5) / R3

[0267] In Expression 5, "Vr5" represents a voltage value of voltage Vr5. "R3" represents a resistance value of resistor R6.

[0268] The output voltage Vout of the driver DRV is expressed by the following expression 6. Vout=Vcenter+R1×(N / M)×Ir+(R1 / R3)×(Vcenter−Vr5)

[0269] With the circuit in Fig. 13, in the present embodiment, the monotony of the DA conversion is ensured by the DA converter DAC in the DA converter circuit 163.

[0270] In the present embodiment, the rise and fall of the output voltage Vout of the driver DRV can be controlled in the driver circuit 162.

[0271] As described above, the semiconductor device of the present embodiment can improve the characteristics of the semiconductor device as in the first embodiment. (4) Fourth embodiment

[0272] A semiconductor device of a fourth embodiment will be described with reference to the Fig. 14 and Fig. 15 described.

[0273] Fig. 14 is a diagram illustrating a configuration example of a DA converter circuit in a semiconductor device (e.g., a memory device) 1 of the present embodiment.

[0274] As in Fig. 14, a resistor chain RS may include a variable resistor (variable resistance element) 57 (57a and 57b).

[0275] The variable resistor 57a is provided at one end of the resistor chain RS. For example, the variable resistor 57a is provided at an initial stage of the resistor chain RS. One end of the variable resistor 57a is connected to a node NDa (and a node ND1). The other end of the variable resistor 57a is connected to one end of a resistor 55 via a node NDc.

[0276] The variable resistor 57a has a resistance value of magnification of 1-α with respect to a resistance value R2 of the resistor 55. The variable resistor 57a has a resistance value of (1-α)R2.

[0277] Variable resistor 57b is provided on the other side of resistor chain RS. For example, variable resistor 57b is provided at an output stage of resistor chain RS. One end of variable resistor 57b is connected to the other end of resistor 55 via node NDc. The other end of variable resistor 57b is connected to a node NDb (and a node ND2).

[0278] The variable resistor 57b has a magnification of α with respect to the resistance value R2 of the resistor 55. The variable resistor 57b has a resistance value of αR2.

[0279] A digital control circuit 191 of a sequencer 190 supplies a control signal (digital signal) Dg to the variable resistors 57a and 57b. The magnitude of the magnification α of the variable resistors 57a and 57b is controlled by the control signal Dg.

[0280] For example, α can take a value in the range from 0 to 0.75. The value of α is specified, for example, by a 2-bit digital signal. In this case, the value of α can be set to one of the values 0, 0.25, 0.5, and 0.75, depending on the value of the digital signal.

[0281] Fig. Figure 15 is an equivalent circuit diagram illustrating an example of the variable resistor 57.

[0282] As in Fig. 15, the variable resistor 57 includes a plurality of resistors 571, 572 and 573 and a plurality of switches SX1, SX2 and SX3.

[0283] The plurality of resistors 571, 572 and 573 are connected in series. The number of resistors 571, 572 and 573 is determined according to the value of α and is in the example in Fig. 15 three. One end of resistor 571 is connected to a node NY1. The other end of resistor 571 is connected to a node NY2. One end of resistor 572 is connected to the other end of resistor 571 via node NY2. The other end of resistor 572 is connected to a node NY3. One end of resistor 573 is connected to the other end of resistor 572 via node NY3. The other end of resistor 573 is connected to a node NY4.

[0284] The plurality of switches SX1, SX2 and SX3 are connected to the resistors 571, 572 and 573. The number of switches SX1, SX2 and SX3 is determined according to the value of α and is in an example in Fig. 15 three. One end of switch SX1 is connected to node NY1. The other end of switch SX1 is connected to node NY4. One end of switch SX2 is connected to node NY2. The other end of switch SX2 is connected to node NY4. One end of switch SX3 is connected to node NY3. The other end of switch SX3 is connected to node NY4.

[0285] When the variable resistor 57 in Fig. 15 the variable resistor 57a in Fig. 14, the node NY1 is connected to the node NDa and the node NY4 is connected to the resistor 55 via the node NDc. When the variable resistor 57 is in Fig. 15 the variable resistor 57b in Fig. 14, node NY1 is connected to resistor 55 via node NDc, and node NY4 is connected to node NDb via node NDc.

[0286] Each of resistors 571, 572, and 573 has a resistance value R9. The resistance value R9 is, for example, equal to 1 / 4 of the resistance value R2 (R2 / 4). In variable resistor 57, any one of the plurality of switches SX1, SX2, and SX3 is turned on based on digital signal Dg. As a result, in variable resistor 57, a current is divided at a position of switch SX in an on state.

[0287] As in Fig. 15, two variable resistors 57a and 57b, each comprising three resistors 571, 572 and 573, can correspond to a digital value of two bits contained in a code CD.

[0288] In the present embodiment, the monotony of the DA conversion is ensured by the DA converter DAC in the DA converter circuit 163.

[0289] In the present embodiment, in a case where the variable resistor 57 is applied to the resistor string RS of the DA converter DAC, the number of resistors 55 in the resistor string RS can be reduced. As a result, the semiconductor device 1 of the present embodiment can downsize the DA converter DAC.

[0290] As a result, the semiconductor device 1 of the present embodiment can reduce the area of the circuit including a plurality of DA converters. Accordingly, the semiconductor device 1 of the present embodiment can reduce the manufacturing cost (chip cost) of the semiconductor device. (5) Fifth embodiment

[0291] A semiconductor device of a fifth embodiment will be described with reference to Fig. 16 described.

[0292] The semiconductor device of the present embodiment may be a device other than a memory device. For example, the semiconductor device of the present embodiment is a wireless communication device.

[0293] Fig. 16 is a block diagram illustrating a configuration example of a wireless communication device 1A of the present embodiment.

[0294] The wireless communication device 1A of the present embodiment includes an antenna 700, a filter 701, a power amplifier 702, a multi-band transceiver 703, and a processor 704.

[0295] The wireless communication device 1A of the present embodiment includes a memory module 705, an additional wireless communication circuit 706A, an antenna 706B, a camera 707, an input interface 708, a display 709, an acoustic device 710, an illumination controller 711, a light-emitting device (LED) controller 712, an acoustic controller 713, and the like.

[0296] The antenna 700 receives a radio frequency signal (radio wave) from outside the wireless communication device 1A. The antenna 700 transmits a radio frequency signal generated in the wireless communication device 1A to outside the wireless communication device 1A.

[0297] Filter 701 performs various types of filtering of the radio frequency signal provided by antenna 700 or power amplifier 702. For example, filter 701 can switch a transmit and receive path of the radio frequency signal.

[0298] The power amplifier 702 amplifies a signal transmitted to the outside of the wireless communication device 1A. The power amplifier 702 amplifies the power for a signal from the multi-band transceiver 703. The power amplifier 702 includes, for example, a driver circuit 162 and a DA converter circuit 163 of the above-described embodiment. In the DA converter circuit 163 used for the power amplifier 702, for example, a current source circuit 59 has a circuit configuration according to one of the Fig. 8, Fig. 9 and Fig. 10 on.

[0299] The multi-band transceiver 703 performs modulation and demodulation processing on the high-frequency signal. The multi-band transceiver 703 performs demodulation processing on the signal received by the antenna 700. As a result, a baseband signal is extracted from the received signal. The multi-band transceiver 703 performs modulation processing on the baseband signal generated in the wireless communication device 1A. As a result, the modulated signal is transmitted from the antenna 700 to the outside of the wireless communication device 1A via the power amplifier 702 and the filter 701.

[0300] The multi-band transceiver 703 is configured to perform signal processing simultaneously using a plurality of carrier frequencies through carrier aggregation. For example, the multi-band transceiver performs various types of signal processing based on various standards of a third-generation mobile communication system, such as a wideband code division multiple access (WCDMA) (registered trademark) standard, various standards of a fourth-generation mobile communication system, such as a Long-Term Evolution (LTE) (registered trademark) Advanced standard, a fifth-generation mobile communication system standard, and a sixth-generation mobile communication system.

[0301] The processor 704 performs various types of calculations and controls in the wireless communication device 1A. The processor 704 includes, for example, a central processing unit (CPU) 719A, a baseband processor 719B, an application processor 719C, and the like.

[0302] The CPU 719A performs control processing with respect to an entire wireless communication device 1A and various types of processing of data.

[0303] The baseband processor 719B performs various types of wireless communication control, such as signal generation, signal demodulation and modulation control, signal coding, and frequency shifting.

[0304] The application processor 719C manages the software (program) in the wireless communication device 1A.

[0305] The memory module 705 stores various data used for the wireless communication device 1A. The memory module 705 includes a volatile semiconductor memory such as SRAM or DRAM and / or a non-volatile semiconductor memory such as flash memory.

[0306] An additional wireless communication circuit 706A performs a wireless communication function additionally used in the wireless communication device 1A, such as a global positioning system (GPS), a wireless local area network (WLAN), and Bluetooth (registered trademark). The additional wireless communication circuit 706A communicates with a device external to the wireless communication device 1A via the antenna 706B.

[0307] Camera 707 can capture a still image and a moving image. Camera 707 can read a one-dimensional code and a two-dimensional code. Camera 707 includes, for example, an image sensor.

[0308] The input interface 708 serves as a user input interface for the wireless communication device 1A. The input interface 708 is, for example, a touch panel, a keypad, or the like. The input interface may be a keyboard or a mouse.

[0309] The display 709 displays to the user the information received from the wireless communication device 1A and the information generated by the wireless communication device 1A. The display 709 is, for example, a liquid crystal display such as a touch panel or an organic electroluminescent (EL) display.

[0310] The acoustic device 710 provides the user with voice information received from the wireless communication device 1A and voice information generated by the wireless communication device 1A. The acoustic device 710 includes a microphone and a speaker.

[0311] The illumination controller 711 controls the illuminance of the display 709. The illumination controller 711 includes, for example, a driver circuit 162 and a DA converter circuit 163 of the above-described embodiment. In a case where the DA converter circuit 163 is used for the illumination controller 711, a circuit 59A in Fig. 8 or a circuit 59B in Fig. 9 is used for the current source circuit 59 of the DA converter DAC.

[0312] The light-emitting device (e.g., LED) controller 712 controls the intensity of light emission of a light-emitting device (e.g., a light-emitting diode), such as the illumination (not illustrated) of the wireless communication device 1A. The light-emitting device controller 712 includes, for example, the driver circuit 162 and the DA converter circuit 163 of the above-described embodiment. In a case where the DA converter circuit 163 is used for the light-emitting device controller 712, the circuit 59A in Fig. 8 or the circuit 59B in Fig. 9 is used for the current source circuit 59 of the DA converter DAC.

[0313] The acoustic controller 713 controls a speech signal of the acoustic device 710. The acoustic controller 713 includes, for example, the driver circuit 162 and the DA converter circuit 163 of the above-described embodiment. In a case where the DA converter circuit 163 is used in the acoustic controller 713, the circuit 59C in Fig. 10 is preferably used for the current source circuit 59 of the DA converter DAC, so that the speech signal can be controlled by a current with positive polarity and a current with negative polarity.

[0314] For example, a SIM card 715 is inserted into a slot 714 of the wireless communication device 1A. The SIM card 715 provides the wireless communication device 1A with identification information of the user using the wireless communication device 1A.

[0315] The wireless communication device 1A is, for example, a smartphone, a personal digital assistant (e.g., a tablet), a laptop, or an unmanned aerial vehicle.

[0316] As described above, the DA converter DAC of the DA converter circuit 163 and the driver DRV of the driver circuit 162 of the above-described embodiment are applied to the wireless communication device 1A as the semiconductor device of the present embodiment.

[0317] The semiconductor device of the present embodiment can achieve similar effects to the above-described embodiment. (6) Sixth embodiment

[0318] A semiconductor device of a sixth embodiment will be described with reference to Fig. 17 described.

[0319] The semiconductor device of the embodiment may be an input / output interface circuit. The input / output interface circuit may be a circuit compatible with optical or wired communications such as Ethernet (registered trademark), or it may be a circuit compatible with wireless communications such as RF.

[0320] Fig. 17 is a block diagram illustrating a configuration example of an input / output interface circuit 1B of the present embodiment.

[0321] In Fig. 17, the input / output interface circuit (transceiver) 1B is a transmission-type differential input / output interface circuit. The input / output interface circuit 1B includes a pair of differential input / output terminals 739A and 739B. The input / output interface circuit 1B receives differential signals IO+ and IO- and transmits the differential signals IO+ and IO- via the differential input / output terminals 739A and 739B. The two differential signals IO+ and IO- are in a complementary relationship to each other.

[0322] In the present embodiment, the two input / output terminals 739A and 739B forming a pair for differential transmission are referred to as a differential input / output terminal pair. A pair of signal lines for differential transmission in the input / output interface circuit 1B is referred to as a differential transmission path.

[0323] The input / output interface circuit 1B includes an analog-to-digital (AD) conversion circuit 720, resistor-capacitor circuits 722A and 722B, capacitor circuits 723A and 723B, a digital-to-analog (DA) conversion circuit 724, a current sink circuit 725, a clock phase adjustment circuit 726, a control clock generator 727, an input monitor 728, an input / output monitor 729, a PVT monitor 730, a global bias generator 731, bias generators 732 and 733, an input / output controller 734, and the like.

[0324] The AD converter circuit 720 receives the differential signals IO+ and IO- input to the input / output interface circuit 1B via the resistor-capacitor (RC) circuits 722A and 722B. The AD converter circuit 720 receives reference signals IOMVR+ and IOMVR- from the bias voltage generator 732. The AD converter circuit 720 converts the signals IO+ and IO- from analog signals to digital signals using the reference signals IOMVR+ and IOMVR-.

[0325] The AD converter circuit 720 includes, for example, a driver circuit 162 and a DA converter circuit 163 of the above-described embodiment. In a case where the AD converter circuit 720 has a successive approximation type circuit configuration, the AD converter circuit 720 includes, for example, a DA converter circuit, a comparison circuit, and a control circuit. The DA converter circuit 163 of the embodiment is used for a DA converter circuit of the successive approximation type AD converter circuit 720.

[0326] RC circuits (hereinafter also referred to as RC networks) 722A and 722B are provided to correspond to the input / output terminals 739A and 739B, respectively. The RC circuit 722A is connected to a signal path of the input / output terminal 739A. The RC circuit 722B is connected to a signal path of the input / output terminal 739B. The RC circuits 722A and 722B control a time constant with respect to the input signal. The RC circuits 722A and 722B include a resistor and a capacitor and can be designed (programmed) after assembly.

[0327] Capacitor circuits 723A and 723B are provided between RC circuits 722A and 722B and DA converter circuit 724. Capacitor circuit 723A is connected to RC circuit 722A. Capacitor circuit 723B is connected to RC circuit 722B. Capacitor circuits 723A and 723B include a plurality of capacitors. Capacitor circuits 723A and 723A smooth signals.

[0328] The D / A converter circuit 724 receives the digital signals. The D / A converter circuit 724 receives the reference signals IOMVR+ and IOMVR- from the bias generator 732.

[0329] The DAC circuit 724 generates an analog signal IODACOUT+ and an analog signal IODACOUT- based on the received digital signals and the reference signals IOMVR+ and IOMVR-. The two analog signals IODACOUT+ and IODACOUT- are signals that are in a complementary relationship to each other.

[0330] The DA converter circuit 724 sends the generated analog signals IODACOUT+ and IODACOUT- to the input / output terminals 739A and 739B via the capacitor circuit 723 and the RC circuit 722. The DA converter circuit 724 transmits the analog signals IODACOUT+ and IODACOUT- to the current sink circuit 725.

[0331] The signals IODACOUT+ and IODACOUT- are output as differential signals IO+ and IO- to the input / output interface circuit 1B.

[0332] The DA converter circuit 724 includes the driver circuit 162 and the DA converter circuit 163 of the above-described embodiment. The DA converter circuit 724 generates the analog signal IODACOUT+ and the analog signal IODACOUT- from the digital signals and the reference signals IOMVR+ and IOMVR- using the driver circuit 162 and the DA converter circuit 163 of the above-described embodiments.

[0333] For example, the DA converter circuit 724 generates the analog signal IODACOUT+ and the analog signal IODACOUT- using two DA converter circuits 163. Alternatively, the DA converter circuit 724 inverts and amplifies the analog signal IODACOUT+ generated by one DA converter circuit 163 with an operational amplifier to generate the analog signals IODACOUT- that form a pair.

[0334] The current sink circuit 725 controls the magnitude of a current flowing through the input / output terminal 739 and the signal line within an allowable range based on the specifications of the input / output interface circuit 1B. The current sink circuit 725 includes, for example, the driver circuit 162 and the DA converter circuit 163 of the above-described embodiment.

[0335] The clock phase adjustment circuit 726 adjusts the phase of a reference clock signal and generates various clock signals used for the input / output interface circuit 1B.

[0336] The control clock generator 727 generates a control clock used for the AD converter circuit 720 and the input / output monitor 729.

[0337] The input monitor 728 monitors the IO+ and IO- signals at the input / output terminals 739A and 739B.

[0338] The input / output monitor 729 monitors a plurality of clock signals from the control clock generator 727.

[0339] The PVT Monitor 730 monitors various bandgap voltages and bias voltages in the input / output interface circuit 1B. The bandgap voltage is a voltage (reference voltage) that serves as a reference for a signal's voltage amplitude. The bias voltage is a voltage for operating the individual circuit blocks in the input / output interface circuit 1B.

[0340] The global bias generator 731 generates a main bias voltage used for each circuit block in the input / output interface circuit 1B.

[0341] The bias generator 732 generates voltages that serve as references for the bias voltages (bias signals) of the AD converter circuit 720 and the DA converter circuit 724. The bias generator 732 includes, for example, the driver circuit 162 and the DA converter circuit 163 of the above-described embodiment. The bias generator 732 generates voltages that serve as references for the bias voltages (bias signals) based on the control signal received from the input / output controller 734 using the driver circuit 162 and the DA converter circuit 163 of the above-described embodiment. The bias generator 733 generates the bias voltages for the AD converter circuit 720 and the input / output controller 734.

[0342] The input / output controller 734 generates the control signal for each circuit block in the input / output interface circuit 1B. The input / output controller 734 supplies the generated control signal to each circuit block.

[0343] As described above, a DA converter DAC of the DA converter circuit 163 and a driver DRV of the driver circuit 162 of the above-described embodiment are applied to the input / output interface circuit 1B as a semiconductor device of the present embodiment.

[0344] Therefore, the semiconductor device of the present embodiment can achieve the same effects as the above-described embodiment. (7) Seventh embodiment

[0345] A semiconductor device of a seventh embodiment will be described with reference to Fig. 18 described.

[0346] The semiconductor device of the embodiment may be a microcontroller.

[0347] Fig. 18 is a block diagram showing a configuration example of a microcontroller 1C of the present embodiment.

[0348] The microcontroller 1C of the present embodiment includes a system on chip (SoC), a system in package (SIP), and a system on package (SoP). The microcontroller 1C is used in an embedded system. The microcontroller 1C of the present embodiment is, for example, a device for use in vehicles. Note that the microcontroller 1C can be used for household electrical appliances, computers, industrial machinery, railway vehicles, aircraft, ships, and the like.

[0349] The 1C microcontroller is classified based on bus width, memory structure, job set, and the like. The bus width indicates the size of a data bus. For example, the 1C microcontroller is classified into an 8-bit microcontroller, a 16-bit microcontroller, or a 32-bit microcontroller based on bus width. The 1C microcontroller can achieve better performance with a larger bus width.

[0350] As in Fig. 18, the microcontroller 1C includes a processor 750, a bus 751, a bus controller 752, memory devices 753 and 754, a DA converter circuit 755, an AD converter circuit 756, a timer 757, an input / output terminal 758, an oscillator 759, an interrupt controller 760, and the like.

[0351] Processor 750 performs various types of processing in microcontroller 1C. Processor 750 performs various types of processing on the supplied data. Processor 750 is, for example, a CPU.

[0352] Bus 751 is connected to processor 750, bus controller 752, memory devices 753 and 754, D / A converter circuit 755, AD converter circuit 756, timer 757, and input / output port 758. Bus 751 is a signal and data transmission path in microcontroller 1C.

[0353] The bus controller 752 controls the bus 751. The bus controller 752 may be provided in the processor 750.

[0354] The storage device 753 stores data in non-volatile form. The storage device 753 is, for example, a NOR flash memory. The NOR flash memory as the storage device 753 includes, for example, a driver circuit 162 and a DA converter circuit 163 of the above-described embodiment. Note that the storage device 753 may be the above-described NAND flash memory.

[0355] The storage device 754 temporarily stores data. The storage device 753 is, for example, a random access memory such as SRAM or DRAM. The random access memory as the storage device 753 includes, for example, the driver circuit 162 and the DA converter circuit 163 of the above-described embodiment.

[0356] The DA converter circuit 755 converts a digital signal (digital value) into an analog signal (analog value). The DA converter circuit 755 includes, for example, the driver circuit 162 and the DA converter circuit 163 of the above-described embodiment.

[0357] The AD converter circuit 756 converts an analog signal into a digital signal. The AD converter circuit 756 includes, for example, the driver circuit 162 and the DA converter circuit 163 of the above-described embodiment.

[0358] The timer 757 manages the time (operating time) in the microcontroller 1C.

[0359] The input / output port 758 functions as a data interface circuit in the microcontroller 1C. The input / output port 758 includes, for example, four ports P1, P2, P3, and P4. The number of ports of the input / output port 758 can be three or fewer, five or more.

[0360] The input / output port 758 receives data, an address, and a signal from outside the microcontroller 1C via the ports P1, P2, P3, and P4. The input / output port 758 transmits the data and signal to the outside of the microcontroller 1C via the ports P1, P2, P3, and P4.

[0361] For example, the input / output port 758 includes an interface based on a GPIO (General Purpose Input / Output) standard, a USART (Universal Synchronous / Asynchronous Receiver Transmitter) standard, an I2C (Inter-Integrated Circuit) standard, or the like.

[0362] The input / output terminal 758 includes, for example, the driver circuit 162 and the DA converter circuit 163 of the embodiment described above.

[0363] Oscillator 759 outputs a clock signal as a synchronization signal to processor 750. The clock signal has a specific cycle (clock number). As a result, processor 750 executes various types of processing at a time synchronized with the clock signal. The clock signal frequency is, for example, 4 MHz, 8 MHz, 12 MHz, 24 MHz, or the like.

[0364] The interrupt controller 760 receives an external interrupt request. The interrupt controller 760 contains, for example, a register for managing the status of an interrupt request.

[0365] The interrupt controller 760 sends various interrupt requests to the processor 750 based on the received external interrupt request. In response to the interrupt request, the processor 750 temporarily interrupts the ongoing processing and executes the processing of the interrupt request. After completing the processing of the interrupt request, the processor 750 resumes the interrupted processing.

[0366] As described above, a DA converter DAC of the DA converter circuit 163 and a driver DRV of the driver circuit 162 of the above-described embodiment are applied to the microcontroller 1C as a semiconductor device of the present embodiment.

[0367] Therefore, the semiconductor device of the present embodiment can achieve the same effects as the above-described embodiment. (8) Other

[0368] The semiconductor device 1 of the present embodiment is not limited to the various components described above. The semiconductor device 1 of the embodiment may be, for example, a random access memory, a read-only memory, an image sensor, an application-specific integrated circuit (ASIC), a processor, or the like.

[0369] Although specific embodiments have been described, these embodiments have been presented only by way of example and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions, and changes may be made in the form of the embodiments described herein without departing from the spirit of the inventions. The appended claims and their equivalents are intended to cover such forms or changes as fall within the scope and spirit of the inventions. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2002-76897 B

[0003] < / m> < / m> < / gesamtkonfiguration>

Claims

[1] A semiconductor device (160) comprising: an operational amplifier (50) including a first input terminal (IT1), a second input terminal (IT2) and an output terminal (OT), the operational amplifier outputting a first voltage (Vout) from the output terminal; a first resistor (51) including one end connected to the first input terminal and another end connected to the output terminal; a variety of second resistors (55 <1> up to 55 <m>) including one end connected to the first input terminal, wherein the plurality of second resistors are connected in series; a variety of switches (SW <1> to SW <m>), each having one end connected to a first node (NDc) between two adjacent resistors of the plurality of second resistors, and another end connected to a second node (NDd), the plurality of switches receiving a digital code (CD); and a current source circuit (59) connected between the second node and a third node (NDz), wherein one switch from the plurality of switches is switched on based on the digital code, and the current source circuit causes a first current (Ir) to flow from some or all of the plurality of second resistors to the third node via the switch in an on state. [2] The semiconductor device according to claim 1, wherein the second input terminal is connected to another end of the plurality of second resistors. [3] A semiconductor device according to claim 1, wherein the first voltage is determined based on N and M, and M is the number of multiple second resistors. [4] The semiconductor device according to claim 3, wherein N represents a value of the digital code associated with the switch that has been set to the on state among the plurality of switches. [5] A semiconductor device according to claim 3, wherein N represents the number of resistors not present between one end of the plurality of second resistors and the switch in the on state. [6] A semiconductor device according to claim 3, wherein N represents the number of resistors present between another end of the plurality of second resistors and the switch in the on state. [7] A semiconductor device according to claim 3, wherein the plurality of second resistors comprises a plurality of connection nodes, and the N is a value indicating a position of a connection node connected to the power source circuit via the switch in the on state, among the plurality of connection nodes. [8] A semiconductor device according to claim 2, wherein the first voltage is expressed by the following expression A Vout=Vcenter+R1×(N / M)×Ir where M represents the number of the plurality of second resistors, N represents the number of second resistors not present between one end of the plurality of second resistors and the switch in the on state, Vcenter represents a voltage applied to the second input terminal, R1 represents a resistance value of the first resistor, and Ir represents the first current. [9] A semiconductor device according to claim 1, wherein the second input terminal is connected to a first voltage node to which a second voltage is applied, and the other end of the plurality of second resistors is electrically separated from the first voltage node and connected to a second voltage node to which a third voltage is supplied. [10] A semiconductor device according to claim 9, wherein the first voltage is expressed by the following expression B Vout=Vc1+R1×(N / M)×Ir+(R1 / R2)×(Vc1−Vc2) / M where M represents the number of the plurality of second resistors, N represents the number of second resistors not present between one end of the plurality of second resistors and the switch in the on state among the plurality of second resistors, Vc1 represents a voltage value of the second voltage, Vc2 represents a voltage value of the third voltage, R1 represents a resistance value of the first resistor, R2 represents a resistance value of one of the plurality of second resistors, and Ir represents the first current. [11] A semiconductor device according to claim 1, further comprising: a third voltage node to which a fourth voltage is supplied; and a third resistor connected between the first input terminal and the third voltage node. [12] A semiconductor device according to claim 11, wherein the first voltage is expressed by the following expression C Vout=Vcenter+R1×(N / M)×Ir+(R1 / R3)×(Vcenter−Vr5) where M represents the number of the plurality of second resistors, N represents the number of second resistors not present between one end of the plurality of second resistors and the switch in the on state among the plurality of second resistors, Vcenter represents a voltage supplied to the second input terminal, R1 represents a resistance value of the first resistor, R3 represents a resistance value of the third resistor, Vr5 represents the fourth voltage, and Ir represents the first current. [13] A semiconductor device according to claim 1, wherein a resistor at one end of the plurality of second resistors is a first variable resistor, a resistor at another end of the plurality of second resistors is a second variable resistor, the first variable resistor has a variable ratio of 1-α with respect to a resistance value of a resistor from the plurality of second resistors, and the second variable resistor has a variable ratio of α with respect to the resistance value of a resistor from the plurality of second resistors. [14] A semiconductor device according to claim 1, wherein the current source circuit causes a current having one polarity to flow in one direction. [15] A semiconductor device according to claim 1, wherein the current source circuit flows a current with bipolarity. [16] A semiconductor device according to claim 1, further comprising: a communication circuit that sends and receives a wireless signal. [17] A semiconductor device according to claim 1, further comprising: an input / output port pair for differential transmission. [18] A semiconductor device according to claim 1, further comprising: a processor that performs the processing of data supplied via a port and interrupt processing supplied from outside. [19] Storage device (1) comprising: a memory cell (MT) that stores data; and a voltage generating circuit (160) that generates a voltage for operating the memory cell; wherein The voltage generation circuit includes: an operational amplifier (50) having a first input terminal (IT1), a second input terminal (IT2) and an output terminal (OT), the operational amplifier outputting a first voltage (Vout) from the output terminal; a first resistor (51) including one end connected to the first input terminal and another end connected to the output terminal; a variety of second resistors (55 <1> up to 55 <m>), each of which has one end connected to the first input terminal, the plurality of second resistors being connected in series; a variety of switches (SW <1> to SW <m>), each having one end connected to a first node (NDc) between two adjacent resistors of the plurality of second resistors, and another end connected to a second node (NDd), the plurality of switches receiving a digital code (CD); and a current source circuit (59) connected between the second node and a third node (NDz), one of the plurality of switches is switched on based on the digital code, and the current source circuit causes a first current (Ir) to flow from some or all of the plurality of second resistors to the third node via the switch in an on state. [20] A storage device according to claim 19, further comprising: a temperature sensor that measures the temperature of the storage device, wherein the digital code is a value corresponding to a measurement result of the temperature measured by the temperature sensor.< / m> < / m> < / m> < / m>

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